CN106098004A - Control device and control method for liquid crystal indicator - Google Patents
Control device and control method for liquid crystal indicator Download PDFInfo
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- CN106098004A CN106098004A CN201610656340.9A CN201610656340A CN106098004A CN 106098004 A CN106098004 A CN 106098004A CN 201610656340 A CN201610656340 A CN 201610656340A CN 106098004 A CN106098004 A CN 106098004A
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- address
- memory element
- encoding data
- control device
- time schedule
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
This application discloses a kind of control device for liquid crystal indicator and control method.Described control device includes: time schedule controller, is used for providing clock signal；And at least one memory element, for storing the scanning encoding data of different scanning pattern, wherein, described time schedule controller is according to selecting signal acquisition access unit address, thus reads the scanning encoding data of different scanning pattern according to access unit address.This control device utilizes the mode of addressing to access different scanning encoding data, owing to without using switch element, therefore can reducing product cost and improving display quality.
Description
Technical field
The present invention relates to Display Technique field, more particularly, to for the control device of liquid crystal indicator and control
Method.
Background technology
Liquid crystal indicator is that the phenomenon that the orientation utilizing liquid crystal molecule changes under the work of electric field changes light
The display device of source light transmittance.Liquid crystal indicator has been widely used for mobile terminal and the such as flat board electricity of such as mobile phone
Depending on large scale display floater in.
Fig. 1 illustrates the equivalent circuit diagram of the liquid crystal indicator according to prior art.Liquid crystal indicator includes the first glass
Glass substrate and the second glass substrate, the first surface of the first glass substrate and the first surface of the second glass substrate are relative.?
Formed on the first surface of one glass substrate and a plurality of controlling grid scan line intersected with each other and a plurality of source data line are set, at the two
Crossover location selection thin film transistor (TFT) and pixel electrode is set.First surface at the second glass substrate forms public electrode.
Comprise liquid crystal layer between pixel electrode and public electrode, pixel capacitance Clc can be equivalent to.In order to the update cycle of pixel it
Between keep voltage, pixel capacitance Clc can storage electric capacity Cs in parallel to obtain the longer retention time.
Gate drivers 310 is connected to a plurality of controlling grid scan line, is used for providing grid voltage G1 to Gm.Source electrode driver
410 are connected to a plurality of source data line, are used for providing gray scale voltage S1 to Sn.Time schedule controller 110 respectively with gate drivers
310 are connected with source electrode driver 410, thus provide various clock signal to gate drivers 310 and source electrode driver 410.
In the driving method of above-mentioned liquid crystal indicator, in each frame period, in the control of time schedule controller 110
Under scan a plurality of controlling grid scan line successively.Thin film transistor (TFT) is gated via controlling grid scan line, and will be with via source data line
The corresponding voltage of GTG applies to pixel capacitance Clc, thus changes the orientation of liquid crystal molecule with the brightness realizing corresponding GTG.
Fig. 2 illustrate according in the liquid crystal indicator of prior art for produce sequential control device schematic frame
Figure.Time schedule controller 110 reads scanning encoding data from storage device 121 and 122, such that it is able to change scanning side as required
Formula, such as positive counter-scanning switching.The liquid crystal indicator of prior art stores different scanning mode in a plurality of storage devices
Scanning encoding data, and utilize the connection between switch element 130 switching sequence controller 110 and multiple storage device.?
During turntable driving, time schedule controller 110, according to the scan mode specified, reads scanning encoding data from corresponding storage device.
But, the switch element in above-mentioned sequential interlock circuit introduces the components such as switching tube and parasitic capacitance, leads
Cause product cost increase and clock and data signal distortion.Therefore, it is desirable to simplify time schedule controller to select scanning encoding data
Control mode, thus reduce product cost and improve display quality.
Summary of the invention
In view of the above problems, it is an object of the invention to provide a kind of control device for liquid crystal indicator and control
Method, wherein utilizes and addresses and the mode of non-switch switching accesses different scanning encoding data.
According to an aspect of the present invention, it is provided that a kind of control device for liquid crystal indicator, including sequencing contro
Device, is used for providing clock signal；And at least one memory element, for storing the scanning encoding data of different scanning pattern,
Wherein, described time schedule controller is according to selecting signal acquisition access unit address, thus reads according to access unit address
The scanning encoding data of different scanning pattern.
Preferably, described time schedule controller includes that multiple selection end, the plurality of selection end receive multiple selection respectively and believe
Number.
Preferably, at least one memory element described includes that multiple memory element, the plurality of memory element store respectively
The scanning encoding data of different scanning pattern, the plurality of memory element includes multiple addresses end, the plurality of address end respectively
Connect into corresponding with the numerical value of preset address high significance bit.
Preferably, when reading the scanning encoding data of different scanning pattern, the level of the plurality of selection signal and institute
The numerical value stating preset address high significance bit is corresponding.
Preferably, at least one memory element described includes that single memory element, described the multiple of single memory element are deposited
Storage area stores the scanning encoding data of different scanning pattern respectively.
Preferably, when reading the scanning encoding data of different scanning pattern, the level of the plurality of selection signal and institute
The address offset amount stating multiple memory block is corresponding.
Preferably, at least one in the plurality of selection end of described time schedule controller selects end ground connection, thus keeps
For numerical value 0.
Preferably, at least one in the plurality of selection end of described time schedule controller selects termination high level, thus
Remain numerical value 1.
Preferably, at least one memory element described includes in multiple addresses end, and the plurality of address end respectively
At least one address end ground connection, thus remain numerical value 0.
Preferably, at least one memory element described includes in multiple addresses end, and the plurality of address end respectively
At least one address termination high level, thus remain numerical value 1.
Preferably, described scanning encoding data for selected from 6 just sweeping coded data, 6 counter sweep coded data, 8 just sweep
Coded data and 8 anti-one swept in coded data.
Preferably, at least one memory element described is EEPROM.
Preferably, described time schedule controller is connected at least one memory element described via I2C bus.
According to a further aspect in the invention, it is provided that a kind of control method for liquid crystal indicator, including: according to selection
Signal acquisition access unit address；And the scanning encoding data of different scanning pattern are read according to access unit address.
Preferably, also include: multiple addresses end of multiple memory element is connected into and the number of preset address high significance bit
It is worth corresponding.
Preferably, according to selecting signal acquisition access unit address to include: in multiple selection terminations of time schedule controller
Receiving multiple selection signal, the level of the plurality of selection signal is corresponding with the numerical value of preset address high significance bit.
Preferably, also include: the memory space of single memory element is divided into multiple memory block.
Preferably, according to selecting signal acquisition access unit address to include: in multiple selection terminations of time schedule controller
Receiving multiple selection signal, the level of the plurality of selection signal is corresponding with the address offset amount of the plurality of memory block.
The device that controls according to this embodiment of the invention is provided without the memory element that switch element switching is different.According to selection
Signal generates access unit address, thus reads different scanning encoding data.Owing to without using switch element, therefore may be used
Reduce product cost to reduce circuit board size, the product cost avoiding switch element to cause and signal and improve display matter
Amount.
Accompanying drawing explanation
By description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the present invention, feature and
Advantage will be apparent from.
Fig. 1 illustrates the equivalent circuit diagram of the liquid crystal indicator according to prior art.
Fig. 2 illustrate according in the liquid crystal indicator of prior art for produce sequential control device schematic frame
Figure.
Fig. 3 illustrates in the liquid crystal indicator of first embodiment of the invention and controls the schematic of device for produce sequential
Block diagram.
Fig. 4 illustrates in the liquid crystal indicator of first embodiment of the invention for producing the flow process of the control method of sequential
Figure.
Fig. 5 illustrates that the mapping selecting signal and memory element in liquid crystal indicator according to a first embodiment of the present invention is closed
System.
Fig. 6 illustrates in the liquid crystal indicator of second embodiment of the invention and controls the schematic of device for produce sequential
Block diagram.
Fig. 7 illustrates in the liquid crystal indicator of second embodiment of the invention for producing the flow process of the control method of sequential
Figure.
Fig. 8 illustrates and selects signal and the mapping of storage address in liquid crystal indicator according to a second embodiment of the present invention
Relation.
Fig. 9 a to 9d is shown respectively the memory space of memorizer in liquid crystal indicator according to a second embodiment of the present invention
The mapping graph of distribution.
Detailed description of the invention
It is more fully described various embodiments of the present invention hereinafter with reference to accompanying drawing.In various figures, identical element
Same or similar reference is used to represent.For the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.
Below in conjunction with the accompanying drawings and embodiment, the detailed description of the invention of the present invention is described in further detail.
Fig. 3 illustrates in the liquid crystal indicator of first embodiment of the invention and controls the schematic of device for produce sequential
Block diagram.This control device is such as in the liquid crystal indicator shown in Fig. 1, for carrying to gate drivers and source electrode driver
For various clock signals.
This control device includes time schedule controller 110 and four memory element 121 to 124.Memory element 121 to 124
Can be such as EEPROM (Electrically Erasable Programmable Read-Only
Memory, EEPROM).Memory element 121 to 124 stores the scanning encoding data of different length and/or coded system, example respectively
As, 6 just sweeping coded data, 6 counter sweep coded data, 8 just sweeping coded data and 8 counter sweep coded data.
Time schedule controller 110 includes that three select end SEL0 to SEL2, and clock end SCL and data terminal SDA.At three
Select end SEL0 to SEL2, select end SEL0 ground connection, thus maintain low level all the time, i.e. remain numerical value 0, select end SEL1 and
SEL2 receives two and selects signal.Three binary numerals selecting end SEL0 to SEL2 to produce are 000,010,100 and
One of 110.For brevity, the most not shown time schedule controller 110 is connected with gate drivers and source electrode driver
Terminal.
The mapping relations of memory element 121 and 124 and selection signal are as shown in Figure 5.Memory element 121 and 124 has respectively
There are three address end A0 to A2, and clock end SCL and data terminal SDA.Three address end A0 to A2 of memory element 121 are respectively
Ground connection so that the binary address that address high significance bit is 000 beginning of memory block.Two address end A0 of memory element 122
With A2 ground connection respectively, an address end A1 connects high level so that the binary system that address high significance bit the is 010 beginning ground of memory block
Location.Two address end A0 and A1 of memory element 123 ground connection respectively, an address end A2 connects high level so that the ground of memory block
Location high significance bit is the binary address of 100 beginnings.One address end A0 ground connection of memory element 124, two address end A1 and
A2 connects high level respectively so that the binary address that address high significance bit is 110 beginnings of memory block.
Time schedule controller 110 is connected to four memory element via I2C bus, such that it is able to respectively from four memory element
Middle reading scanning encoding data.I2C bus is the twin wire universal serial bus developed by PHILIPS company, including clock bus SCL
With data/address bus SDA, thus realize synchronous data communication.To this end, the clock end SCL of time schedule controller 110 to be connected to clock total
Line SCL, data terminal SDA are connected to data/address bus SDA.
In this embodiment, time schedule controller 110 is as main frame, and four memory element are as from machine.At data/address bus SDA
In the byte transmitted, including slave addresses and reading of content, thus realize addressing.Selection end according to time schedule controller 110
The selection signal that SEL0 to SEL2 provides, can select one of four memory element, reads the scanning encoding data wherein stored.
In this control device, the connection selecting end connected mode and four access unit address ends of time schedule controller
Mode is corresponding.Each access unit address end connected mode is different, correspond to the address high significance bit numerical value preset.Time
The selection signal selecting end to provide of sequence controller is used for when addressing producing address high significance bit numerical value, such that it is able to select four
One of individual memory element reads scanning encoding data.
Different from the control device of the prior art shown in Fig. 2, it is provided without according to the control device of this embodiment of the invention
The memory element that switch element switching is different.Four memory element are both connected to public clock bus SCL and data/address bus SDA
On.The utilization of this control device addresses and the mode of non-switch switching accesses different scanning encoding data.Owing to opening without using
Close unit, therefore can reduce circuit board size, the product cost avoiding switch element to cause and signal and reduce product cost
With improve display quality.
Fig. 4 illustrates in the liquid crystal indicator of first embodiment of the invention for producing the flow process of the control method of sequential
Figure.
In step S01, this control method starts.
In step S02, the selection end at time schedule controller 110 provides and selects signal, and producing address height when addressing has
Effect bit value, thus select the memory element of correspondence.
In step S03, time schedule controller 110 reads scanning encoding data from the memory element selected.
In step S04, it is judged that whether scanning encoding data read successfully.If reading unsuccessful, then go to step
S02, reselects memory element and reads scanning encoding data.If reading successfully, then go to step S05, this control method
Terminate.
Fig. 6 illustrates in the liquid crystal indicator of second embodiment of the invention and controls the schematic of device for produce sequential
Block diagram.This control device is such as in the liquid crystal indicator shown in Fig. 1, for carrying to gate drivers and source electrode driver
For various clock signals.
This control device includes time schedule controller 110 and memory element 121.Memory element 121 can be such as that electricity can
EPROM (Electrically Erasable Programmable Read-Only Memory,
EEPROM).The capacity of memory element 121 for example, 256K memory space, is divided into four memory blocks by memory space.Storage sky
Between four memory blocks address with select signal mapping relations as shown in Figure 8, space map as shown in Fig. 9 a to 9d.First
Memory block is followed successively by 000000H-00F00FH, 100000H-10F00FH, 200000H-to the address realm of the 4th memory block
20F00FH, 300000H-30F00FH, respectively storage different length and/or the scanning encoding data of coded system, such as, 6
Just sweeping coded data, 6 counter sweep coded data, 8 just sweeping coded data and 8 counter sweep coded data.
Time schedule controller 110 includes that three select end SEL0 to SEL2, and clock end SCL and data terminal SDA.At three
Select end SEL0 to SEL2, receive three and select signal.Three binary numerals selecting end SEL0 to SEL2 to produce are
000, one of 001,010 and 011.For brevity, the most not shown time schedule controller 110 and gate drivers and source electrode
The terminal that driver is connected.
Further, time schedule controller 110 produces address offset amount according to the binary numeral selecting signal to produce, thus
The different memory areas that signal will be selected to map to memory element 121.Such as, be respectively 000 at the binary numeral selecting signal,
001,010 and 011 time, address offset amount is respectively 000000H, 100000H, 200000H and 300000H.
Time schedule controller 110 is connected to memory element via I2C bus, such that it is able to read from four memory blocks respectively
Scanning encoding data.
In this embodiment, time schedule controller 110 is as main frame, and memory element is as from machine.Transmit at data/address bus SDA
Byte in, including slave addresses and reading of content, thus realize addressing.Selection end SEL0 according to time schedule controller 110 is extremely
The selection signal that SEL2 provides, can select one of four memory blocks, reads the scanning encoding data wherein stored.
In this control device, the address selecting end connected mode and four memory blocks of memory element of time schedule controller
Side-play amount is corresponding.The address offset amount of each memory block is different.The selection signal selecting end to provide at time schedule controller is used
Corresponding address offset amount is produced, such that it is able to select one of four memory blocks to read scanning encoding data when in addressing.
Different from the control device of the prior art shown in Fig. 2, it is provided without according to the control device of this embodiment of the invention
The memory element that switch element switching is different.Time schedule controller 110 and memory element 121 are connected to public clock bus SCL
With on data/address bus SDA.The utilization of this control device addresses and the mode of non-switch switching accesses different scanning encoding data.By
In without using switch element, therefore can reduce circuit board size, the product cost avoiding switch element to cause and signal and
Reduce product cost and improve display quality.
Fig. 7 illustrates in the liquid crystal indicator of second embodiment of the invention for producing the flow process of the control method of sequential
Figure.
In step S01, this control method starts.
In step S02, the selection end at time schedule controller 110 provides and selects signal, produces address offset when addressing
Amount, thus select the memory block of correspondence.
In step S03, time schedule controller 110 reads scanning encoding data from the memory block selected.
In step S04, it is judged that whether scanning encoding data read successfully.If reading unsuccessful, then go to step
S02, reselects memory block and reads scanning encoding data.If reading successfully, then going to step S05, this control method is tied
Bundle.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, the most not
Limit the specific embodiment that this invention is only described.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is to preferably explain the principle of the present invention and actual application, so that affiliated
Technical field technical staff can utilize the present invention and amendment on the basis of the present invention to use well.The present invention is only by right
Claim and four corner thereof and the restriction of equivalent.
Claims (10)
1. for a control device for liquid crystal indicator, including:
Time schedule controller, is used for providing clock signal；And
At least one memory element, for storing the scanning encoding data of different scanning pattern,
Wherein, described time schedule controller is according to selecting signal acquisition access unit address, thus according to access unit address
Read the scanning encoding data of different scanning pattern.
Control device the most according to claim 1, wherein, described time schedule controller includes multiple selection end, the plurality of
End is selected to receive multiple selection signal respectively.
Control device the most according to claim 2, wherein, at least one memory element described includes multiple memory element,
The plurality of memory element stores the scanning encoding data of different scanning pattern respectively, and the plurality of memory element includes many respectively
Individual address end, the plurality of address end connects into corresponding with the numerical value of preset address high significance bit.
Control device the most according to claim 3, wherein, when reading the scanning encoding data of different scanning pattern, institute
The level stating multiple selection signal is corresponding with the numerical value of described preset address high significance bit.
Control device the most according to claim 2, wherein, at least one memory element described includes single memory element,
Multiple memory blocks of described single memory element store the scanning encoding data of different scanning pattern respectively.
Control device the most according to claim 5, wherein, when reading the scanning encoding data of different scanning pattern, institute
The level stating multiple selection signal is corresponding with the address offset amount of the plurality of memory block.
7. for a control method for liquid crystal indicator, including:
According to selecting signal acquisition access unit address；And
The scanning encoding data of different scanning pattern are read according to access unit address.
Control method the most according to claim 7, also includes:
Multiple addresses end of multiple memory element is connected into corresponding with the numerical value of preset address high significance bit.
Control method the most according to claim 7, wherein, includes according to selecting signal acquisition access unit address:
Multiple selection ends at time schedule controller receive multiple selection signals, the level of the plurality of selection signal and preset address
The numerical value of high significance bit is corresponding.
Control method the most according to claim 7, wherein, includes according to selecting signal acquisition access unit address:
Multiple selection ends at time schedule controller receive multiple selection signals, the level of the plurality of selection signal and multiple storages
The address offset amount in district is corresponding.
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| CN201610656340.9A CN106098004A (en) | 2016-08-11 | 2016-08-11 | Control device and control method for liquid crystal indicator |
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| CN106057165A (en) * | 2016-08-12 | 2016-10-26 | 昆山龙腾光电有限公司 | Control device used for liquid crystal display apparatus and control method thereof |
| CN106782409A (en) * | 2017-02-16 | 2017-05-31 | 昆山龙腾光电有限公司 | For the control device and control method of liquid crystal display device |
| CN107146587A (en) * | 2017-06-21 | 2017-09-08 | 昆山龙腾光电有限公司 | Source electrode drive circuit and display panel |
| CN110491332A (en) * | 2019-09-30 | 2019-11-22 | 京东方科技集团股份有限公司 | Driver, display device and its application method |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: Kunshan Longteng Optronics Co., Ltd. |
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Application publication date: 20161109 |