CN1447247A - Method for controlling access of display memory and device of controlling displays - Google Patents
Method for controlling access of display memory and device of controlling displays Download PDFInfo
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- CN1447247A CN1447247A CN 03114168 CN03114168A CN1447247A CN 1447247 A CN1447247 A CN 1447247A CN 03114168 CN03114168 CN 03114168 CN 03114168 A CN03114168 A CN 03114168A CN 1447247 A CN1447247 A CN 1447247A
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Abstract
This invention discloses a control method for accessing display memory; a microprocessor utilizes the address signal generated by a cursor address controller to read/write on the address display controller to read on the display memory, when the micropressor accesses it, the refresh circuit is forbidden to read on it. Further more, a TDMA controller is multiplexed to a cursor address controller when the micropressor accesses the display memory, the said TDMA controller is multiplexed to an address display controller when the refresh circuit accesses the display memory.
Description
Technical field
The present invention relates to display control technology, particularly a kind of control method and display control apparatus of visiting display-memory.
Background technology
During exploitation liquid crystal display (being called for short LCD) controller, generally all adopt special-purpose LCD controller chip.The structured flowchart of single purpose LCD controller as shown in Figure 1 (is example with the sed1335 chip).Cursor address controller and microprocessor are the interface section of microprocessor (CPU) visit video memory, and refresh circuit and LCD address control unit are the refresh control part.As can be seen from the figure, the two parts in the empty frame are independent mutually.If refresh circuit is just from video memory reading of data clear screen, and this moment, CPU attempted to visit video memory, will cause bus collision, the reason of lcd screen flicker when this reads and writes video memory just.
In a word,, cost an arm and a leg though this chip functions of lcd controller chip that prior art is used is powerful, the initialization procedure more complicated, redundancy feature is more, and speed is slower, thereby has reduced the reliability of system; And there is the bus noise in the lcd controller of prior art, causes that flicker appears in lcd screen when the read-write video memory; Cursor address controller and LCD address control unit are independent mutually, have taken more hardware resource (register).
Summary of the invention
The object of the present invention is to provide a kind of control method and display control apparatus of visiting display-memory, to eliminate this access conflict to display-memory; Further, simplify the structure of controller, reduce cost.
Technical scheme of the present invention:
A kind of control method of visiting display-memory comprises step: the address signal that microprocessor utilizes the cursor address controller to produce carries out read/write operation to display-memory; And the address signal that refresh circuit utilizes the explicit address controller to produce carries out read operation to display-memory; It is characterized in that: forbid that when the microprocessor access display-memory refresh circuit carries out read operation to display-memory.
According to said method:
Be multiplexed with the cursor address controller when the microprocessor access display-memory by a time division multiplex address control unit, this time division multiplex address control unit is multiplexed with the explicit address controller when refresh circuit visit display-memory.
When carrying out refresh operation in the end of microprocessor access display-memory, refresh circuit and time division multiplex address control unit at first carry out reset operation.
During the microprocessor access display-memory, stop the refresh signal of forbidding of refresh operation according to the control signal generation of microprocessor output.
The bus of Microprocessor Interface and refresh circuit is isolated.
A kind of display control apparatus, comprise: the video memory interface that is used to connect display-memory, with this video memory interface microprocessor linked interface, cursor address controller, refresh circuit and explicit address controller, it is characterized in that also comprising the time schedule controller that is connected with refresh circuit with described Microprocessor Interface, be used for forbidding or allowing described refresh circuit visit display-memory according to the control signal of Microprocessor Interface.
A kind of display control apparatus, comprise: the video memory interface that is used to connect display-memory, with this video memory interface microprocessor linked interface and refresh circuit, microprocessor conducts interviews to display-memory by described Microprocessor Interface and video memory interface, and refresh circuit passes through the video memory interface from display-memory reading of data refresh display; It is characterized in that also comprising:
Time schedule controller is connected with refresh circuit with described Microprocessor Interface, is used for forbidding or allowing described refresh circuit visit display-memory according to the control signal of Microprocessor Interface;
The time division multiplex address control unit, be connected with refresh circuit with described video memory interface, Microprocessor Interface, time schedule controller, when the microprocessor access display-memory, this time division multiplex address control unit is multiplexed with the cursor address controller under the control of time schedule controller, when brush circuit visit display-memory, under refresh circuit and time schedule controller control, be multiplexed with the display address control unit.
The present invention stops to refresh when the microprocessor access display memory, and the competition conflict when having avoided the visit video memory on data line and the address wire has solved the screen flicker problem that therefore causes; Cursor address and explicit address are taked time-sharing multiplex, and can realize by programmable logic device (PLD), also do not need peripheral circuit, thereby make DLL (dynamic link library) very simple, speed is very fast, has also reduced cost simultaneously; The bus of refresh circuit and Microprocessor Interface is taked quarantine measures, eliminated the bus interference fully, can improve display quality significantly.
Description of drawings
Fig. 1 is the display controller structural drawing of prior art;
Fig. 2 is the display controller circuit theory synoptic diagram of the embodiment of the invention 1;
Fig. 3 is the display controller circuit theory synoptic diagram of the embodiment of the invention 2;
Fig. 4, Fig. 5 are the main process flow diagram of the display controller work of embodiment 2.
Embodiment
Embodiment 1
Consult Fig. 2, illustrated display controller is to have increased time schedule controller and bus controller on the basis of existing technology, time schedule controller is connected with low byte signal wire A0 by the high byte A1 of chip selection signal line CS, cursor address, the output of time schedule controller is connected with the explicit address controller with refresh circuit, bus controller, cursor location controller respectively, and the control line of Microprocessor Interface and refresh circuit is connected with the video memory interface through bus controller with data line.
When the microprocessor access display-memory, time schedule controller is judged according to the combination of the high low byte signal of chip selection signal CS/ and address A1A0, with the high byte arrival (Addr_high_come) that produces the address, low byte arrival (Addr_low_come), data arrivals (data_come) and the CPU visit control signals such as (CPU_vist) of address.Such as when chip selection signal CS=" 0 ", if address signal A1A0=" 01 " expression CPU is sending low address, address signal A1A0=" 10 " expression CPU is sending high address, represents during address signal A1A0=" 00 " that CPU is sending video data.Control signal CON1 is the CPU interrogation signal, is used to forbid or starts refresh, and when the CPU interrogation signal was " 1 ", expression CPU was visiting video memory, forbids refresh circuit visit video memory, stops refresh operation.It is " 0 " that visit finishes back CPU interrogation signal, allows refresh circuit visit video memory, starts refresh operation.Signal CON2 is data arrival (data_come) signal, is used to notify bus controller to switch bus, and when this signal was " 1 ", the data that expression CPU sends had arrived, and connect video memory data line and cpu data line, otherwise the connection refresh circuit is counted line.Signal CON3 produces according to the high and low byte signal of CPU interrogation signal and address, when the CPU interrogation signal is " 1 ", the cursor address controller is effective, when address low byte signal (Addr_low_come) is " 1 ", read low byte address from CPU, when address high byte signal (Addr_high_come) is " 1 ", read high byte address, and splicing 16 bit address pass out to the video memory address wire from CPU.When the CPU interrogation signal was " 0 ", the explicit address controller was effective, and the refresh address in clock signal clk of the every output of refresh circuit, explicit address controller adds 1.
From on can find out, time schedule controller is according to the high byte A1 and low byte signal wire A0 generation stopping the to brush signal of chip selection signal line CS, cursor address, this signal makes refresh circuit stop refresh operation, only by the cursor address controller display-memory is carried out data read/write operation, avoided refresh circuit and microprocessor to visit display-memory simultaneously and the bus collision that causes by microprocessor.After the microprocessor access display-memory finished, time schedule controller was no longer exported and is stopped to brush signal, allowed refresh circuit to carry out refresh operation under clock control.
Bus controller is mainly used in when brush circuit visit display-memory isolates microprocessor control signal and bus signals, if the Signal Spacing measure is externally arranged, promptly Microprocessor Interface does not have input signal during microprocessor is not visited display-memory, can the corresponding signal line be directly connected to the video memory interface without bus controller.
In the present embodiment, time schedule controller can only be used chip selection signal CS, judges high address or low address or data according to the number of times of chip selection signal CS saltus step, to produce control signal corresponding.
Embodiment 2
Consult shown in Figure 3ly, display controller also comprises time division multiplex address control unit, time schedule controller and bus controller except comprising video memory interface, Microprocessor Interface, refresh circuit.The time division multiplex address control unit is connected with Microprocessor Interface by data line D0-D7, and its address output is connected with the video memory interface, and the time division multiplex address control unit also is connected with refresh circuit by control line; Time schedule controller is connected with low byte signal wire A0 with the chip selection signal line of Microprocessor Interface, the high byte A1 of cursor address, and the output signal line of time schedule controller is connected with time division multiplex address control unit, bus controller and refresh circuit respectively; The control line of Microprocessor Interface and refresh circuit is connected with the video memory interface through bus controller with data line.
The generation of control signal CON1, CON2 and CON3 is consulted described in the embodiment 1.When microprocessor (CPU) visit video memory, time schedule controller provides control signal CON1, and this control signal is forbidden refresh circuit visit display-memory, refreshes with time-out; Simultaneously, provide control signal CON3, because CPU interrogation signal this moment (cpu_vist) is " 1 ", the time division multiplex address control unit is multiplexed with the cursor address controller, when address low byte signal (Addr_low_come) is " 1 ", read low byte address, when being " 1 " in address high byte signal (Addr_high_come) from CPU, read high byte address, and the address VA0-VA15 that is spliced into 16 bit widths delivers to the video memory address wire from CPU; Bus controller is kept apart data line, sheet choosing and read signal and the video memory of refresh circuit according to control signal CON2, and with data line, the chip selection signal of microprocessor, read/write signal and video memory are connected, thereby data are write or read video memory.After the microprocessor access video memory finished, CPU interrogation signal (CPU-vist) was " 0 ", and control signal CON3 makes the time division multiplex address control unit be multiplexed with the explicit address controller, and control signal CON1 notice refresh circuit refreshes again; Control signal CON2 notice bus controller cuts off getting in touch of signal such as the data line of CPU and video memory, and the getting in touch of connection refresh circuit data line signal and video memory.Refresh address in clock signal clk of the every output of refresh circuit, time division multiplex address control unit adds 1.It is the programmable logic device (PLD) realization of XC9572 that the time division multiplex address control unit can adopt model.Share hardware resource by explicit address controller and the timesharing of cursor address controller, effectively prevented the competition conflict on the video memory address wire, also saved the internal register of programmable logic device (PLD) (cpld) simultaneously, reduced cost significantly.
Bus controller is mainly used in when brush circuit visit display-memory isolates microprocessor control signal and bus signals, if the Signal Spacing measure is externally arranged, promptly Microprocessor Interface does not have input signal during microprocessor is not visited display-memory, can the corresponding signal line be directly connected to the video memory interface without bus controller.
Consult shown in Figure 4ly, the general algorithm of time division multiplex address control unit is: judge whether microprocessor visits display-memory; If then refresh circuit stops to refresh, and cursor address is sent into the time division multiplex address control unit; Otherwise the permission refresh operation, the time division multiplex address control unit increases explicit address automatically according to the brush clock.
But algorithm shown in Figure 4 has defective.Suppose that refresh circuit refreshes, the value of address register is 0x100 (display address) in moment T1 time division multiplex address control unit, so when refresh clock arrives, will according to the data (color value) at video memory 0x100 address place indicator screen (x1 y1) locates the point of respective color that draws.If microprocessor (CPU) attempts to visit the 0x104 address of video memory at this moment, according to flow process shown in Figure 3, after CPU finished visit to display-memory, the value of address register was 0x104 in the time division multiplex address control unit.So when refresh clock arrives, the data at place, video memory 0x104 address will be given display, promptly at (x1, y1) locate the point of respective color that draws, and in fact, the data at 0x104 place, video memory address should appear at display (x1+4 y1) locates (to suppose the width of x1+4 less than screen, lcd is 256 looks), therefore certainly will cause expendable demonstration dislocation.
Consult shown in Figure 5, if certain video memory of CPU visit constantly then is provided with zone bit flag=1; During the refresh circuit refresh display, if be checked through flag=1, just the value of knowing address (Addr) register in the current time division multiplex address control unit may lead to errors, therefore earlier the value of this address register is composed 0, relevant register in the replacement refresh circuit, promptly carry out reset operation, so that from (0 of indicator screen, 0) the coordinate place restarts to refresh, promptly from display screen (0,0) the video memory address of coordinate position correspondence begins sense data, has so just solved the screen display problem of misalignment.
Time schedule controller and bus controller can be integrated in the present embodiment, also can adopt the following programmable logic device (PLD) of 72 macroelements to realize display controller.
Claims (12)
1, a kind of control method of visiting display-memory comprises step: the address signal that microprocessor utilizes the cursor address controller to produce carries out read/write operation to display-memory; And the address signal that refresh circuit utilizes the explicit address controller to produce carries out read operation to display-memory; It is characterized in that: forbid that when the microprocessor access display-memory refresh circuit carries out read operation to display-memory.
2, the control method of visit display-memory as claimed in claim 1, it is characterized in that, be multiplexed with the cursor address controller when the microprocessor access display-memory by a time division multiplex address control unit, this time division multiplex address control unit is multiplexed with the explicit address controller when refresh circuit visit display-memory.
3, the control method of visit display-memory as claimed in claim 2 is characterized in that, when carrying out refresh operation in the end of microprocessor access display-memory, refresh circuit and time division multiplex address control unit at first carry out reset operation.
As the control method of claim 1,2 or 3 described visit display-memories, it is characterized in that 4, during the microprocessor access display-memory, the control signal of exporting according to microprocessor stops refresh operation.
5, the control method of visit display-memory as claimed in claim 4 is characterized in that, described control signal comprises chip selection signal, reaches high byte address indicator signal and low byte address indicator signal.
6, the control method of visit display-memory as claimed in claim 2 is characterized in that, the bus of Microprocessor Interface and refresh circuit is isolated.
7, a kind of display control apparatus, comprise: the video memory interface that is used to connect display-memory, with this video memory interface microprocessor linked interface, cursor address controller, refresh circuit and explicit address controller, it is characterized in that also comprising the time schedule controller that is connected with refresh circuit with described Microprocessor Interface, be used for forbidding or allowing described refresh circuit visit display-memory according to the control signal of Microprocessor Interface.
8, display control apparatus as claimed in claim 7, it is characterized in that also comprising bus controller, described Microprocessor Interface is connected with described video memory interface by this bus controller with refresh circuit, and this bus controller selects Microprocessor Interface or refresh circuit to be communicated with described video memory interface according to the control signal of time schedule controller output.
As claim 7 or 8 described display control apparatus, it is characterized in that 9, described time schedule controller is connected with the chip selection signal line of described Microprocessor Interface, perhaps be connected with address signal line with the chip selection signal line of described Microprocessor Interface respectively.
10, a kind of display control apparatus, comprise: the video memory interface that is used to connect display-memory, with this video memory interface microprocessor linked interface and refresh circuit, microprocessor conducts interviews to display-memory by described Microprocessor Interface and video memory interface, and refresh circuit passes through the video memory interface from display-memory reading of data refresh display; It is characterized in that also comprising:
Time schedule controller is connected with refresh circuit with described Microprocessor Interface, is used for forbidding or allowing described refresh circuit visit display-memory according to the control signal of Microprocessor Interface;
The time division multiplex address control unit, be connected with refresh circuit with described video memory interface, Microprocessor Interface, time schedule controller, when the microprocessor access display-memory, this time division multiplex address control unit is multiplexed with the cursor address controller under the control of time schedule controller, when brush circuit visit display-memory, under refresh circuit and time schedule controller control, be multiplexed with the display address control unit.
11, display control apparatus as claimed in claim 10, it is characterized in that also comprising bus controller, described Microprocessor Interface is connected with described video memory interface by this bus controller with refresh circuit, and this bus controller selects Microprocessor Interface or refresh circuit to be communicated with described video memory interface according to the control signal of time schedule controller output.
As claim 10 or 11 described display control apparatus, it is characterized in that 12, described time schedule controller is connected with the chip selection signal line of described Microprocessor Interface, perhaps be connected with address signal line with the chip selection signal line of described Microprocessor Interface respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03114168 CN1211742C (en) | 2003-04-09 | 2003-04-09 | Method for controlling access of display memory and device of controlling displays |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03114168 CN1211742C (en) | 2003-04-09 | 2003-04-09 | Method for controlling access of display memory and device of controlling displays |
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| CN1447247A true CN1447247A (en) | 2003-10-08 |
| CN1211742C CN1211742C (en) | 2005-07-20 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100382140C (en) * | 2003-12-26 | 2008-04-16 | 株式会社日立制作所 | Display apparatus |
| CN101127208B (en) * | 2007-08-15 | 2010-05-19 | 西安龙腾微电子科技发展有限公司 | Asynchronous pseudo-double port image memory access conflict processing method |
| CN106098004A (en) * | 2016-08-11 | 2016-11-09 | 昆山龙腾光电有限公司 | Control device and control method for liquid crystal indicator |
| CN108776597A (en) * | 2018-06-19 | 2018-11-09 | 深圳繁易电气有限公司 | A method of the anti-flicker of screen being applied in man-machine interface start-up course |
| CN113052749A (en) * | 2021-03-02 | 2021-06-29 | 长沙景嘉微电子股份有限公司 | Video display method and graphics processor |
-
2003
- 2003-04-09 CN CN 03114168 patent/CN1211742C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100382140C (en) * | 2003-12-26 | 2008-04-16 | 株式会社日立制作所 | Display apparatus |
| CN101127208B (en) * | 2007-08-15 | 2010-05-19 | 西安龙腾微电子科技发展有限公司 | Asynchronous pseudo-double port image memory access conflict processing method |
| CN106098004A (en) * | 2016-08-11 | 2016-11-09 | 昆山龙腾光电有限公司 | Control device and control method for liquid crystal indicator |
| CN108776597A (en) * | 2018-06-19 | 2018-11-09 | 深圳繁易电气有限公司 | A method of the anti-flicker of screen being applied in man-machine interface start-up course |
| CN113052749A (en) * | 2021-03-02 | 2021-06-29 | 长沙景嘉微电子股份有限公司 | Video display method and graphics processor |
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| Publication number | Publication date |
|---|---|
| CN1211742C (en) | 2005-07-20 |
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Address after: 518057 Nanshan District science and Technology Industrial Park, Guangdong, Shenzhen Branch Road, No. Patentee after: VERTIV TECH Co.,Ltd. Address before: 518057 Nanshan District science and Technology Industrial Park, Guangdong, Shenzhen Branch Road, No. Patentee before: EMERSON NETWORK POWER Co.,Ltd. |
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Effective date of registration: 20201209 Address after: Room 1513-1514, 2 / F, Kechuang City, 17 Huaguoshan Avenue, hi tech Industrial Development Zone, Lianyungang City, Jiangsu Province 222000 Patentee after: Jiangsu Dafa Environmental Protection Technology Co.,Ltd. Address before: 518057 No. 1, FA Lu, Nanshan District science and Technology Industrial Park, Guangdong, Shenzhen Patentee before: Vertiv Tech Co.,Ltd. |
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Granted publication date: 20050720 |