CN113052749A - Video display method and graphics processor - Google Patents
Video display method and graphics processor Download PDFInfo
- Publication number
- CN113052749A CN113052749A CN202110229027.8A CN202110229027A CN113052749A CN 113052749 A CN113052749 A CN 113052749A CN 202110229027 A CN202110229027 A CN 202110229027A CN 113052749 A CN113052749 A CN 113052749A
- Authority
- CN
- China
- Prior art keywords
- display
- video data
- address
- decoded video
- frame memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1407—General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T9/00—Image coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The embodiment of the application provides a video display method and a graphic processor, wherein the method comprises the following steps: acquiring decoded video data, and storing the decoded video data in a frame memory of a graphic processor; inquiring a register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
Description
Technical Field
The present application relates to the field of computer graphics processing technologies, and in particular, to a video display method and a graphics processor.
Background
The basic function of the graphics processor is to decode and display video data, after the GPU decodes the video data, each decoded frame data may be copied to a frame memory area of a screen display, and the data in the frame memory area is displayed when the screen is refreshed, so that a video may be displayed on the screen.
Because the refresh rate of the screen is fixed and the time for copying data is uncertain, if the copying process happens at the time point when the screen refresh frame is not completed, when the screen picture is displayed to half, the second half of the picture content can be covered by new data, thereby causing the tearing phenomenon of the video picture.
Disclosure of Invention
The embodiment of the application provides a video display method and a graphics processor, which can effectively solve the problem of tearing of video pictures.
According to a first aspect of embodiments of the present application, there is provided a video display method, including: acquiring decoded video data, and storing the decoded video data in a frame memory of a graphic processor; inquiring a register to determine the validity of a display address, wherein the display address is an address corresponding to a display frame memory area for screen display; and copying the decoded video data to a display frame memory area for display according to the validity of the display address.
According to a second aspect of embodiments of the present application, there is provided a graphics processor, the graphics processor comprising a hardware decoding module, a double rate synchronous dynamic random access memory, and a display module; the hardware decoding module is used for acquiring decoded video data and storing the decoded video data in the double-rate synchronous dynamic random access memory; the display module is used for inquiring the register to determine the validity of a display address, and the display address is an address corresponding to a display frame storage area for screen display; and the display module is also used for copying the decoded video data to a display frame memory area for display according to the validity of the display address.
According to a third aspect of embodiments of the present application, there is provided a video display apparatus including: the acquisition module is used for acquiring decoded video data and storing the decoded video data in a frame memory of the graphics processor; the determining module is used for inquiring the register to determine the validity of a display address, wherein the display address is an address corresponding to a display frame storage area used for screen display; and the copying module is used for copying the decoded video data to a display frame memory area for display according to the validity of the display address.
According to a fourth aspect of embodiments herein, there is provided an electronic device comprising one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method as applied to an electronic device, as described above.
According to a fifth aspect of the embodiments of the present application, there is provided a computer-readable storage medium having a program code stored therein, wherein the method described above is performed when the program code runs.
The video display method provided by the embodiment of the application is adopted to obtain the decoded video data and store the decoded video data in the frame memory of the graphic processor; inquiring a register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a block diagram of a graphics processor according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a video display method according to an embodiment of the present application;
FIG. 3 is a flow chart of a video display method according to another embodiment of the present application;
FIG. 4 is a flow chart of a video display method according to yet another embodiment of the present application;
FIG. 5 is a functional block diagram of a video display apparatus according to an embodiment of the present application;
fig. 6 is a block diagram of an electronic device for executing a video display method according to an embodiment of the present application.
Detailed Description
The basic function of a Graphics Processing Unit (GPU) is to decode and display video data, and after the GPU decodes the video data, each decoded frame of data may be copied to a frame memory area for screen display, and when a screen is refreshed, the data in the frame memory area is displayed, so that a video may be displayed on the screen.
Because the refresh rate of the screen is fixed and the time for copying data is uncertain, if the copying process happens at the time point when the screen refresh frame is not completed, when the screen picture is displayed to half, the second half of the picture content can be covered by new data, thereby causing the tearing phenomenon of the video picture.
The inventor finds in research that after the GPU decodes the video data, the decoded video data is stored in the GPU frame memory, and the data in the GPU frame memory can be copied to the frame memory area for display.
Therefore, the embodiment of the present application provides a video display method, which obtains decoded video data and stores the decoded video data in a GPU frame memory; inquiring a register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Referring to fig. 1, a graphics processor according to an embodiment of the present application is shown. A Graphics Processing Unit (GPU) 10 includes a hardware decoding module 11, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM)12, and a display module 13.
The hardware decoding module 12 is configured to decode video data, and store the decoded video data in a frame buffer, that is, in the DDR SDRAM 12.
The display module 13 is configured to query the register to determine validity of a display address, where the display address is an address corresponding to a display frame storage area for screen display; and copying the decoded video data to a display frame memory area for display according to the validity of the display address.
Referring to fig. 2, an embodiment of the present application provides a video display method, which may specifically include the following steps.
The basic function of the graphics processor is video decoding display, that is, the GPU has a function of decoding video data and copying the decoded video data to a display frame memory for display.
Generally, the GPU may include a hardware decoding module and a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The GPU may decode the video data through a hardware decoding module to obtain decoded video data. When the decoded video data is obtained, the GPU may store the decoded video data into a GPU frame memory, i.e., a DDR SDRAM in the GPU, for subsequent use.
In some embodiments, the video data may also be decoded by other means, for example, software decoding, and the GPU may obtain the decoded video data and store the decoded video data in the DDR SDRAM.
And 120, inquiring a register to determine the validity of a display address, wherein the display address is an address corresponding to a display frame memory area for screen display.
Generally, after the decoded video data is stored in the GPU frame memory, the decoded video data in the GPU frame memory may be copied to a display frame memory, and displayed on a screen when the screen is refreshed. Specifically, the decoded video data may be copied to a display frame memory and output to a display screen through an interface for display.
The display address and the validity of the display address may be set into a register before copying the decoded video data. The two registers may be a first register and a second register, respectively, the display address may be set to the first register, the second register is a display address valid attribute, the output module determines the display address valid attribute according to the display device and the refresh rate, and if the display address valid attribute is valid, the value of the second register is updated. As an embodiment, when the display address is valid, the value of the second register may be updated to 1; the value of the second register may be updated to 0 when the display address is invalid.
In some embodiments, the validity of the display address may be determined by querying a register at a predetermined interval. The time interval may be acquired, when the time interval satisfies the preset interval, the register is queried to determine the validity of the display address, and when the time interval does not satisfy the preset interval, the decoded video data may be directly copied to the display frame memory area. The preset interval may be set according to actual needs, and is not specifically limited herein.
The display address is an address corresponding to a display frame memory area for screen display, and when the screen is refreshed in the display frame memory area, the data in the display frame memory area can be displayed on the screen. Therefore, after the decoded video data is stored in the GPU frame memory, the register can be inquired to determine the validity of the display address, and the subsequent steps are carried out according to the inquired validity of the display address.
And step 130, copying the decoded video data to a display frame memory area for display according to the validity of the display address.
After determining the validity of the display address, the decoded video data may be copied to a display frame storage area indicated by the display address for display according to the validity of the display address.
The validity of the display address may or may not be valid. When the validity of the display address is determined to be valid, the decoded video data may be directly copied to a display frame memory area.
And when the validity of the display address is determined to be invalid, carrying out short dormancy for a preset time, inquiring the register again to determine the validity of the display address, and copying the decoded video data to a display frame storage area for display until the validity of the display address is determined to be valid.
When the decoded video data is copied to a display frame Memory region for display, the decoded video data may be copied to the display frame Memory region from a frame Memory of the graphics processor in a Direct Memory Access (DMA) manner. The DMA hardware has high copying speed, can ensure that the decoded video data is copied to a display frame memory area for display in time, and ensures the integrity of the picture.
The video display method provided by the embodiment of the application acquires decoded video data and stores the decoded video data in a frame memory of a graphic processor; inquiring a register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, and copying the data when the display address is valid, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
Referring to fig. 3, another embodiment of the present application provides a video display method, which focuses on the process of querying a register at preset intervals on the basis of the foregoing embodiment, and specifically, the method may include the following steps.
After the GPU decodes the video data, the decoded video data may be obtained. The GPU may obtain a time interval from the decoded video data. Specifically, the number of frames of the decoded video data may be counted to determine the time interval.
A time interval may be obtained by counting the number of frames of the decoded video data, and when the time interval satisfies a preset interval, step 240 may be performed. When the time interval does not satisfy the preset interval, step 260 may be performed.
Assuming that the preset interval is 60 frames, when the GPU starts decoding the video data, the frame number of the decoded video data may be acquired as the time interval, and when the frame number of the decoded video data is 60 frames, it indicates that the time interval satisfies the preset interval. At this time, the acquisition of the frame number of the decoded video data is restarted, that is, after 60 frames of video data are decoded, step 240 is executed, and the frame number of the decoded video data is recalculated from 0.
If the number of frames of the acquired decoded video data is 20, it indicates that the time interval does not satisfy the preset interval, so step 260 may be performed.
In some embodiments, a timer may be preset, the timer may output a signal once at a preset interval, and whether the preset interval is satisfied may be determined according to the signal output by the timer. The GPU may consider the time interval to satisfy the preset interval upon receiving the timer output signal.
The preset interval may be set according to actual needs, and is not specifically limited herein.
And step 250, copying the decoded video data to a display frame memory area for display according to the validity of the display address.
When it is determined that the time interval meets the preset interval, steps 240 to 250 may be performed, validity of the display address is determined by querying the register, and the decoded video data is copied to the display frame memory area for display according to the validity of the display address. The rest of steps 240 to 250 can refer to the corresponding parts of the previous embodiments, and are not described herein again.
And when the time interval is determined not to meet the preset interval, directly copying the decoded video data to a display frame memory area for display.
According to the video display method provided by the embodiment of the application, under the condition that the time interval meets the preset interval, the register is inquired to determine the validity of the display address, and the decoded video data is copied to the display frame memory area to be displayed according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
Referring to fig. 4, a video display method according to still another embodiment of the present application is mainly described in the foregoing embodiments, where the process of copying the decoded video data according to the validity of the display address may include the following steps.
Step 310 may refer to corresponding parts of the foregoing embodiments, and will not be described herein.
At step 320, the display address is stored in a first register.
After storing the decoded video data to the GPU frame memory, a frame memory address for screen display may be set to the register. Two registers can be set, wherein one register is set for upper software and is provided for hardware; and the other is used for writing back after the hardware state is changed and can be fed back to upper software, and the upper software is used for acquiring the effective attribute of the current address. Specifically, an address corresponding to a display frame memory area for screen display, that is, a display address, may be stored in the first register. The second register stores the validity of the display address, and may determine whether the display address is valid according to the output refresh rate and the characteristics of the display device, and update the determined validity of the display address to the value of the second register.
Because the validity of the display address is stored in the second register, the second register can be directly inquired, and the validity of the display address is determined according to a result returned by the second register.
In some embodiments, the result returned by the second register may be 0 or 1. If the returned result of the second register is 1, it indicates that the display address in the first register is being refreshed by the screen for display, so that it can be determined that the display address is valid. If the return result of the second register is 0, it indicates that the display timing is not reached, so that it can be determined that the display address is invalid.
And step 360, if the display address is determined to be valid, copying the decoded video data from the frame memory of the graphics processor to a display frame memory area for display.
When the display address is determined to be valid, the decoded video data may be copied to a display frame memory region from a frame memory of the graphics processor for display.
Specifically, the decoded video data may be copied to a display frame memory area indicated by the display address in the first register in a DMA frame memory copy manner, and displayed.
If the display address is determined to be invalid, if the decoded video data is copied to the display frame memory area at this time, the phenomenon of tearing of the video picture may occur. That is, at this time, a part of the video data of the previous frame is being displayed on the screen, and at this time, copying new video data to the display frame memory area will overwrite the video data of the previous frame, resulting in that a part of the screen is the video data of the previous frame, and another part is the currently copied video data.
Therefore, when the display address is determined to be invalid, the second register can be inquired again after waiting for a preset time, namely, the temporary sleep is performed, and if the display address is determined to be valid according to a result returned by the second register, the decoded video data can be copied to a display frame storage area for display. And if the display address is still determined to be invalid at the moment, continuously waiting for a preset time, and then inquiring the second register again. And circulating in this way, and copying the decoded video data to a display frame memory area for display until the display address is determined to be valid.
The preset time is usually in the order of microseconds, and may be 5us, for example, and the preset time may be adjusted according to actual needs, and is not specifically limited herein.
According to the video display method provided by the embodiment of the application, the display address is stored in the first register, and the validity of the display address is stored in the second register; querying a second register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
Referring to fig. 5, an embodiment of the present application provides a video display apparatus 400, where the video display apparatus 400 includes an obtaining module 410, a determining module 420, and a copying module 430. The obtaining module 410 is configured to obtain decoded video data and store the decoded video data in a frame memory of a graphics processor; the determining module 420 is configured to query a register to determine validity of a display address, where the display address is an address corresponding to a display frame storage area for screen display; the copy module 430 is configured to copy the decoded video data to a display frame storage area for display according to the validity of the display address.
Further, the video display apparatus 400 is further configured to obtain a time interval; determining whether the time interval satisfies a preset interval; if the time interval meets the preset interval, executing a query register to determine the validity of a display address until the decoded video data is copied to a display frame memory area for display; and if the time interval does not meet the preset interval, copying the decoded video data to a display frame memory area for display.
Further, the determining module 420 is further configured to store the display address in a first register; updating the validity of the display address into a second register; querying the second register; and determining the validity of the display address according to the result returned by the second register.
Further, the determining module 420 is further configured to determine that the display address is valid if the returned result of the second register is 1; and if the return result of the second register is 0, determining that the display address is invalid.
Further, the copy module 430 is further configured to copy the decoded video data from the frame memory of the graphics processor to a display frame memory area for display if it is determined that the display address is valid; and if the display address is determined to be invalid, waiting for a preset time, continuously querying the second register, and copying the decoded video data from a frame memory of the graphics processor to a display frame memory area for display until the display address is determined to be valid.
Further, the copy module 430 is further configured to copy the decoded video data from the frame memory of the graphics processor to the display frame memory area corresponding to the display address in the second register by means of direct memory access.
The video display device provided by the embodiment of the application acquires decoded video data and stores the decoded video data in a frame memory of a graphic processor; inquiring a register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
It should be noted that, as will be clear to those skilled in the art, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Referring to fig. 6, an embodiment of the present application provides a block diagram of an electronic device 500, where the electronic device 500 includes a processor 510, a memory 520, and one or more applications, where the one or more applications are stored in the memory 520 and configured to be executed by the one or more processors 510, and the one or more programs are configured to perform the above-mentioned video display method.
The electronic device 500 may be a terminal device such as a notebook computer or a personal computer capable of running an application program. The electronic device 500 in the present application may include one or more of the following components: a processor 510, a memory 520, and one or more applications, wherein the one or more applications may be stored in the memory 520 and configured to be executed by the one or more processors 510, the one or more programs configured to perform a method as described in the aforementioned method embodiments.
Processor 510 may include one or more processing cores. The processor 510 interfaces with various components throughout the electronic device 500 using various interfaces and circuitry to perform various functions of the electronic device 500 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 520 and invoking data stored in the memory 520. Alternatively, the processor 510 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 510 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 510, but may be implemented by a communication chip.
The Memory 520 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 520 may be used to store instructions, programs, code sets, or instruction sets. The memory 520 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The data storage area may also store data created during use by the electronic device 500 (e.g., phone books, audio-visual data, chat log data), and so forth.
The electronic device provided by the embodiment of the application acquires decoded video data and stores the decoded video data in a frame memory of a graphic processor; inquiring a register to determine the validity of the display address; and copying and displaying the decoded video data in a frame memory area for display according to the validity of the display address. And determining the time for copying the decoded video data according to the validity of the display address, so that the integrity of each frame of picture can be ensured when the screen is refreshed, and the picture is prevented from being torn.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method for video display, the method comprising:
acquiring decoded video data, and storing the decoded video data in a frame memory of a graphic processor;
inquiring a register to determine the validity of a display address, wherein the display address is an address corresponding to a display frame memory area for screen display;
and copying the decoded video data to a display frame memory area for display according to the validity of the display address.
2. The method of claim 1, further comprising:
acquiring a time interval;
determining whether the time interval satisfies a preset interval;
if the time interval meets the preset interval, executing a query register to determine the validity of a display address until the decoded video data is copied to a display frame memory area for display;
and if the time interval does not meet the preset interval, copying the decoded video data to a display frame memory area for display.
3. The method of claim 1, wherein the query register determines validity of the display address, comprising:
storing the display address in a first register;
updating the validity of the display address into a second register;
querying the second register;
and determining the validity of the display address according to the result returned by the second register.
4. The method of claim 3, wherein determining the validity of the display address according to the result returned by the second register comprises:
if the return result of the second register is 1, determining that the display address is valid;
and if the return result of the second register is 0, determining that the display address is invalid.
5. The method according to claim 3, wherein copying the decoded video data to a display frame memory area for display according to the validity of the display address comprises:
if the display address is determined to be valid, copying the decoded video data from a frame memory of the graphics processor to a display frame memory area for display;
and if the display address is determined to be invalid, waiting for a preset time, continuously querying the second register, and copying the decoded video data from a frame memory of the graphics processor to a display frame memory area for display until the display address is determined to be valid.
6. The method of claim 5, wherein copying the decoded video data from the frame memory of the graphics processor to a display frame memory area for display comprises:
and copying the decoded video data from a frame memory of the graphics processor to a display frame memory area corresponding to the display address in the second register in a direct memory access mode.
7. A graphics processor comprising a hardware decode module, a double-rate synchronous dynamic random access memory, and a display module;
the hardware decoding module is used for acquiring decoded video data and storing the decoded video data in the double-rate synchronous dynamic random access memory;
the display module is used for inquiring the register to determine the validity of a display address, and the display address is an address corresponding to a display frame storage area for screen display;
and the display module is also used for copying the decoded video data to a display frame memory area for display according to the validity of the display address.
8. A video display apparatus, characterized in that the apparatus comprises:
the acquisition module is used for acquiring decoded video data and storing the decoded video data in a frame memory of the graphics processor;
the determining module is used for inquiring the register to determine the validity of a display address, wherein the display address is an address corresponding to a display frame storage area used for screen display;
and the copying module is used for copying the decoded video data to a display frame memory area for display according to the validity of the display address.
9. An electronic device, characterized in that the electronic device comprises:
one or more processors;
a memory electrically connected with the one or more processors;
one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform the method of any of claims 1-6.
10. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110229027.8A CN113052749B (en) | 2021-03-02 | 2021-03-02 | Video display method and graphics processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110229027.8A CN113052749B (en) | 2021-03-02 | 2021-03-02 | Video display method and graphics processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113052749A true CN113052749A (en) | 2021-06-29 |
| CN113052749B CN113052749B (en) | 2023-04-07 |
Family
ID=76509516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110229027.8A Active CN113052749B (en) | 2021-03-02 | 2021-03-02 | Video display method and graphics processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113052749B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6440891A (en) * | 1987-08-06 | 1989-02-13 | Nec Corp | Display controller |
| CN1204821A (en) * | 1997-06-26 | 1999-01-13 | 日本电气株式会社 | Graphic processor and graphic processing method |
| JP2003099243A (en) * | 2001-09-21 | 2003-04-04 | Sharp Corp | Graphic display device and its control method |
| CN1447247A (en) * | 2003-04-09 | 2003-10-08 | 艾默生网络能源有限公司 | Method for controlling access of display memory and device of controlling displays |
| CN1816844A (en) * | 2003-04-30 | 2006-08-09 | 诺基亚有限公司 | Synchronization of image frame update |
| CN108476306A (en) * | 2016-12-30 | 2018-08-31 | 华为技术有限公司 | A kind of method that image is shown and terminal device |
| CN110148391A (en) * | 2019-03-29 | 2019-08-20 | 珠海亿智电子科技有限公司 | A kind of method and terminal device avoiding image display tearing |
| CN111107411A (en) * | 2019-12-30 | 2020-05-05 | 威创集团股份有限公司 | Distributed cross-node video synchronization method and system |
| US10672098B1 (en) * | 2018-04-05 | 2020-06-02 | Xilinx, Inc. | Synchronizing access to buffered data in a shared buffer |
| CN111866408A (en) * | 2020-07-30 | 2020-10-30 | 长沙景嘉微电子股份有限公司 | Graphic processing chip and video decoding display method |
-
2021
- 2021-03-02 CN CN202110229027.8A patent/CN113052749B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6440891A (en) * | 1987-08-06 | 1989-02-13 | Nec Corp | Display controller |
| CN1204821A (en) * | 1997-06-26 | 1999-01-13 | 日本电气株式会社 | Graphic processor and graphic processing method |
| JP2003099243A (en) * | 2001-09-21 | 2003-04-04 | Sharp Corp | Graphic display device and its control method |
| CN1447247A (en) * | 2003-04-09 | 2003-10-08 | 艾默生网络能源有限公司 | Method for controlling access of display memory and device of controlling displays |
| CN1816844A (en) * | 2003-04-30 | 2006-08-09 | 诺基亚有限公司 | Synchronization of image frame update |
| CN108476306A (en) * | 2016-12-30 | 2018-08-31 | 华为技术有限公司 | A kind of method that image is shown and terminal device |
| US10672098B1 (en) * | 2018-04-05 | 2020-06-02 | Xilinx, Inc. | Synchronizing access to buffered data in a shared buffer |
| CN110148391A (en) * | 2019-03-29 | 2019-08-20 | 珠海亿智电子科技有限公司 | A kind of method and terminal device avoiding image display tearing |
| CN111107411A (en) * | 2019-12-30 | 2020-05-05 | 威创集团股份有限公司 | Distributed cross-node video synchronization method and system |
| CN111866408A (en) * | 2020-07-30 | 2020-10-30 | 长沙景嘉微电子股份有限公司 | Graphic processing chip and video decoding display method |
Non-Patent Citations (2)
| Title |
|---|
| CHEN Y K: "Implementation of H.264encoder and decoder on personal computers" * |
| 叶丹敏;: "GPU解码数据快速拷贝的应用研究" * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113052749B (en) | 2023-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2019144743A1 (en) | Information display method and apparatus | |
| CN109194960B (en) | Image frame rendering method and device and electronic equipment | |
| CN108282686B (en) | Video picture processing method and device and electronic equipment | |
| CN111639289A (en) | Webpage loading method and device | |
| CN108566634B (en) | Method and device for reducing continuous awakening delay of Bluetooth sound box and Bluetooth sound box | |
| JP2019128939A (en) | Gesture based voice wakeup method, apparatus, arrangement and computer readable medium | |
| CN107818008B (en) | Page loading method and device | |
| WO2016155379A1 (en) | Method, device and system for dynamically acquiring app interface control data | |
| CN114051145B (en) | Video compression processing method, device and medium | |
| CN112199040B (en) | Storage access method and intelligent processing device | |
| CN107807934A (en) | Page display method and device and computing device | |
| CN106610828B (en) | Android system-based GIF animation playing method and device | |
| CN113052749B (en) | Video display method and graphics processor | |
| CN110413540B (en) | Method, system, equipment and storage medium for FPGA data caching | |
| CN116721007A (en) | Task control method, system and device, electronic equipment and storage medium | |
| CN116483737B (en) | Data processing method and device, electronic equipment and storage medium | |
| CN115878247A (en) | Front-end element adaptive display method, device, storage medium and system | |
| CN115458127A (en) | Medical picture display processing method and system | |
| CN114331808A (en) | Action posture storage method, device, medium and electronic equipment | |
| US20200387494A1 (en) | Detection of Layout Table(s) by a Screen Reader | |
| CN113066450B (en) | Image display method, device, electronic equipment and storage medium | |
| CN111143084B (en) | Interaction method, device, equipment and medium of service program and interface program | |
| CN113568550B (en) | Animation display method and device based on animation component and terminal equipment | |
| JP3482255B2 (en) | Image data processing apparatus and information system using the same | |
| CN111539183B (en) | Data processing method, device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |