KR880001930Y1 - Interface circuit controlling analog input - Google Patents
Interface circuit controlling analog input Download PDFInfo
- Publication number
- KR880001930Y1 KR880001930Y1 KR2019850010819U KR850010819U KR880001930Y1 KR 880001930 Y1 KR880001930 Y1 KR 880001930Y1 KR 2019850010819 U KR2019850010819 U KR 2019850010819U KR 850010819 U KR850010819 U KR 850010819U KR 880001930 Y1 KR880001930 Y1 KR 880001930Y1
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- circuit
- voltage
- amplifier
- interface circuit
- analog input
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
- Amplifiers (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 회로도이다.2 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 비반전증폭회로 2,6,7 : 전압활로우1: non-inverting amplifier circuit 2,6,7: voltage pull
3 : 전압제어회로 4,5 : 반전증폭회로3: voltage control circuit 4, 5: inversion amplifier circuit
8 : 궤환회로 OP1~OP6: OP엠프8: feedback circuit OP 1 to OP 6 : OP amplifier
본 고안은 OP앰프를 사용하여 전압제어회로의 출력을 피이드백 시킴으로써 에러를 보정함과 더불어 보다 정확한 비율로 전압레인지를 변환시킬수 있도록 된 아날로그제어 신호 인터페이스회로에 관한 것이다.The present invention relates to an analog control signal interface circuit capable of converting a voltage range at a more accurate rate by correcting an error by feeding back the output of the voltage control circuit using an OP amplifier.
현재 사용하고 있는 아날로그제어신호 인터페이스회로는 트랜지스터로 구성되어 있는데, 여기서 사용되어지는 트리지스터는 특성이 선형적(linear)으로 되어 있지 않기 때문에 정확한 전압변이를 할수가 없고, 또 아날로그제어신호는 제어직접회로에 따라 제어범위가 일정하게 정해져 나오도록 되어져 있다. 그러나, 실제로 제어받는 부위에서는 제어집적회로에서 송출되는 제어범위에 항상 맞아떨어지지 않았고, 이때문에 상호인터페이스할 수 있는 회로를 구성함에 있어서 종래에서 제1도와 같이 트랜지스터로 구성하였었다.The analog control signal interface circuits currently used are composed of transistors. The transistors used here are not linear because their characteristics are not linear, and analog control signals cannot be controlled directly. Depending on the circuit, the control range is fixed. However, the actual controlled part did not always fit the control range transmitted from the control integrated circuit, and therefore, in the circuit which can be interfaced with each other, the transistor was conventionally constructed as shown in FIG.
제1도의 회로는 트랜지스터(TR1)(TR2)를 이용하여 제어 범위를 변화시키는 것으로 일반적인 트랜지스터 특성이 비선형적이므로 정확한 비율로 변환되지 않는 단점이 있었다.The circuit of FIG. 1 has a disadvantage in that the control range is changed by using the transistors TR 1 (TR 2 ), and the general transistor characteristics are nonlinear, so that they are not converted to the correct ratio.
따라서 본 고안은 트랜지스터특성의 비선형적인 것을 배제한 OP엠프의 특성을 이용하므로서, 원하는 전압제어범위로 맞추어 주면서 출력전압을 입력전압과 비교하여 그 차이분을 피이드백시켜 에러를 보정하도록 되어 보다 정확하게 제어될수 있는 아날로그제어신호 인터페이스회로를 제공함에 그 목적이 있다.Therefore, the present invention utilizes the characteristics of the OP amplifier excluding the nonlinearity of the transistor characteristics, while adjusting the output voltage to the input voltage while feedbacking the difference between the input voltage and correcting the error. It is an object of the present invention to provide an analog control signal interface circuit.
이하 본 고안의 구성 및 적용, 효과를 예시도면에 의거 하여 상세히 설명하면 다음과 같다.Hereinafter, the configuration, application, and effects of the present invention will be described in detail with reference to the accompanying drawings.
본 고안은 직병렬로 연결된 저항(R10~R13)에 비반 전증폭회로(1)와 전압활로우(2)로 구성되는 전압제어회로(3), 2개의 반전증폭회로(4)(5)와 2개의 전압활로우(6)(7)로 구성되는 궤환회로(8)가 각각 연결되고, 상기 전압제어회로(3)와 상기 궤환회로(8)가 상호 연결된 구조로 되어 있다.The present invention is a voltage control circuit (3) consisting of a non-inverting amplification circuit (1) and a voltage swing (2) to a resistor (R 10 ~ R 13 ) connected in series and parallel, two inverting amplifier circuit (4) (5) ) And a feedback circuit (8) consisting of two voltage swings (6) and (7) are connected, and the voltage control circuit (3) and the feedback circuit (8) are connected to each other.
미설명부호 OP1~OP6는 OP앰프를 나타낸다.Reference numerals OP 1 to OP 6 represent OP amplifiers.
제2도는 상기한 구조로 되어 있는 본 고안의 회로도로서, 입력단으로는 항상 펄스폭변조(PWM)의 신호가 입력된다.2 is a circuit diagram of the present invention having the above-described structure, in which a signal of pulse width modulation (PWM) is always input to an input terminal.
이러한 신호는 저 과 콘덴서(C11)를 통해 직류로 되면서 B전압이 저항(R11)에 공급되고, 여기서 일반적인 의 최대출력전압(VA)이 5V로서 전압제어회로(3)에 있는 OP엠프(OP1)의 (+)단자에 공급되 앰프(OP1)(-)단자에 저항(R14)(R15)이 연결되므로 비반전증폭회로(1)의 출력신호가 호로서 송출하게 된다.This signal goes directly through the low capacitor (C 11 ) A voltage is supplied to a resistor (R 11), where the maximum output voltage (V A) of the general OP amplifier in the voltage control circuit 3 as a 5V are supplied to the positive terminal of the (OP 1), the amplifier (OP 1 Since the resistor (R 14 ) (R 15 ) is connected to the (-) terminal, the output signal of the non-inverting amplifier circuit 1 is sent out as a call.
비반전증폭회로(1)의 이득은이고, 예를 들어 O~5V의 제어레인지를 0~10V로 설정하고 싶을때는로 설정하면 된다.The gain of the non-inverting amplifier 1 For example, if you want to set the control range of 0 ~ 5V to 0 ~ 10V, Set to.
따라서, OP엠프(OP1)에서 송출된 전압은 전압할로우(2)의 OP앰프(OP2)의 (+)단자와 반전증폭회로(4)의 OP앰프 (OP3)의 (-)단자로 각각 공급되고, 번저 전압할로우(2)는 일종의 버퍼역활을 하여 비반전증폭회로(1)와 출력단을 격리시켜 주게 되며, 반전증폭회로(4)에서는 OP앰프(OP3)의 이득을 상기의 비를 역으로의 비로 된다.Thus, OP amplifier a voltage transmitted from the (OP 1) is of the voltage-hollow (2) OP amplifier (OP 2) of the (+) terminal and the inverting amplifier circuit (4) OP amplifier (OP 3) of the (-) to the terminal Each of them is supplied and the burner voltage hollow 2 acts as a buffer to isolate the non-inverting amplifier circuit 1 from the output stage. The inverting amplifier circuit 4 gains the gain of the OP amplifier OP 3 . Reverse the rain Becomes the ratio of.
즉 반전증폭회로(4)의 OP앰프(OP3)에서 출력되는 전압을로 되고, 한편으로 저항(R13)을 통한 직류로된 전단(OVA)이 전압활로우(6)를 통해 저항(R16)을 매개한 반전증폭회로(5)의 (-)단자로 공급되며, 이에 따라 OP앰프(OP4)의 (+)단자가 접지되면서 반전증폭회로(5)의 출력신호는 반전증폭회로(4)의 출력신호와 전압활로우(6)의 출력신호가 합해진 것으로 전압활로우(7)의 OP 앰프(OP5)의 (+)단자에 공급된다.That is, the voltage output from the OP amplifier OP 3 of the inversion amplifier circuit 4 On the other hand, the front end ( O V A ), which is a direct current through the resistor (R 13 ), is connected to the negative terminal of the inverted amplifier circuit (5) through the resistor (R 16 ) through the voltage swing (6). As a result, the positive terminal of the OP amplifier OP 4 is grounded, and the output signal of the inverted amplifier circuit 5 is combined with the output signal of the inverted amplifier circuit 4 and the output signal of the voltage swing 6. It is supplied to the positive terminal of the OP amplifier OP 5 of the voltage swing 7.
즉, 궤환회로(8)의 출력신호인 전압활로우(7)의 출력신호(VC)는 피이드백된 전위로서 저항(R14)에 입력되고, 피이드백된 전위(VC)는로 표시되며, 또한 전압 제어회로 (3)에 있는 비반전 증폭회로(1)의 출력신호 (Va)로 표시된다. 따라서, 비반전증폭회로(1)의 출력신호(VB)를 피이드백시킴으로써 에러를 보정하여 보다 정확한 비율로 전압레인지를 변화시킬수가 있게 되는 것이다.That is, the output signal V C of the voltage swing 7, which is the output signal of the feedback circuit 8, is input to the resistor R 14 as a fed back potential, and the fed back potential V C is And the output signal (V a ) of the non-inverting amplifier circuit (1) in the voltage control circuit (3). Is displayed. Therefore, the output signal (V B) of the non-inverting amplifier circuit (1) which will allow the sikilsu changing the voltage range in a more precise ratio by correcting the error by the back feedback.
그런데 만약 여기서 에러가 없다면 피이드백된 전위(VC)가 0이 되므로 OP앰프(OP3)의 출력전압(VB)은로 된다 .However, if there is no error here, the fed back potential V C becomes 0, so the output voltage VB of the OP amplifier OP 3 Becomes.
상기한 바와같이 본 고안은 OP앰프로서 아날로그제어신호 인터페이스회로를 구성한 것으로, 전압제어회로의 출력신호를 피이드백시킴으로써 그 에러를 보정하여 보다 정확한 비율로 전압레인지를 변화시킬 수 있는 아날로그 제어신호 인터페이스회로를 제공한 것이다.As described above, the present invention constitutes an analog control signal interface circuit as an OP amplifier. The analog control signal interface circuit can change the voltage range at a more accurate rate by correcting the error by feeding back the output signal of the voltage control circuit. Will be provided.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850010819U KR880001930Y1 (en) | 1985-08-24 | 1985-08-24 | Interface circuit controlling analog input |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850010819U KR880001930Y1 (en) | 1985-08-24 | 1985-08-24 | Interface circuit controlling analog input |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870004238U KR870004238U (en) | 1987-03-31 |
| KR880001930Y1 true KR880001930Y1 (en) | 1988-05-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850010819U KR880001930Y1 (en) | 1985-08-24 | 1985-08-24 | Interface circuit controlling analog input |
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| Country | Link |
|---|---|
| KR (1) | KR880001930Y1 (en) |
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1985
- 1985-08-24 KR KR2019850010819U patent/KR880001930Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR870004238U (en) | 1987-03-31 |
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