KR880001880Y1 - Color pattern generating circuit - Google Patents

Color pattern generating circuit Download PDF

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KR880001880Y1
KR880001880Y1 KR2019850003101U KR850003101U KR880001880Y1 KR 880001880 Y1 KR880001880 Y1 KR 880001880Y1 KR 2019850003101 U KR2019850003101 U KR 2019850003101U KR 850003101 U KR850003101 U KR 850003101U KR 880001880 Y1 KR880001880 Y1 KR 880001880Y1
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circuit
signal
color
color pattern
clock
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KR2019850003101U
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Korean (ko)
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KR860012560U (en
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이갑수
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삼성전자 주식회사
정재은
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H2231/00—Applications
    • H01H2231/036—Radio; TV

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음.No content.

Description

칼라 패턴 발생회로Color pattern generating circuit

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 본 고안 회로도의 각부 파형도.2 is a waveform diagram of each part of the present invention circuit diagram.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 클럭 발생회로 20 : 영상신호 발생회로10: clock generating circuit 20: video signal generating circuit

30 : 영상신호 절환회로 40 : 칼라 엔코더회로30: video signal switching circuit 40: color encoder circuit

1N : 인버터 N1: 낸드 게이트1N: Inverter N 1 : NAND Gate

1 : 클럭발생기 2 : 분주기1: Clock Generator 2: Divider

Q1,Q2,Q3: 트랜지스터 GC,RC,BC : 절환스위치Q 1 , Q 2 , Q 3 : Transistor GC, RC, BC: Switch

R1……R11: 저항R 1 . … R 11 : resistance

본 고안은 프로그램된 칼라패턴(Pattern) 신호를 마이크로 프로세서로 제어하기 편리하게 한 칼라 패턴 발생회로에 관한 것이다.The present invention relates to a color pattern generating circuit which makes it easy to control a programmed color pattern signal with a microprocessor.

칼라 패턴 발생회로는 임의의 도형이나 문자를 모니터로 출력시킬 수 있게 한 것으로 선전 광고등에 널리 응용할 수 있으나 대부분 R(적), G(녹), B(청) 신호가 출력되지 않으므로 사용하기에 불편하며 항상 고정된 패턴 신호가 출력되도록 구성되어 원하고자 하는 화상처리를 행하기가 곤란한 것이었다.The color pattern generator can output arbitrary figures or characters to the monitor and can be widely used in advertising, but most of them are inconvenient to use because they do not output R (red), G (green), or B (blue) signals. It is difficult to perform desired image processing because it is configured to always output a fixed pattern signal.

본 고안은 이와 같은 점을 감안하여 RGB신호와 동기 신호 및 칼라 패턴 신호처리를 각각 제어할 수 있도록 구성하여 원하고자 하는 칼라 패턴(칼라바, 문자, 도형) 신호를 제어할 수 있는 칼라 패턴 발생회로를 제공하고자 하는 것으로 클럭 발생회로에서 출력되는 클럭을 분주기에서 분주하여 R,G,B 영상신호를 출력시키고 영상신호 및 인버터된 싱크신호로 낸드 게이트를 통하여 칼라 엔코더회로를 통하여 출력되는 칼라 패턴이 출력되게 구성시킨 것이다.The present invention is designed to control the RGB signal, the sync signal, and the color pattern signal processing in consideration of the above points, and can control the color pattern (color bar, character, figure) signal desired. The clock output from the clock generation circuit is divided by the divider to output the R, G, and B video signals, and the color pattern output through the color encoder circuit through the NAND gate as the video signal and the inverter sync signal is The output is configured.

이를 첨부 도면에 의하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to the accompanying drawings.

본 고안은 클럭 발생회로(10)의 발진 주파수를 영상신호 발생회로(20)의 클럭주파수로 사용할 수 있게 구성시킨 것으로 클럭 발생회로(10)는 저항(R1)(R2), 가변저항(VR), 콘덴서(C1)(C2)를 연결 구성시키어 가변저항(VR)으로 출력되는 발진 주파수를 조정하게 구성시키며 영상신호 발생회로(20)는 분주기(2)를 통하여 2,4,8,16분주된 신호를 출력시켜 4분주 신호를 청색(B) 영상신호, 8분주된 신호를 적색(R) 영상신호, 16분주된 신호를 녹색(G) 영상신호가 출력되게 구성시켜 영상신호 절환회로(30)에 인가되게 구성시키고 2분주된 영상신호를 인버터(1N)를 통하여 일측 낸드 게이트(N1)에 인가시키고 타측에는 영상신호 (R)(G)(B)가 인가되어 싱크펄스(SY)의 출력이 칼라 엔코더회로(40)에 인가되게 구성시킨 것이다.The present invention is configured to use the oscillation frequency of the clock generation circuit 10 as the clock frequency of the image signal generation circuit 20, the clock generation circuit 10 is a resistor (R 1 ) (R 2 ), variable resistor ( VR, and condenser (C 1 ) (C 2 ) is configured to adjust the oscillation frequency output to the variable resistor (VR) and the video signal generation circuit 20 is divided into 2, 4, Outputs 8,16 divided signals to output 4 divided signals into blue (B) video signals, 8 divided signals into red (R) video signals, and 16 divided signals into green (G) video signals It is configured to be applied to the switching circuit 30 and the video signal divided by two is applied to one NAND gate N 1 through the inverter 1N, and the other side is applied to the image signal R (G) (B) so that the sync pulse is applied. The output of (SY) is configured to be applied to the color encoder circuit 40.

그리고 영상신호 절환회로(30)에 인가되는 R,G,B신호는 칼라 엔코더 회로(40)에 입력되는 조건을 만족시킬 수 있게 저항(R3-R8)로 분배시켜 인가시키고 각각의 출력점에 트랜지스터(Q1)(Q2)(Q3)를 구성시키어 그 베이스측에 저항(R4)(R10)(R11)를 통하여 절환스위치(GC)(RC)(BC)와 연결되게 구성시켜 전원(VCC)이 공급되게 구성시킨 것이다. 이와 같이 구성된 본 고안에서 가변저항(VR)를 조절하여 클럭 발생회로(10)에서 발생되는 클럭을 맞춘다.In addition, the R, G, and B signals applied to the image signal switching circuit 30 are distributed and applied to the resistors R 3- R 8 so as to satisfy the conditions input to the color encoder circuit 40. Transistors Q 1 , Q 2 , and Q 3 to be connected to the switching switch GC, RC, BC through the resistors R 4 , R 10 , and R 11 on the base side thereof. It is configured to supply power (VCC). In the present invention configured as described above, the clock generated by the clock generation circuit 10 is adjusted by adjusting the variable resistor VR.

이 클럭신호는 모니터의 수평주사주파수(15,75 KHZ)의 16배인 252 KHZ로 발진신호가 분주기(2)에 공급되도록 하여 분주기(2)내에서 분주한 신호로서 R,G,B의 영상신호와 싱크펄스(SY)를 얻게 되는 것으로 싱크펄스는 2분주된 신호가 인버터(1N)를 통하여 반전된 것과 상기 R,G,B 영상신호를 낸드시켜 얻으며 이 싱크펄스(SY)를 칼라 엔코더회로에 인가시킨다. 따라서 클럭(CK)이 제2도와 같이 공급되면 영상신호 절환회로(30)의 저항(R3-R8)으로 분배되어 칼라 엔코더회로(40)에 인가되는 것으로 제2도와 같이 출력되는 영상신호를 얻을수가 있는 것으로 칼라 엔코더회로(40)를 통하여 칼라패턴 신호를 출력시킬 수가 있는 것이다. 즉, R,G,B 영상신호가 교호로 인가되어 출력될때에 영상신호 절환회로(30)의 절환스위치(RC)를 접속시키면 트랜지스터(Q2)가 도통하여 적색(R)영상신호가 트랜지스터(Q2)를 통하여 흐르게 되므로 칼라 엔코더회로(40)에는 적색 영상신호가 출력되지 않게 되는 것으로 수동으로 절환스위치(GC)(RC)(BC)를 절환시켜 원하는 여러가지 패턴의 칼라 영상신호를 얻을 수가 있으며 절환스위치를 전자적인 스위칭 스위치로 대치시키고 마이크로 프로세서의 출력으로 스위칭스위치를 제어하도록 구성시키면 소프트웨어적인 프로그램에 의하여 칼라 신호의 발생시간 및 순서 등을 원하는 대로 출력시킬 수 있는 효과가 있는 것이다.This clock signal is a signal divided in the frequency divider 2 so that the oscillation signal is supplied to the frequency divider 2 at 252 KHZ, which is 16 times the horizontal scan frequency (15,75 KHZ) of the monitor. The video signal and the sync pulse (SY) are obtained. The sync pulse is obtained by inverting the signal divided by two through the inverter (1N) and NAND the R, G, and B video signals. The sync pulse (SY) is a color encoder. Applied to the circuit. Therefore, when the clock CK is supplied as shown in FIG. 2, the clock signal CK is distributed to the resistors R 3 through R 8 of the image signal switching circuit 30 and applied to the color encoder circuit 40. It is possible to obtain a color pattern signal through the color encoder circuit 40. That is, when the switching switch RC of the video signal switching circuit 30 is connected when the R, G and B video signals are alternately applied and output, the transistor Q 2 conducts and the red (R) video signal becomes a transistor ( Q 2 ), so that the red video signal is not output to the color encoder circuit 40. By manually switching the switch (GC) (RC) (BC), a color video signal having various patterns can be obtained. By replacing the switching switch with an electronic switching switch and configuring the switching switch to be controlled by the output of the microprocessor, it is possible to output the generation time and sequence of the color signal as desired by a software program.

이상에서와 같이 본 고안은 클럭신호를 일정한 배수로 분주하여 각각의 칼라 영상신호를 얻을 수 있도록 함으로써 칼라 영상신호(R,G,B)의 제어가 편리할 뿐 아니라 칼라 영상신호 및 2분주된 신호로 싱크펄스(SY)를 얻을 수 있도록 함으로서 회로의 단순화를 기할 수가 있는 것으로 임의의 도형이나 문자를 모니터로 출력시키는 선전 광고등에 편리한 칼라 패턴 발생회로를 제공할 수가 있는 것이다.As described above, the present invention divides the clock signal by a predetermined multiple so that each color image signal can be obtained, and the color image signals R, G, and B are not only convenient to control, but also the color image signal and the divided signal. It is possible to simplify the circuit by obtaining the sync pulse (SY), and it is possible to provide a color pattern generating circuit which is convenient for propaganda advertisements for outputting arbitrary figures or characters to a monitor.

Claims (1)

클럭 발생회로(10)의 클럭(CK)이 영상신호 발생회로(20)의 분주기(2)에 인가되게 구성시켜 배수로 분주된 각각의 R,G,B 영상신호와 인버터(1N)를 통하여 출력되는 분주신호를 낸드 게이트(N1)에서 싱크펄스(SY)가 구성시킨후 영상신호 절환회로(30)에 인가되는 신호를 저항으로 분배시키고 절환스위치(GC)(RC)(BC)로 트랜지스터(Q1)(Q2)(Q3)를 제어하여 칼라 엔코더회로(40)에 인가되는 각 영상신호를 싱크펄스 및 제어하도록 구성시킨 칼라 패턴 발생회로.The clock CK of the clock generation circuit 10 is configured to be applied to the divider 2 of the image signal generation circuit 20 and output through the respective R, G, B image signals divided by multiples and the inverter 1N. After the divided pulses are configured by the sync pulse SY at the NAND gate N 1 , the signals applied to the image signal switching circuit 30 are distributed to the resistors, and the switching switches GC, RC, BC are connected to the transistors. Q 1 ) (Q 2 ) (Q 3 ) is a color pattern generating circuit configured to sink pulse and control each video signal applied to the color encoder circuit (40).
KR2019850003101U 1985-03-23 1985-03-23 Color pattern generating circuit KR880001880Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019850003101U KR880001880Y1 (en) 1985-03-23 1985-03-23 Color pattern generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019850003101U KR880001880Y1 (en) 1985-03-23 1985-03-23 Color pattern generating circuit

Publications (2)

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KR860012560U KR860012560U (en) 1986-10-10
KR880001880Y1 true KR880001880Y1 (en) 1988-05-21

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KR2019850003101U KR880001880Y1 (en) 1985-03-23 1985-03-23 Color pattern generating circuit

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