KR880001537B1 - Insulating layer making process - Google Patents

Insulating layer making process Download PDF

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Publication number
KR880001537B1
KR880001537B1 KR1019850009598A KR850009598A KR880001537B1 KR 880001537 B1 KR880001537 B1 KR 880001537B1 KR 1019850009598 A KR1019850009598 A KR 1019850009598A KR 850009598 A KR850009598 A KR 850009598A KR 880001537 B1 KR880001537 B1 KR 880001537B1
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South Korea
Prior art keywords
polyimide
insulating layer
isolation layer
grooves
making process
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KR1019850009598A
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Korean (ko)
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KR870006641A (en
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이은구
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주식회사 금성사
허신구
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Priority to KR1019850009598A priority Critical patent/KR880001537B1/en
Publication of KR870006641A publication Critical patent/KR870006641A/en
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Publication of KR880001537B1 publication Critical patent/KR880001537B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The silicon substrate (1) is dry-etched to form wells (2) with depth of 1 μm at isolated positions and formed with an oxidization layer (3) in the length of 1000-2000∦. It is coated with a chemical compound like polyimide having small viscosity, and then dry-etched again to improve the flatness of the semiconductor surface.

Description

반도체소자의 격리층 제조방법Method for manufacturing isolation layer of semiconductor device

제 1 도 내지 제 3 도는 본 발명의 제조공정을 나타낸 단면도.1 to 3 are cross-sectional views showing the manufacturing process of the present invention.

제 4 도 및 제 5 도는 종래 기술의 제조공정을 보인 단면도.4 and 5 are cross-sectional views showing the manufacturing process of the prior art.

본 발명은 반도체소자의 격리층 제조방법에 관한 것으로, 특히 반도체소자의 격리층을 점도가 낮은 폴리이미드와 같은 절연물질을 사용하여 형성할 수있게 함으로써 개별 능동소자의 전기적 격리 효율을 증가하고 반도체소자 표면의 편평도를 증가하게한 격리층 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an isolation layer of a semiconductor device. In particular, the isolation layer of a semiconductor device can be formed using an insulating material such as polyimide having a low viscosity, thereby increasing the electrical isolation efficiency of individual active devices and The present invention relates to a method for producing an isolation layer that increases the surface flatness.

종래에는 제 4 도에 도시한 바와 같이 실리콘기판(1)에 1㎛두께의 요홈(2)을 형성하고 산화막(SiO2)(3)을 성장시킨 후 제 5 도에 도시한 바와 같이 요홈(2)내에 산화물이나 폴리실리콘등을 증착 몰입하여 격리층(4´)을 형성함으로써 요홈(2) 사이의 개별소자(5)들이 전기적으로 격리되도록 하였으나, 이와 같은 종래의 반도체소자는 폴리실리콘과 같은 점도가 높은 물질을 요홈(2)에 몰입하였으므로 격리층(4´)에 제 5 도에 도시한 기공(6)등이 내재하게되어 반도체의 절연효과가 감소되고 실리콘 표면이 함몰하여 요입부(7)가 발생하게 되므로 편평도가 양호하지 못하여 소자의 신뢰도가 저하되는 문제점이 있었다.Conventionally, as shown in FIG. 4, grooves 2 having a thickness of 1 탆 are formed on the silicon substrate 1, and oxide films (SiO 2 ) 3 are grown, and then grooves 2 are shown in FIG. However, the individual elements 5 between the grooves 2 are electrically isolated by depositing and immersing oxides or polysilicon into the insulating layer 4 ', but such a conventional semiconductor element has the same viscosity as polysilicon. Since a material having a high content is immersed in the recess 2, pores 6 and the like shown in FIG. 5 are inherent in the isolation layer 4 ', thereby reducing the insulating effect of the semiconductor and recessing the silicon surface, thereby reducing the recess 7. Since the flatness is not good because there is a problem that the reliability of the device is lowered.

본 발명은 이와 같은 종래 기술의 문제점을 해소하기 위하여 창안한 것으로 이를 첨부한 예시도면에 의하여 상세히 설명하면 다음과 같다.The present invention has been made to solve the above problems of the prior art and will be described in detail with reference to the accompanying drawings.

제 1 도에 도시한 바와 같이 실리콘기판(1)을 건식식각법을 이용하여 전기적으로 절연할 부분에 1㎛ 정도의 요홈(2)을 형성하고 1000-2000Å 두께로 산화막(3)을 성장시킨다.As shown in FIG. 1, the groove 2 having a thickness of about 1 m is formed in a portion to electrically insulate the silicon substrate 1 by dry etching, and the oxide film 3 is grown to a thickness of 1000 to 2000 microns.

그후 제 2 도에 도시한 바와 같이 점도가 낮은 폴리이미드층(4)을 도포하고 빛 또는 열로 폴리이미드층(4)을 고체화시킨 다음 제 3 도에 도시한 바와 같이 건식식각법으로 폴리이미드층(4)을 식각하여 실리콘 표면을 완전히 편평하게 한다.Thereafter, as shown in FIG. 2, the polyimide layer 4 having a low viscosity is applied, and the polyimide layer 4 is solidified with light or heat, and then, as shown in FIG. Etch 4) to make the silicon surface completely flat.

이와 같이된 본 발명은 실리콘기판(1)에 요홈(2)을 요입시키고 그 요홈(2)에 점도가 낮은 폴리이미드를 몰입하여 격리층(4)이 형성되어 있으므로 각 요홈(2) 사이에 형성된 개별소자(5)들이 전기적으로 격리되게 된다.In the present invention as described above, the groove 2 is recessed in the silicon substrate 1 and the polyimide having a low viscosity is immersed in the recess 2 so that the isolation layer 4 is formed. The individual elements 5 are electrically isolated.

한편 이와 같은 본 발명을 실시함에 있어서 폴리이미드(예로서 ; (C6H5-C=N-C6H5)n)는 900℃이상의 고온에서는 변형될 수 있으므로 반도체 제조공정은 저온에서 행하여야 한다.On the other hand, in carrying out the present invention, polyimide (for example; (C 6 H 5 -C = NC 6 H 5 ) n) may be deformed at a high temperature of 900 ° C or higher, so the semiconductor manufacturing process should be performed at low temperature.

상기한 바와 같이된 본 발명은 반도체소자의 절연층을 점도가 낮은 폴리이미드로 몰입하여 형성함으로써 절연층이 기공이 없이 형성되어 절연효과가 우수하며 또한, 실리콘 표면을 완전히 편평하게 형성할 수 있으므로 소자의 신뢰도를 증가하는 이점이 있다.The present invention as described above is formed by immersing the insulating layer of the semiconductor device with a low viscosity polyimide, the insulating layer is formed without pores, excellent insulation effect, and can form a completely flat silicon surface There is an advantage to increase the reliability.

Claims (1)

실리콘기판(1)에 요홈(2)을 형성하고 그 요홈(2)에 절연물질을 몰입시켜 격리층(4)을 형성함에 있어서, 실리콘 기판(1)에 형성한 요홈(2)에 폴리이미드와 같은 점도가 낮은 화합물을 몰입시켜 격리층(4)을 형성하고 폴리이미드를 건식식각하여 실리콘 표면을 편평하게 함을 특징으로 하는 반도체소자의 격리층 제조방법.In forming the grooves 2 in the silicon substrate 1 and immersing the insulating material in the grooves 2 to form the isolation layer 4, the grooves 2 formed in the silicon substrate 1 have polyimide and A method for producing an isolation layer of a semiconductor device, characterized by immersing a compound having the same low viscosity to form an isolation layer (4) and dry etching the polyimide to make the silicon surface flat.
KR1019850009598A 1985-12-19 1985-12-19 Insulating layer making process KR880001537B1 (en)

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KR1019850009598A KR880001537B1 (en) 1985-12-19 1985-12-19 Insulating layer making process

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KR870006641A KR870006641A (en) 1987-07-13
KR880001537B1 true KR880001537B1 (en) 1988-08-19

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