KR870007458A - Reset and Data Protection Circuits in Microprocessor-Based Systems - Google Patents

Reset and Data Protection Circuits in Microprocessor-Based Systems Download PDF

Info

Publication number
KR870007458A
KR870007458A KR1019860000253A KR860000253A KR870007458A KR 870007458 A KR870007458 A KR 870007458A KR 1019860000253 A KR1019860000253 A KR 1019860000253A KR 860000253 A KR860000253 A KR 860000253A KR 870007458 A KR870007458 A KR 870007458A
Authority
KR
South Korea
Prior art keywords
reset
circuit
output
low voltage
cpu
Prior art date
Application number
KR1019860000253A
Other languages
Korean (ko)
Other versions
KR890001224B1 (en
Inventor
박승건
Original Assignee
삼성전자 주식회사
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 강진구, 삼성반도체통신 주식회사 filed Critical 삼성전자 주식회사
Priority to KR1019860000253A priority Critical patent/KR890001224B1/en
Publication of KR870007458A publication Critical patent/KR870007458A/en
Application granted granted Critical
Publication of KR890001224B1 publication Critical patent/KR890001224B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

마이크로트로세서를 이용한 시스템에 있어서 리세트 및 데이타 보호회로Reset and Data Protection Circuits in Microprocessor-Based Systems

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 블럭도2 is a block diagram according to the present invention.

제4도는 본 발명에 따른 제2도의 구체회로도4 is a detailed circuit diagram of FIG. 2 according to the present invention.

제7도는 본 발명에 따른 메모리용량 확장시의 제4도의 또 다른 실시예시도.7 is another exemplary embodiment of FIG. 4 at the time of expanding the memory capacity according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 저전압 감지부 20 : 단안정 멀티바이브 레터회로10: low voltage detection unit 20: monostable multi-vibration letter circuit

30 : 레지회로 40 : 버퍼회로30: register circuit 40: buffer circuit

50 : 마이크로프세서 60 : 기입 방지회로50: microprocessor 60: write protection circuit

70 : 메모리 선택회로 80 : 메모리70: memory selection circuit 80: memory

90 : 게이트회로 61,71 : 어드레스신호 입력단자90: gate circuit 61,71: address signal input terminal

11 : 전원 입력단자 100 : 어드레스 및 데이타 버스11: power input terminal 100: address and data bus

R1,R11-R17: 저항 OP11: 연산증폭기 DF1-DF2: 디플립플롭R 1 , R 11 -R 17 : Resistor OP 11 : Operational Amplifiers DF 1 -DF 2 : Deflip-Flop

MMV : 단안정 멀티바이브레터 DEC : 디코드 BUF : 버퍼MMV: Monostable Multivibrator DEC: Decode BUF: Buffer

Claims (3)

CPU(50), 메모리(80)를 구성한 시스템에 있어서, 전원 전압이 변동되더라도 온, 오프 점에서만 출력이 변화되도록 히스테리시스 특성에 의해 비교되어지는 저전압감지부(10)와, 상기 저전압감지부(10)의 출력이 있을 때마다 일정한 펄스폭을 만들어 리세트 상태를 유지시키는 펄스가 발생되는 단안정 멀티바이브레이터회로(20)와, 저전압감지부(10)신호에 의해 리세트되며 단안정 멀티바이브레터(20)의 출력펄스를 에지(Edge)트리거에서 래치시키는 래치회로(30)와, 상기 래치회로(30)의 출력에 따라 CPU(50)를 리세트되도록 리세트신호를 드라이버하는 버퍼회로(40)와 CPU(50)의 어드레스 신회중 칩실렉터 신호를 받아 디코딩하여 전원의 정상. 비정상에 따라 메모리(80)기입을 제어하는 기입 방지회로(60)와, CPU(50)의 칩실렉터 어드레스 신호를 받아 메모리(80)칩을 선택하며 확장시 메모리 영역에 따라 각각 칩메모리(80)를 선택하는 메모리 선택회로(70)와, 래치회로(30)의 출력과 메모리 선택회로(70)의 출력의 논리합(OR)하여 칩을 실렉터되도록 하는 게이트회로(90)로 구성된 것을 특징으로 하는마이크로프로세서를 이용한 시스템에 있어서 리세트 및 데이타 보호회로.In the system constituting the CPU 50 and the memory 80, the low voltage sensing unit 10 and the low voltage sensing unit 10, which are compared by the hysteresis characteristic so that the output changes only at the on and off points even when the power supply voltage varies. The monostable multivibrator (20) and the low voltage sensing unit (10) signal are generated by generating a pulse to maintain a reset state by generating a constant pulse width whenever there is an output of A latch circuit 30 for latching the output pulse of the circuit 20 at an edge trigger, and a buffer circuit 40 for driving a reset signal to reset the CPU 50 according to the output of the latch circuit 30. And the chip selector signal of the CPU 50 during the address shift is decoded to normalize the power supply. In response to abnormality, the write protection circuit 60 controlling the write of the memory 80 and the chip selector address signal of the CPU 50 are selected to select the memory 80 chip. And a gate circuit 90 configured to select a chip by performing a logical OR between the output of the latch circuit 30 and the output of the memory selection circuit 70. Reset and data protection circuits in systems using processors. 제1항의 저전압감지부(10)에 있어서, 연산증폭기(OP11)의 비반전입력단으로 저항(R13-R16)과, 반전입력으로 저항(R11-R12); 제너다이오드(ZD) 및 리세트스위치(SW1)을 출력단에 구성한데서 히스테리시스 특성을 갖도록하여 반전입력(V-)전압과 비반전입력전(V+)압이 비교되어 제너 다이오드(ZD)의 제너전압을 전원전압(Vcc)보다 낮게 하여 저전압이 감지되도록 구성된 것을 특징으로 하는 마이크로 프로세서를 이용한 시스템에 있어서 리세트 및 데이타 보호회로.The low voltage sensing unit (10) of claim 1, comprising: a resistor (R 13 -R 16 ) to a non-inverting input terminal of the operational amplifier (OP 11 ), and a resistor (R 11 -R 12 ) as an inverting input; A Zener diode (ZD) and the reset switch (SW 1) to have a hysteresis characteristic configuration handeseo to an output-inverting input (V -) of the comparison voltage and the non-inverting input I (V +) voltage zener diode (ZD) generator A reset and data protection circuit in a system using a microprocessor, characterized in that a low voltage is detected by lowering a voltage below a power supply voltage (V cc ). 제1항의 기입 방지회로(60)에 있어서, CUP(50)으로부터 칩실렉터 어드레스신호를 디코더입력단자(61)로 받아 리세트나 전원오프시 디플립플롭(DF2)의 세트단자(S)출력에 따라 데이타 기입이 방지되도록 디코더(DEC)와 디플립플롭(DF2)를 구성함을 특징으로 하는 마이크로프로세서를 이용한 시스템에 있어서 리세트 및 데이타 보호회로.The write prevention circuit (60) of claim 1 receives the chip selector address signal from the CUP (50) to the decoder input terminal (61), and outputs the set terminal (S) of the flip-flop (DF 2 ) upon reset or power-off. A reset and data protection circuit in a system using a microprocessor, characterized in that a decoder (DEC) and a deflip-flop (DF 2 ) are configured to prevent data writing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860000253A 1986-01-17 1986-01-17 Reset and data protecting circuit KR890001224B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860000253A KR890001224B1 (en) 1986-01-17 1986-01-17 Reset and data protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860000253A KR890001224B1 (en) 1986-01-17 1986-01-17 Reset and data protecting circuit

Publications (2)

Publication Number Publication Date
KR870007458A true KR870007458A (en) 1987-08-19
KR890001224B1 KR890001224B1 (en) 1989-04-27

Family

ID=19248046

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860000253A KR890001224B1 (en) 1986-01-17 1986-01-17 Reset and data protecting circuit

Country Status (1)

Country Link
KR (1) KR890001224B1 (en)

Also Published As

Publication number Publication date
KR890001224B1 (en) 1989-04-27

Similar Documents

Publication Publication Date Title
KR870000705A (en) Semiconductor memory
KR880008228A (en) Display
KR870006466A (en) Programmable Input / Output Address Providing Circuit for Computer
KR900010788A (en) Output feedback control circuit of integrated circuit device
KR900003898A (en) Dynamic memory
KR880014564A (en) Output buffer control circuit for memory device
KR920008599A (en) Computer system with expansion unit with built-in power supply
KR880000859A (en) Microprocessor
KR940022567A (en) Semiconductor integrated circuit
KR910017290A (en) ROM data protection method and device
KR860004349A (en) Process I / O Device of Sequence Controller
KR870007458A (en) Reset and Data Protection Circuits in Microprocessor-Based Systems
KR960024875A (en) Information processing device with mode setting circuit
KR840003159A (en) Inverter Control Circuit
KR890015285A (en) Malfunction prevention circuit of semiconductor integrated circuit
KR900002193A (en) Microprocessor
KR890002549Y1 (en) Preservation circuit of record data
KR950034262A (en) Low Power Consumption Semiconductor Memory Device
KR910012972A (en) Write malfunction prevention circuit, memory device and data processing device having same
KR970076838A (en) Semiconductor memory device
KR910006845A (en) Central memory expansion unit
KR940008120Y1 (en) Memory controller for display
KR900010554A (en) Congestion Monitoring Circuit of Microprocessor
JPS63116250A (en) Memory control circuit
KR900013393A (en) Region Classification Method and Circuit of Virtual Memory

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050322

Year of fee payment: 17

EXPY Expiration of term