KR870007458A - Reset and Data Protection Circuits in Microprocessor-Based Systems - Google Patents
Reset and Data Protection Circuits in Microprocessor-Based Systems Download PDFInfo
- Publication number
- KR870007458A KR870007458A KR1019860000253A KR860000253A KR870007458A KR 870007458 A KR870007458 A KR 870007458A KR 1019860000253 A KR1019860000253 A KR 1019860000253A KR 860000253 A KR860000253 A KR 860000253A KR 870007458 A KR870007458 A KR 870007458A
- Authority
- KR
- South Korea
- Prior art keywords
- reset
- circuit
- output
- low voltage
- cpu
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Storage Device Security (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 블럭도2 is a block diagram according to the present invention.
제4도는 본 발명에 따른 제2도의 구체회로도4 is a detailed circuit diagram of FIG. 2 according to the present invention.
제7도는 본 발명에 따른 메모리용량 확장시의 제4도의 또 다른 실시예시도.7 is another exemplary embodiment of FIG. 4 at the time of expanding the memory capacity according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 저전압 감지부 20 : 단안정 멀티바이브 레터회로10: low voltage detection unit 20: monostable multi-vibration letter circuit
30 : 레지회로 40 : 버퍼회로30: register circuit 40: buffer circuit
50 : 마이크로프세서 60 : 기입 방지회로50: microprocessor 60: write protection circuit
70 : 메모리 선택회로 80 : 메모리70: memory selection circuit 80: memory
90 : 게이트회로 61,71 : 어드레스신호 입력단자90: gate circuit 61,71: address signal input terminal
11 : 전원 입력단자 100 : 어드레스 및 데이타 버스11: power input terminal 100: address and data bus
R1,R11-R17: 저항 OP11: 연산증폭기 DF1-DF2: 디플립플롭R 1 , R 11 -R 17 : Resistor OP 11 : Operational Amplifiers DF 1 -DF 2 : Deflip-Flop
MMV : 단안정 멀티바이브레터 DEC : 디코드 BUF : 버퍼MMV: Monostable Multivibrator DEC: Decode BUF: Buffer
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019860000253A KR890001224B1 (en) | 1986-01-17 | 1986-01-17 | Reset and data protecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019860000253A KR890001224B1 (en) | 1986-01-17 | 1986-01-17 | Reset and data protecting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR870007458A true KR870007458A (en) | 1987-08-19 |
KR890001224B1 KR890001224B1 (en) | 1989-04-27 |
Family
ID=19248046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860000253A KR890001224B1 (en) | 1986-01-17 | 1986-01-17 | Reset and data protecting circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR890001224B1 (en) |
-
1986
- 1986-01-17 KR KR1019860000253A patent/KR890001224B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR890001224B1 (en) | 1989-04-27 |
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A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050322 Year of fee payment: 17 |
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EXPY | Expiration of term |