KR870004582A - Real Time Picture-Digit Conversion Circuit - Google Patents

Real Time Picture-Digit Conversion Circuit Download PDF

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Publication number
KR870004582A
KR870004582A KR1019850007514A KR850007514A KR870004582A KR 870004582 A KR870004582 A KR 870004582A KR 1019850007514 A KR1019850007514 A KR 1019850007514A KR 850007514 A KR850007514 A KR 850007514A KR 870004582 A KR870004582 A KR 870004582A
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KR
South Korea
Prior art keywords
signal
circuit
output
computer
control
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KR1019850007514A
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Korean (ko)
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KR880002133B1 (en
Inventor
이형준
이재룡
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정재은
삼성전자 주식회사
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Priority to KR1019850007514A priority Critical patent/KR880002133B1/en
Publication of KR870004582A publication Critical patent/KR870004582A/en
Application granted granted Critical
Publication of KR880002133B1 publication Critical patent/KR880002133B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Processing (AREA)

Abstract

내용 없음No content

Description

리얼 타임(Real Time) 화상-디지트 변환회로Real Time Picture-Digit Conversion Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명을 도시하는 블럭도.1 is a block diagram showing the present invention.

제2도는 제1도를 구체적으로 도시하는 회로도.2 is a circuit diagram specifically showing the first diagram.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

BUF : 버퍼회로 THD COM : 임계치 비교회로BUF: Buffer Circuit THD COM: Threshold Comparison Circuit

THDH M : 상위 임계치 THDH L : 하위 임계치THDH M: upper threshold THDH L: lower threshold

DIC : 데이타 입력제어기 DOC : 데이타 출력제어기DIC: Data Input Controller DOC: Data Output Controller

Claims (1)

CCTV 카메라 시스템의 화상-디지트 변환회로에 있어서, 입력화상 신호를 완충하는 입력버퍼(BUF)와 호스터 컴퓨터에 연결한 데이타 입력 제어회로(DIC)와, 호스터 컴퓨터에 연결한 데이타 출력제어회로(DOC)와 컴퓨터내 메모리 번지 지정을 위한 번지 신호를 발생시키는 어드레스 번지 발생회로(ADG)와, 컴퓨터 제어신호를 완충시키는 제어 버퍼회로(CBF)와, 사용자가 화상 디지틀 신호 변환시 요구하게 되는 선택신호를 줄 수 있는 스위치 박스(S/W Box)와, 주변장치와의 데이타 전송시 컴퓨터를 거치지 않고 직접 제어되도록 하고 상기 제어버퍼회로(CBF)에 제어신호를 가해 컴퓨터에서 주(Main) 데이타가 출력토록 하며 데이타 입력제어회로(DIC)와 데이타 출력 제어회로(DOC)에 클럭과 제어신호를 발생시켜 데이타 입, 출력을 제어하도록 스위치 제어신호를 발생하는 DMA 스위치 회로(DMA S/W)와, 입력화상 신호와 스위치와 클럭제어신호(CLCG)신호 의해 동기 검파신호가 출력되는 동기 검파회로(SYDE)와, 화상 아나로그 신호가 컴퓨터에 저장되도록 디지틀 신호로 변환되는 A/D 변환기(A/D)와, 컴퓨터 데이타 입력제어회로(DIC)에서 16비트에 대한 신호가 출력되어 상위 8 비트와 하위 8 비트가 "로우"와 "하이"로 임계치가 설정되는 상, 하 임계치 회로(THD H, THD L)와 상기 상, 하 임계치 회로에서 컴퓨터에 출력된 디지틀 신호가 아나로그 신호로 변환시키는 D/A 변환기(D/A1-D/A2)와, 상기 D/A 변환기 출력과 입력된 화상 신호가 비교되는 임계치 비교회로(THD COM)와, 상기 임계치 비교회로(THD COM)출력이 동기 검파회로 출력과 합산되어 지는 합산회로(SUM)등으로 구성된 것을 특징으로 하는 리얼 타임(REAL TIME) 화상-디지트 변환회로.An image-digit conversion circuit of a CCTV camera system, comprising: an input buffer (BUF) buffering an input image signal, a data input control circuit (DIC) connected to a host computer, and a data output control circuit connected to a host computer ( An address address generation circuit (ADG) for generating a address signal for designating a memory address in the computer, a control buffer circuit (CBF) for buffering a computer control signal, and a selection signal required by the user for converting an image digital signal. In order to transmit the data to and from the S / W Box and peripheral devices, it is controlled directly without passing through the computer, and a control signal is applied to the control buffer circuit (CBF) so that the main data is output from the computer. It generates a switch control signal to control the data input and output by generating a clock and a control signal to the data input control circuit (DIC) and the data output control circuit (DOC). A DMA switch circuit (DMA S / W), a synchronous detection circuit (SYDE) in which a synchronous detection signal is output by an input image signal, a switch and a clock control signal (CLCG) signal, and a digital signal so that an image analog signal is stored in a computer. The A / D converter (A / D) and the computer data input control circuit (DIC) convert the signal to 16 bits, and the upper and lower 8 bits are set to "low" and "high". The upper and lower threshold circuits (THD H, THD L) and the D / A converter (D / A 1 -D / A 2 ) for converting digital signals output from the computer from the upper and lower threshold circuits to analog signals; And a threshold comparison circuit (THD COM) for comparing the D / A converter output and an input image signal, and a summation circuit (SUM) for adding the threshold comparison circuit (THD COM) output with a synchronous detection circuit output. And a REAL TIME image-digit conversion circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850007514A 1985-10-12 1985-10-12 Real time image-digit conversion circuit KR880002133B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850007514A KR880002133B1 (en) 1985-10-12 1985-10-12 Real time image-digit conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850007514A KR880002133B1 (en) 1985-10-12 1985-10-12 Real time image-digit conversion circuit

Publications (2)

Publication Number Publication Date
KR870004582A true KR870004582A (en) 1987-05-11
KR880002133B1 KR880002133B1 (en) 1988-10-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850007514A KR880002133B1 (en) 1985-10-12 1985-10-12 Real time image-digit conversion circuit

Country Status (1)

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KR (1) KR880002133B1 (en)

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KR880002133B1 (en) 1988-10-15

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