KR880008627A - Median filtering circuit - Google Patents

Median filtering circuit Download PDF

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Publication number
KR880008627A
KR880008627A KR860010884A KR860010884A KR880008627A KR 880008627 A KR880008627 A KR 880008627A KR 860010884 A KR860010884 A KR 860010884A KR 860010884 A KR860010884 A KR 860010884A KR 880008627 A KR880008627 A KR 880008627A
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KR
South Korea
Prior art keywords
buffer memory
image
value
output
processing apparatus
Prior art date
Application number
KR860010884A
Other languages
Korean (ko)
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KR890004678B1 (en
Inventor
고순섭
Original Assignee
한형수
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 한형수, 삼성전자 주식회사 filed Critical 한형수
Priority to KR1019860010884A priority Critical patent/KR890004678B1/en
Publication of KR880008627A publication Critical patent/KR880008627A/en
Application granted granted Critical
Publication of KR890004678B1 publication Critical patent/KR890004678B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/20—Circuitry for controlling amplitude response
    • H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Processing (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음.No content.

Description

메디안 필터링 회로Median filtering circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 블럭도.1 is a block diagram according to the present invention.

제2도는 본 발명에 따른 제1도의 화상처리장치(40)의 상세 블럭도.2 is a detailed block diagram of the image processing apparatus 40 of FIG. 1 according to the present invention.

제3도는 본 발명에 따른 제2도의 윈도우 추출회로(31)의 구체 회로도.3 is a detailed circuit diagram of the window extraction circuit 31 of FIG. 2 according to the present invention.

Claims (2)

피사체 영상을 직접 입력할 수 있는 비디오 카메라(10)와, 상기 비디오 카메라(10)의 출력 비디오 신호를 디지털 신호로 변환하여 그 레이값을 얻어내는 아나로그／디지탈 변환기(20)와, 상기 아나로그／디지탈 변환기(20)의 출력신호를 순차적으로 저장하는 영상버퍼메모리(30)를 구비한 영상 처리장치에 있어서, 상기 영상버퍼메모리(30)의 출력신호에서 윈도우 픽설 값증 중간값을 선택하여 물체가 포함된 이미지를 스무싱 필터링 하는 화상처리장치(40)와, 상기 화상처리장치(40)의 출력값을 일시 버퍼링하는 버퍼메모리(50)와, 상기 버퍼메모리(50)의 저장된 데이타를 이용하여 영상을 프로세싱하는 호스트 컴퓨터(60)로 구성함을 특징으로 하는 메디안 필터링 회로.A video camera 10 capable of directly inputting a subject image, an analog / digital converter 20 for converting an output video signal of the video camera 10 into a digital signal to obtain gray values, and the analog An image processing apparatus having an image buffer memory 30 that sequentially stores output signals of the digital converter 20, wherein an intermediate value of a window fixture value is selected from an output signal of the image buffer memory 30. An image is processed by using an image processing apparatus 40 for smoothing and filtering an included image, a buffer memory 50 temporarily buffering an output value of the image processing apparatus 40, and data stored in the buffer memory 50. Median filtering circuitry, characterized in that it comprises a host computer (60) for processing. 제1항에 있어서, 화상처리장치(50)가 영상버퍼메모리로 부터 윈도우를 추출하는 윈도우 추출회로(31)와, 상기 윈도우 추출회로(31)의 추출값에서 중간값을 취하기 위해 분류하는 분류회로(32)와, 상기 영상버퍼 메모리(30)에 기입／독출 제어신호를 출력하고 상기 분류회로(32)에 클럭신호를 공급하는 제어 및 클럭 발생회로(33)와, 상기 분류회로(32)의 출력을 다음 처리를 위해 순차적으로 저장하는 버퍼메모리(50)로 구성함을 특징으로 하는 회로.2. The classification circuit according to claim 1, wherein the image processing apparatus (50) classifies a window extraction circuit (31) for extracting a window from the image buffer memory, and takes a median value from the extraction value of the window extraction circuit (31). And a control and clock generation circuit 33 for outputting a write / read control signal to the video buffer memory 30 and supplying a clock signal to the sorting circuit 32, and the sorting circuit 32. And a buffer memory (50) which sequentially stores the output for subsequent processing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860010884A 1986-12-18 1986-12-18 Median filtering circuits KR890004678B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860010884A KR890004678B1 (en) 1986-12-18 1986-12-18 Median filtering circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860010884A KR890004678B1 (en) 1986-12-18 1986-12-18 Median filtering circuits

Publications (2)

Publication Number Publication Date
KR880008627A true KR880008627A (en) 1988-08-31
KR890004678B1 KR890004678B1 (en) 1989-11-24

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ID=19254116

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860010884A KR890004678B1 (en) 1986-12-18 1986-12-18 Median filtering circuits

Country Status (1)

Country Link
KR (1) KR890004678B1 (en)

Also Published As

Publication number Publication date
KR890004678B1 (en) 1989-11-24

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