JPH07320046A - Image processor - Google Patents

Abstract

PURPOSE:To obtain binarized data with a simple configuration by binarizing a video signal by a comparator and converting the output of the comparator into sampling data by a flip-flop circuit. CONSTITUTION:The comparator 2 compares the video signal Va with threshold value Vth from a threshold value generating circuit 1. A flip-flop circuit 3 latches the output Vb of the comparator 2 each time a clock signal CLK is inputted. A synchronous separating circuit 5 extracts a vertical and a horizontal synchronizing signal from the signal Va. An acknowledgement signal generating circuit 6 generates write acknowledgement signals VEN and HEN on the basis of those signals. A one-bit memory 4 stores the output of the flip-flop circuit 3 when a write acknowledgement signal is outputted from an AND circuit 7. Thus, the binarized data are stored in a memory 4 and character patterns, etc., are recognized with the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device for converting a video signal obtained from an image pickup device into binary data and performing image recognition based on the binary data.

[0002]

2. Description of the Related Art Conventionally, there is an image processing apparatus for photographing a target object such as a mail with an image pickup device and converting a video signal output from the image pickup device into binary data for image recognition. Image processing device, the video signal is A / D
A converter converts the data into 8-bit digital data, stores the data in an 8-bit memory, binarizes the data stored in the memory with a binarizing circuit, and then recognizes a character pattern or the like. As described above, the reason why the A / D converter converts into 8-bit digital data is that the video signal has a gray scale depending on the light amount of the illumination light source that illuminates the target object, the color of the target object, and the like. By once converting into 8-bit (256 gradations) digital data, it is possible to deal with such gradation of light and shade.

[0003]

Since the conventional image processing apparatus recognizes the target object as described above, the A / D converter, the 8-bit memory, and the binary value are obtained in order to obtain the binary data. However, there is a problem in that the cost is increased due to the need for a digitizing circuit. SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing device that can obtain binarized data with a simple configuration in order to solve the above problems.

[0004]

According to the present invention, there is provided a threshold value generating circuit for generating a threshold value whose setting can be changed according to a target object, and an input video signal based on the threshold value.
A comparator that digitizes, a flip-flop circuit that latches the output signal of this comparator for each clock signal input and performs sampling, and a write control that generates a write enable signal based on the vertical and horizontal synchronization timing of the video signal. It has a circuit and a memory which is provided to output data to the recognition processing unit and which stores the output of the flip-flop circuit when the write enable signal is output.

[0005]

According to the present invention, the comparator binarizes the video signal based on the threshold value from the threshold value generating circuit, and the flip-flop circuit samples the output of the comparator. Then, when the write enable signal is output from the write control circuit, the output of the flip-flop circuit is stored in the memory.

[0006]

1 is a block diagram of an image processing apparatus showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the image processing apparatus. Reference numeral 1 is a threshold value generating circuit for generating a threshold value Vth for binarization, 2 is a comparator for comparing the video signal Va output from an image pickup device (not shown) with the threshold value Vth, and 3 is this comparator. A flip-flop circuit 4 that latches the output signal Vb of 2 for each input of the clock signal CLK is a 1-bit memory that stores the output of the flip-flop circuit 3 when a write enable signal described later is output.

Reference numeral 5 denotes a sync separation circuit for extracting a vertical sync signal and a horizontal sync signal from the video signal Va, and 6 denotes a write enable signal VEN for the vertical sync timing and a write enable signal HEN for the horizontal sync timing based on these sync signals. Signal generating circuit for generating
Is an AND circuit. Further, the sync separation circuit 5, the permission signal generation circuit 6, and the AND circuit 7 constitute a write control circuit.

In FIG. 2, HSYNC is a horizontal synchronizing signal,
VSYNC is a vertical synchronizing signal. In addition, FIG.
FIG. 2C shows a signal viewed at the horizontal sync timing over two horizontal scanning periods, and FIGS. 2D to 2F show signals viewed at the vertical sync timing centered on the vertical sync signal VSYNC. .

Next, the operation of such an image processing apparatus will be described. When the image capturing device captures an image of the place where the postal code of the mail is written as the target object, for example, as shown in FIG.
A video signal Va as shown in (d) is output from the imaging device. A portion where the level is lowered as indicated by L in FIG. 2A is a portion where the shade is high, that is, a portion corresponding to a character.

The comparator 2 compares the video signal Va with the threshold value Vth output from the threshold value generating circuit 1. As a result, the output signal Vb of the comparator 2 is as shown in FIG.
As shown in, the level becomes "L" level during the period when the video signal Va is equal to or higher than the threshold value Vth, and becomes "H" level during the period below.

The threshold generation circuit 1 comprises a voltage source (not shown) and a variable resistor connected to this voltage source,
As a result, the threshold value Vth is generated, and the setting of the threshold value Vth can be changed by operating the variable resistor. This is because the information of the target object included in the video signal Va changes depending on the light amount of the illumination light source, the color of the target object, and the like. Therefore, in order to perform the binarization by the comparator 2 as described above, This is because it is necessary to change the threshold value Vth.

Then, the flip-flop circuit 3 latches the output signal Vb of the comparator 2 for each input of the clock signal CLK and outputs it from the terminal Q. Clock signal CL
K is a signal whose cycle is, for example, 82 nsec and which is synchronized with the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC.

As a result of sampling the output of the comparator 2, binarized data that can be processed by a recognition processing unit (not shown) is obtained, and the binarized data is stored in the 1-bit memory 4. At this time, since the data output from the flip-flop circuit 3 includes information unnecessary for image recognition, the following write control is performed in order to save the memory capacity.

First, the sync separation circuit 5 takes out the vertical sync signal VSYNC and the horizontal sync signal HSYNC from the video signal Va, and the permission signal generation circuit 6 performs vertical sync as shown in FIG. 2E based on these sync signals. A write permission signal VEN relating to timing and a write permission signal HEN relating to horizontal synchronization timing as shown in FIGS. 2C and 2F are generated. Next, the logical product circuit 7 takes the logical product of the write enable signals VEN and HEN and outputs the final write enable signal.

The 1-bit memory 4 stores the output of the flip-flop circuit 3 when the write enable signal is output, that is, when the output of the AND circuit 7 is at "H" level. Therefore, when viewed at the horizontal scanning timing, the data of the period t in the signal Vb of FIG.
It will be stored in the bit memory 4. Then, the binarized data is stored in the 1-bit memory 4, and this data is output to the recognition processing unit to perform the recognition processing of the character pattern and the like.

The 1-bit memory 4, the sync separation circuit 5, the permission signal generation circuit 6, and the AND circuit 7 are also provided in the conventional image processing apparatus. In this embodiment, the conventional image processing apparatus is used. , A / D converter, 8-bit memory, binarization circuit, threshold value generation circuit 1, comparator 2,
By replacing with the flip-flop circuit 3, it is possible to obtain binary data with a simple configuration. Further, even when the information of the target object changes due to the light amount of the illumination light source, the color of the target object, etc., it can be easily dealt with by changing the threshold value Vth.

In the present embodiment, the vertical separation signal VSYNC and the horizontal synchronization signal HSYNC are generated by the synchronization separation circuit 5.
However, some of the image pickup devices output the vertical and horizontal synchronization timings as VD signals and HD signals, so that the write enable signal may be generated directly from these signals.

FIG. 3 is a block diagram of an image processing apparatus showing another embodiment of the present invention. Since the configuration excluding the threshold value generating circuit is the same as the example of FIG. 1, the portions having the same configuration are omitted. . 1a is a threshold value generating circuit, 10 is an operational amplifier, Vc
Is a control voltage for determining the threshold value Vth. The threshold value generating circuit 1 in the example of FIG. 1 can change the threshold value Vth by operating the variable resistor. However, in the present embodiment, the threshold value Vth is changed based on the control voltage Vc input from the outside. It is determined.

At this time, if the cable or the like for transmitting the control voltage Vc becomes long, noise may occur on the control voltage Vc. The threshold value generating circuit 1a constitutes a low-pass filter centered on the operational amplifier 10, and removes noise included in the control voltage Vc. In this way, the threshold value Vth can be set according to the target object from a distance from the image processing apparatus.

[0020]

According to the present invention, since the comparator directly binarizes the video signal and the flip-flop circuit converts the output of the comparator into sampling data, the binarized data can be obtained with a simple structure. Therefore, the cost of the image processing apparatus can be reduced. Further, even when the information of the target object changes depending on the light amount of the illumination light source, the color of the target object, etc., it can be easily dealt with by changing the setting of the threshold value.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing apparatus showing an embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of the image processing apparatus in FIG.

FIG. 3 is a block diagram of an image processing apparatus showing another embodiment of the present invention.

[Explanation of symbols]

1, 1a ... Threshold value generation circuit, 2 ... Comparator, 3 ... Flip-flop circuit, 4 ... 1-bit memory, 5 ... Sync separation circuit, 6 ... Permission signal generation circuit, 7 ... AND circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 1/40 103 A

Claims (1)

[Claims] 1. An image processing apparatus for converting a video signal obtained by photographing a target object into binarized data, and performing image recognition in a recognition processing unit based on this data, in a setting according to the target object. A threshold value generation circuit for generating a variable threshold value, a comparator for binarizing an input video signal based on the threshold value, and an output signal of the comparator for each clock signal input. A flip-flop circuit that performs latching and sampling, a write control circuit that generates a write enable signal based on vertical and horizontal synchronization timings of the video signal, and a write control circuit that is provided to output data to the recognition processing unit. An image processing apparatus comprising: a memory that stores the output of the flip-flop circuit when a permission signal is output.