KR970049252A - Board Isolation Circuit of Bus System - Google Patents

Board Isolation Circuit of Bus System Download PDF

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Publication number
KR970049252A
KR970049252A KR1019950064252A KR19950064252A KR970049252A KR 970049252 A KR970049252 A KR 970049252A KR 1019950064252 A KR1019950064252 A KR 1019950064252A KR 19950064252 A KR19950064252 A KR 19950064252A KR 970049252 A KR970049252 A KR 970049252A
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KR
South Korea
Prior art keywords
board
processor
bus
control
boards
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Application number
KR1019950064252A
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Korean (ko)
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KR100374335B1 (en
Inventor
이승왕
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950064252A priority Critical patent/KR100374335B1/en
Publication of KR970049252A publication Critical patent/KR970049252A/en
Application granted granted Critical
Publication of KR100374335B1 publication Critical patent/KR100374335B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)

Abstract

1.청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

공통 버스를 사용하는 시스템.System using a common bus.

2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve

다수의 프로세서들이 공통버스를 사용하여 데이타를 전송하는 시스템에서 특정 프로세서 장애시 해당 프로세서를 버스에서 격리시킨다.In a system in which multiple processors use a common bus to transfer data, they isolate the processor from the bus in the event of a particular processor failure.

3.발명의 해결 방법의 요지3. Summary of solution of invention

다수의 프로세서 보드들이 버스에 공통 연결되며,상기 프로세서들의 버스 사용권을 제어하는 마스터보드로 구성되는 버스시스템에서 마스터보드는 각 프로세서 보드들의 상태를 분석하며,장애 발생을 감지할 시 해당 프로세서보드의 장애 상태를 나타내는 제어비트 및 프로세서 보드의 식별정보를 제어채널 데이타로 생성하여 직렬 스트림으로 변환한 후 공통 버스 상에 출력한다, 그러면 각 프로세서 보드들은 직렬 스트림의 제어채널 정보를 병렬 변환한 후 제어채널 정보의 보드식별정보를 검사하며 자기 식별정보일 시 제어비트들을 검사하여 장애 상태일 시 자신의 보드를 공통 버스 상에서 격리한다.A plurality of processor boards are commonly connected to a bus, and in a bus system composed of master boards for controlling bus usage of the processors, the master board analyzes the states of the respective processor boards and detects a failure in the corresponding processor board. The control bits representing the status and identification information of the processor board are generated as control channel data, converted into serial streams, and output on the common bus. Then, each processor board converts the control channel information of the serial streams in parallel and then controls channel information. It checks the board identification of the board and checks the control bits at the time of self-identification to isolate its board on the common bus in case of failure.

4.발명의 중요한 용도4. Important uses of the invention

다수의 프로세서 보드들이 공통 버스를 사용하여 데이타를 전송하는 시스템에서 특정 프로세서 보드 장애시 해당하는 프로세서 보드만을 격리시키므로 시스템의 성능을 향상시킬 수 있다.In a system in which multiple processor boards use a common bus to transfer data, only the processor board is isolated in the event of a specific processor board failure, thereby improving system performance.

*선택도: 제3도 및 제4도* Selectivity: 3rd and 4th degree

Description

버스 시스템의 보드 격리회로Board Isolation Circuit of Bus System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따라 프로세서 보드들의 상태를 정의하는 제어채널의 구성을 도시하는 도면.3 is a diagram illustrating a configuration of a control channel for defining states of processor boards in accordance with the present invention.

제4도는 본 발명에 따른 글로벌 버스 시스템에서 제어 채널을 전송하는 회로의 구성을 도시하는 도면.4 is a diagram showing a configuration of a circuit for transmitting a control channel in a global bus system according to the present invention.

Claims (1)

다수의 프로세서 보드들이 버스에 공통 연결되며,상기 프로세서들의 버스 사용권을 제어하는 마스터보드로 구성되는 버스시스템에 있어서,프로세서보드의 상태를 나타내는 제어비트 및 프로세서 보드의 식별정보인 어드레스비트들을 발생하는 제어부와, 상기 제어비트 및 어드레스비트들을 저장하는 버퍼와, 상기 버퍼에서 출력되는 제어비트 및 어드레스비트들을 검사하여 패리티비트를 생성하는 수단과, 상기 버퍼에서 출력되는 제어비트 및 어드레스비트와 상기 패리티비트를 제어채널 정보를 수신하며,상기 제어채널 정보를 수신하여 직렬데이타 스트림으로 변환하여 상기 버스에 출력하는 수단으로 구성되는 상기 마스터 보드와, 상기 버스에 병렬연결되며 직렬 스트림의 제어채널 정보를 병렬 변화하는 수단과,상기 병렬 변환된 제어채널 정보의 보드식별 정보를 검사하며 자기 식별정보일시 제어비트들을 검사하여 해당하는 기능을 제어하는 제어부로 구성되는 프로세서보드들을 구비하여,상기 마스터보드에서 프로세서보드들의 상태를 분석하여 비정상상태의 프로세서보드를 버스에 격리시키는 것을 특징으로 하는 버스시스템의 보드 격리회로.In the bus system comprising a plurality of processor boards are commonly connected to the bus, the master board for controlling the bus right of the processor, the control unit for generating a control bit indicating the state of the processor board and the address bits that are identification information of the processor board And means for generating a parity bit by inspecting a buffer storing the control bits and address bits, the control bits and address bits output from the buffer, and a control bit and address bits and the parity bits output from the buffer. Receiving the control channel information and converting the control channel information into a serial data stream and outputting the serial data stream to the bus; Means, and the parallel control channel definition The processor board comprises a control board for inspecting the board identification information of the self-identification information temporary control bits to control the corresponding function, by analyzing the state of the processor boards in the master board bus Board isolation circuit of a bus system, characterized in that the isolation. ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the original application.
KR1019950064252A 1995-12-29 1995-12-29 Circuit for isolating board of bus system KR100374335B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950064252A KR100374335B1 (en) 1995-12-29 1995-12-29 Circuit for isolating board of bus system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950064252A KR100374335B1 (en) 1995-12-29 1995-12-29 Circuit for isolating board of bus system

Publications (2)

Publication Number Publication Date
KR970049252A true KR970049252A (en) 1997-07-29
KR100374335B1 KR100374335B1 (en) 2003-05-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950064252A KR100374335B1 (en) 1995-12-29 1995-12-29 Circuit for isolating board of bus system

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100800764B1 (en) * 2002-01-10 2008-02-01 삼성전자주식회사 Device for controlling error of common bus in a communication system and method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100800764B1 (en) * 2002-01-10 2008-02-01 삼성전자주식회사 Device for controlling error of common bus in a communication system and method thereof

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Publication number Publication date
KR100374335B1 (en) 2003-05-17

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