KR870001369B1 - Image signal modulating method and apparatus - Google Patents

Abstract

New high density image signal transformation method and its appratus are presented. It is possible to use existing T.V. (30frame/sec 1frame 525 scanning line) without modifying trausmission system, to eliminate flicker phenomena, and to improve the degree of vertical scattering; thus high density image signal transformation is implemented. The necessary parts of this system include; an A/D converter, a synchronous seperator, several multiplexers, a frame memory address counter for data, arithmetic and logic circuits, a clock generator and a control signal generator.

Description

High density video signal conversion method and device therefor

1 is a schematic configuration diagram of an apparatus of the present invention.

2 (a)-(c) are explanatory diagrams of a first embodiment of the method of the present invention.

Explanatory drawing of the 2nd Example of the method of this invention also FIG. 3 (a)-3 (c).

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion method and apparatus in a conventional water receiver system of a television receiver, and more particularly, to a video signal conversion method and apparatus for improving the image quality of a television receiver without changing a transmission (broadcasting) system.

In the conventional NTSC transmission and reception system, the number of images transmitted and received per second is 30, and one image is composed of 525 scanning lines.

However, the viewer who actually sees the screen perceives the flicker phenomenon of the screen in 30 images per second (that is, 30 frames). Especially, the larger the screen, the more seriously the flicker phenomenon is felt. You get tired easily.

In addition, one frame is composed of 525 scanning lines, so that the interval between the scanning lines and the scanning lines is wide, so that the viewer can easily view a screen of poor quality, which makes the viewer's eyes tired easily.

In particular, when the screen is larger, the injection player is maintained as it is, so the vertical resolution becomes worse and the screen quality worsens.

According to the present invention, it is necessary to change the television award system without changing the transmission (broadcasting) system. Therefore, the present invention is newly developed by using the currently used receiver (30 frames per second, 1 frame 525 scan lines) as it is. The present invention provides a method and apparatus for converting a video signal for high density video, which can be used for a television with the system of the present invention, and at the same time, to eliminate the phenomenon of polykerage and to increase the vertical resolution. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram of an apparatus which can carry out the method of the present invention, which connects an analog video signal output of a known television receiver tuner circuit 1 to a synchronous separation circuit 2 and an analog-to-digital signal converter 3, The output of the analog digital signal converter 3 is connected to the first multiplexer 4 and the arithmetic logic circuit 5, and the output of the first multiplexer 4 is the first program memory 6 and the second frame memory ( 7) and the outputs of the first frame memory 6 and the second frame memory 7 are connected to the third multiplexer 9 and the arithmetic logic circuit 5 through the second multiplexer 8, and the third The output of the multiplexer 9 is connected to the first and third inputs of the fifth multiplexer 14 via memories 10 and 12 and the output of the arithmetic logic circuit 5 is connected to the memory (through the fourth multiplexer 15). 11, 13, and the output of the memory (11, 13) is connected to the second and fourth input of the fifth multiplexer 14, the fifth mul The output of the flexure 14 is connected to a known image circuit section 17 through a digital-to-analog converter 16, and to the memory 6, 7, 10, 11, 12, 13, respectively, an addressing counter 6 ', 7 ', 10', 11 ', 12', 13 '), wherein the output of the synchronous separator 2 is applied to the control signal circuit 18 so as to output the whole as the output of the control signal circuit 18. Allows you to control the operating time of system components.

The operation of such a device is that when a television signal is received by a known television tuner circuit section 1, a television video signal (analog signal) is supplied to the synchronous separation circuit 2 and the analog-to-digital converter 3.

The analog video signal received by the analog-digital converter 3 is converted into a digital video signal. The digital image signal output corresponding to the first frame in the analog-to-digital converter 3 is simultaneously supplied to the first multiplexer 4 and the arithmetic logic circuit 5, and the first frame multiplexer 4 receives the first frame memory ( 6) is remembered.

When the digital image signal output corresponding to the first frame is stored in the first frame memory 6, the second frame memory 7 transmits the stored frame corresponding digital image signal through the second multiplexer 8 to the third multiplexer 9 And the digital video signal output corresponding to the first frame, when no digital video signal is stored in the second frame memory 7, the signal is supplied to the second multiplexer 8. There will be no. Accordingly, the third multiplexer 9 does not input any signal to the memories 10 and 12, and the arithmetic logic circuit 5 stores the digital image signal corresponding to the first frame in the memory 11.

Next, when the digital video signal output corresponding to the second frame is stored in the second frame memory 7 by the first multiplexer 4, the digital video corresponding to the first frame stored in the first frame memory 6 at this time. The signal is simultaneously applied to the third multiplexer 9 and the arithmetic logic circuit 5 via the second multiplexer 8.

At the same time, since the digital video signal corresponding to the second frame is directly supplied from the analog-to-digital converter 3 to the arithmetic logic circuit 5, the digital video signals corresponding to the first frame are summed between the scan lines in the frame and divided in half. The digital video signal of the first interpolation frame to be interpolated between and the second frame is output.

The digital video signal of the first interpolation frame is stored in the memory 13 by the fourth multiplexer 15. The output of the third multiplexer 8 (digital video signal corresponding to the first frame) is also stored in the memory 12. After that, when the digital video signal output corresponding to the third frame is generated by the analog-to-digital converter 3, the digital-to-analog circuit 5 directly stores the digital video signal in the first frame memory 6 through the first multiplexer 4. Is approved.

The digital video signal corresponding to the third frame is stored in the first frame memory 6, and the digital video signal corresponding to the second frame stored in the second frame memory 7 is arithmetic through the second multi-plexer 8. The logic circuit 5 and the third multiplexer 9 are applied. At this time, the digital video signal corresponding to the second frame and the digital video signal corresponding to the third frame are applied to the arithmetic logic circuit 5, summed and divided in half, and the digital video signal of the second interpolation frame to be interpolated between the second and third frames. Is output.

The digital video signal of the second interpolation frame is stored in the memory 11 by the fourth multiplexer 15. In addition, the digital video signal corresponding to the second frame applied to the third multiplexer 9 is stored in the memory 10. At this time, the contents stored in the memory 10-13 are as follows.

Therefore, the information is stored in the memories 10 and 11, and the contents of the memories 12 and 13 are sequentially decoded by the fifth multiplexer 14 at twice the existing frame rate and then digital-analog. When the deciphering digital signal is supplied to the converter 16, it is converted into an analog signal and supplied to the known video circuit unit 17.

Next, when a digital video signal corresponding to the fourth frame generated by the analog digital converter 3 is generated, the above process is repeated, and the digital video signal corresponding to the third frame is stored in the memory 12 and 13 in the digital interpolation frame. At the same time as the video signal is stored, the digital video signal corresponding to the second frame stored in the memories 10 and 11 is decoded by the fifth multiplexer 14 so that the digital video signal of the second interpolation frame is decoded. It is supplied to the known image circuit unit 17 through).

In this way, a video without the polyker phenomenon can be displayed on a television set.

In addition, referring to FIGS. 2 (a) and 2 (c), the present invention for eliminating the polyker phenomenon is described. The analog-digital signal converter is provided by inputting the detected video signal of the TV tuner circuit 1. The digital-to-digital signal converter 3 converts the digital signal into the digital signal in (3), and then converts the digital signal into the first frame memory 6 in the odd frame and the second frame memory 7 in the even frame in the first multiplexer 4. And the analog-digital signal converter by selecting the content of the second frame memory 7 in the odd frame and the content of the first frame memory 6 in the even frame in the second frame. The fourth multiplexer 15 stores the memory 11 in the odd numbered frame and the memory 13 in the even numbered frame in the fourth multiplexer 15. Is the odd frame in memory 10 By storing the result of the second multiplexer 8 in the memory 12, the contents of the memory 12 and the memory 13 are stored in the fifth multiplexer 14 when the odd frame is used. 10) and the contents of the memory 11 are sequentially read, and the digital-to-analog signal converter 16 generates an analog video signal with twice the number of frames.

The operation of this method is described in detail by dividing the frame signal into odd and even numbers.

(1) in the case of radix frames

After the video signal detected by the tuner circuit part 1 of the television receiver is converted into a K-bit digital signal by the sampling frequency (f ₁ : 2 (c) A) in the analog-digital signal converter 3, It is stored in the first frame memory 6 via one multiplexer 4.

In the second frame memory 7, the video signal of the frame at the even-numbered frame is already stored, and this signal is applied to the arithmetic logic circuit 5 through the second multiplexer 8 to convert the analog-digital signal converter. After interpolation with the output of (3), the result is applied to the fourth multi-plexer 15.

The fourth multiplexer 15 stores the result of the arithmetic logic circuit 5 in the memory 11, and the third multiplexer 9 stores the contents of the second frame memory 7 in the memory 10. Save it. The fifth multiplexer 14 sequentially selects the contents of the memory 12 and the memory 13 by using a block of frequency (f ₂ : see also the second (c) J), and converts the digital-analog signal. The unit 16 converts the contents of the selected memory into an analog output video signal.

(2) In case of storm frame

The video signal detected by the tuner circuit part 1 of the television receiver is converted into the digital signal by the sampling frequency f ₁ in the analog-digital signal converter 3 and then passed through the first multiplexer 4 to the second frame. It is stored in the memory (7). In the first frame memory 6, the video signal of the frame in the odd frame is already stored, and this signal is applied to the arithmetic logic circuit 5 through the second multiplexer 8 to convert the analog-digital signal converter ( It is interpolated with the output of 3) and the result enters the fourth multiplexer 15.

The fourth multiplexer 15 reloads the result of the arithmetic logic circuit 5 in the memory 13. At the same time, the third multiplexer 9 stores the contents of the first frame memory 6 in the memory 12.

The fifth multiplexer 14 sequentially selects the contents of the memory 10 and the memory 11 by using a block of frequency f ₂ , and the contents of the memory selected by the digital-analog signal converter 16. Is converted into an analog output video signal.

In this way, the frames F ₁ to F ₃ as shown in FIG. 2 (a) are doubled as the frames F ₁ to F ₃ as in FIG. 2 (a) (F ₁ , F ₁ ', F _2). , F ₂ ', F ₃ , F ₃ ') Flicker is lost. This operation is performed as a time relationship as shown in FIG. 2 (b).

The method of the present invention for increasing the vertical resolution with reference to FIGS. 3 (a)-3 (c) is as follows.

The detected video signal of the TV tuner circuit unit is inputted and converted into a digital signal by the analog-to-digital signal converter 3, and then the odd-numbered frame is input to the first frame memory 6 and the even-numbered frame by the first multiplexer 4. Stores the output of the analog-to-digital signal converter 3 in the second frame memory 7, simultaneously stores the contents of the second frame memory 7 in the odd frame and the first frame memory 6 in the even frame. The content is selected by the second multiplexer 8 and computed together with the output of the analog-digital signal converter 3 so that the memory of the fourth multiplexer 15 is the memory 11 for the odd scan line and the memory for the even scan line. And stores the result of the second multiplexer 7 in the memory 12 when the even multiple scan line is the odd scan line in the third multiplexer 9. Radix scan in the fifth multiplexer 14 Is the memory 12, the contents of the memory 13, and the contents of the memory 10 and the memory 11 are sequentially read. How to spill it. This method is described in detail according to the odd and excellent frame.

(1) In the case of radix frames

After the video signal detected by the tuner circuit section 1 of the television receiver is converted into a K-bit digital signal by the sampling frequency (f ₁ : 3 (c) in Fig. A) in the analog-digital signal conversion section 3, The first frame memory 6 is stored in the first frame memory 6 via the first muffler flexure 4.

The second frame memory 7 already stores the video signal of the first frame in the even frame, which enters the arithmetic logic circuit 5 through the second multiplexer 8 and converts the analog-digital signal. Interpolated with the output of the part 3, the result enters the 4th multiplexer 15. As shown in FIG.

The fourth multiplexer 15 outputs the result of the arithmetic logic circuit 5 to the memory 11 for even scan lines, to the memory 13 for even scan lines, and to the memory 12 for even scan lines. Save it.

A fifth multiplexer (14) when the rider scanning line in the case where the contents of memory 12 or memory 13, best scan line, the frequency the content of the memory 10 and the memory (11) (f _2: the 3 (c) is also sequentially selected using a block of J), and the digital-analog signal converter 16 converts the contents of the selected memory into an analog output video signal.

(2) In case of storm frame

The video signal detected by the tuner circuit section 1 of the television receiver is converted into a digital signal by the analog-digital signal converter 3 and then stored in the second flame memory 7 via the first multiplexer 4.

In the first frame memory 6, the video signal of the frame in the odd frame is already stored, and this signal enters the arithmetic logic circuit 5 through the second multiplexer 8 and the analog-digital signal converter 3 The interpolation with the output of) results in the fourth multiplexer 15.

The fourth multiplexer 15 stores the result of the arithmetic logic circuit 5 in the radix memory 13.

At the same time, the third multiplexer 9 stores the contents of the first frame memory 6 in the memory 10 in the case of the even scan line and in the memory 12 in the case of the even scan line.

The fifth multiplexer 14 sequentially selects the contents of the memory 12 and the memory 13 in the case of the odd scan line and the contents of the memory 10 and the memory 11 in the case of the even scan line. The analog signal converter 16 converts the contents of the selected memory into an analog output video signal. This doubles the number of scanning lines l ₁ to l ₅₂₅ as shown in FIG. 3 (a) (l ₁ , l ₁ ', l ₂ , l ₂ ', …… l ₅₂₄ ', l ₅₂₅ ) the vertical resolution is improved.

This action takes place as a time relationship as shown in Fig. 3 (b).

As described above, according to the present invention, if only the processing of the image receiver in the internal circuit of the television receiver is changed without changing the equipment of the transmission (broadcasting) side, the conventional flicker phenomenon can be prevented and the vertical resolution can be improved. It can increase the screen size of the television set and reduce the fatigue of the viewer when watching the television set.

Claims (2)

High-density video images read out by a multiplexer by connecting the analog video signal output of a known television receiver tuner circuit to a synchronous separation circuit and an analog-digital signal converter, and applying the output of the analog digital signal converter to a memory and an arithmetic logic circuit. In the signal converter, the output of the analog digital signal converter 3 is connected to the first multiplexer 4 and the arithmetic logic circuit 5, and the output of the first multiplexer 4 is stored in the order of the input frames so as to store the first frame. Connected to the memory 6 and the second frame memory 7, and outputs of the first frame memory 6 and the second frame memory are connected to the third multiplexer 9 and the arithmetic logic circuit 5 through the second multiplexer 8. ), And the arithmetic logic circuit calculates an interpolated frame to be interpolated between the frames so that the output of the third multiplexer 9 is connected to the fifth multiplexer 14 through the memories 10 and 12. A first and a third input and an output of the arithmetic logic circuit 5 to a memory 11, 13 through a fourth multiplexer 15, the output of the memory 11, 13 being a fifth multiplexer 14 Are connected to the second and fourth inputs of the circuit, but the output of the fifth multiplexer 14 is connected to a known image circuit unit 17 through a digital-to-analog converter 16, and the memory 6, 7, 10, 11, 13 ) Is connected to addressing counters 6 ', 7', 10 ', 11', 12 ', 13', where the output of the synchronous separator 2 is applied to the control signal circuit 18 An apparatus for converting high-density video signals as an output of the control signal circuit 18 to control the operating time of the entire system elements. In the video signal conversion method for converting a digital signal from the detected analog video signal of the known TV tuner circuit section 1 into the analog digital signal conversion section 3, and extracting a double digital signal, the first multiplexer ( 4) In the odd frame, the output of the analog-to-digital signal converter 3 is stored in the first frame memory 6 in the even frame and in the second frame memory 7 in the even frame, and simultaneously in the second frame memory 7 in the odd frame. In the even frame, the content of the first frame memory 6 is selected as the second multiplexer 8 to be calculated together with the output of the analog-to-digital signal converter 2 to form an interpolated frame signal. The fourth multiplexer 15 stores the memory 11 in the odd frame and the memory 13 in the even frame so that the calculated interpolation frame signal is stored in the memory and then the fifth multiplexer. Stand 14, a high-density image conversion method for video signal that takes an analog image signal read out sequentially frame number doubled as.

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