KR850000886A - PCM voice signal exchange method - Google Patents

PCM voice signal exchange method Download PDF

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Publication number
KR850000886A
KR850000886A KR1019830002903A KR830002903A KR850000886A KR 850000886 A KR850000886 A KR 850000886A KR 1019830002903 A KR1019830002903 A KR 1019830002903A KR 830002903 A KR830002903 A KR 830002903A KR 850000886 A KR850000886 A KR 850000886A
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South Korea
Prior art keywords
pcm
counter
bit
voice signal
serial
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KR1019830002903A
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Korean (ko)
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KR850001262B1 (en
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김종성
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이재연, 하인츠디터케루트
금성통신 주식회사
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Priority to KR1019830002903A priority Critical patent/KR850001262B1/en
Publication of KR850000886A publication Critical patent/KR850000886A/en
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Publication of KR850001262B1 publication Critical patent/KR850001262B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

내용 없음.No content.

Description

PCM 음성신호 교환방법PCM voice signal exchange method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 이용되는 키텔레폰 시스템에 있어서의 통화로 구성을 예시한 블럭도.1 is a block diagram illustrating the configuration of a call in a key telephone system in which the present invention is used.

제2도는 본 발명에 의한 PPCM 음성신호교환방법의 실시예인 PCM 음성신호교환회로의 블럭도이다.2 is a block diagram of a PCM voice signal exchange circuit, which is an embodiment of the PPCM voice signal exchange method according to the present invention.

Claims (1)

계수기 입력재생회로(230)이 2,048MHZ 발진기(229)로 부터 클럭을 받아 계수기(202)와 계수기(204)에 4비트씩 교대로 보내어 계수기(202)와 계수기(204)가 계수기입력재생회로(230)로 부터 4비트씩의 클럭을 받을 때마다 계속 계수하도록 하고, 다중화 PCM 음성신호송신선로(1)(2)(3)(4)의 두번째 타임슬롯의의 동기펄스에 의해 계수기(202)가 리셋되도록 하는 동시에 32번째 타임슬롯의 동기펄스에 의해 계수기(204)가 리셋되도록 하며, 각각 32개의 8비트 직렬 PCM 음성신호가 다중화 되어 실리는 4개의 다중화 PCM 음성신호 송신선로(1)(2)(3)(4)의 각 송신선로마다 직렬/병렬변환회로(207)(208)(209)(210)와, 래치(211)(212)(213)(214)를 각각 연결하여 다중화 PCM 음성신호 송신선로(1)(2)(3)(4)로 부터 입력되는 첫번째 8비트 직렬음성신호를 8비트 병렬 PCM 음성신호를 만들어 래치(211)(212)(213)(214)를 각각 연결하여 다중화 PCM 음성신호송신선로(1)(2)(3)(4)로 부터 입력되는 첫번째 8비트 직렬 PCM 음성신호를 8비트 병렬 PCM 음성신호로 만들어 래치로(211)(212)(213)(214)에 저장한후, 두번째 8비트 직렬 PCM 음성신호의 첫번째 비트에서 4번째 비트가 직렬/병렬변환회로(207)(208)(209)(210)로 들어올 때 래치출력제어회로(215)로 하여금 래치(211)(212)(213)(214)에 출력제어 신호를 차례로 인가하게 하는 동시에 계수기(202)가 RAM(201)의 해당 어드레스를 차례로 지정케 하여 계수기(202)가 지정한 RAM(201)의 어드레스에 래치(211)(212)(213)(214)로 부터 출력된 8비트 병렬 PCM 음성신호가 기억되게 하는 동시에, 계수기(202)가 RAM(231)의 어드레스를 지정하는 동안 마이크로프로세서로 하여금 제어단자(201)에 제어신호를 인가하게 하여 마이크로프로세서가 래치(205)(206)에 입력시켜 저장한 통화회로 구성에 관한 데이타 및 어드레스에 따라 RAM (203)의 해당 어드레스에 해당 메이타가기 억되게 하며, 다중화 PCM 음성신호 송신선로(1)(2)(3)(4)로 부터 2번째 8비트 직렬 PCM 음성신호의 5번째에서 8번째비트가 직렬/병렬 변환회로(207)(208)(209)(210)로 들어올 때 계수기(0204)가 RAM(203)의 어드레스를 차례로 지정하여 RAM(203)의 해당어드레스에 기억된 데이타가 출력되어 출력된 데이타에 해당하는(201)의 어드레스에 기억된 8비트 병렬 PCM 음성신호가 차례로 출력되도록 하는 동시에 래치 입력제어회로(220)가 교환하고자하는 PCM 음성신호채널에 해당하는 래치(221)(222)(223)(224)에 입력제어신호를 인가하게 하여 RAM(201)로부터 출력된 8비트병렬 PCM 음성신호가 해당래치와 병렬/직렬변환회로를 통하여 8비트 직렬 PCM 음성신호로 바뀌어 다중화 PCM 음성신호 수신선로로 송출되도록 하며, 다중화 PCM 음성신호 송신선로(1)(2)(3)(4)의 모든 채널도 상기와 동일한 방법으로 다중화 PCM 음성신호 수신선로로 송출되도록 한 PCM 음성신호 교환방법.The counter input reproducing circuit 230 receives the clock from the 2,048 MHZ oscillator 229 and sends it to the counter 202 and the counter 204 alternately by 4 bits, so that the counter 202 and the counter 204 receive the counter input reproducing circuit ( Each time the clock is received from the processor 4, the clock is continuously counted, and the counter 202 is operated by the synchronization pulse of the second time slot of the multiplexed PCM voice signal transmission line (1) (2) (3) (4). 4 multiplexed PCM audio signal transmission lines (1) (2) in which 32 8-bit serial PCM audio signals are multiplexed and loaded, respectively, and the counter 204 is reset by the synchronization pulse of the 32nd timeslot. Multiplexed PCM by connecting serial / parallel conversion circuits 207, 208, 209, 210, and latches 211, 212, 213, 214 for each transmission line of < RTI ID = 0.0 > Latch (211) (212) (213) (2) by making an 8-bit parallel PCM voice signal from the first 8-bit serial voice signal input from voice signal transmission line (1) (2) (3) (4). 14) by connecting the first 8-bit serial PCM voice signal input from the multiplexed PCM voice signal transmission line (1) (2) (3) (4) into an 8-bit parallel PCM voice signal and latching (211) ( 212) (213) and 214, and latch output control when the fourth bit from the first bit of the second 8-bit serial PCM audio signal enters the serial / parallel conversion circuits 207, 208, 209, and 210. The circuit 215 causes the counters 212, 212, 213, and 214 to sequentially apply output control signals to the latches 211, 212, 213, and 214, while the counter 202 sequentially assigns the corresponding addresses of the RAM 201 to the counters 202. The 8-bit parallel PCM audio signal output from the latches 211 (212) (213) (214) is stored at the address of the designated RAM 201, and the counter (202) stores the address of the RAM (231). During the designation, the microprocessor applies a control signal to the control terminal 201 so that the microprocessor inputs and stores the latch 205 and 206. According to the data and address related to one communication circuit configuration, the corresponding memory is stored at the corresponding address of the RAM 203, and the second 8 from the multiplexed PCM voice signal transmission line (1) (2) (3) (4) When the fifth to eighth bits of the bit serial PCM voice signal enter the serial / parallel conversion circuits 207, 208, 209, and 210, the counter 0204 sequentially assigns addresses of the RAM 203 so that the RAM ( The data stored in the corresponding address of 203 is outputted so that the 8-bit parallel PCM audio signal stored at the address of 201 corresponding to the output data is sequentially outputted, and the PCM to be exchanged by the latch input control circuit 220. An 8-bit parallel PCM audio signal output from the RAM 201 is applied to the latch and parallel / serial conversion circuits by applying an input control signal to the latches 221, 222, 223, and 224 corresponding to the audio signal channel. Multiplexed PCM voice signals through 8-bit serial PCM voice signals Into the furnace and sent to a multiplexing PCM speech signal transmission line (1) (2) (3) (4) all the way channel also exchange a PCM audio signal to be sent out to the multiplexing PCM audio signal can sinseollo in the same manner as described above in. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019830002903A 1983-06-25 1983-06-25 Exchanges system of p.c.m. audio signal KR850001262B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019830002903A KR850001262B1 (en) 1983-06-25 1983-06-25 Exchanges system of p.c.m. audio signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019830002903A KR850001262B1 (en) 1983-06-25 1983-06-25 Exchanges system of p.c.m. audio signal

Publications (2)

Publication Number Publication Date
KR850000886A true KR850000886A (en) 1985-03-09
KR850001262B1 KR850001262B1 (en) 1985-08-26

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KR1019830002903A KR850001262B1 (en) 1983-06-25 1983-06-25 Exchanges system of p.c.m. audio signal

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