KR100247416B1 - Data delay apparatus por channel for testing echo removing device - Google Patents

Abstract

The present invention relates to an apparatus for delaying data of a predetermined channel within a frame for a predetermined time for a test of an echo canceller. A conversion unit 1; A memory 2 for storing the data of the channel converted into the parallel state through the serial-to-parallel conversion unit 1 at an address corresponding to the write address signal, and outputting the data stored at the address corresponding to the read address; A delay unit (3) to which a predetermined synchronous clock and delay time signal is applied, synchronously outputs the write address signal in synchronization with the synchronous clock, and delays and outputs a read address signal corresponding to the write address signal by a predetermined frame; A serial-to-parallel converter 4 for converting and outputting data output from the memory 2 in parallel in synchronization with the channel selection signal; And a multiplexer 5 for inserting and outputting channel data of the parallel-to-serial converter 4 in a channel corresponding to the channel selection signal in the current frame.

That is, in the present invention, the delay time for each channel of the test data for testing the performance of the echo canceller can be freely set.

Description

Channel-specific data delay device for testing echo cancellers

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for testing an echo canceller for canceling echoes occurring in data communications, and more particularly to delaying channel data used in communications for a predetermined time to test echo cancellers. Relates to a device.

In the advanced information society, mobile communication services that can exchange various types of information regardless of time and space are required.

In a digital mobile communication network system, a mobile subscriber of a digital mobile communication network echoes due to impedance mismatch in a two-wire and four-wire conversion circuit in a circuit-switched network during a call with a fixed subscriber connected to the circuit-switched network, and wirelessly between the mobile station and the mobile station and the base station. In order to reduce the use band due to the effectiveness of the channel, voice coding of frame to frame is performed. At this time, the voice data is affected by a reverberation due to a processing delay of several tens of ms, so that the mobile subscriber feels inconvenience in the call. Therefore, an echo canceller is used to remove the reverberation.

On the other hand, the voice data over the telephone channel does not have the same processing delay time, but different delay time depending on hardware characteristics of transmission line and base station, and so on. You will need to test it.

That is, in order to test the echo cancellation device, it is necessary to delay the voice data for each telephone channel at a different time. However, there is a problem in the related art that there is no device capable of selectively setting the delay time of the voice data.

The present invention has been made to solve such a problem, an object of the present invention is a data delay device for each channel for the test of the echo canceller that can freely set the delay time for each channel of the test data for testing the performance of the echo canceller. To provide.

A channel-specific data delay device for testing an echo canceller according to the present invention is a device for delaying a predetermined time of data of a predetermined channel in one frame for a test of an echo canceller, and corresponding to a channel selection signal among a plurality of channels in one frame. A serial-to-parallel converter configured to input only channel data and convert the channel data into a parallel state; A memory for storing the data of the channel converted into the parallel state through the serial-to-parallel conversion unit at an address corresponding to the write address signal, and outputting the data stored at the address corresponding to the read address; A delay unit (3) to which a predetermined synchronous clock and delay time signal is applied, and sequentially outputs the write address signal in synchronization with the synchronous clock, and delays and outputs a read address signal corresponding to the write address signal by a predetermined frame; A serial-to-parallel converter for converting and outputting data output from the memory 2 in parallel in synchronization with the channel selection signal; And a multiplexer for inserting and outputting channel data of the parallel-to-serial converter into a channel corresponding to the channel selection signal in the current frame.

1 is a block diagram of a channel-specific data delay device for testing an echo canceller in accordance with the present invention.

<Description of the code | symbol about the principal part of drawing>

1: Serial and parallel converter 2: Memory

3: delay unit 4: parallel-serial conversion unit

5: multiplexer

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a channel-specific data delay apparatus for testing an echo canceller according to the present invention. As illustrated, frame data in a serial state is applied to a serial-to-parallel converter 1. Here, data is formed of a plurality of channels (one channel is usually formed of 8 bits) in one frame as in general telephone communication.

A channel selection signal is applied to the serial-to-parallel converter 1 as shown in addition to the frame data, and inputs only data of a channel corresponding to the channel selection signal, that is, channel data corresponding to the channel selection signal among a plurality of channels in one frame. To convert to parallel state. As such, it will be apparent to those skilled in the art that the channel selection signal can be easily generated and output by a user using a processor (not shown).

The data of the channel converted into the parallel state through the serial to parallel conversion unit 1 is applied to the memory 2, and the memory 2 is converted to the parallel to an address corresponding to the write address signal applied from the delay unit 3. The channel data of the section 1 is stored, and the data of the address according to the read address signal read is output. At this time, a predetermined synchronous clock and delay time signal is applied to the delay unit 3 as shown, and the delay unit 3 synchronizes the read address signal corresponding to the above-described write address signal with a predetermined time ( Frame) delayed output. That is, the delay unit 3 outputs the address output as the write address as the read address after the passage of time corresponding to the delay time signal.

The channel data output from the memory 2 is applied to the parallel and serial converter 4, and the parallel and serial converter 4 converts the channel data (in parallel state) of the memory 2 into a serial state and outputs the serial data. At this time, the above-described channel selection signal is applied to the parallel-to-serial conversion unit 4, and the parallel-to-serial conversion unit 4 is configured to output the channel data converted into the serial state in synchronization with the channel selection signal. That is, as described above, the data of the predetermined channel, which is converted into the parallel state by the serial-to-parallel conversion unit 1, is delayed by a predetermined time (frame) through the memory 2, so that the delayed channel data is described below. It is output in synchronization with this channel selection signal for insertion into a corresponding sequence channel in a delayed frame.

The channel data converted into the serial state through the parallel-to-serial converter 4 is applied to the multiplexer 5, and the current frame data and the channel selection signal are applied to the multiplexer 5, and thus the multiplexer Reference numeral 50 deletes the data of the channel corresponding to the channel selection signal from the current frame data, and inserts and outputs the channel data of the parallel-to-serial converter 4 described above into this erased channel.

That is, in the present invention, the memory 2 uses the memory 2 to delay the predetermined channel data by one frame and insert the delayed channel data into the corresponding channel in the frame after the predetermined frame. It is possible to delay the predetermined frame. Here, it will be readily understood that the user can freely set the delay time as described above.

In addition, in the present invention, if the separate display unit 6 is configured as shown, the delayed time for each channel may be facilitated. The technique of displaying the delayed time through the display unit 6 is a conventional technique in the technical field of the present invention, and thus, a detailed description thereof is omitted.

As described above, in the present invention, the delay time for each channel of the test data for testing the performance of the echo canceller can be freely set.

Claims (2)

An apparatus for delaying a predetermined time of data of a predetermined channel in one frame for a test of an echo canceller, A serial-to-parallel converter (1) for inputting only channel data corresponding to a channel selection signal among the plurality of channels in one frame and converting the same into a parallel state; A memory (2) for storing the data of the channel converted into a parallel state through the serial-to-parallel conversion unit (1) at an address corresponding to a write address signal, and outputting data stored at an address corresponding to a read address; A predetermined synchronous clock and delay time signal are applied, and the write address signal is sequentially output in synchronization with the synchronous clock, and the read address signal corresponding to the write address signal is delayed by a predetermined frame corresponding to the delay time signal. A delay unit 3 for outputting; A serial-to-parallel converter (4) for converting and outputting data output from the memory (2) in parallel in synchronization with the channel selection signal; And a multiplexer (5) for inserting and outputting channel data of the parallel-to-serial converter (4) in a channel corresponding to the channel selection signal in a current frame. The method of claim 1, And a display unit (6) for displaying a time at which the write address signal and the output address signal are delayed in the delay unit (3).

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