KR840003373A - A circuit using a constant address area as a common beneficiary in a multiple BANK memory system with a large address range memory device - Google Patents

A circuit using a constant address area as a common beneficiary in a multiple BANK memory system with a large address range memory device Download PDF

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Publication number
KR840003373A
KR840003373A KR1019830000024A KR830000024A KR840003373A KR 840003373 A KR840003373 A KR 840003373A KR 1019830000024 A KR1019830000024 A KR 1019830000024A KR 830000024 A KR830000024 A KR 830000024A KR 840003373 A KR840003373 A KR 840003373A
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KR
South Korea
Prior art keywords
memory
bank
common
address area
memory device
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Application number
KR1019830000024A
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Korean (ko)
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KR850000710B1 (en
Inventor
최봉락
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강진구
삼성전자공업 주식회사
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Priority to KR1019830000024A priority Critical patent/KR850000710B1/en
Publication of KR840003373A publication Critical patent/KR840003373A/en
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Publication of KR850000710B1 publication Critical patent/KR850000710B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

내용 없음No content

Description

번지수 범위가 큰 메모리소자로된 다수 벵크(BANK)메모리 시스템에서 일정번지수 영역을 공통벵크로 사용하는 회로A circuit using a constant address area as a common beneficiary in a multiple BANK memory system with a large address range memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 메모리뱅크 운영상태도.1 is a conventional memory bank operating state diagram.

제2도는 종래의 회로도.2 is a conventional circuit diagram.

제3도는 본 발명의 메모리뱅크 운영상태도.3 is a memory bank operating state of the present invention.

제4도는 본 발명의 회로도.4 is a circuit diagram of the present invention.

Claims (2)

번지수범위가 큰 메모리소자(M1~M8다수의 메모리 벵크(BANK 0,1,2,3)를 구성하되, 상기 메모리벵크중 1개의 메모리벵크의 상위 또는 하위 주소영역을 공통으로 선택되도록하고, 나머지 메모리벵크의 같은 주소영역은 선택되지 않도록 연결한번 지수범위가 큰 메모리소자로된 다수벵크메모리 시스템에서 일정 번지수 영역을 공통벵크로 사용하는 회로.A memory device having a large address number range (M 1 to M 8 ) constitutes a plurality of memory banks BANK 0, 1, 2, and 3, and selects an upper or lower address area of one of the memory banks in common. A circuit using a predetermined address area as a common bank in a multiple-bank memory system having a memory device having a large exponential range once connected so that the same address area of the remaining memory banks is not selected. 제1항에 있어서 상기 메모리벵크(BANK 0,1,2,3)중 1개의 메모리벵크의 공통영역인 A부분만 선택되도록하되, 이는 MPU의 최상위 주소비트(A14,A15)를 디코딩하려는 디코더 (D1)와메모리벵크 선택신호(BNo,BN1)를 디코딩하는 디코머(D2)을 두고 이에 메모리선택제어신호(Ms)를 받아 낸드케이트(N1,2)를 통하여 멀티플렉서(MUX)를 동작시키되, 이 멀티플렉서 (MUX)는 공통부분A로 쓸려는 메모리벵크의 수소만 지정되도록 입력단(B1B2B3)을 공통으로 연결하여서된 것.The method of claim 1, wherein the memory bengkeu (BANK 0,1,2,3) but to select only the common region of a portion A of the one memory bengkeu of which to decode the most significant address bits (A 14, A 15) of the MPU A decoder (D 1 ) and a decoder (D 2 ) for decoding the memory bank selection signals (BNo, BN 1 ) are placed therein, and the multiplexer (MUX) is received through the NAND gates (N 1 , 2 ) which receive the memory selection control signal (Ms). ), But the multiplexer (MUX) is connected to the input terminals (B 1 B 2 B 3 ) in common so that only hydrogen of the memory bank to be written to the common part A is designated. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019830000024A 1983-01-06 1983-01-06 Memory bank system KR850000710B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019830000024A KR850000710B1 (en) 1983-01-06 1983-01-06 Memory bank system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019830000024A KR850000710B1 (en) 1983-01-06 1983-01-06 Memory bank system

Publications (2)

Publication Number Publication Date
KR840003373A true KR840003373A (en) 1984-08-20
KR850000710B1 KR850000710B1 (en) 1985-05-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830000024A KR850000710B1 (en) 1983-01-06 1983-01-06 Memory bank system

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KR (1) KR850000710B1 (en)

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KR850000710B1 (en) 1985-05-15

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