KR830003758A - Signal conversion circuit - Google Patents

Signal conversion circuit Download PDF

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Publication number
KR830003758A
KR830003758A KR1019800003356A KR800003356A KR830003758A KR 830003758 A KR830003758 A KR 830003758A KR 1019800003356 A KR1019800003356 A KR 1019800003356A KR 800003356 A KR800003356 A KR 800003356A KR 830003758 A KR830003758 A KR 830003758A
Authority
KR
South Korea
Prior art keywords
conversion circuit
signal conversion
memory element
adder
circuit according
Prior art date
Application number
KR1019800003356A
Other languages
Korean (ko)
Other versions
KR830001722B1 (en
Inventor
료오지 이마제끼
에쓰오 야마자끼
다까오 사사끼
Original Assignee
이나바 세이우에몽
후지쓰 후아낙크 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 이나바 세이우에몽, 후지쓰 후아낙크 가부시끼가이샤 filed Critical 이나바 세이우에몽
Priority to KR1019800003356A priority Critical patent/KR830001722B1/en
Publication of KR830003758A publication Critical patent/KR830003758A/en
Application granted granted Critical
Publication of KR830001722B1 publication Critical patent/KR830001722B1/en

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form

Abstract

내용 없음No content

Description

신호 변환회로Signal conversion circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 실시예 1의 주요부를 설명하는 블록도, 제3도는 본 발명의 다른 실시예의 주요부를 설명하는 블록도.1 is a block diagram for explaining the essential part of Embodiment 1 of the present invention, and FIG. 3 is a block diagram for explaining the main part of another embodiment of the present invention.

Claims (3)

시각 펄스에 따라 그속에 순차적으로 입력신호를 필기하기 위한 n메모리요소, n메모리요소의 내용을 함께 가산하기 위한 가산기 및 가산기로부터의 가산된 출력을 1/n로 분할하기 위한 디바이더로 구성된 신호 변환회로.A signal conversion circuit comprising an n memory element for writing an input signal sequentially in accordance with a time pulse, an adder for adding together the contents of the n memory element, and a divider for dividing the added output from the adder into 1 / n . 이전 레지스터를 형성하기 위해 n메모리요소가 캐스케이트 접속된 특허청구의 범위 1항에 따른 신호 변환회로.A signal conversion circuit according to claim 1, wherein n memory elements are cascaded to form a previous register. 주사기에 의해 주사된 입력신호를 그속에 필기하기 위해 메모리요소가 배치된 특허청구의 범위 1항에 따른 신호변환회로.A signal conversion circuit according to claim 1, wherein a memory element is arranged to write therein an input signal scanned by a syringe. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019800003356A 1980-08-25 1980-08-25 Signal conversion circuit KR830001722B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019800003356A KR830001722B1 (en) 1980-08-25 1980-08-25 Signal conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019800003356A KR830001722B1 (en) 1980-08-25 1980-08-25 Signal conversion circuit

Publications (2)

Publication Number Publication Date
KR830003758A true KR830003758A (en) 1983-06-22
KR830001722B1 KR830001722B1 (en) 1983-08-31

Family

ID=19217525

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019800003356A KR830001722B1 (en) 1980-08-25 1980-08-25 Signal conversion circuit

Country Status (1)

Country Link
KR (1) KR830001722B1 (en)

Also Published As

Publication number Publication date
KR830001722B1 (en) 1983-08-31

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