KR830000609B1 - Electronic instrument - Google Patents

Abstract

No content.

Description

Electronic instrument

1 is a principle block diagram based on the system basic concept of the present invention.

2 is an envelope mode diagram used in FIG.

3 is a basic explanatory diagram of the sound wave waveform setting method of FIG.

4 (a), (b), (c) are diagrams showing relative changes in the sound waveform according to the envelope coefficient values.

5 (a), (b), (c), (d), (e), and (f) are explanatory diagrams of logic symbols used in this embodiment.

6 is a drawing connection state diagram of FIGS. 7 (a), (b), (c) and (d).

7 (a), (b), (c) and (d) are specific circuit diagrams of the system heart of the present invention.

FIG. 8 is a time chart showing a selective output state corresponding to the scale associated with the block address state in FIGS. 7 (a) and 7 (b).

FIG. 9 is a time chart showing the addition timing output for each octave associated with the synchronization register of FIG.

FIG. 10 is an explanatory diagram of the number of scale steps in FIGS. 7 (a) and 7 (b).

11 (a), (b) and (c) are time charts illustrating waveform periods for each scale in the present system.

FIG. 12 is a detailed view of the shift memory in FIG.

Fig. 13 is a diagram showing the type of volume curve used in this system.

14 is a combination explanatory diagram of the volume curve form for each α and β in the present system.

Fig. 15 is an explanatory diagram of designating block addresses for alpha and beta of a sound wave waveform in the present system.

FIG. 16 is a detailed view of the waveform program designation section in FIG.

FIG. 17 is an explanatory diagram of output additions in FIG.

18 is a time chart of the output cycle counter in FIG.

19 is a basic related explanatory diagram of the number of cycles used in the description of FIG.

20 is an explanatory diagram of a cycle mode designation state for each α and β in the present system.

21 is a detailed diagram related to the periodic mode for each α and β in the present system.

22, 23, and 24 are waveform diagrams for explaining tremolo control used in the present system.

25 (a) and 25 (b) are waveform diagrams illustrating expression negative tremolo control used in the present system.

FIG. 26 is an explanatory view of the drawing connection state of FIGS. 27 (a) and (b).

27 (a) and 27 (b) are concrete circuit diagrams of a control unit which controls FIGS. 7 (a), (b), (c) and (d).

28 (a) and 28 (b) show the quartet relationship time chart in FIG. 27 (a).

29 (a) and 29 (b) show time charts associated with keying timing and registration signals in FIG. 27 (b).

30 is an explanatory diagram of a time clock selection state by various clock time generation circuits.

31 shows the vibrato control time chart in the present system.

32 is an explanatory diagram of various volume granularity states with time-dependent change of attack.

33 is an explanatory diagram of various volume change states accompanying the decay of the decay over time;

FIG. 34 is an explanatory diagram of the state of volume change according to the change over time of release time.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument using digital technology. In the electronic musical instrument, a sound source frequency corresponding to each playing key is determined based on an average scale. Is divided into a plurality of frequency division circuits, and there is a so-called frequency division sound source system that obtains each sound source frequency by selecting a division ratio combination of the frequency division stages.

Then, the waveform is read out from the sound waveform memory, for example, at the sound source frequency corresponding to the playing key.

In any case, the conventional method is to create a single sound mainly, and in the case where a chord by simultaneous operation of a plurality of playing keys is possible, a parallel cycle processing circuit is provided for each of the simultaneously operated plurality of playing keys. The configuration is enlarged.

It is also conceivable that one scale period control circuit can be used time-divisionally for simultaneous operation of multiple performance keys. In this case, however, the n performance keys have a resolution of 1 / n. The processing is controlled once every n hours, and considering this, it is a complicated circuit configuration to generate the musical sound by setting the scale period for each playing key, so it is still optimal and simple scale period to enable the chord performance by digital technology. Control technology is not established.

Moreover, in electronic musical instruments such as electron organs, electronic pianos, and scene sizers, in order to obtain a musical sound having a large number of tones, it is important to create various musical waveforms corresponding to the musical sound.

Therefore, various methods of setting the sound wave waveform have been considered. Example: A sinusoidal wave from the fundamental wave to the high frequency of the required order in the harmonic order is divided into a plurality of storage devices in order by storing the amplitude-displayed digital signal, respectively, and the sinusoidal wave of the desired order in accordance with the sound specification. To simultaneously read, synthesize, and set a sound wave waveform of a predetermined shape, and to preset and store basic waveforms such as a triangular wave, a sine wave, a square wave, and a stationary wave in a fixed memory digitally in a waveform storage device; Acoustic Wave Form It is a digital or analogue fixed memory.

On the other hand, in order to make the sound sound similar to a predetermined musical instrument sound, not only the sound wave waveform is similar, but also the volume envelopes such as granularity and arrival are overlapped. The sound wave waveform setting by digital technology which is effective for analog large scale integrated circuit (LSI) by analog technique or need complicated control circuit without overlapping effective volume envelope by digital technology The reality is that technology is not yet established.

Again, in general, the tone of a musical sound generated by a natural instrument has a waveform based on its frequency specifications (e.g., harmonic structure at steady state) and a volume envelope from granularity to attenuation, but in fact, The musical sound pronounced in the musical instrument is different from other books, namely, the delay of the high frequency component and the subtle fluctuations of the high frequency component in pronunciation, and the overlapping and attenuation of the vocal components in the pronunciation found in the musical instrument. As a change of tone, the tone has distinctive features.

Therefore, in order to remove the mixed light from the electrical signal from the sound sound pronounced in the electronic musical instrument and to give a natural feeling, it is necessary to give the above-described overtone structure change to the waveform and the volume envelope.

However, in the conventionally provided electronic musical instruments, for example, in electronic electronic organs, no harmonic structure change is given to each sound, and a volume envelope is simply superimposed on a sound wave waveform that is uniquely defined. Even if a musical sound such as Chenvaro is preset, the sound waveform is a single waveform that is set in advance.

An example of a thin-sized instrument, a thin-sized instrument: an analog filter operation such as a VCF (voltage-controlled filter) changes the filter band over time, but the direction of change is from "low frequency to high frequency". Or "high frequency to low frequency", and it is a relatively simple operation, and in order to express a more natural feeling, various effect devices must be used again.

Moreover, in enabling chord playing, filters and effects devices must be formed for each key, and the circuit configuration becomes complicated and large, and it becomes an extremely expensive instrument.

As described above, in the conventional electronic musical instrument, the change over time of the harmonic structure itself is made by using analog technology, and there are various problems to apply it to the chord performance as it is. It is a reality that a sound wave setting technology suitable for LSI (large-scale integrated circuit) has been not established yet using the furnace technology.

In addition, in general, the sound quality of a musical sound generated by a natural instrument is an important factor in the waveform by the frequency spectrum (e.g., harmonic structure in a steady state) and the volume envelope from granularity to attenuation. The sound of sound produced in musical instruments is different from other elements, such as the delay of high frequency components during sounding and the subtle fluctuations of harmonics in sound, and the high frequency of attenuation of sound components found in sounding instruments. Changes in the overtone structure due to the metal's dissipation, etc. result in the distinctive tone characteristics of each musical instrument.

Therefore, in order to remove the mixing caused by the electric signal from the musical sound generated in the electronic musical instrument and to impart a natural feeling, it is necessary to give the above-described change of the overtone structure to the other of the waveform and the volume envelope.

Thus, in an example of an electronic musical instrument that has been provided in the past: in Orgen, a desired sound wave waveform is obtained by arbitrarily combining desired harmonics with a drop burr, a doublet, or the like, and a volume envelope is overlapped to generate a predetermined sound. will be. In this case, however, the sound wave waveform is uniquely set by the combination of the above-mentioned drop burrs or daubrets, and even if two sounds are combined, it is impossible to control each sound and change the overtone structure over time. You can't get effective music because you can't get it.

The present invention was conceived in light of the point of view, and in an electronic musical instrument for setting the period of the counting means corresponding to the musical scale of the playing key, two steps are performed by the period control by the period setting and the micro period control. The present invention provides an electronic musical instrument capable of controlling the period of the scale by a single digital technology that is optimal for process control according to the dynamic circulation of a plurality of playing keys.

In addition, the present invention provides an electronic musical instrument capable of digitally controlling not only the control of the sound wave waveform, but also the volume control in which the granularity and the arrival curve of the volume are different, such as a piano and a guitar.

In addition, the present invention can simultaneously indicate and synthesize a plurality of different waveforms, and can also vary the granularity and arrival curve of the volume between the waveforms as well as the tops of the waveforms. It is to provide an electronic musical instrument that can obtain an effective tone.

In addition, the present invention can simultaneously have a plurality of different waveforms and synthesize them, and not only the difference of the waveforms but also the period between the different waveforms, except for the relationship of M: N, the sound tone is effectively changed over time. It is to provide an electronic musical instrument that obtains the sound to have.

Hereinafter, the electronic musical instrument embodiment of the present invention will be described in detail. Referring to FIG. 1, the memorial concept of the system of the present invention will be described with reference to the original configuration diagram of FIG. 1. In FIG. 1, 1 represents a playing key group (eg, octave, A pitch input code register that stores different pitch input codes in response to each key operation of the 48 pitch keys enabling the 12th basic pitch range, and this pitch input code is provided to the scale period setting circuit 2 to control the scale clock frequency. Supplied.

Therefore, in the scale period setting circuit 2, different scale clock frequency signals are generated in accordance with each of the pitch input codes, and are supplied as a coefficient complementary signal to the period coefficient circuit 3 which counts the period of the sound wave basic one cycle in multiple steps.

Periodic relay circuit 3 preferably constitutes a counter that counts in binary. In this example, "1", "2", "4", "8", "16", "32", "64", "128" It is a circuit which obtains the count state of "256" from "0" to "255" of decimal number, and accordingly, 1 cycle of ups and downs of a sound wave waveform corresponds to each count value of "256" binary. It is displayed by the coefficient staff of "256".

This " 256 " coefficient step blocks one or more characteristic step numbers as one unit and divides one cycle into m blocks. In other words, in this embodiment, m-16 is divided into "16" blocks, and one block is displayed in the counting step of "16" (counting state of "0" to "15" in decimal). The 4-bit count value indicated by the weight stages of the "16", "32", "64", and "128" of the counting circuit 3 can be correspondingly assigned to the block address of "16" over time. It is made from table to table.

TABLE 1

The output of each 8-bit stage of the period counting circuit 3 is supplied to the scale period setting circuit 2 described above, and as described later, the output frequency control of the scale clock frequency signal corresponding to the pitch input code is performed.

Again, the upper four bit weights "16", "32", "64", and "128" of the period counter circuit 3 are supplied to the waveform program designator 5 for each block as a block address signal of 16 blocks by opening the decoder 4. do.

This waveform program designation unit 5 is represented by one sound wave waveform "0" to "15".

The block address is used to indicate the amplitude and the amount of change in amplitude of the waveforms (absolute values of "0", "1", "2" and "4" in this example) with + (down) and-(down). The amplitude variation (derivative value) is called a derivative coefficient value.

The differential count value designated by the waveform program designator 5 for each block address and the indication signals of "+" and "-" are sequentially outputted to the block address signal at the decoder 4 and supplied to the multiplication circuit 6.

In the multiplication circuit 6, a volume curve creation counter (hereinafter referred to as an envelope counter) that digitally controls the volume control for increasing or decreasing the volume of the performance as time passes from the time when the key is operated, 7 is a control value ( Counter value) is supplied to multiply in synchronism with the block address according to the differential coefficient value of waveform program designator 5 and its "+" and "-" instructions.

The above-described envelope counter 7 selects from among various volume curves (hereinafter referred to as envelope bra) modes described below, and assigns a specified clock (called an envelope clock) to an attack and decay (described below). Decay) or up / down coefficient control according to the volume control status of the release.

That is, these are integer values of the count values "0"-"31" of the envelope counter 7, and are called these envelope count values (denoted by E). An example of an envelope mode is shown in FIG.

Thus, the differential coefficient specified in advance for each block address by waveform program designator 5 designates the constant multiple of the envelope coefficient value E shown in the second figure to be accompanied by "+" or "-". The multiplication circuit 6 generates ± (differential coefficient value × envelope coefficient value E).

That is, FIG. 3 illustrates one example. The relationship between the envelope coefficient value E for each block differential coefficient value of block addresses "0" to "15" of one sound wave waveform is shown. Envelope coefficient value E in the case of FIG. 2 is the amount of change in the relative magnitude of the sound wave waveform including the volume control value at the time points (indicated by the X table in FIG. 2) at "5", "10", "20", and "30". Becomes as shown in FIG. 4 (a), (b), (c).

Of course, the relative change in the acoustic waveform is eventually shifted as the envelope coefficient E over time.

In the present embodiment, on the other hand, only the block address "0" does not specify the differential coefficient values "+" and "-", and the change amount is always zero.

The above-mentioned output of the multiplication circuit 6 is supplied to one input side of the Arthur 8, and the output of the eighth output is fed back to the other input side of the Arthur 8 by opening the accumulator 9, so that the current multiplication output value of the current block As the amount of change is accumulated, the acoustic waveform diagrams of FIGS. 3, 4, (a), (b), and (c) described above are taken out as the output of the accumulator 9.

The output of the accumulator 9 is pronounced as a pitch corresponding to the playing key operated by the speaker 11 by opening the D / A converter (digital-analogue converter).

In more detail, the above-mentioned statement, that is, the volume control means will be described in detail. First, the height of the sound corresponding to the playing key operated in FIG. 1 depends on the content of the pitch input code set in the pitch input code register 1. FIG. Is determined.

The set pitch input code changes the frequency of the output clock of the scale period setting circuit.

This output clock is supplied to a 256-bit counter, i.e., the period count circuit 3, eventually; When the pitch is high, the output clock frequency becomes high, and accordingly, the counter 3 also shortens the period for counting 256 clocks, and the scale period corresponding to the short note, that is, the high pitch, is set to circuit 2. One note period set here is divided into 16 blocks by the decoder 4.

The output of the decoder 4 is supplied to the waveform program designation unit 5 as a block address signal, and the absolute value of the change amount "0", "1", "2" and "4" of the waveforms of the waveforms at the corresponding address position is "+". It is read with a sign of "-" and supplied to the multiplication circuit 6. This is called differential coefficient.

The multiplication circuit 6 is supplied with a value representing the basic portion of the volume change curve from the counter 7.

The counter 7 gives the multiplication circuit 6 a control value for digitally changing the volume with the passage of time when the playing key is operated.

The counter 7 also counts up and down the specified clock in accordance with several different envelopes (volume curves).

Example: As shown in Fig. 2, when the volume curve mode instruction is "Attack", it is UP counted in a straight line from "0" to "30", and when it is decay, it counts nothing and counts the count value of "30" and release. At that time, the count is counted down from "30" to "0".

As in the second illustration, the count value of the envelope counter 7 is an integer value of 32 units from "0" to "31", which is the envelope count value E on which the volume change is based. Example: When the envelope count value "E" when the block address is "1" is E = 5, and the derivative value at this time is "+2" in Fig. 3, the volume control value (output value of the multiplication circuit 6) Becomes "+2.5" like the waveform in the middle of FIG.

In addition, when E = 10, it becomes "+2.10" like the lower waveform of FIG. As shown in Fig. 4 (b), the larger the value of "E" is, the larger the change in waveform is.

The output of the multiplication circuit 6 is accumulated for each block in the Arthur 8 and the accumulator 9, and is finally taken out as a sound wave waveform in Figs. 4 (a) and (b) or the output of this accumulator 9.

In addition, when the period counting means is described, the period counting means is to digitally set the pitch of a musical note in response to an operated playing key. Here, the pitch is set as a period which is the inverse of the frequency of the musical tone. That is, the shorter the period, the higher the frequency of the generated sound. Regardless of the pitch, the period of the musical sound generated in FIG. 1 is set to the length and length of the counting time from the counter 3 " 0 "

Therefore, when a high pitch playing key is operated, the clock frequency supplied from the pitch cycle setting circuit 2 to the count 3 is increased by the output of the pitch input code register 1, and a counter from "0" to "255" is made as soon as that.

Therefore, one period of the sound wave waveform is set by the counter 3 as described above, and this period is set by the counter 3, and this one period is set to "16", "32", "64" and "128" among the counters. The output is divided into 16 blocks using 4 bits of output. This is the same as the first indication. That is, the count 3 is from 0 to 15, and the upper 4 bits of the counter 3 are all 0, but when the count is 16, the bit is neutralized at 19. The count is 1. The lower five bits of 3 become `` 10000 ''.

This corresponds to the upper four bits "1000" indicated by the block address "1" in the first table.

When the count value of the counter 3 reaches "32", the lower 6 bits of the counter 3 become "10000", which corresponds to the upper 4 bits "0100" indicated by the block address "2" of the first table. In this manner, each time the count value of the counter 3 is increased by "16", the upper 4 bits change as shown in the first table, and the block address is increased by "+1".

In this way, one period of the acoustic waveform is divided into m blocks (here m = 16).

For each block divided into m blocks as described above, the positive or negative integer value output from the waveform program designation section 5 and the envelope E output from the counter 7 are multiplied by the multiplication circuit 6, and the waveform volume is accumulated by the accumulator 9. Thus controlled sound signal output is obtained.

In this way, the sound wave waveform can be divided into multiple blocks by arbitrarily instructing the granularity and arrival differential coefficient of the waveform for each block, and at the same time, the volume control can be performed in relation to the envelope coefficient value. .

Next, the present invention will be described in detail in a specific configuration, but the description of the logic symbols used in the following drawings is shown in FIGS. 5A, 5B, 4C, 3D and 5E. Among them, logical expressions, truth tables, and general logic symbols corresponding to each logic symbol are described, and examples of combination circuits are described.

Therefore, it is particularly important to note that the inverter symbols attached to the input lines of the ora gate and the end gate are not valid only for the gate, and refer to the example of the combination circuit of the angular plane for details.

FIG. 6 is a drawing combination state diagram of FIGS. 7 (a), (b), (c) and (d), and 20 is input of 4 bits ('1', '2', '4', '8' weight). The scale register consists of eight tines of memory that shifts the output stage to the 4-bit parameter in the direction of the arrow, and 21 is the input / output terminal of 2 bits ('1' and '2' weights). This is an octave code register consisting of eight line memories shifted to a two-bit paratlet, and it stores the scale input code and octave input code corresponding to each operated key.

That is, the scale input code and the octave input code corresponding to the generation of the input instruction signal associated with the operation of the performance key described below are connected to the AND gates 22-27, OA gates 28-1 to 28-4, and OA gates 29 and 30. In addition, each scale code register is input to the octave code register 21.

The input scale code and octave code (hereinafter referred to as pitch code) are parametrically shifted in the direction of the arrow by the shift pulse Φ (the basic clock of this system), and each input is inhibited after 8% of the shift time. The so-called dynamic shift operation is performed again by cyclically inputting the gates 31-1 to 31-4 and the inhibit gates 32 and 33.

In addition, the pitch codes in the registers 20 and 21 are controlled to be erased in response to the inhibit gates 31-1 to 31-4 and the inhibit gates 32 to 33 synchronized with the new input instruction signal.

In addition, the pitch code register 20 and the octave code register 21 have eight line memories. For example, even if up to eight performance keys are operated simultaneously, the corresponding scale input code and octave input code are synchronized with the input instruction signal. By sequentially inputting according to the timing order, dynamic shift cyclic holding can be performed.

That is, eight sounds are controlled in time and division. Scale codes and octave codes in the present system are added to the second and third tables.

TABLE 2

TABLE 3

34 denotes a period for counting one sound wave waveform (cycle) in accordance with pitch codes cyclically stored in the electric scale code register 20 and the octave code register 21, similar to the scale code register 20 and the octave code register 21 described above. It consists of eight line memories which shift to dynamic one by one by the shift pulse (phi) in an arrow direction.

This period coefficient register 34 is basically a 4-bit hexadecimal number ("0" to 1 shown in Table 1), which stores a coefficient value corresponding to each block address in order to divide one cycle of a sound wave waveform into "16" blocks according to a time course. Block coefficient register 34-1 corresponding to the block address of the block " 16 " of " 15 ", and 4 bits 16 for controlling the number of steps for each block described later in order to extract the addition timing signal for commanding block coefficient enhancement. Vibrator Coefficient Register TC Register) 34-2 and Block Coefficient Register 34-1.

The contents of each line memory coefficient generated at each output of the block coefficient register 34-1 and the cycle number register 34-3 pass through the waveform program designation unit 35 as it is for each block to be described later. Circulation-holding is performed for each dynamic by opening the gate-inhibit gates 37-1 to 37-7, and Arthur 36, which counts the binarial coefficients in this cycle, is "+1" when the addition timing signal is generated. Will be.

In addition, the 4-bit ("1", "2", "4", and "8" weight) outputs of the block coefficient register 34-1 (see Fig. 8A) designate a specific block address among the block addresses of "16". Supplied to the block state detection circuit 38 for detection, and the 0 block address signal shown in FIG. 8 (b) in the output? Is output to the output signal shown in FIG. 8 (c) in the outputs ①, ②, ③, and ④, respectively. It is taken out.

The outputs 1 through 4 are supplied to the scale step matrix circuit 39 which determines the step correction number for each scale to be described later.

의 조건으로 「0」블록 어드레스 신호를 출력 ①은 웨이트「1」출력을 그대로 취출하고 기수 블록어드레스신호를 출력 ②은 웨이트「1」가 "0"이며 또 웨이트「2」가 "1"이다.That is, the output ⓞ of the block state detection circuit 38 is connected to the inverted end gate 38-1, the inhibit gates 38-2, and 38-3 in series so that the weights " 1 "," 2 "," 4 ""8" is "0" at the same time

Outputting a block address signal of " 0 " under the condition of " 1 " outputs the weight " 1 " output as it is, and outputs an odd block address signal " 2 " and " 1 "

2]의 조건을 취하는 인히빗트 게이트 38-4에 의하여「2」, 「6」, 「10」, 「14」블록어드레스신호를 출력 ③은 웨이트 「4」가 "1"이고 또 웨이트「2」, 「1」이 동시에 "0"인 [4.

.

]의 조건을 취하기 위하여 인히빗트 게이트 38-5, 38-6을 순차 직렬 접속하여 「4」, 「12」블록어드레스신호를 출력 ④은 웨이트「8」이 "1"로서 웨이트「4」, 「2」, 「1」이 "0"인 [8.

.

.

]의 조건을 취하기 위하여 인히빗트 게이트 38-7-~38-9를 순차 직렬접속하고 「8」블록 어드레스 신호를 각각 출력하는 것이다.[

[2], "6", "10", and "14" block address signals are output by the inhibit gate 38-4, which takes the conditions of 2). The weight "4" is "1" and the weight "2". , Wherein "1" is "0" at the same time [4.

.

[4] and 12 block output signals are output by connecting Inhibit Gates 38-5 and 38-6 sequentially in order to take the condition of ④. The weight "8" is "1" and the weight "4", " 2 "," 1 "is" 0 "[8.

.

.

In order to take the condition of], the Inhibit Gates 38-7 to 38-9 are serially connected in series, and the "8" block address signals are output respectively.

On the other hand, the output of the 4-bit end of the Synchronization Coefficient Register (TC register) 34-2 is connected to the input of Arthur 40, and the output of the 5-bit end of this 40 is connected to the subtractor 41, and again the 4-bit output of the subtractor 41 is the circulating control gate. Inhibit gate 42-1 42-4 is opened to return to the input shaft of the corresponding bit end.

The output of each stage of the synchronization coefficient register 34-2 is an addition timing generation circuit 43 that outputs the addition timing signal to be supplied to the above-mentioned Arthur 36 according to each octave, and the 3-bit output of the "1", "2", and "4" weights. It is supplied to the weight shift circuit 44 mentioned later.

In addition, the addition timing generating circuit 43 and the weight shift circuit 44 generate an octave code deco that generates the _first to fourth octave signals 0 ₁ to 0 ₄ according to the output state of two bits to be output from the octave code register 21 described above. The output signal of odd 45 is combined. That is, the inverted and gate 45-1 of the octave code decoder 45 is the first octave signal 0 ₁ , the inhibit gate 45-2 is the second octave 0 ₂ , and the inhibit gate 45-3 is the third octave signal. 0 ₃ and the end gate 45-4 output the fourth octave signal 0 ₄ in response to detecting the code state shown in FIG. 3.

The octave signals 0 _{1 to} 0 ₃ are supplied to the AND gates 43-1, 43-2, and 43-3 of the addition timing generation circuit 43, respectively, and the octave signals 0 ₂ are supplied to the AND gate 44-1 of the weight shift circuit 44, respectively. ₃ is supplied to the AND gates 44-2 and 44-3, and the octave signal 0 ₄ is supplied to the AND gates 44-4, 44-5, and 44-6.

In the AND gate 43-1 of the counting timing generating circuit 43, the " 1 ", " 2 " and " 4 " weight output signals of the synchronous coefficient register 34-2 are coupled to each other through the oragate 43-4 and 43-5. The output signals of the "2" and "4" weights output from 43-4 are coupled to the AND gate 43-2, and the output signals of the "8" weight are coupled to the AND gate 43-3.

The outputs of these AND gates are coupled to the inhibit gates 43-6, 43-7, and the invertad AND gate 43-8, respectively, and the output signals of the invertad and gate "8" are combined again.

These inadvertit and gate 43-8 outputs are connected to the inhibit gate 43-7 and the output of the inhibit gate 43-7 is connected in series to the inhibit gate 43-6. One subtracted timing signal is obtained.

That is, in the counting state of the synchronization coefficient register 34-2 to the tine memory as shown in FIG. 9 (as shown in FIG. 9 (a), on the output lines ⓐ, ⓑ, and ⓒ in the addition timing generating circuit 43). The output signals shown in Fig. 9 (b) are shown in Fig. 9 (c) in the Inhibit Gate 43-5 output ⓓ in synchronization with the respective outputs of the octave signals 0 _{1 to} 0 ₄ in the octave code decoder 45. It is taken out as an output signal.

That is, in the first octave signal 0 ₁ , the synchronization coefficient register 34-2 is only at the time of "0" count, and in the second octave signal 0 ₂ only at the count of "0" and "1", in the third octave signal 0₃, it is "0". "... only when the coefficient" 3 ", the fourth octave signal O ₄ will be in the" 0 "to output as the timing signal is added by the adding the timing generating circuit 43 only when the coefficient of" 7 ".

The addition timing signal thus obtained is supplied as an "+8" addition command signal to Arthur 40 and a gate open signal to AND gate 46-1 46-4, and a +1 addition command signal to Arthur 36 of FIG. It is also applied as.

On the other hand, the octave signals 0 ₁ , 0 ₂ , 0 ₃ , 0 ₄ output from the octave code decoder 45 pass through the above-described addition timing generating circuit 43 and are respectively added to the subtractor 41 in FIG. "-2", "-4" and "-8" command signals are supplied.

Therefore, in the cyclic loop of the cycle count register 34-2 → Arthur-40 → subtractor 41 → synchronous machine register 34-2, basically, the addition timing signal described above with the counter 40 is counted for the counter memory output from the synchronization coefficient 34-2. In addition, "+8" is added, and the addition result is a numerical value corresponding to the octave signals 0 _{1 to} 0 ₄ ("-1" for the octave signal 0 "," -2 "for the octave signal 0 ₂ , and"-"for the octave signal 0₃). 4 " and the octave signal 0 " are subtracted by " -8 ").

In step 40, the step correction number corresponding to the sound scale at AND gates 46-1 to 46-4, which are opened in synchronization with the generation of the addition timing signal described above, is adjusted to the block coefficient state of the block coefficient register 34-1 described above. It is supplied by the RIX circuit 39.

That is, one cycle of the sound wave waveform becomes a "16" block address according to the time course, and each block address becomes a clock number eight times or more (eight times or more of the basic clock period) of the basic clock?. It can be said that one step of the basic clock ø. Corresponds to one sound wave waveform step, and eventually each clock address is 8 steps or more.

Among the "16" block addresses of a single acoustic wave type, eight steps each are set to 128 steps in total, which is the highest sound in this system (actually, as described later, 130 steps are the highest sound in the system (C # 7)). Is).

관계가 되도록 증가하게함에 따라 순차 음계에 맞추어 긴 주기가 되어 저음을 얻게 된다.This gives you 12 steps between each step from the highest step number to one octave down.

As the relationship increases, the bass is long in time with the sequential scale.

The scale step matrix circuit 39 of FIG. 7B basically divides the period set value by the counting (+) value of the period coefficient register 34 into a tide and a fine and does not match the scale. It stores the control value which makes the period control.

Thus, the output signals 1, 2, 3 and 4 of the block state detection circuit 38 described above and the 4-bit output of the scale code register 20 are input.

In the example of the scale step matrix circuit 39, an AND function matrix circuit 36-1 for detecting the code state of each of the 12 scales shown in the second table is formed, and 12 output lines ①-⑫ corresponding to the scale are shown in FIG. The same C scale detection line-C # scale detection line) is taken out and connected to the AND gates 39-4 to 39-14 through the first or second functional matrix circuit 39-2 and the second or second functional matrix circuit 39-3. .

The first OR function matrix circuit 39-2 controls the number of attempts of "0, 0, 1, 1, 2, 2, 3, 4, 5, 5, 5, 6, 7" in order of C, C "for each scale. to output the hydrolysis step to the output line of the third cord to the state of _{X 1, X 2, X 3} , the hydrolysis step is that each of the singer "16" block for each scale.

That is, it is as showing in a 4th table | surface.

TABLE 4

The second oar function matrix circuit 39-3 is a circuit for giving a step correction mantissa corresponding to the tide to the one cycle angular scale of the sound waveform. In this case, the step correction mantissa value is applied to the collective average at the timing of the plural block addresses. In order to select ①-④ output from the block state detection circuit 38 for each scale, the block address indicated by "0" is selected according to the scale as shown in FIG.

In other words, the plurality of selected block addresses is the tide control timing.

The selection signal is supplied to the AND gates 39-4 to 39-14 corresponding to the scale.

Again the output of the AND gate 39-4 - 39-14 are connected to the series circuit of the gate Iowa 39-15 - 39-25 in the final Iowa output of the gate line X 39-25 ₄ scale every "1" to "15" in A "+1" correction signal is output to the selected block address.

In other words, the step correction number to be output from the scale step matrix circuit 39 becomes a periodic control value, which is [step correction number matching the divisor + plus the step correction number according to the tide].

Thus, the output signal from the output line of the scale step matrix circuit 39, X ₁ , X ₂ , X ₃ , and X ₄ is an inhibit gate that opens when the zero block address signal is output from the block state detection circuit 38. It is supplied to 47-1 ~ 47-4.

Inhibit gates 47-1 to 47-3 are supplied to AND gates 46-2 to 46-4, respectively, with corresponding oragates 48-1 to 48-3 corresponding to the outputs of inhibit gate 47-4. It is supplied to the gate 46-1.

Therefore, in addition to the "0" block address signal, the step correction singer to be "+1" with respect to the above-described block address in synchronism with the generation of the above-mentioned addition timing signal is supplied to the adder 40 as the addition signal.

When the "0" block address signal output from the block state detection circuit 38 is generated, a "+2" correction value is applied by opening the OR gate 48-4 and the AND gate 46-2, and in synchronization with the generation of the addition timing signal described above. +8 "is added and simultaneously.

Eventually, the added value for each block address by the scale supplied to Arthur 40 is the highest octave (fourth octave signal 0 ₄ ) as shown in the tenth illustration, and the value corresponds to the number of steps (basic clock number) in each block address. The number of steps of one cycle of acoustic sound waves of each scale is the same as that of the Uran diagram of FIG.

관계가 되어 있는 것이다.That is, the number steps between each scale is 12

It is a relationship.

Of course, the above-described addition timing supplied to the Arthur 40 differs depending on the octave synths 0 _{1 to} 0 ₄ and differs by the chidaoctave signals 0 _{1 to} 0 ₄ subtracted by the subtractor 41 and the octave is low (the octave signal 0 ₁ direction). As the load increases, the period of one cycle of the sound wave waveform becomes longer.

Thus, the period coefficient register 34, the scale code register 20, and the octave code register 21 described above use eight line memories, and one cycle in the direction of the arrow of each register is cycled by 8 시프트 shift pulses. The control is performed based on one cycle, and according to the present system, the shift memory described below can be used to control the register to any position within one cycle.

In other words, in the present system, the shift memory 49 for shifting the basic clock ø ₀ with eight line memories in the direction of the arrow is placed on the generating unit side (just before the D / A conversion circuit) in the output section 7c. It should be arranged.

The shift memory 49 is composed of eight lines of memory by a code expressed by three bits (" 1 ", " 2 " and " 4 " weights) outputted from the weight shift circuit 44 described above in FIG. Which is addressed, and addresses "0" to "7" are sequentially in the line memory near the output side.

In other words, by this address designation, a maximum 8 ° ₀ shift time delay is possible.

The address of the shift memory 49 is designated when the addition timing signal supplied to the addition timing generation circuit 43 in FIG. 7A is supplied by adding the AND gates 50 and 51 in FIG. 7C. The output signal of the AND gate 51 to be applied to is called an enable signal.

The output of the weight 1 of the synchronization coefficient register 34-2 is provided in the AND gates 44-1, 44-3, and 44-6 of the weight shift circuit 44 in FIG. The output of 2 is the output of the weight 4 to the AND gate 44-4, and the AND gate 44-6 to the output line Y ₁ , and the AND gates 44-3 and 44-5 to open the OA gate 44-7. On line Y ₂ , AND gates 44-4 and 44-5 are coupled to output line Y ₄ by opening OA gate 44-9, which is supplied with OA gates 44-8 and AND gate 44-1 outputs.

That is, the 3-bit output represented by these output lines Y ₁ , Y ₂ , and Y ₄ is provided to the shift memory 49 as an addressing code, and the output of the synchronization coefficient register 34-2 is adapted to the octave signals 0 _{1 to} 0 ₄ . The address designation shown in the fifth table is used.

TABLE 5

And, as will be described later, the output value from Arthur 52 in the line memory at the designated address is shifted over with sequential ø ₀ pulses and taken out from the output of the shift memory 49.

In this way, one cycle of the weak sound waveform for each scale becomes a step in the reference clock unit, and the number of steps in each scale is different, and the operation is explained using FIG. Shall be.

The operation in FIG. 11A is 0 ₄ of the highest octave shown in FIG. 10, and the scale name is "C".

The addition timing signal is output from the addition timing generation circuit 43 at the time when the period count register 34 is in the initial state of " 0 ", so that the operation timing 48-4, in synchronization with the " 0 " block address signal from the block state detection circuit 38, The AND gate 46-3 is opened, and the "+2" correction value is given at the same time as the "+8" addition command, thus adding (0 + 10) to Arthur 40.

This addition value 10 is subtracted "-8" with the subtractor 41 as the 4th octave signal 0 ₄ , and the subtraction output value "2" is fed back to the synchronization coefficient register 34-2.

The addition timing signal is supplied to the Arthur 36 as a " + 1 " addition instruction, and is also provided to the shift memory 49 in Fig. 7C as an enable signal.

At this time, the address of the shift memory 49 is " 0 " and the output timing of the output unit 52 described later in the line memory " 0 "

After following the ₀ 8ø shift time is a "2" output in synchronization with the coefficient register 34-2 is "1" is output from the block count register 34-1. (See (b) and (e) of each FIG. 11 (a).)

At this point, since the block coefficient raster 34-1 output is "1", the output of the block state detection circuit 38 ① is applied to the scale step matrix circuit 39. However, at scale "C", the output signal is generated in this matrix circuit 39. Therefore, only the " + 8 " command is supplied to Arthur 40 in synchronization with the addition timing without giving the step correction number, so that (2 + 8) is added.

The subtractor is subtracted -8 to 41 again, and the subtracted output value "2" is fed back to the synchronization coefficient register 34-2.

In addition, a "+1" signal is supplied to Arthur 36 in synchronization with the addition timing signal, and the addition value "2" is fed back to the block coefficient register 34-1.

Again, this addition timing signal is applied to the shift memory 49 described above as an enable signal, and the output value "2" of the synchronization coefficient register TC 34-2 is supplied to the weight shift circuit 44 so that "1" at the output Y ₂ . The time signal is taken out and the address " 2 " of the shift memory 49 is designated as shown in the fifth table.

As a result, the block address " 1 " output timing is in a state of being output from the shift memory 49 with a delay time of 2 ° ₀ shift as shown in (i) of FIG.

That is, the block address between "0" and "1" is 10 steps.

By repeating the same operation as below, in the musical scale "C", there are 8 step intervals between the following block addresses, and one cycle of the sound wave waveform as in the tenth period is 130 steps.

In addition, in Fig. 1 (b) and (c), the operation description of the scale "BC #" in the fourth octave signal 0 ₄ is similarly shown in the state diagram of Fig. 11 (a).

FIG. 12 shows the details of the shift memory 49 and the Arthur 52 in FIG. 7 (c). The eight tine memories (49-4 to 49-7 are 10 bits each of 49-1 to 49-8 are shown in FIG. Shifts to the basic clock ø ₀ .

Input control circuits 49-9 to 49-16 are formed on the input side of each of the line memories 49-1 to 49-8. In the figure, the gate circuit is displayed for only one bit for simplicity. It is.

In addition, to the decoders 49-17 of the shift memory 49, an address designation signal of three bits of Y ₁ , Y ₂ , and Y ₄ of the weight shift circuit 44 of FIG. 7A is applied, where "0" to "7". Addressing is performed.

That is, the line memories 49-1 to 49-8 are associated with the addresses "0" to "7".

Thus, the address " 0 " to " 7 " designation signals are provided to the AND gates 49-18 to 49-25 to which the enable signals are supplied, and their outputs are supplied to the input control circuits 49-9 to 49-16. The input control circuits 49-9 to 49-16 input the output of the above-mentioned Arthur 52 in the line memory of the designated address and shift it to the output side sequentially.

At the output of the line memory 49-1, the output order 49-26 and the latch circuit 49-27 are opened and supplied to the D / A conversion circuit (see FIG. 1).

In addition, the output of the latch circuit 49-27 accumulates as it is circulated to the output order 49-26.

The line memory output immediately before the designated addresses of the line memories 49-1 to 49-8 is applied to the alternative weight stage of Arthur 52 by opening the oragate 49-28 (only one bit is shown).

Next, 35 in Fig. 7 (a) is a synchronization set register, in which one line of 8-bit line memory is connected in series, and 54 is 7 bits (" 1 "," 2 "," 4 ") with an envelope register. , "8", "16", "32", "64" weight) are configured to be connected in parallel in the direction of eight arrows, and all of them shift in the sequential arrow direction in synchronism with the shift pulse? ₀ .

For example, the electric scale code register 20, the octave code register 21, the periodic coefficient register 34, the sync set register 53, and the envelope register 54 each have a line memory corresponding, that is, output from the scale code register 320 and the octave code register 21. For the scale code, the control output corresponding thereto is in the state generated in the period coefficient register 34, the synchronization set register 53, and the envelope register 54.

Envelopes as 32 coefficient values of "0" to "31" displayed by the 5-bit output of "1", "2", "4", "8", and "16" weight of the tactical envelope register 54. The two counts of " 32 " and " 64 " indicate four envelope states of attack, decay, release and clear. Thus, the seven-bit output of each stage of envelope register 54 is applied to the corresponding weight input terminal of Arthur 55.

Each bit output of the Arthur 55-1, which counts the envelope control value, is opened through the Inhibit Gates 56-1 to 56-5 which control the output prohibition at the time of the carry output signal. ”,“ 2 ”,“ 4 ”,“ 8 ”, and“ 16 ”weights are circulated to the corresponding input side.

In addition, the output signal generated in the Arthur 55-1 is an inhibit gate to be prohibited by the output of the inverted end gate 57 which detects a clear state of 00 as the state detection weights "32" and "64" of the envelope register 54. 55-2 is applied to the carry input of state 55-3 for state counting. That is, Arthur 55-3 imports a carry output signal except for the clear state of the envelope. The output of the Arthur 55-3 is held circular by opening the inhibitor gates 58-1 and 58-2 at the "32" and "64" weight input terminals of the envelope register 54.

In addition, the input instruction signal for the combustion key in Fig. 7 (a) is applied to the input side of the "32" weight stage of the envelope register 54, and thus the input signal is applied. The envelope immediately becomes in an attack state due to the generation of the indication signal.

Here, the relationship between the envelope state and the two-bit code state of the "32" and "64" weights is shown in Table 6.

TABLE 6

The output of the sync set register 53 in FIG. 7A is applied to one input terminal of the end gate 60 and the inhibit gate 61.

The other input terminal of the AND gate 60 is supplied with 62 outputs of the AND gate which take a logic between the aforementioned "0" block attack address signal and the addition timing signal output from the addition timing generation circuit 43.

The set of the sync set registers 53 is performed by applying a lock signal (generally referred to as an envelope clock) output from the inhibit gate 63 to the input side through the OR gates 64 and 65 in accordance with the envelope state described below. .

In addition, since the serial connection output signals of the Inhibit Gate 66-1 66-5 and the Invertad and Gite 66-5 which detect the " 0 " The envelope clock is controlled so as not to pass through this inhibit gate 63 in the "

Thus, when the "1" signal is set in the sync set register 53, the AND gate 60 is opened in synchronism with the "0" block addition timing signal by the AND gate 62, and an addition timing signal to the Arthur 55 is generated. Output is forbidden, so the "0" signal is written to the sync set register 53 to cancel the set.

The addition timing signal output from the AND gate 60 is supplied as the gate open signal to the AND gates 67-1 to 67-5, and the addition value to the below-mentioned envelope 55 is supplied to the AND gates 67-1 to 67-5. The envelope time elapses. That is, the synchronization set register 53 is for synchronizing the addition value applied to the envelope-order "0" block address of the acoustic waveform.

The output of the sync set register 53 is " 0 ". When the envelope register 54 is all " 0 ", a reset signal to be described later is output from the inhibit gate.

The 5-bit outputs of the above-mentioned envelope registers 54 of "1", "2", "4", "8", and "16" weights are applied to the exclusion oragate 69-1 to 69-5 of the weight shift circuit. Each is supplied.

The switches S ₁ , S ₂ , S ₃ , S ₄ , S ₅ , and S ₆ in FIG. 7 (c) are volume curve type indicating switches for α and β, and the switches of S ₁ , S ₂ , S ₃ , The pairs indicate the attack (A), decay (D), and the lease (R) in the α-volume curve form, respectively, and the pairs of S ₂ , S ₄ , S ₆ , and the switch indicate A, D, and R in the volume curve form, respectively.

That is, the type of the volume curve type can be indicated seven times by three switches as shown in FIG. 13, and in this example, two types of the volume curve type can be simultaneously selected, and one is selected by the α (switch S ₁ , S ₂ , S _3). And select (), and select the other one as β (switch S ₂ , S ₄ , S ₆ ,). Accordingly, the type of combination instruction in the form of a volume curve for each of α and β is as shown in FIG.

Here, the above-mentioned block address waveform program designation section 35 in FIG. 7A shows each of the " 16 " block addresses that display one period of the sound waveform as " 0 " to " 15 ", as described in FIGS. By specifying the granularity and arrival differential coefficient of the waveform with "+" (up) and "-" (down), α in the previously-specified volume curve format is specified for each block address, or β It is possible to designate the signal as "1" signal for β instruction or "0" signal output for α finger.

That is, the designation example is shown in FIG. 15, and the differential coefficient values "1", "2", "4", and "+" and "-" are indicated for each block, and the volume curve format of α and β is selected again. It is supposed to be.

For details of the waveform program designation unit 35, the switches A ₁ to A ₁₅ which designate the absolute values of the block address differential coefficients "1", "2", and "4" as shown in FIG. , B ₁ to B ₁₅ , α / β volume curve type Indication position C ₁ to C ₁₅ +/- Indication switches D ₁ to D ₁₅ are formed, and the block coefficient register 34- The count values "1" to "15" of the 1 block state detection signals are combined.

The differential coefficient designation switches A ₁ to A ₁₅ and B ₁ to B ₁₅ of the blocks are decoded by E ₁ to E ₁₅ , respectively, and three indication signals of differential coefficients "1", "2" and "4" are displayed. As a result, each corresponding indicating signal acknowledgment opens the oragate and is taken out.

In addition, since the block address "0" is always set to the "0" level, there is no switch designation, and thus block addresses "1" to "15" can be designated.

Thus, the waveform program designation unit 35 is supplied to Arthur 52 in the (-) command signal 7 (c) designated for each block address, and the command signals of the differential coefficient values "1", "2", and "4" are shown in FIG. The β command signal is applied to the exclusive orifices 70 and 71 of FIG. 7B again in the weight shift circuit 69 in (c). The β command signal is normally passed through the exclusive oragate 70 to the inactive gates 72-1 to 72-3 and the end gates 72-4 to 72-6 of the volume curve type control circuit 72 for each of α and β. Is approved.

Thus, the AND gates 72-4 to 72-6 are synchronized with the β command signal ("1"), and the inhibit gates 72-1 to 72-3 are synchronized with the α command signal ("0") and have a volume curve for each αβ. Indicated switches S ₁ to S ₂ are output according to the indicated αβ, and the outputs of the inhibit gate 72-2 and the end gate 72-5 are the inhibit gate 72-3 and the end gate 72-6 to the oragate 72-8. The output of is connected to Oagate 72-9.

The output of Oagate 72-7 is fed to Andgate 72-10, Inhibit Gate 72-11, 72-12 and Andgate 72-13, and the output of Oagate 72-8 is ANDGATE 72-14 and Inhibit At gate 72-12, the output of oragate 72-9 is fed to endgate 72-15.

The output of AND gate 72-14 is also applied to inhibit gate 72-11 and AND gate 72-13.

Again, the AND gate 72-10 and the inhibit gate 72-11 open the oragate 72-16 to the oragate 72-17, and the output of the inhibit gate 72-12 opens the AND gate 72-18 to the oragate 72-. At 19, ANDGATE 72-13 and 72-15 are supplied to OAGATE 72-20 and again OAGATE 72-17, 72-19 and 72-20 are connected in series, eventually leading to the output of OAGATE 72-17. It is supplied to one end gate 50. The detection signals from the envelope state detection circuit 73 are connected to the AND 72-10, 72-14, 72-15, and 72-18, that is, normally, the inverted AND gate 73-1 is connected to the envelope. 00 grill state, Inhibit gate 73-2 detects attack, Inhibit gate 73-3 detects decay state, AND gate 73-4 detects lease state, and inhibit gate 73-2 detects in AND gate 72-10. The bead gate 73-3 is supplied as the gate open signal to the AND gates 72-14 and 72-18.

The inverted AND gate 73-1 is supplied to the inhibit gate 73-5 at the same time as the all-zero state detection signal of the above-mentioned envelope register 54 (see FIG. The output of the inhibit gate 73-5 is again supplied to the AND gate 73-15 as the gate open signal by opening the OR gate 73-6 simultaneously with the AND gate 73-4.

Therefore, the oragate 72-16 of the volume curve type control circuit 72 for each αβ is in an attack state, and the volume curve type is output in the case of the directions of Figs. 72-18 is a command of "31" command in case of the instruction of 4 in FIG. 13 without decay instruction when decay state and attack instruction are present.

In addition, in the case of Fig. 13 (1), (3), (5), (6) and (7), which is the "down" instruction of the decay and release, the oragate 72-20 is taken out as a signal indicating the complementary value inverting the envelope count value.

On the other hand, the ORA gates 72-17 are output in the respective attack, decay, and lease states only when there is a switch instruction of the attack (A), decay (D), and the lease (R). It is output as an enable signal for.

The 31 command signal output from the AND gate 72-18 is supplied to the OA gates 69-6 to 69-10 of the weight shift circuit 69, and the plural command signals output from the OA gate 72-20 are connected to the exclusive OA gate 69-11. It is supplied to Exclusive OA gates 69-1 to 69-5.

That is, the weight shift circuit 69 weights "1", "2", "4", "8", and "16" of the envelope register 54 when the aforementioned "31" command signal and the maintenance command signal do not exist. Envelope coefficients indicated by are passed through the Exclusive OA gates 69-1 to 69-5, and the specified coefficient values of the differential coefficient values "1", "2", and "4" for each block address indicated by the waveform program designator 25 The weight shift (in this case, ± differential coefficient value X envelope coefficient value E) is applied, and the multiplication value is supplied to Arthur 52.

That is, the differential coefficient value "1" instruction signal is supplied to one input terminal of the AND gates 69-12 to 69-16, the instruction signal is input to one input terminal of the AND gates 69-17 to 69-21, and the four instruction signal is connected to the AND gate 69-. It is supplied to one input terminal of 22 ~ 69-26.

The signal corresponding to the weight "1" of the envelope coefficient value is input to the other input terminal of the AND gates 69-12, 69-17, and 69-22, and the other input terminal of the gates of the AND gates 69-13, 69-18 and 69-23. The signal corresponding to "2" is the other input terminal of ANDGATE 69-14, 69-19, 69-24, and the signal corresponding to the weight "4" is of ANDGATE 69-15, 69-20, 69-25 The signal corresponding to the weight "8" is supplied to the other input terminal, and the signal corresponding to the weight "16" is supplied to the other input terminals of the AND gates 69-16, 69-21, and 69-26.

And again, the AND gates 69-12 are on the input `` 1 '' of Arthur 52, and the AND gates 69-13 and 96-17 are on the input side of the weight `` 2 ''. 18, 69-22 are on the input side of the weight "4" by Oagate 69-28, 69-29, and endgates 6-15, 69-19, 69-23 are on Oagate 69-30, 69-31 On the input side of the weight "8", the AND gates 69-16, 69-20, and 69-24 are on the input side of the weight "16" by the oragate 69-32, 69-33, and the AND gates 69-21 and 69-25 are Opening the oragate 69-34 is connected to the input side of the weight "32", and the AND gate 69-26 is connected to the input side of "64".

Therefore, the weight shift circuit 69 obtains the multiplication value shown in FIG. 17 in accordance with the differential coefficient values "1", "2", and "4". Thus, when the "31" command signal output from the volume curve type control circuit 72 for each αβ is supplied to the ORA gates 69-6 to 69-10, the envelope count value becomes 31 regardless of the output of the envelope register 54. You lose.

When the maintenance command is supplied to the Exclusive OAQ 69-11, the envelope count value indicated by 5 bits of the envelope register 54 is reversed, and the multiplication value shown in the 17th becomes the inverse coefficient value. Therefore, the difference from the case shown in FIGS. 1 to 4 is that the multiplication for each block address is in accordance with the volume curve format indicated by αβ as in FIG. 15, and thus the differential derivative value X envelope coefficient E (where E Becomes Eβ in accordance with the α volume curve format).

In this way, the multiplication value input to the Arthur 52 is supplied to the shift memory 49.

That is, by indicating two volume curve types of αβ, a waveform according to α and a waveform following β can be simultaneously indicated, so that the granularity and arrival curve of the volume are different between the different waveforms. Synthetic acoustic waveforms will be able to change.

For this reason, it is possible to give remarkable changes over time in the overtone structure, so that a musical sound having an effective tone can be generated, and is particularly suitable for expressing the characteristic peculiar to the musical instrument during the pronunciation seen in brass and expression musical instruments.

Of claim 7, also (b), switches S _10, S _11, S ₁₂ are αβ to be indicative of a specific period The mode specifying the switches S _10, S _11, S ₁₂ is (referred dyutiyi (Duty)) cycle control circuit The three switches are turned on and off, and the mode designation signals indicated by eight zeros to seven numbers in the end function matrix circuit 74-1 are taken out from the output line. It is input to the function matrix circuit 74-2.

+16.32.

]의 조건인 제18도(c)의 출력 상태를 얻게 된다.On the other hand, the 3-bit (" 16 "," 32 " and " 64 " weight) outputs of the cycle number register 34-3 to be counted for each cycle of the waveform shown in Fig. 7A are also supplied to the duty control circuit 74. The output state of FIG. 18 (b) is output from the inverted AND gate 74-3 according to the cycle number count state, and the AND gate 74-5, the inhibit gate 74-6, and the OR gate 74-4. By the above-mentioned inverted endgate 74-3 state [

+16.32.

The output state of FIG. 18C is obtained.

The signal [10] of the cycle number register 34-3 shown in FIG. 18A is supplied to the inhibit gates 74-7 and 74-8, and the above-described inverted end gate 74-3 output is the AND gate 74. The outputs of oragate 74-4 are supplied to AND gates 74-11 and 74-12.

Here, the basic relationship between the duty cycle and the cycle count state will be described with reference to FIG. 19.

That is, "0" indicates a cycle without waveform output, and "1" indicates a cycle of waveform output "yes". The duty "1", "1/2", and "1/4" take out a waveform output every "1" cycle, every "2" cycle, and every "4" cycle, respectively. The duty "1/3" is obtained by setting the "6" cycle state immediately without performing the cycle coefficients of "4" and "5". That is, when the corresponding load is designated 6 and 7 of the modal Modal to "0" to "7", the number to be standing in a combination of specified per cycle described above αβ The mode switches S _10, S _11, in S ₁₂ 3 bitteu, The output K ₁ output signal from the OA function matrix circuit 74-2 is generated, and the output signal of the weight "64" of Arthur 36 is simultaneously supplied to the AND gate 74-13, and the output signal is opened by the OR gate 74-14. It is supplied to the weight 32 of the cycle register 34-3, and the state of "4" and "5" is blown.

The K ₂ output of the OA function matrix circuit 74-2 is connected to the Oagate 74-15, the K ₃ output to the Oagate 74-15, and the K ₄ output to the Oagate 74-15. K ₅ output is opened to Inhibit Gate 74-8 to Oagate 74-16, and K ₆ output is to Opengate 74-9 to Oagate 74-17 to K ₇ output to Opengate 74-10. To Oagate 74-18, K ₈ output is connected to Oagate 74-19 by opening Andgate 74-11, and K ₉ output is connected to Oagate 74-20 by opening Andgate 74-12. 74-15, 74-17 and 74-19 are connected in series to output X ₁ (α), and oracle 74-16, 74-18 and 74-20 are connected in series to take output X ₂ (β). Therefore, the output signals generated at the outputs X ₁ (α) and X ₂ (β) are as shown in FIG. 20 in correspondence with the cycle mode designation numbers "0" to "5" for each αβ.

That is, the output X ₁ (α), we will be on the basis of the waveform cycle, the output M X ₂ (β) by α indicated by the period N of the waveform indicated by the extracted β.

Therefore, while the periodic modes "0" to "5" are constants M and N, the periodic modes "6" and "7" are periodic Ms and N are both integers, and the other is cycle controlled in a non-integer relationship.

Again, the outputs X ₁ (α) and X ₂ (β) are supplied to the inhibit gate 75 and the AND gate 76, respectively, and in the exclusive oragate 71, the α instruction signal ("") is synchronized with the α / β instruction signal. 1 "), the AND gate 76 is opened, and their outputs are again output from the OR gate 79 through the inhibit gates 77 and 78 which will be described later, and are supplied to the AND gate 51 in FIG.

Here, the switch R ₂ is connected to the exclusive oragate 71, and is formed to invert the α / β instruction signal for each block address outputted from the waveform programator 35 by operation, and thus the AND gate 76 is connected to the α instruction signal. The inhibit gate 75 is output in synchronization with the β indicating signal so that the output X ₁ becomes a duty of α output X ₂ .

The switch R ₂ is connected to the inhibit gates 80 and 81 to which the P signal and the inverted signal P, which will be described later, are supplied, respectively, to separate αβ or to indicate non-separation, which is output from the inhibit gates 80 and 81 during operation. Therefore, X ₁ (α) and X ₂ (β) (where X ₁ (β) at the time of switch R ₁ ) indicating duty ratios by α and β by the mode commands from Inhibit Gates 77 and 78, respectively. , X ₂ (α)) is extracted.

신호 (단, 후술하겠으나 중주지시에만 발생한다)가 출력되며 전술한 각 레지스터의 우수라인 메모리는 α로서, 기수라인 메모리는 β로 지시되게되며 이를 일람표로 이해하게 쉽게 표시한 것이 제21도이다.When the switch R _{2 is not} operated, the P signal,

A signal (however, it will be described later, but generated only in the midpoint instruction) is outputted, and the even-line memory of each of the above-described registers is α, and the odd-line memory is indicated by β, and it is shown in FIG.

On the other hand, in this case, the case where switch designation of the switch R ₂ and R ₃ described below is not made is shown. In addition, the non-isolated instruction by the switch R ₂ is valid only in the middle period.

Switch R ₃ IX is greater when the sheave Iowa doeyeo connected to the gate 70 this is operated, the α / β instruction signal assigned to each designation section 35 waveform program block is reversed. That is, in the twenty-first graph, the relationship of? /? Is completely reversed.

In this way, the octave operation can be performed by specifying the αβ period, and the sound wave type duty can be changed and the tone can be different for each octave, which is an effective function.

In addition, considering the α / β ratio separation operation of FIG. 21, in the case of mode designation [6], α: β has a period of 1: 1.5, and β becomes a perfect 4 degree bass with respect to α. Β is twice as long as α, but β's waveform is 2/3 times and twice as long as the period of α, and β is a full 5 degrees high and octave low component for α. .

Since the period control can be performed in the periodic relationship M: N between the different waveforms as described above, the change in the harmonic structure of each waveform to be synthesized and the change in the harmonic structure due to the synergistic effect obtained by the synthesis have a more natural change over time. Effective musical notes can be obtained.

In FIG. 7 (b), the switch T ₁ is a conventional tremolo (referred to as tromoloflat) indicating switch, and T ₂ is a quench tremolo indicating switch in which the tremolo is controlled only during operation, and the quench tremolo is instructed. The Tremolo Plains Sichuan is open.

The switches T ₃ , T ₄ and T ₅ indicate the depth of the tremolo (called the amplitude value) and are sequentially maximal "1" (100% depth), "1/2" (50% depth), "1" / 4 "(25% depth).

The designated signal of the switch T ₁ or T ₂ is supplied to the tremolo control circuit 84 by outputting an output instruction signal having a specified amplitude value so as to be supplied to the AND gates 83-1 to 83-3 via the oragate 82.

Thus, the AND gates 83-1 to 83-3 are provided to the AND gates 84-3 and 84-4 by opening the oragate 84-1 or 84-2. The output of the AND gate 83-2 is supplied to the OR gate 84-6 and the AND gate 84-7 through the AND gate 84-5 to which the "64" weight output of the envelope register 54 is coupled.

Therefore, the weight " 16 " of the envelope register 54 is always " 1 " in the decay state and the lease state.

The AND gate 84-8 output which detects the state of detecting the lease state again is provided to the AND gate 84-3 described above, and its output opens an inhibit gate 84-9 which can be opened other than the mandrin designation described later. By being taken out as an output signal from the oragate 84-10, the inhibit gate 84-7 does not open in the lease state, and the inhibit gate 84-11 can be opened.

On the other hand, in the tremolo instruction, the output of the " 64 " weight of the envelope register 54 is supplied to the AND gate 84-4, and the output is always connected to the " 69 " weight of the envelope register 54 by opening the oragate 84-12. In order to supply the "1" signal, the clear state of "00" is not set, and the decay state and the lease state are repeated.

The output of the AND gate 83-3 is given the weight "64" output of the envelope register 54, is opened to the OR gates 84-14 and 84-15 by opening the AND gate 84-13, and also to the bit gate 84-16. Supplied. This inhibit gate 84-16 does not open in a release state like the inhibit gate 84-17, and in this state, the inhibit gates 84-17 and 84-8 can be opened. In addition, the output of the Narrow Lobe register 45 wave "32" is opened by the Inhibit Gate 84-20 to which the AND gate 84-19, which is effective only in the case of the Tremolo triggering switch T ₆ described later, is combined. Is given to gates 84-21. That is, since the gate output prohibition signal from the AND gate 84-42 is applied to the inhibit gates 84-21, the output becomes "0" without being widened in the tremolo instruction. Therefore, in the envelope state detection circuit 73, only the output signal of the inhibit gate 73-3 deg. State is not taken out. That is, in the tremolo indicating switches T ₁ and T ₂ , the envelope coefficients of the envelope register 54 have amplitude values of 1/1, 1/2, and 1/4 according to the volume curve form (see FIG. 13). According to the depth indication, an example is shown in FIG. 22 to FIG. 24.

On the other hand, tremolo is not limited to the volume curve forms ①, ④, and ⑤ in FIG. T ₆ is a switch when tremolo is released. When it is operated, the output signal of the inhibit gate 84-22, which is output in the lease state from the AND gate 84-19, and the condition that the envelope resistor 54 becomes "16" or more, passes through. Done. If the clear state of "00" in the envelope register 54 is detected by the inverted end gate 73-1 of the state detection circuit 73, the inhibit gate 73-5 and the ora gate 73-6 are opened to open the end gate 72. -15 is outputted as a release instruction signal. Therefore, the first half of the lease state operates as a decay clock signal to be described later, and eventually becomes a tremolo moving in accordance with the volume curve form as shown in FIG. 25 (a, b) (in the case of specifying the tremolo depth 1/1). To become an effective function. The quench tremolo instruction switch T ₂ is effective when the tremolo type instruction switch T ₁ is turned off in advance, and the tremolo effect is obtained only during operation. Depending on the output state of the 32 and 64 weight stages of the envelope register 54, the attack state detection signal ⓐ is applied to the inhibit gate 85 and the decay state detection signal ⓓ to the inhibit gate 86 is inhibited from the AND gate 87. As the serial circuit of the gate 88, the lease detection signal c is the output of the inverted gate 66-6 described above, and the lease detection signal hr is taken out by the series circuit of the AND gates 89 and 90. . Further, 91 is a synchronous reset of the register specified ririseu high, and the line memory 1 has the bitteu 8 present, and the shift operation by the shift pulse ø _0.

In this way, the high-lith hr means a relatively fast attenuation for preventing the clock sound when the playing keys are off (especially when specifying a settling tone such as an organ sound). The hr set signal to be described later is outputted, and the signal is opened by the inverted signal of the inhibit gate 93 and the inverted signal of the AND gate 62 in FIG. 7 (a). The gate 94 is opened and input to the high-list register set register 91.

The output signal of the inhibit gate 93 is an inhibit signal whose gate is opened in a state other than the AND gate 95 and the envelope state "00" in synchronization with the output signal of the AND gate 62 (addition timing when the " 0 " block address signal is generated). The gate 96, oragate 64 and oragate 65 are opened and input set to the sync set register 53 for envelope clock to perform high-rising operation. Although the above has described the configuration which is the heart of the system, the timing relationship for controlling the circuit configuration of Figs. 7 (a), (b), (c), and (d), various clock signals for envelope control, and quartet The configuration of the circuits of Fig. 27 (a) (b) in Fig. 26 connected to Fig. 26 will be described with respect to the control signal, the playing key group, the key input control, and the like. The basic clock signal ø ₀ (at 2 7 2 5 20 Hz) output from the one-clock generator 100 is composed of eight components constituting registers 20, 21, 34, 53, and 54 of FIGS. 7A and 7D. It is supplied to the line counter 101 which has a significant count on one cycle of the line memory. The line counter 101 performs an octal binary counting operation with three combs. The output of each bit end (see FIG. 28A) is supplied to the control timing generation circuit 102. FIG. The control timing generation circuit 102 is supplied with the respective instruction signals of the W ₁ (non-weighted instruction), W ₂ (doubled instruction), and W ₃ (quadrant instruction) contact wishes at the middle command switch W. Inverted gate 102-1 and inverted and gate 102-2 are used for output signal. In non-weighted case, open signals 102-3 and 102-4 are used to output “1” coral and oragate 102 at output ⓓ. The signal " 1 " In addition, the AND signal 102-7, the oA gates 102-3, and 102-4 are opened for the duplex instruction, and the output signal shown in FIG. In the quartet instruction, the AND gates 102-10, 102-11, and oragate 102-4 are opened, and the output signals shown in FIG. The output signal shown in Fig. 28 (d) at the output? Is generated by opening the gate 102-6. Quartet each comb teudan output of the indication switch contact W W ₄ 8 quartet instruction signal, quartet instruction signal, second instruction signal, and quartet of line counter 101 is supplied to a circuit 103. The timing signal generating quartet.

Thus, the quartet instruction signal or the quartet instruction signal is output to the oragate 103-1, and the middle oil (output from any instruction of 2, 4, or quintet) is output from the oragate 103-2.

신호로서 각 게이트에서 출력되며 제7도(c)의 인히빗트게이트 80, 81에 인가하게 된다. 또 오아게이트 103-2에서 출력되는 중주유신호는 앤드게이트103-5에 공급됨으로 그 출력에서 라인카운터 101의 웨이트「1」출력신호가 취출되며 오아게이트 104를 개하여「+1」지령신호로서 출력된다.The middle circumferential oil signal of the oragate 103-2 is supplied to the AND gate 103-3 and the inhibit gate 103-4, so that the weight "1" output signal of the line counter 101 is a P signal, as shown in FIG.

The signal is output from each gate and applied to the inhibit gates 80 and 81 of FIG. In addition, the heavy fuel oil signal output from the OA gate 103-2 is supplied to the AND gate 103-5, and the weight “1” output signal of the line counter 101 is taken out from the output, and the OA gate 104 is opened and output as a “+1” command signal. do.

The output of the OA gate 103-1 is supplied to the AND gate 103-6, so that the output signal from the weight "2" of the line counter 101 is outputted, and the OA gate 103-7 is opened and supplied to the OA gate 103-8.

The duo indication signal is supplied to the inhibit gate 103-9, and an inverted signal of the line counter 101 is taken out from the output thereof, and the oragate 103-8 is applied by opening the oragate 107. Again Oagate 103-8 is applied. The heavy fuel oil signal output from the oragate 103-2 is applied to the oragate 103-8 as the inverted output signal by opening the oragate 103-10.

In addition, the operation signal of the vibramo designation switch B is applied to this oragate 103-10.

That is, the output of the OA gate 103-8 outputs the output signals shown in (g) and (i) of FIG.

When the octet command signal is supplied to the AND gate 103-11, the output signal of the weight " 4 " of the line counter 102 is outputted from the AND gate 103-11. It is output as a signal shown in (k). Therefore, timing signals shown in (f) and (g) of FIG. 28 (b) are output from the oragates 104 and 105 at the time of the assignment of the duo, respectively, and (h) and (i) of FIG. 28 (b). One timing signal is output from the orifices 104 and 105 at the time of the quartet designation, and (J), (K) (I) and the timing signal shown in FIG. It is output from the gates 104-106 and applied to the AND gates 97-1 to 97-3 shown in Fig. 7A, and is supplied to Arthur 40 as an additional value in synchronization with the " 0 " block address signal.

That is, the electric addition mantissa of the quintet instruction is used to load the frequency difference to each line memory.

The timing signals of the above-described outputs ⓐ, ⓑ, and ⓒ output from the control timing generation circuit 102 are supplied to the input control circuit 107 and the timing signals from the output ⓐ are also supplied to the octave counter 108 in FIG. 27 (b). .

In other words, this octave counter 108 is a binary counter with a 3-bit octal, which is counted every 8-line time of 8 ° ₀ , and the lower and lower 2-bits (weights "1" and "2" are four-octave coded states. (a) An octave input code (see (a) in Figure 20 (a)).

Each 3-bit output of the octave counter 180 is supplied to the synchronization signal generating circuit 109 and also provided to the decoder 110. Thus, the three-bit all-zero count state is detected by the inverted end gate 1089-1 and the inhibit gate 109-2, and the timing shown in (b) of FIG. 29 (a) as the detection output? The signal is taken out and applied to the scale counter 110 as a count complement signal.

In this scale counter 111, the lower 2-bit is used as a ternary binary counter and the upper 1-bit binary counter is operated as the carry (see (C) of FIG. 29 (a)).

In practice, a four-bit scale counter is combined with the highest bit of the counter 108, and thus the four-bit output becomes the threshold input code of Fig. 7A.

The counter 111 is supplied to the synchronization signal generating circuit 109 and also to the decoder 112.

From the outputs 1 to 8 of the decoder 110, different timing signals as shown in (d) of FIG. 29 (b) are output and applied to the eight main lines of the playing key group 113. In the playing key group 113, 48 playing keys are arranged in a matrix, and six output lines are supplied to the end gates 114-1 to 114-6 of the key operation timing detection circuit 114, respectively.

에서 발생하는 상이한 6개의 타이밍신호(제29도(b)의 (e)참조)가 각각 순차적으로 결합되어 있다.The outputs of decoder 112 are provided at the AND gates 114-1 to 114-6.

Six different timing signals (see (e) of FIG. 29 (b)) generated at s are combined sequentially.

Thus, the output of ANGATE 114-1 to 114-6 is outputted by the OAGATE 114-7 ~ 114-11 serial circuit, and the corresponding key input timing signal operated out of the 48 playing keys is outputted from the output circuit. It is input to key input F / F 107-1 of. The timing signal output from the synchronization signal generation circuit 109 is detected in accordance with the counting state of the counters 108 and 111, and the timing signal timed by the (f) of FIG. 3 to 109-5 are detected, and in the output ⓕ, the timing signal shown in (g) of FIG. 29 (b) is inverted and gate 109-1, inhibit gate 109-2, 109-7, and 109-. Use 8 to detect.

Again output ⓠ in claim 29 also (b) (h) shown a timing signal that AND gate 109-9, inhibit bitteu gate 109-10, 109-11 use, is detected, the output S ₄ ⓗ the output of the counter 111 of the At the output ①, the timing signal shown in (i) of FIG. 29 (b) is detected using the inhibit gate 109-12, and the output signal 1 (j) of (29) in the output 1 is detected. The gates 109-13 and Inhibit gates 109-14 are used for detection and output.

The shift register 115-1 of the various clock time generation circuits 115 operates dynamically at 241 bits and is shifted by the clock signal every eight line times at the output? Of the control timing generation circuit 102.

Therefore, one cycle of the shift register 115-1 is in synchronization with the total 24 digits of the ternary number of the octal counter 111 of the counter 108 described above.

The shift register 115-1 has independent counting portions of the first coefficient portion, the second coefficient portion, and the third coefficient portion in 8-bit units, and the first coefficient portion and the second coefficient portion are vibrato and envelope time clock signals. It is used for the generation, and the third coefficient part is used for the time coefficient of a predetermined time when there is a new key to be described later.

Basically, the first coefficient unit is an 8-bit binary counter operating as a timing signal (see Fig. 29 (b)), and the second coefficient unit is a 2-bit operating timing signal at output ⓗ. An 8-bit binary counter that counts ternary numbers, and the third coefficient unit is an 8-bit binary counter that operates as a timing signal at the output ⓔ.

Thus, the output signal at the output d, of this shift register 115-1 is supplied to Arthur 115-3 by opening an oragate, and the output is circulated to the input side of the shift register 115-1.

In addition, the carry signal is applied to the inhibit gate 115-4 through the carry F / F 107-2 at Arthur 115-3. This inhibit gate 115-4 is to be prohibited from output when the timing signal (i) of the synchronization signal generation circuit 109 is generated. The output is applied to the Arthur 115-3 by opening the oragate 115-5.

The output (i) timing signal is also input to the oragate 115-5 through the inhibit gate 115-5. Output d ₂ of shift register 115-1 is inverted and gate 115-7, inhibit gate 115-8, output d ₃ is inhibit gate 115-9 and endgate 115-10, and output d ₄ is inhibit Output d ₅ to gate 115-11 and end gate 115-12 to inhibit gate 115-13 and to gate 115-14, output d ₆ to inhibit gate 115-15 and to gate 115-16, output d ₇ Is applied to ANDGATE 115-17

Inverted End Gates 115-7, Inhibit Gates 115-9, 115-11, 115-13, and 115-15 are sequentially cut-off gates 115-10, 115-12, 115-14, 115-16, and 115-15, respectively. -17 is applied and the output of each AND gate is taken out as a fully shorted clock (8 ° ₀ time width).

In addition, the output d ₁ is applied to the inhibit gate 115-8, and the output is supplied to the AND gate 115-18.

The above-described synchronous signal generating circuit 109 output timing signal is applied to the AND gate 115-18, and is applied to the order 115-3 by opening the OR gate 115-2.

That is, the ternary count of the lower two bits of the coefficient part is controlled.

The shift register 115-1 output d ₁ is applied to the AND gate 114-19, and the AND gate 115-14 output is applied to the AND gate 115-20, and these outputs are chattered in synchronization with the above-described timing signal 108 output timing signal. It is supplied as a reset or set signal to flip-flops 115-21 (delays) for determining the prevention time, respectively.

Thus, 116 is a vibra art clock line circuit, and the AND gate 116-1 is coupled with the time clock signal at AND gate 116-10, and the AND gate 116-2 is coupled with the time clock signal at AND gate 115-12. The outputs of 116-1 and 116-2 are coupled to AND gate 116-4 and inhibit gate 116-5 by opening orifice 116-3.

Again, the output of the inhibit gate 116-5 is an AND gate 116-6 to which the timing signal of the electrical synchronization signal generating circuit 109 is applied, and the output of the AND gate 116-4 is an AND gate 116-7 to which an output ⓑ timing signal is applied. the output of these aND gates doeyeo 116-6, 116-7 supply is output to one of Iowa gate 116-8 non bra as amorphous clock signal ø _B. In other words, the Ibibrato clock signal? _B becomes a different time clock signal by vibratoclock selection switches S _A and S _B selection designation. As shown in FIG. 30, the S _A switch designates whether to extract the time clock signal determined by the first coefficient unit of the shift register 115-1 or the time clock signal determined by the second coefficient unit.

In this way, the vibrator clock signal? _B is applied as the count compensation signal of the octal binary counter 117 in FIG. This counter 117 generates the signal of Fig. 31A at each output stage and is applied to the vibrato control circuit 118.

And, output by the coefficient e _1, the state 31 view (b) showing the timing and the signal is detected by the inhibitor bitteu gate 118-1, AND gate 118-2, and the output e ₂ is the Fig. 31 (c) showing and a timing signal is detected by the inhibitor bitteu gate 118-3 aND gate 118-4, and the output e ₃ is 31 degree (d) is a timing signal showing detected by the aND gate 118-5, 118-6, and the output In e ₄ , the timing signal shown in FIG. 31 (e) is detected by the inverted and gates 118-7 and AND gate 18-8, and in the output e ₅ , the timing signal shown in FIG. 31 (f) is suppressed. detected by the gate 118-9, and, again, the output e ₆ 31 FIG. (g) is detected by a timing signal shown by the inhibitor bitteu gate 118-10. In the end the output e ₇ 31 FIG. (H) shown a timing signal is output e _1, e _2, Iowa gate 118-10, and is detected by a series circuit of 118-11 takes the Iowa e _3, e output in the ₈ The timing signal shown in Fig. 31 (i) is detected by the series circuits of the OR gates 118-13 and 118-14 which take the logic of the outputs e ₁ , e ₂ , and e ₅ .

Therefore, the timing signals of the outputs e ₇ , e ₈ , and e ₄ are Vibraa, and the AND gates 118-15 to 118-17 and OA gate 104-105 are opened at the time of designation of the switch B operation. The " 0 " block signal is output to the AND gates 97-1 to 97-3 to be supplied. That is, when instructing Vibraa, ΔP ₁ , ΔP ₂ , and ΔP ₄ are output according to the counter value of the counter 117. 119 is an envelope clock select circuit for selecting an envelope clock to be applied to the inhibit gate 63 of FIG. AR and RB are switches for selecting the time clock signal in the lease state. DA and DB are switches for selecting the time clock signal in the decay state. RC is a select switch for the slow release clock signal, and OA is an alleged sound (normal sound). Envelope designation switch.

The time clock signal output from the AND gate 115-12 described above is output to the AND gates 119-1 to 119-3, the time clock signal output from the AND gate 115-14 is applied to the AND gates 119-4 to 119-6 and the AND gate. The time clock signals output from 115-16 are applied to the AND gates 119-7 to 119-9, and the time clock signals output from the AND gates 115-17 are applied to the AND gates 119-10 and 119-11.

Again, the select contact outputs of the R _B switches are applied to the AND gates 119-1, 119-4, 119-7, and 117-10, respectively, and these AND gate outputs are connected in series with the OR gates 119-12 to 119-14 to take an oar. It is supplied to the circuit and its output is coupled to the AND gate 119-15 and the inhibit gate 119-16.

The output timing timing signal of the above-described synchronization signal generating circuit 109 is applied to the AND gates 119-17 to 119-19, and the output? Timing signal is applied to the AND gates 119-20 to 119-22. The AND gate 119-15 and the inhibit gate 119-16 are provided to the AND gates 119-20 and 119-17, respectively, and the output thereof is opened by the OR gate 119-23 so that the release state detection signal shown in FIG. The applied AND gates 119-24 are opened and output as the release clock signal? R.

The RA switch designates whether to take out the time clock signal determined by the first coefficient unit of the shift register 115-1 or to extract the time clock signal determined by the second coefficient unit as shown in FIG.

The AND gates 119-2, 119-5, and 119-8 are supplied with the D _B switch select contact outputs, respectively, and the outputs of these AND gates are supplied to the series circuits of the oA gates 119-25 and 119-26 to take the oars. The outputs are supplied to AND gates 119-27 and inhibit gates 119-28, respectively.

Again, the ANDGATE 119-27 and INHIBIT GATE 119-28 outputs are supplied to the ANDGATE 119-30 through the ANDGATE 119-21, 119-18 and OAGATE 119-20, respectively. The decay clock signal is output at the decay state detection signal of.

Subsequently, the select contact output of the switch R _C is applied to each of the AND gates 119-6, 119-9, and 119-11, and these AND gate outputs are supplied to the series circuits of the OR gates 119-31 and 119-32 to take an oar. The output of the throw-release clock signal? S ₂ is taken out by opening the AND gates 119-33 and 119-19 when the throw-through state detection signal to be supplied in Fig. 7 (d) is generated.

The AND gate 119-3 is outputted when the high-lead state detection signal or the attack state detection signal to be supplied in FIG. 7 (d) is opened by opening the oragate 119-37, and the high-gate clock signal at the AND gate 119-22 is generated. It is output as an attack clock signal? _A.

Thus, the lease clock signal ø _R output from the AND gates 119-24, the decay clock signal ø _D output from the AND gates 119-30, the slow-down clock signal ø _S2 output from the AND gates 119-19, and the AND gates 119-22. The high clock clock signal øH _{R to} be outputted from the time clock signal is the envelope clock signal from the series circuit outputs of the OR gates 119-34, 119-35, and 110-36. Supplied. 120 is an addition value designating circuit to be supplied to the attacker, decay state, release state, throw-out state, and high release state FIG. 7 (c) Envelope Arthur 55, and the envelope value is " + " As a result of this, the envelope granularity and arrival time are rapidly controlled as time passes.

That is, the Aa switch is a selection switch of five contacts, and each of the contact outputs is connected with "+1", "+2", and "+4" through the AND gates 120-1 to 120-5 to which the attack state detection signal is applied. Addition command signals of " + 8 " and " + 32 "

The Da switch is a 5 contact selector switch, and each contact output is connected with an AND gate 120-11 to 120-15 and an OR gate 120-6 to 120-10 to which a detection signal is applied. 2 "," +4 "," +8 "and" +32 "are output as addition value command signals.

When the release state detection signal is generated, the OA gate 120-16 is opened to generate an addition command signal, and when the release state detection signal is generated, the OA gate 120-17 is opened to generate the +1 addition command signal. When the high release state detection signal is generated, Oagate 120-18 is opened to obtain the "+8" addition value command signal, and this addition value is set to AND gates 67-1 to 67-5 in Arthur 55 of Fig. 7 (c). It is supplied by opening.

As a result, the time clock signal different from each of the first and second coefficients to be output from the AND gates 115-10, 115-12, 115-12, 115-14, 115-16, and 115-17 is a vibra art clock. The selection circuit 116 and the envelope clock select circuit 119 are respectively selected at the points indicated by the "0" table in FIG. 30 in accordance with the instructions, and again, the addition value to the envelope 55 for the envelope can be selected in synchronization with the selected time clock signal. It is.

32, 33 and 34 exemplify inclined planes of envelope count values in the attack, decay, and lease states, respectively. Subsequently, a timing signal (time width of 8 ° ₀ ) corresponding to the operated play key output from the above-described key operation timing detection circuit 114 is input to the key input synchronization F / F 107-1, and the output thereof is the AND gate 107-3. Is applied to.

The AND gate 107-3 is output in synchronization with the set output of the chattering prevention flip-flop 115-21, and generates a key-on signal as it is supplied to the inbit bit gate 107-4.

That is, the inhibit gate 107-4 will be described later, but when the output of the 48-bit shift register 107-5 corresponding to the number of playing keys (48 in this case) is 0, The keyon signal is obtained and supplied to the AND gate 107-6.

The AND gate 107-6 is an empty line memory in response to a reset signal (indicated by a cleared empty line memory in the envelope register 54) to be output from the inhibit gate 68 shown in FIG. The above-described input instruction signal for setting the solidification input data of the new key and the envelope attack state is generated.

Moreover, it becomes an input instruction signal for designating a plurality of line memories in accordance with the quintet instruction state.

That is, the reset signal to be output from the inhibit gate 68 of FIG. 7A is supplied to the AND gate 107-7 and the inhibit gate 107-8 of the input control circuit 107.

The output of the AND gate 107-7 is held by opening the ORA gate 107-9 and the inhibit gate 107-10 and is coupled to the inhibit gate 107-11-input which is to be prohibited by the above-described inhibit gate 107-8. .

The AND gate 107-7 and the inhibit gate 107-8 output the signal from the control timing generation circuit 102, i.e., the signals shown in Figs. 28 (a) (c) and (d) of the double and quadruple specifications. In the designation without a middle note, the " 1 " signal and the signal shown in (b) of FIG. 28 (a) are applied as the gate signal.

Again, the signal shown in (b) of FIG. 28 (a) opens the insert gate 107-12 at the output? To inhibit the output of the inhibit gate 107-10 and releases the holding.

Therefore, the above-described inhibit gate 107-11 generates a signal synchronized with the output? Signal matched to each of the mid-commands, and outputs the key-on signal at the AND gate 107-6. Thus, the output signal of the AND gate 107-6 is supplied to the inhibit gate 107-14.

The AND gate 107-14 is output in synchronism with the signal of the output ⓓ of the control timing controller 102, and is inputted to the flip-flop 107-16 having a 1-bit delay (1 ø ₀ is a delay time) by opening the OA gate 107-15. The output is supplied to the secondary oragate 107-15 through the inhibit gates 107-17 to be circulated.

That is, the inhibit gates 107-17 are held until the gate output is inhibited by the output signal (see Fig. 28 (a) (b)) at the output? Of the control timing generation circuit 102.

Therefore, the output signal from the inhibit gates 107-13 is generated from the occurrence of the AND gate 107-6 output until the gate is inhibited as the output of the inhibit gates 107-17.

Accordingly, inhibit bitteu gate 107-13 in accordance with the instructions quartet between ₀ 8ø time width of the key-on signal, 1ø ₀ time width (quintet indicated the absence), 2ø ₀ time width (in the case of two directions quartet) 4ø ₀ time width ( In the case of a quartet instruction), an input instruction signal with an 8 ° ₀ time width (in the case of a quartet instruction) is generated.

In this case, the duplex instruction combines _four line memories L ₀ and L ₁ , L ₂ and L ₃ , L ₄ and L ₅ , and L ₆ and L _{7. In the} quartet instruction, L ₀ to L ₃ and L ₄ to L ₇ Two combinations, the octet is one combination of L ₀ ~ L ₇ , and the same pitch input code is input to the multi-line memory of the scale co-register 20 and the octave code register 21 of FIG. At the same time, the plurality of line memories of the envelope register 54 degrees of FIG. 7 (d) are in an attack state, and the plurality of line memories are operable in each register.

Thus, the AND gate 107-6 output opens the oragate 107-18 at the same time as the 1-bit delay flip-flop 107-16 output described above, and again the oragate 107-19 to which the output signal of the shift register 107-5 is input. And is applied to the endgate 107-20.

OAGATE 107-18 is taken out in synchronization with the input instruction signal, and its output signal is a timing signal corresponding to the pressed key output from OAGATE 107-21 at ANDGATE 107-20. Supplied as a signal.

The shift register 107-5 is sequentially shifted in synchronism with the timing signal (see (b) in Fig. 28 (a)) of the output timing of the control timing generation circuit 102 when the " 1 " signal is written therein. While it is in circulation, it is released but released when the key is released.

The AND gate 107-20 output is supplied as a gate inhibit signal to the inhibit gate 107-22.

On the other hand, as the key is pressed, the keyon signal to be output from the inhibit gate 107-4 is set to flip-flop 107-24 by opening the oragate 107-23, and the set output is the inhibit gate 107-25. Circulation is seen.

The circular hold is an AND gate 107-26 which takes a logical relationship between the output ⓔ timing of the synchronization signal generating circuit 109 (see FIG. 29 (f)) and the carry flip-flop (F / F) 107-2 output. Cleared in synchronization with the generation of the output.

That is, the set output of the flip-flop 107-24 is applied to the inhibit gates 115-22 in the various clock time generation circuits 115, and the third coefficient portion of the shift register 115-1 starts counting operation. The holding time can be calculated by using the system. In this system, it is about 45ms after pressing the performance key.

Thus, the set output signal of the flip-flop 107-24 is applied to the above-mentioned inhibit gate 107-22 by opening the oragate 107-27 as in the above-described switch 0 _{A for} specifying the scale, volume, and volume. Supplied to gates 107-28.

The coincidence detection signal of the primary circuit 121 is applied to the AND gates 107-28 again, and the high-release set (reset) signal is outputted from the output of the AND gates 107-28, and the oragate 92 in FIG. It is set in the high-order sync set register 91.

The coincidence circuit 121 is a high pitched lunar code output from each stage of 0 ₁ , 0 ₂ , 0 ₁ , 0 ₂ , 0 ₄ , 0 ₈ of counters 108 and 111, and scale code register 20 and octave code shown in FIG. You will see a match with the pitch output code from register 21.

That is, when switch 0 _A is set to OFF, pitch codes are input to the line memories of the scale coregister 20 and the octave code register 21 during the holding time of the flip-flop 107-24 (approximately 45 ms). In this case, the high release set signal is output from the AND gates 107-28 and placed in the high release state.

As described above, the high-release state refers to a state in which a note is rapidly extinguished when the playing key is dissociated. In addition, when switch 0 _A is set to ON, the line memory of the same pitch output code as the dissociated play key is set to the high-release state when the play key is dissociated (without output 107-20).

As a result, it is possible to realize an off state of the playing key without a creek.

In this way, the scale controller of the present invention uses the cycle setting means cycle setting control value for setting the cycle of the counting means corresponding to the scale, taking into account the dynamic shift 1 cycle of the multiple-line memory (8 copies in this case). By dividing into, it is possible to perform counting control (+) according to the digital scale, and the control value is memorized by the matrix circuit. Therefore, LSI is converted into a very simple circuit to be a suitable scale controller.

According to the configuration of the present invention, a plurality of waveforms can be simultaneously indicated and synthesized, and the granularity of the volume can be varied between the respective waveforms, so that an effective tone musical sound can be obtained.

Of course, in the above-described embodiment, the volume curve type can be specified for each of the two types of α and β, but this is not limited to two, but two or more waveforms can be synthesized.

In addition, according to the present invention, a plurality of waveforms can be simultaneously instructed and synthesized, and each waveform can have different granularity and arrival of the volume, and can change the period between waveforms with different synthesized sounds by controlling M: N. Can be produced in a variety of ways to obtain a tone, a sound with an extremely variable effect.

Of course, in the above-described embodiment, it is possible to specify each of the two types for each of the volume curve types α and β, but the present invention is not limited to two, but may be made of two or more waveform compositions.

On the other hand, the waveform program designation unit 35 degrees for each block of FIG. 7A is designated as a switch as shown in FIG. 16, but is stored in a fixed enterprise device such as a ROM (lead-on memory) by setting a required instruction state in advance. You may let it do.

In addition, it is possible to devise various methods such as having the necessary instructions be incorporated in the own card, and reading them out in business, and allowing the buffer gear to be flipped into a memory such as flip-flop. The volume curve type can be designated as two types for each of α and β, but this is not limited to two types.

Also, the number of blocks of one sound wave waveform is not limited to 16. The differential coefficients are not limited to only "1", "2", and "4" for each block, and the design can be changed arbitrarily.

Again, a filter circuit may be formed after the D / A conversion circuit, and in this case, for example, a plurality of digital filters may be prepared and arbitrarily selected by a switch. Accordingly, the resonance of an instrument having a wind instrument or an acostech, etc. Different effects can be achieved, such as reverberation characteristics or transmission characteristics of wind instruments.

The scale code register 20, the octave code register 21, the period coefficient register 34, and the envelope register 54 may be constituted by random access memory (RAM).

In addition, various circuit configurations can be adopted within the scope not departing from the gist of the present invention.

As described above, the present invention provides an electronic musical instrument having a period setting means for generating a sound wave waveform in accordance with the coefficient progression of the electronic counting means, and for determining the period of the musical scale by setting the period of the counting means corresponding to the playing key rhythm. In this case, the cycle setting value of the cycle setting means is divided into the number of numbers and the number of tides, and for the number of numbers, the predetermined coefficient value is selected corresponding to the playing key, and the period control by the advancement of the coefficient or the delay is performed. At the plural timings of the predetermined count value state determined in correspondence with the playing keys, the cycle control by the advancement or delay of the coefficients is performed, and a plurality of count value memory line memories corresponding to the plural playing keys capable of playing chords can be formed, thereby allowing a dynamic circulation cycle. Even in this case, each line memory is docked by one cycle setting means. The boundaries of periodic control can be effective.

In addition, as a digital control technology, it becomes possible to use a simplified circuit that performs scale control.

In the present invention, in an electronic musical instrument, a cycle counting circuit that counts one cycle of acoustic sound waves in a plurality of steps is selected, and a block in which a specific number of steps is determined is divided into m blocks. The digital sound technology allows digital sound volume control to set randomly the sound wave waveform by instruction for each block, while the volume control value of digital volume control means is set to "+" or "-". It is possible to provide the used sound setting method, and digitally control the volume control in which the granularity and the arrival curve of the volume such as piano and guitar are different.

As a result, the main control part can be composed of LSI except for the output sound generator, so that it can exert great power in terms of simplification of reliability and can be used as a general purpose electronic musical instrument. will be.

In addition, the present invention uses a digital method to count one cycle of acoustic wave waveforms into a plurality of steps, and by dividing a cycle into blocks by setting one block based on the specific number of steps, and dividing a plurality of different waveforms into each block. Since the granularity and arrival of the waveforms can be specified arbitrarily (including "+" and "-") of digital volume control for each block, the granularity and arrival curve of the volume can be changed between different waveforms. It is possible to arbitrarily set the volume change as well as the top of the waveform to give a remarkable change in overtones structure over time, and to obtain not only a musical sound having an effective tone, but also a circuit using digital technology, which is suitable for LSI. It is controlled like a common circuit and has the effect of being an extremely hard electronic instrument.

In addition, in order to simultaneously indicate a plurality of different waveforms, the present invention designates one waveform for each cycle (one block becomes one or more specific step numbers) for one sound wave waveform, and synthesizes the same waveform. Periodic relationship between the different waveforms of the synthesized sound can be controlled by M: N, so that each of the waveforms to be synthesized has a more natural change over time due to the change of the overtone structure and the overtone structure due to the synergistic effect obtained by synthesizing them. Effective musical notes can be obtained.

In addition, waveform synthesis and periodic control are suitable for LSI by digital technology, and different waveforms can be arbitrarily changed in integer relations, making it an extremely effective instrument.

Claims (1)

Corresponding to the passage of time in the operation of the performance key, the volume curve creation counter 7 for generating a volume control device for digitally controlling the increase or decrease of the performance volume and the musical sound wave for digitally generating the sound waveform. It is connected to the period counting means (3, 34-1, 34-2, 36, 40, 41) for counting one cycle of the waveform in plural steps and two cycle counting means to divide one period of the acoustic waveform into m blocks. Sound wave waveform indicating means (5) for instructing the order and the width of the sound wave waveform to each block of the sound wave waveform by the order 4 or the sum of the sound volume control values being an integer multiple of the order. And 35). The electronic musical instrument comprising one or more cycles of the sound wave waveform divided into m blocks to be arbitrarily designated, and the volume control can be simultaneously performed.

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