JPS6042948B2 - Musical sound waveform generator for electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a musical waveform generating device for an electronic musical instrument that uses a digital method to change the overtone structure of musical tones over time to produce musical tones with effective tones.

In general, the timbre of a musical sound generated by a natural instrument is determined by its waveform based on its frequency spectrum (for example, overtone structure in a steady state) and the volume envelope from rise to decay. The produced musical tones are affected by various other factors, such as the delay in high-frequency components and subtle fluctuations in harmonic components found in brass instruments, etc., as well as the superposition of noise components and noise components found in plucked string instruments, etc. The characteristics unique to musical instruments are due to changes in the overtone structure over time due to the rapid disappearance of harmonic components during decay.

Therefore, in order to remove the unpleasantness caused by electrical signals from musical sounds produced by electronic musical instruments and to give them a natural feel, it is necessary to change the overtone structure over time in addition to the waveform and volume envelope. However, among the electronic musical instruments that have been provided in the past, for example, electronic organs, there is nothing that changes the overtone structure for each note, but simply superimposes a volume envelope on a uniquely defined musical sound waveform.
Furthermore, even if musical tones such as piano or cembalo are preset, the musical sound waveform is a single preset waveform.

Furthermore, in the case of a synthesizer, which is a single musical instrument, the filtering band is changed over time by analog filter operation such as a VCF (voltage controlled filter), but the direction of the change is "low frequency → The operations are relatively simple, such as "high frequency" or "high frequency - low frequency," and various effect devices must be used to express a more natural illusion. Moreover, in a musical instrument that allows chord performance, filters and effect devices must be provided for each key, which not only complicates the circuit configuration and increases the size of the instrument, but also results in an extremely expensive musical instrument. In this way, in conventional electronic musical instruments, changes in the harmonic structure itself over time are performed using analog technology, and there are various problems in applying it to chord performance as it is, and in the end, the harmonic structure changes over time for each note. LSL (
At present, a tone waveform setting technique suitable for large-scale integrated circuits has not yet been established.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a musical sound waveform generator for an electronic musical instrument, which can produce a musical tone with an effective tone by significantly changing the overtone structure over time. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a musical sound waveform generator for an electronic musical instrument according to the present invention will be described in detail below with reference to the drawings.

First, we will explain the basic concept of the musical sound waveform generator of this system.
The explanation will be made in connection with the principle configuration diagram shown in the figure. In Fig. 1, 1 is a group of performance keys not shown (for example, 48 pitch keys that enable a basic range of 4 octaves and 1 dark scale).
This is a pitch input code register that stores different pitch input codes corresponding to each key operation, and this pitch input code is supplied to the pitch clock frequency control circuit 2. Therefore, a different pitch clock frequency signal is generated from the control circuit 2 according to each pitch input code, and the frequency signal is sent to the cycle counting circuit 3, which counts the cycle of one basic cycle of the musical sound waveform in multiple steps. Supplied as a signal. The period counting circuit 3 is preferably composed of a counter that performs binary counting operation, and in this example, r1'12jr4'9r8j
It is 8 bits weighted by r16"9r32"9r64,1128. R25
This is a circuit that obtains 1256 counting states up to 5J, so that one basic cycle of a musical tone waveform is represented by R256 counting steps corresponding to each count value of R256 digits. The counting steps of this R256J are divided into blocks with a specific number of steps of 1 or more as one unit, and one cycle is divided into m blocks. That is, in this example, it is divided into m=16 Rl6J blocks, and one block has 116 counting steps (
Therefore, Rl6J, r3 of the period counting circuit 3
The state of the 4-bit count value represented by the wait stages of 2J, r64J, and rl28J can be associated with the address of the block of R16 over time, which is shown in Table 1. The 8-bit output of each stage of the period counting circuit 3 is supplied to the pitch clock frequency control circuit 2, which controls the output frequency of the pitch clock frequency signal corresponding to the pitch input code, as will be described in detail later. They will be forced to do this. Furthermore, the output of the upper 4 bits (weights R16, R32J, r64J, and 1128) of the period counting circuit is sent to the waveform program specifying section 5 for each block as a block address signal for 16 blocks via the decoder 4.
supplied to This waveform program designation section 5 is indicated by a one-cycle musical waveform ROJ-Rl5. The amount of change in the amplitude of the rise and fall of the waveform at each block address (
In this example, the absolute value of ROJ, llj, r2J, r4j) is specified with + (up) and 1 (down),
The amount of change (differential value) in this amplitude will be referred to as a differential coefficient. The differential coefficient value specified for each block address by the waveform program specifying section 5 and the specifying signals of 1+yo and r-yo are sequentially outputted in synchronization with the block address signal from the decoder 4 and supplied to the multiplication circuit 6. The multiplier circuit 6 also includes a volume curve creation counter (hereinafter referred to as an envelope counter) 7 that digitally controls the volume to increase or decrease the performance volume as time elapses from the time the performance key is operated. The control value (counter count value) is supplied, and eventually the differential coefficient value of the waveform program specifying section 5 and its 1
+J, r- will be multiplied in synchronization with the block address according to the instructions. The envelope counter 7 controls a specified clock (referred to as an envelope clock) according to one of the various volume curve (referred to as an envelope hereinafter) modes to be described later, to each of attack, decay, and release, which will be described later. The count is controlled to increase or decrease depending on the volume control state of the volume.
In other words, the count value of envelope counter 7 is 10~R
This is an integer value of 3l, which will be referred to as an envelope coefficient value (denoted as E). One example of envelope mode is shown in FIG. Therefore, the waveform program specification section 5
The differential coefficient value specified in advance for each block address is specified to indicate an integral multiple of the envelope coefficient value E shown in FIG. 2 with 1+yo or 1-yo; As an operation, the multiplication circuit 6 performs the calculation (differential coefficient value×envelope coefficient value E). That is, FIG. 3 is an illustration of one example, and shows the relationship between the envelope coefficient value E and the differential coefficient value of each block of block addresses 10-Rl5J in one cycle of the musical sound waveform. mode is second
In the case shown in the figure, the envelope coefficient value E is R5. J, r
The amount of change in the relative magnitude of the musical sound waveform including the volume control value at the points 1O, R2O, and R3O (indicated by the x marks in Figure 2) is shown in Figure 4 A, B, and C. It becomes like that. Of course, the relative change in the tone waveform changes sequentially depending on the envelope coefficient value E over time. still,
In this example, only block address ROJ has differential coefficient value J+
The amount of change is always zero when the designation of , 1, and 1 is performed. The output of the multiplication circuit 6 is supplied to one input side of the adder 8, and the output of the adder 8 is fed back to the other input side of the adder 8 via the accumulator 9. Therefore, the multiplication output of the previous block is This time for the value. The amount of change, which is the multiplication output value of the block, is accumulated.In the end, the musical sound waveform diagrams in FIGS.
It is extracted as the output of

The output of the accumulator 9 is then outputted via a D/A converter (digital-to-analog converter) 10 as a pitch corresponding to the performance key operated by the speaker 11. In this way, the tone waveform settings can be divided into multiple blocks of one cycle of the tone waveform, and the differential coefficient values of the waveform rise and fall for each block can be arbitrarily specified, and at the same time, the relationship with the envelope coefficient value can be specified. This also allows for volume control. Next, we will explain in detail a specific configuration example of the present invention based on the above concept, but first, we will explain the logical symbols used in the following drawings in FIGS. 5A, B, C, D, and E, which include logical formulas, truth tables, and general logical symbols corresponding to each logical symbol, as well as examples of combinational circuits. .

What must be particularly noted here is that the inverter symbol attached to the input line of an OR gate and an AND gate is valid only for that gate.For details, please refer to the combinational circuit examples in each figure. FIG. 6 shows a combined state of FIGS. 7A, B, C, and D.

In Figure 7A, 20 is 4 bits ClJ, r2, R
It has an input/output end of 4jr8j weight), and 4jr8j weight).
A scale code register consisting of 8 line memories that shift bits in parallel, 21 is a 2-bit σ1J,r
This is an octave code register consisting of eight line memories that shift 2 bits in parallel in the direction of the arrow, and has input/output terminals for 2-bit input/output. will begin to remember. That is, the corresponding scale input code and octave input code are input to the AND gate 22 in synchronization with the generation of an input instruction signal related to the operation of the performance keys, which will be described later.
~27, Or Gate 28-1 ~ 28-4, Or Gate 2
The signals are input to a scale code register 20 and an octave code register 21 via 9 and 30, respectively. The input scale code and octave code (hereinafter referred to as pitch code) are sequentially shifted in parallel in the direction of the arrow by a shift pulse φo (the basic clock of this system), and after a shift time of 8φo, each output terminal A so-called dynamic shift operation is performed in which the signals are circulated again through inhibit gates 31-1 to 31-4 and inhibit gates 32 and 33, respectively. Then, the inhibit gates 31-1 to 31-1 are activated in synchronization with the new input instruction signal.
By closing 31-4 and inhibit gates 32-33, the pitch code in each register 20, 21 is controlled to be erased. Also, scale code register 2
0. Since the octave code register 21 has eight line memories, for example, even if a maximum of eight performance keys are operated at the same time, the timing of the corresponding scale input code and octave input code will be synchronized with the input instruction signal. It is possible to input data sequentially in order of order and dynamically shift and cyclically hold each data.

In other words, eight sounds are controlled in a time-division manner. The scale chords and octave chords in this system are listed in Tables 2 and 3. 34 is musical waveform 1
A cycle counting register that counts cycles according to the scale codes stored in circulation in the scale code register 20 and the octave code register 21, respectively;
Similar to the scale code register 20 and octave code register 21 described above, a shift pulse φ is applied in the direction of the arrow.

The memory is comprised of eight line memories which are sequentially and dynamically shifted according to the following. This period count register 3
4 is basically a 4-bit multiplier (the first
A block counting register 34-1 consisting of the block addresses of Rl6J blocks of RO to Rl5 shown in the table) and a block to be described in detail later for taking out the addition timing signal that commands the block counting increment. From the 4-bit cycle count register (TC register) 34-2 that controls the number of steps per cycle and the 3-bit octal cycle count register 34-3 that is counted and incremented every cycle of the block count register 34-1. It will be configured. The count contents of each line memory generated from each output of the block count register 734-1 and the cycle number register 34-3 pass directly through the waveform program designation section 35 for each block, which will be described later. The adder 36 is dynamically held in circulation through each of the inhibit gates 37-1 to 377-7, which are circulation gates, and in this circulation cycle, the adder 36 makes a binary counting step.
is incremented by 1+1J when the above-mentioned addition timing signal is generated. In addition, the 4 bits of the block count register 34-1) (RlJ, r2, R4, R8 wait) output (see Figure 8a) is used to detect a specific block address among the block addresses of Rl6. The RO block address signal shown in FIG. 8b is supplied from the output 9 to the block state detection circuit 38 of
The output signals shown in FIG. 8 are taken out from 3 and 4, respectively. Among them, outputs 1 to 4 are supplied to a scale step matrix circuit 39 which determines the number of step corrections for each scale, which will be described in detail later. That is, the output 9 of the block state detection circuit 38
By sequentially connecting the invertenoid AND gate 38-1 and the inhibit gates 38-2 and 38-3 in series, the weights r1, R2J, r4, and R8J are all ゜“0゛〔T ROJ under the conditions of −Σ・T−T]
Output 1 takes the output of weight RlJ as it is and outputs the odd block address signal. Output 2 outputs the odd block address signal when weight 11J is '4'' and weight R2J
R2 yo, R6 yo, RlO.J, rl
4 block address signal, output 3 is wait R4J
is ゜゜1゛, and weights R2 and r1 are both ゜゛O
In order to obtain the condition [4・l・complete], inhibit gates 38-5 and 38-6 are connected in series and R4, r
l2J block address signal, output 4 is wait R8
In order to obtain the condition [8・T−]・T] where J is 6′r′ and weights R4J and r′2Jr1J are “゜0゛”, inhibit gates 38-7 to 38-9 are connected in series in sequence. R8
J block address signals are output respectively. On the other hand, the output of each 4-bit stage of the synchronous counting register (TC register) 34-2 is connected to the input of an adder 40, and the output of each 5-bit stage of this adder 40 is connected to a subtractor (subtractor) 41. The 4-bit output of the tractor 41 is the inhibit gate 42-1 to 42, which are circulation control gates.
-4 to the input side of the corresponding bit stage.

Further, the outputs of each stage of the synchronous counting registers 34-2 are the addition timing generation circuits 43 and 1 which output the addition timing signals supplied to the adder 36 in accordance with each octave.
, R2. , r4J weights are supplied to a weight shift circuit 44, which will be described later. Furthermore, this addition timing generation circuit 43 and weight shift circuit 44
An output signal of an octave code decoder 45 that generates first to fourth octave signals 01 to 04 according to the output state of the 2 bits output from the octave code register 21 is coupled to the octave code decoder 45 . That is, the inverted AND gate 45-1 of the octave code decoder 45 receives the first octave signal 01, the inhibit gate 45-2 receives the second octave signal 02, and the inhibit gate 45-3 receives the second octave signal 02.
and AND gate 45-4 output the third octave signal 03 and the AND gate 45-4 output the fourth octave signal 04 by detecting the code states shown in Table 3 above, respectively. The octave signals 01 to 03 are supplied to AND gates 43-1, 43-2, and 43-3 of the addition timing generation circuit 43, respectively, and the octave signal 0 is generated. is sent to AND gate 44-1 of weight shift circuit 44, octave signal 03 is sent to AND gates 44-2 and 44-3, and octave signal 0 is sent to AND gate 44-1 of weight shift circuit 44.
4 is supplied to AND gates 44-4, 44-5 and 44-6. The AND gate 43-1 of the addition timing generation circuit 48 has r1 and R2 of the synchronous counting register 34-2.
The output signal of J, r4 weight is OR gate 43-4,
43-5 and output from the OR gate 43-4, the output signals of R2J and r4 wait are connected to the AND gate 43-2, and further to R3. The output signal of the J weight is coupled to an AND gate 43-3. In addition, the outputs of these AND gates are input to inhibit gates 43-6 and 43.
-7 and an inverted AND gate 43-8, and the output signal of weight R8J is further coupled to the inverted AND gate 43-8. The output of these inverted AND gates 43-8 is connected to the inhibit gate 43-7, and the output of the inhibit AND gate 43-7 is connected in series to the inhibit gate 43-6. The above-mentioned addition timing signal is obtained from the output of -6. That is, FIG. 9 shows the synchronization count register 3 in one line memory.
As can be understood from the drawing showing the counting state of 4-2 (FIG. 9a), the signals shown in FIG. The output signal is taken out from the output 4 of the inhibit gate 43-6 as the output signal shown in FIG. That is, in the first octave signal 01, the synchronous count register 34-2 counts 10J only, and in the second octave signal 02, it counts ROJ. l5r
Only lJ time measurement, 3rd octave signal 03 is RO~
Only when counting 13J, the 4th octave signal 04 is RO
The addition timing generation circuit 43 outputs the addition timing signal only when counting J-R7. Then, the addition timing signal obtained in this way is added to the adder 4.
0 to 1+8J addition command signal, and AND gate 4
6-1 to 46-4 as a gate opening signal, and is also applied as a 0+1J addition command signal to the adder 36 in FIG. 7B. On the other hand, octave signals 01, 02, 0
3 and 04 pass through the addition timing generation circuit 43 and are respectively 0-1 to the subtractor 41 in FIG. 7B.
．． It is supplied as a command signal for Jr-2, R-4, and R-8J.

Therefore, in the circular loop of cycle count register 34-2 → adder 40 → subtractor 41 → synchronous count register 34-2, basically the count memory value output from synchronous count register 34-2 is The adder 40 adds 1+8J in synchronization with the addition timing signal, and the addition result is a numerical value corresponding to octave signals 01-04 (1-13 for octave signal 01, 0-2.j. octave for octave signal 02). For signal 03, subtraction is performed by 1-4J, and for octave signal 04, it is subtracted by 1-8J. The adder 40 has an AND gate 46-- which is opened in synchronization with the generation of the addition timing signal.
A step correction number corresponding to the scale from 1 to 46-4 is supplied from the scale step matrix circuit 39 in accordance with the block calculation state of the block calculation register 34-1. In other words, one cycle of the musical waveform consists of R16 block addresses as time progresses, and each block address consists of a clock number that is 8 times or more the basic clock φo (a cycle that is 8 times the basic clock period or more). Become. This basic clock φ. One shot corresponds to one step of the musical sound waveform, and each block address ends up being more than eight steps. The highest tone in this system is when each R16J block address of one cycle of the musical sound waveform has 8 steps, making a total of 128 steps.
(Actually, as you will see later, in this system, the number of steps is 130 as the highest note (C#7).) Then, the number of steps between each scale from the number of steps of the highest note to one octave below is calculated. By increasing the number of steps to the opening factor of 21Σ, the cycle becomes longer and lower pitches are obtained in accordance with the scale.The number of step corrections corresponding to this scale is incorporated into the scale step matrix circuit 39, which will be explained next. The scale step matrix circuit 39 in FIG.
4 output signal and the 4-bit output of the scale code register 20 are input.

This scale step matrix circuit 39 is provided with an AND function matrix circuit 39-1 that detects the chord state of each dark scale shown in Table 2, and has 12 output lines 1 to 1 corresponding to the scale. O (from the C scale detection line to the C# scale detection line shown in the figure) is taken out, and the first OR function matrix circuit 39-2 and the second
It passes through an OR function matrix circuit 39-3 and is coupled to AND gates 39-4 to 39-14. The first OR function matrix circuit 39-2 performs C-C for each scale.
# in order RO, O, l, l, 2, 2, 3, 4, 5, 5,
The step addends of 6 and 7 are output on lines Xl, X2, and X3.
It outputs a chord consisting of three chords, and its step addend is added to each R16J block for each scale. That is, as shown in Table 4. The second OR function matrix circuit 39-3 is a circuit for giving a step correction addend to each scale of one cycle of a musical sound waveform.In this case, if the step correction addend value is applied to multiple block addresses, The outputs 1 to 4 outputted from the block state detection circuit 38 are selected according to each scale in order to add them on average.As shown in FIG. The indicated block address is selected.

The selection signal is the AND gate 39-4 according to the musical scale.
~39-14 will be supplied. Furthermore, the outputs of AND gates 39-4 to 39-14 are output to OR gate 39-1.
5 to 39-25 in series, and RlJ to Rl for each scale from the output line X4 of the final OR gate 39-25.
A 1+1J correction signal is output to a selected block address out of 5J. That is, the step correction number output from the scale step matrix circuit 39 is (step addend+step correction addend). In addition, or gate 39
Since the "0" signal is supplied to one end of the -15, the output of the AND gate 39-4 is directly obtained from the OR gate 39-15.
The output signals from the output lines Xl, X2, X3, and X4 are connected to the inhibit gates 47-1 to 47-4 whose gates are opened except when the block address signal output from the block state detection circuit 38 is generated. is supplied to Inhibit gates 47-1 to 47-3 are supplied to AND gates 46-2 to 46-4 via corresponding OR gates 48-1 to 48-3, respectively, and the output of inhibit gate 47-4 is supplied to AND gates 46-2 to 46-4, respectively. The signal is supplied to the gate 46-1. Therefore, except for the JO job address signal, in synchronization with the generation of the addition timing signal, a step correction addend that is 1+1J is added to the adder 40 in addition to 1+8J for the step addend for each block address and the selected block address. It will be supplied as a signal. Also, when the ROj block address signal output from the block state detection circuit 38 is generated, the OR gate 4
A 1+2 correction value is applied via an AND gate 46-3, and the 1+2 correction value is applied in synchronization with the generation of the addition timing signal.
This will be added together with the 8-jo addition. In the end, adder 4
The addition value for each block address based on the scale supplied to 0 is the 10th in the highest octave (4th octave signal 04).
Furthermore, this value corresponds to the number of steps (basic clock number) in the block address, and the number of steps in one cycle of the musical sound waveform of each scale is also shown on the right in Figure 10. It is shown in the column. That is, the number of steps between each scale is 121Σ.
Of course, the above-mentioned addition timing supplied to the adder 40 differs depending on the octave signals 01 to 04, and the value subtracted by the subtractor 41 also depends on the octave signals 01 to 0.
4, and as the octave becomes lower (in the direction of octave signal 01), the period of one cycle of the musical sound waveform becomes longer. Therefore, the period counting register 34
The scale code register 20 and the octave code register 21 have eight line memories, and one cycle in the arrow direction of each register is one cycle with an 8φo shift pulse, so the musical waveform can only be controlled every cycle. Normally, this is not possible, but according to this system, by using the shift memory described below, it is possible to control any position within one register cycle.

That is, in this system, eight line memories are arranged in the direction of the arrow on the output sound generation section side (immediately before the D/A conversion circuit) in FIG. 7c, and the basic clock φ is used. A shift memory 49 that performs a shift operation is provided. This shift memory 49 stores the 3 bits (Rl.J, r2ll4 weight) output from the weight shift circuit 44 described above in FIG. 7A.
One of the eight line memories is addressed by the code represented by , and the address is ROJ-R7 in order from the line memory closest to the output side. That is, with this address specification, a maximum of 8φo
This makes it possible to delay shift time. Further, the address of this shift memory 49 is specified only when the addition timing signal output from the addition timing generation circuit 43 of FIG. 7A is supplied via the AND gates 50 and 51 of FIG. 7C. The output signal of the AND gate 51 applied to the shift memory 49 is called an enable signal. The output of the weight RlJ of the synchronous counting register 34-2 is applied to the AND gates 44-1, 44-3 and 44-6 of the weight shift circuit 44 in FIG. is applied with the output of the weight R2J, the output of the weight R4 is applied to the AND gate 44-4, the AND gate 44-6 is applied to the output line Y1, and the AND gates 44-3 and 44-5 are applied to the OR gate 44-7. to output line Y2 through AND gate 4
4-4 and 44-5 are coupled to output line Y4 via OR gate 44-9, which is supplied with the outputs of OR gate 44-8 and AND gate 44-1.

That is, 3 represented by these output lines Yl, Y2, Y4
The bit output is now supplied to the shift memory 49 as an addressing code, and the synchronous counting register 34
The output of -2 becomes the address designation shown in Table 5 in accordance with the octave signals 01 to 04. Then, the output values from the adder 52 are sequentially outputted from the almost addressless line memory "λ('-(7)1i■i"), which will be described in detail later.

It is taken out from the output of the shift memory 49 which has been shifted up by a pulse. Similarly, one cycle of the musical sound waveform for each scale is the basic clock φ.

The number of steps is different for each scale, and the operation will be explained using FIG. 11A in order to better understand how to create a cycle for each scale. The operation in Figure 11A is the highest octave 0 shown in Figure 10.
4 and the scale name is "C". Since the addition timing signal is output from the addition timing generation circuit 43 when the period counting register 34 is in the initial state of 10J, the RO output from the block state detection circuit 38 is OR gate 48 and AND gate 46- in synchronization with the block address signal.
3, it will be given along with the 1+2J correction value power increase +8J addition command, so the adder 40 will give (A)+1
0) is added. This added value 10 is subtracted by 1-8J by the fourth octave signal 04 in the subtractor 41, and the subtracted output value R2J is fed back to the synchronous count register 34-2. Further, the addition timing signal is supplied to the adder 36 as a 1+1j addition command, and is also supplied to the shift memory 49 in FIG. 7C as an enable signal.
At this time, the address of the shift memory 49 is 10, and the output timing state is such that the output value of the adder 52, which will be described later, can be immediately output from the line memory RO of the shift memory 49. Next, after 8φo shift time, R2 is output from the synchronous count register 34-2, and 1L is output from the block count register 34-1 (respectively as shown in FIG. 11A (7).
(See B, e). At this point, the block count register 34 is
Since the output of -1 is r1, one output of the block state detection circuit 38 is applied to the scale step matrix circuit 39, but in the scale ゛゛C゛, no output signal is generated from this matrix circuit 39, so the adder No step correction number is given to 40, and only the 1+8J command is supplied in synchronization with the addition timing signal, resulting in (2+
8) is performed. Furthermore, 1- with subtractor 41
8J is subtracted, and the subtracted power value R2J is finally returned to the synchronization count register 34-2. Further, the 1+L signal is supplied to the adder 36 in synchronization with the addition timing signal, and the addition value R2
The data is returned to the block count register 34-1. Further, this addition timing signal is applied to the shift memory 49 as an enable signal, and the synchronous counting register (TC)
Since the output value R2J of 34-2 is supplied to the weight shift circuit 44, the ゜゜1゛ signal is taken out from the output Y2, and as can be seen from Table 5, the address R2 of the shift memory 49 is specified. become. As a result, the output timing of block address 1 is delayed by 2φo shift time as shown in FIG. 11A(7)i.
It will be in a state where it will be output from. That is, block address R
OJ (there are 10 steps during 5r1J).
Thereafter, the same operation is repeated, and in the scale 64C1', the intervals between the following block addresses are 8 steps, and one cycle of the tone waveform has 130 steps as shown in FIG. Also, in FIGS. 11B and C, the scale ゛"B゛゜゜C # in the fourth octave signal 04 is also shown.
An explanation of the operation is shown in a manner similar to the state diagram of FIG. 11A. Figure 12 shows the shift memory 4 in Figure 7C.
9 and the details of adder 52, 49-1 to 49-4
9-8 are 8 line memories each consisting of 10 bits (
49-4 to 49-7 are omitted in the drawing) and a basic clock φ. to shift. Each line memory 49-1 to 49-
Input control circuits 49-9 to 49-16 are provided on the input side of 8, and although a gate circuit for only one bit is shown in the drawing for simplification, it is a gate circuit that is similar for all bits. It consists of Further, the 3-bit address designation signal Yl, Y2, Y3 of the weight shift circuit 44 of FIG. be exposed. That is, the line memories 49-1 to 49-8 are associated in the order of addresses RO to R7j. Therefore, the designation signal of address ROJ-R7J is applied to the AND gate 49-18 to which the enable signal is supplied.
~49-25, and its output is input to the input control circuit 49-25.
19-49-16. Input control circuit 49-9
49-16 is for inputting the output of the adder 52 from the line memory at the designated address and sequentially shifting it to the output side. The output of the line memory 49-1 is then supplied to the D/A conversion circuit (see FIG. 1) via the output adder 49-26 and the latch circuit 49-27. Moreover, the output of the latch circuit 49-27 is output to the output adder 49-
It is accumulated by circulating the data 26 times. Furthermore, the output of the line memory just before the specified address of the line memories 49-1 to 49-8 is sent to the OR gate 49.
-28 (only 1 bit shown) through adder 5
2 corresponding weight stages. Next, Figure 7A
53 is a synchronous set register consisting of eight 1-bit line memories connected in series, and 54 is an envelope register with 7 bits CL9r'2"9r4"9r8"9r1
It consists of eight line memories (6"9r32"9r64" weight) connected in parallel in the direction of the arrow.
Both are shift pulses φ.

are sequentially shifted in the direction of the arrow in synchronization with. In short, the scale code register 20, the octave code register 21, the period count register 3 synchronization set register 53,
The envelope register 54 is associated with each line memory. That is, for the pitch code output from the scale code register 20 and octave code register 21, the corresponding control output is sent to the period counting register 3. The signal is generated from the male synchronous set register 53 and the envelope register 54. RL of the envelope register 54, r2 . J, r4J
The envelope coefficient value is indicated by the 32 count values of ROJ-R3l expressed by the 5-bit output of J32., r8, and 116J weights. The two weight bits of J, r64J indicate four envelope states: attack, decay, release, and clear of the envelope. Therefore, 7 of the envelope register 54
The output of each stage of bits is applied to the corresponding weight input terminal of the adder 55. Each bit output of the adder 55-1 that counts the envelope control value in the adder 55 is input to the envelope register r1, R2yo, R4. , r8jrl6J are circulated to the corresponding input side of the weight. Further, the carry output signal generated from the adder 55-1 is sent to the envelope register 54.
An inhibit gate 55 whose gate is prohibited by the output of an inverted AND gate 57 that detects the clear state of ROOJ using state detection weights R32J and R64.
-2 to the carry input terminal of the adder 55-3 for state counting. That is, the adder 55-3 accepts the carry output signal except in the envelope clear state. The output of the adder 55-3 is then R32J, r64. of the envelope register 54. The signal is held at the weight input terminal of J via inhibit gates 58-1 and 58-2. Also, this envelope register 5
The input instruction signal of the performance key shown in FIG. 7A is applied to the input side of the R32J wait stage of No. 4 through the OR gate 59, and therefore, the envelope immediately enters the attack state upon generation of the input instruction signal. It becomes like being left behind. Here, Table 6 shows the relationship between the envelope state and the 2-bit code state of weights R32 and R64J. The synchronous set register 5 in FIG. 7A
The output of 3 is AND gate 60, inhibit gate 61
is applied to one input terminal of

The other input terminal of the AND gate 60 is supplied with the output of an AND gate 62 which takes the logical product of the RO block address signal and the addition timing signal outputted from the addition timing generation circuit 43. Further, the setting of the synchronization set register 53 is such that a clock signal outputted from the inhibit gate 63 (collectively referred to as an envelope clock) passes through OR gates 64 and 65 and is set on the input side according to the state of the envelope, which will be described in detail later. This is done by applying . Incidentally, since the inhibit gate 63 is applied with the serially connected output signals of the inhibit gates 66-1 to 66-5 and the inverted AND gate 66-5, which detect the all ROJ state of the envelope register 54, the all ROJ state is applied to the inhibit gate 63. In the active state, the envelope clock is controlled so as not to pass through this inhibit gate 63. When the r1-o signal is set in the synchronization set register 53, the RO. AND gate 60 in synchronization with the addition timing signal of J block.
is released, an addition timing signal to the adder 55 is generated, and the output of the inhibit gate 61 is inhibited, so a "0" signal is written to the synchronous set register 53 and the set is released. gate 6
The addition timing signal output from 0 is AND gate 6
7-1 to 67-5 as a gate open signal, and an addition value to an envelope adder 55, which will be described later, is used to calculate the envelope time elapsed in the attack, decay, and release states. It will start to change. That is, the synchronization set register 53 is for synchronizing the added value applied to the envelope adder 55 with the ROJ block address of the musical tone waveform. Also,
When the output of the synchronous set register 53 is ROJ and the envelope register 54 is all RO, the inhibit gate 68 outputs a reset signal to be described later. Rl. of the envelope register 54. , l2J, r4J, r'
81r16! The 5-bit weight output is sent to the exclusive OR gates 69-1 to 69 of the weight shift circuit 69.
-5 respectively. Switch Sl in Figure 7C
, S2, S3, S4, S5, and S6 are volume curve format designation switches for α and β, and the set of switches Sl, S3, and S designate attack A1 decay D1 release R in the α volume curve format, respectively. The set of switches S2, S4, and S6 respectively indicate A, D, and R of the β volume curve type.

That is, seven types of volume curve formats can be specified using three switches as shown in Fig. 13, and in this example, two types of volume curve formats can be selected at the same time, and one can be selected at α.
(selected by switches Sl, S3, ■), and the other is called β (selected by switches S2, S4, S6). Therefore, the types of combination instructions for α and β volume curve formats are as shown in FIG. Now, as explained in FIGS. 1 to 3, the waveform program designation section 35 of the block address mentioned above in FIG.
Each block address of Rl6J indicated by OJ-Rl5J indicates the differential coefficient value of the rise and fall of the waveform with 1+J (up) and - (down), and furthermore, for each block address, the above-mentioned It is possible to specify either α or β in a previously specified volume curve format, and in the case of β instruction, the RlJ signal is output, and in the case of α instruction, the ROJ signal is output. That is, an example of the specification is shown in FIG. 15, in which the differential coefficient values Rljr2jr4J and 1+Jr-yo are specified for each block, and the volume curve format of α and β is also selected. It is becoming possible to do this. In this way, one period of the musical sound waveform is divided into 16 blocks, and each block is divided into 16 blocks.
It comes to belong to one of two groups: the α group and the β group. The details of the waveform program designation section 35 are shown in FIG. 16, and the differential coefficient values r1, R2,
Switches A1 to Al5, which specify the absolute value of R4J,
Bl6, α/β volume curve format instruction switch C1 to Cl5
, +/- instruction switches D1 to Dl5 are provided, and the common line of the switch group for each block address indicates the count value r1 to Rl5 of the block count register 34-1.
The block state detection signals of the two are combined. Furthermore, differential coefficient value designation switches A1 to Al5, B1 for each block
~Bl5 are respectively differential coefficient values Rl.~Bl5 via decoders E1~El5. Three instruction signals, J, r2, and R4J, are output, and the corresponding instruction signals are eventually taken out via an OR gate. Furthermore, block address ROJ
Since is always set to the ROJ level, there is no switch specification, and therefore block addresses R1J to R15 can be specified. Therefore, the waveform program specification section 35
The (-) command signal specified for each block address is supplied to the adder 52 in FIG. 7C, and the differential coefficient value RL is
, r2J, and r4J are applied to the weight shift circuit 69 in FIG. 7C, and the β command signal is applied to the exclusive OR gates 70 and 71 in FIG. and,
This β command signal is normally exclusive or gate 7
0, the inhibit gates 72-1 to 72-3 and the AND gate 7 of the αβ volume curve type control circuit 72
2-4 to 72-6. Therefore, AND gates 72-4 to 72-6 are synchronized with the β instruction signal (“1”),
The inhibit gates 72-1 to 72-3 are output in synchronization with the instruction signal (゜“0゛) in accordance with α and β selected and instructed by the αβ separate volume curve format instruction switches S1 to S6. Therefore, the outputs of the inhibit gate 72-1 and the AND gate 72-4 are sent to the OR gate 72-7, the outputs of the inhibit gate 72-2 and the AND gate 72-5 are sent to the OR gate 72-8, and the outputs of the AND gate 72-4 are sent to the OR gate 72-7. -3
The output of AND gate 72-6 is connected to OR gate 72-9. The output of the OR gate 72-7 is the AND gate 72-10, the inhibit gates 72-11, 72
-12 and the AND gate 72-13, and the output of the OR gate 72-8 is supplied to the AND gate 72-14 and the inhibit gate 72-12.
The output of is supplied to AND gate 72-15. Also,
The output of AND gate 72-14 is applied to the inhibit gate 72-11 and AND gate 72-13. Further, the AND gate 72-10 and the inhibit gate 72-11 pass through the OR gate 72-16 to the OR gate 72-17, and the output of the inhibit gate 72-12 passes through the AND gates 72-18 to the OR gate 72-19.
, AND gates 72-13 and 72-15 are supplied to OR gates 72-20, and further OR gates 72-17 and 7
2-19 and 72-20 are connected in series and are eventually supplied to the AND gate 50 as the output of the OR gate 72-17. Said And 72-10, 72-14, 72
-15, 72-18 are envelope state detection circuits 73;
That is, normally, the inverted AND gate 73-1 is connected to the detection signal from the envelope RO.
OJ clear state, inhibit gate 73-2 is in attack state, inhibit gate 73-3 is in decay state,
AND gate 73-4 detects the release state, inhibit gate 73-2 goes to AND gate 72-10, inhibit gate 73-3 goes to AND gate 72-14,
72-18 as a gate open signal. Further, the inverted AND gate 73-1 is supplied to the inhibit gate 73-5 together with the all ROJ state detection signal of the envelope register 54 (see FIG. 7D marked with *), and the inhibit gate 73-5 is 73-5
The output of is further connected to AND gate 73-4 and OR gate 7.
3-6 to the AND gate 72-15 as a gate open signal. Therefore, the OR gate 72-16 of the αβ-specific volume curve format control circuit 72 is in the attack state when the volume curve format is in the instructions 4 to 7 in FIG. 13, and in the decay state when the volume curve format is in the instructions 2 and 3 in FIG. The AND gate 72-18 takes out the R3lJ command signal in the case of instruction 4 in FIG. 13, which is in the decay state and there is no decay instruction when there is an attack instruction. In addition, the or gate 72-20 is the descending instruction for Decay and Release, 1, 3, 5 in Fig. 13,
In the case of 7, it is taken out as a signal indicating a complementary value obtained by inverting the envelope count value. On the other hand, or gate 72-
17 is output in each attack, decay, and release state only when a switch instruction for attack A1 decay D1 release R is given, and outputs the addition timing signal at that time as an enable signal to the shift memory 49.
The R3lJ command signal output from the AND gate 72-18 is sent to the OR gate 69-6 of the weight shift circuit 69.
~69-10 and the complement command signal output from the OR gate 72-20 is the exclusive OR gate 6.
Exclusive OR Gate 69 via 9-11
-1 to 69-5. That is, the weight shift circuit 69 inputs Rl, r2 . ，
The envelope coefficient value given by r4, R8J, rl6Jl weight is an exclusive or gate 69
−1 to 69-5 and the differential coefficient value RlJ for each block address specified by the waveform program specifying unit 35,
A weight shift (in this case, the differential coefficient value x the envelope coefficient value E) is performed in accordance with the designated coefficient values of r2J and r4J, and the multiplied value thereof is supplied to the adder 52. That is, the instruction signal of differential coefficient value RL is input to one input terminal of AND gates 69-12 to 69-16, the instruction signal of R2J is input to one input terminal of AND gates 69-17 to 69-21, and the instruction signal of R4J is input to one input terminal of AND gates 69-17 to 69-21. ANDGATE 69-22~
It is supplied to one input end of 69-26. The other input terminals of the AND gates 69-12, 69-17, and 69-22 receive a signal corresponding to the weight RlJ of the envelope coefficient value.
The other input terminal of AND gate 23 receives a signal corresponding to weight R2j, the other input terminal of AND gates 69-14, 69-19, and 69-24 receives a signal corresponding to weight R4J, and AND gates 69-15, 69- A signal corresponding to the weight R8J is supplied to the other input terminals of the AND gates 20 and 69-25, and a signal corresponding to the weight Rl6 is supplied to the other input terminals of the AND gates 69-16, 69-21 and 69-26. become. Furthermore, AND gate 69-12 is connected to AND gate 69-13 and 6 on the input side of weight 11 of adder 52.
9-17 is weight R2 via or gate 69-27
On the input side of J, AND gates 69-14, 69-18,
69-22 is an AND gate 69-1 on the input side of weight R4J by OR gates 69-28 and 69-29.
5, 69-19, 69-23 is or gate 69-30,
AND gates 69-16, 69-20, and 69-24 are connected to the input side of weight R8J through OR gates 69-32 and 69-33, and AND gate 69-31 is connected to the input side of weight R8J. 21 and 69-25 are connected to the input side of weight R32 through OR gates 69-34, and AND gate 69-26 is connected to the input side of weight R64. Therefore, this weight shift circuit 6
9 is the 17th one according to the differential coefficient values RlJ, r2yo, R4yo.
The multiplication value shown in the figure is obtained. Then,
R3l output from αβ volume curve format control circuit 72
When the J command signal is supplied to the OR gates 69-6 to 69-10, the envelope coefficient value is forced to R3lJ regardless of the output of the envelope register 54. Also, the complement command is an exclusive or gate 69
-11, the envelope coefficient value represented by the 5 bits of the envelope register 54 is inverted, and the first
The multiplication value shown in FIG. 7 is the inverse count value. Therefore, the difference from the cases shown in Figures 1 to 4 is the first point.
As can be seen from Figure 5, the multiplication for each block address is α,
It is to follow the volume curve format specified for each β, and in the end, the differential coefficient value x the envelope coefficient value E (however, E is α
If the volume curve format is followed, then Eα, and if the volume curve format is followed, it will be Eβ).

The multiplication value input to the adder 52 in this manner is supplied to the shift memory 49. That is, by specifying the two volume curve formats α and β, it is possible to simultaneously specify the waveform according to α, and as a result, the rise and fall curves of the respective volume can be made different between different waveforms. By combining these, it is possible to create a synthesized musical sound waveform that is rich in variety.

For this reason, the overtone structure changes significantly over time, making it possible to generate musical tones with effective timbre.
It is especially suitable for expressing the unique characteristics of brass instruments and plucked string instruments when producing sounds. In FIG. 7B, the switches SlO, SlI, Sl.

is supplied to a period (called duty) control circuit 74,
When these three switches are on or off, eight mode designation signals indicated by numbers RO~R7J are taken out from the AND function matrix circuit 74-1 from the output line, and the output line is connected to the OR function matrix circuit 74-1.
-2 is input. On the other hand, 3 of the cycle number register 34-3 is incremented every cycle of the waveform shown in FIG. 7A.
Since the bit (Rl6JNr32, 1L wait) output is also supplied to this duty control circuit 74, the output state of FIG. or gate 7
From 4-4, an AND gate 74-5, an inhibit gate 74-6, and the inverted AND gate 74-
Depending on the condition of 3. [hill]? +16·32·i], the output state shown in FIG. 18c is obtained. And the 18th
The signal [16] of the cycle number register 34-3 shown in FIG. and 74-10, and the output of OR gate 74-4 is supplied to AND gates 74-11 and 74-10.
4-12 (This must be supplied. Here, the basic relationship between the duty and the cycle counting state is as shown in Figure 19. In other words, the waveform shown by RO is RlJ indicates a cycle with no output, and RlJ indicates a cycle with waveform output.Duty r1, Rll2
J. ．． RL4J takes out a waveform output every ゜"1゛ cycle, ゜"2゛cycle, and ゜"4゛cycle every time. For duty Rll3, cycle counting is performed for ``4'' and 4'5. In other words, ROJ to R7J specified by the combination of 3 bits of the cycle mode designation switches S, O, Sll, and Sl. When specifying R6J and R7.! among the modes associated with the numbers, the output K1 output signal is generated from the OR function matrix circuit 74-2, and the weight R64J of the adder 36 is output.
The output signal is supplied to the AND gate 74-13 along with the output signal of , and the output signal is supplied to the weight R32J of the cycle number register 34-3 via the OR gate 74-14 to skip the cycle states of "4゛,゜"5゛. It is. Further, the K2 output of the OR function matrix circuit 74-2 is sent to the OR gate 74-15, the K3 output is sent to the OR gate 74-16,
The K4 output goes to the OR gate 74-15 via the inhibit gate 74-7, and the current output goes to the inhibit gate 74-15.
8 to OR gate 74-]6, K6 output goes to OR gate 74-17 via AND gate 74-9, K7
The output is sent to the OR gate 74 via the AND gate 74-10.
-18, K8 output goes through AND gate 74-11 to OR gate 74-19, K9 output goes to AND gate 74-19.
-12 to the OR gate 74-20, and the OR gates 74-15, 74-17, and 74-19 are connected in series to output the output X1 (α), and the OR gates 74-16,
74-18, 74-, and 20 are connected in series to output X2 (
There is a way to extract β). Therefore, the output X1(α),
The output signal generated at 2(β) is the number RO! designated by αβ period mode. - Corresponding to R7J, it becomes as shown in FIG. That is, the period M is extracted from the output X1 (α) based on the waveform specified by the α instruction, and the period N based on the waveform specified by the β instruction is extracted from the output X2 (β). Therefore, in the periodic mode ROJ-R5J, the periods M and N are both integers, but in the periodic modes R6J and R7, if one of the periods M and N is an integer, the other is periodically controlled in a non-integer relationship. Become. Further, the outputs X1 (α) and X2 (β) are supplied to an inhibit gate 75 and an AND gate 76, respectively, and normally the exclusive OR gate 71 outputs an α instruction signal ゜“0” in synchronization with the α/β instruction signal. The inhibit gate 75 is activated when the β instruction signal “゛1” is activated, and the AND gate 7 is activated when the β instruction signal “゜1” is activated.
6 is opened, and their outputs are further outputted from an OR gate 79 via inhibit gates 77 and 78, which will be described in detail later, and supplied to an AND gate 51 in FIG. 7c. Here, the switch R1 is connected to the exclusive OR gate 71, and when operated, the waveform program specifying section 35
The AND gate 76 is provided to invert the α/β instruction signal for each block address output from the AND gate 76.
is output in synchronization with the α instruction signal, and the inhibit gate 75 is output in synchronization with the β instruction signal, so that the output X1 has a duty of β and the output X2 has a duty of α.

The switch R2 is connected to inhibit gates 80 and 81 to which a P signal and its inverted signal F, which will be described later, are supplied, respectively, and is used to instruct whether to separate αβ or not.When operated, the inhibit gates 80 and 81 No output is obtained from the inhibit gates 77 and 78, therefore, X1 representing the duty of α and β according to the respective mode specifications is output from the inhibit gates 77 and 78.
(α), X2 (β) (However, when switch R1 is set, X1 (
β), X2(α)) signal is extracted. When the switch R2 is not operated, the inhibit gates 80 and 81 output the P signal and the F signal (however, as will be described later, they are generated only when a duet instruction is given), and the even number line memory of each register is α, and the odd number line memory is Line memory is now indicated by β, and this is shown in an easy-to-understand table in the second section.
Figure 1. In this case, the case where switch R2 and R3, which will be described next, are not designated is shown. Further, the non-separation instruction by the switch R2 is valid only when there is a duet. Switch R3 is connected to exclusive OR gate 70, and when this is operated, the α/β instruction signal designated for each block by waveform program designation section 35 is inverted.
That is, in the table shown in FIG. 21, the α/β relationships are all reversed. In this way, octave operation can be performed by specifying the cycle mode for each αβ, which is an effective function because the duty of the musical sound waveform can be changed and the timbre can also be made different for each octave.

Also, referring to the α/β non-separation operation in FIG. 21, mode specification 16. In the case of J, α:β has a period of 1:1.5, and β is a perfect fourth lower than α, and the mode specification is R.
In the case of 7, the period of β is twice that of α, but the waveform of β is considered to be a combination of 2B times the period of α and twice the period, and β is a perfect fifth higher than α. component and the component an octave lower. In FIG. 7D, switch T1 is a normal tremolo (called tremolo flat) instruction switch,
T2 is a touch tremolo instruction switch that applies tremolo only during operation, and when instructing touch tremolo, the tremolo flat instruction switch is left open.

Switches T3, T4, and T5 are switches that indicate the depth of the tremolo (referred to as the amplitude value), and they are set in order to the maximum r1 (10
0% depth), Rll2 (50% depth), Rll4
J (25% depth) can be specified. Since the designation signal of the switch T1 or T2 is supplied to the AND gates 83-1 to 83-3 via the OR gate 82, the output designation signal of the designated amplitude value is taken out and supplied to the tremolo control circuit 84. Therefore, and gate 83-1 to 83-3
is applied to AND gates 84-3 and 84-4 via OR gate 84-1 or 84-2. Furthermore, the output of the AND gate 83-2 is R of the envelope register 54.
AND gate 84-5 to which 64J weight outputs are combined
The signal is supplied to an OR gate 84-6 and an AND gate 84-7. Therefore, in the decay state and the release state, the weight Rl6J of the envelope register 54 is always ゜゛1゛. Furthermore, the output of the AND gate 84-8 that detects the release state is given to the AND gate 84-3, and the output is sent to the AND gate 84-3 via an inhibit gate 84-9 which can be opened except when designated by a mandolin, which will be described later. Taken as output signal from OR gate 84-10. Therefore, the inhibit gate 84-7 is not opened in the released state, and the inhibit gate 84-11 can be opened. On the other hand, in the tremolo instruction, the output of the weight 1 of the envelope register 54 is supplied to the AND gate 84-4, and its output is always applied to the weight R69 of the envelope register 54 via the OR gate 84-12.
Because the signal is supplied, the clear state of ROO is not achieved, but the state is reversed between the decay state and the release state. The output of the AND gate 83-3 is given the output of the weight R64J of the envelope register 54.
13 to OR gates 84-14, 84-15, and also to inhibit gate 84-16. This inhibit gate 84-16 is not opened in the released state like the inhibit gate 84-7, and in this state, the inhibit gates 84-17 and 84 are not opened.
-8 can be opened. In addition, the output of the weight R32J of the envelope register 54 is output from an AND gate 84--which is valid only when the tremolo-picking instruction switch T6, which will be described later, is activated.
19 is further applied to an inhibit gate 84-21 via an inhibit gate 84-20 to which the signal is coupled.
That is, since the gate output prohibition signal from the AND gate 84-4 is applied to the inhibit gate 84-21, it is not opened in response to a tremolo instruction and always outputs "0.0".
Therefore, the envelope state detection circuit 73 can take out only the decay state output signal of the inhibit gate 73-3. That is, in the tremolo instruction switches Tl and T2, the envelope coefficient value of the envelope register 54 is changed to the value shown in FIG. from the second
An example is shown in Figure 4. Note that tremolo is not applied to volume curve types 1, 4, and 5 in FIG. 13. T6 is a tremolo repelling instruction switch, and when this is operated, the output signal of the inhibit gate 84-22, which is applied under the conditions that the AND gate 84-19 is in the released state and the envelope register 54 is R16 or more, passes through. I come to do it. Further, when the cleared state of ROO of the envelope register 54 is detected by the inverted AND gate 73-1 of the state detection circuit 73, the signal is sent to the AND gate 72-15 via the inhibit gate 73-5 and the OR gate 73-6. It is output as a release instruction signal. Therefore, the first half of the release state is operated by the decay clock signal, which will be described later, and as a result, as shown in FIG. 25A,
As shown in B (however, with a specified tremolo depth of 1 ha)
This creates a plucked string-like tremolo that corresponds to the volume curve format, making it an effective function. The touch tremolo instruction switch T2 is effective when the flat tremolo instruction switch T1 is turned off in advance, and produces a tremolo effect only during operation.

Depending on the output states of the R32J and r64J wait stages of the envelope register 54, the inhibit gate 35 outputs the attack state detection signal 5, the inhibit gate 86 outputs the decay state detection signal 4, and the series circuit of the AND gate 87 and the inhibit gate 88 outputs the attack state detection signal 5. Release detection signal 1
The high release detection signal e is output from the above-mentioned inverted AND gate 66-6, and the AND gate 89
A slow release detection signal 9 is extracted by a series circuit of and 90.

Further, 91 is a synchronous set register for high release designation, which has eight 1-bit line memories and a shift pulse φ. to perform a shift operation. Thus, high release 6 means a relatively fast attenuation to prevent click sounds when a performance key is turned off (sometimes when a steady sound such as an organ sound is specified). When a 5-set signal to be described later is outputted for this purpose, that signal is passed through an OR gate 92 to an inhibit gate 93 and a seventh
The signal is input to the high release synchronization set register 91 via the inhibit gate 94 which is opened by the inverted signal of the AND gate 62 in FIG. The output signal of inhibit gate 93 is the output signal RO. of AND gate 62. The above-mentioned envelope clock is synchronized via an AND gate 95, an inhibit gate 96 whose gate is opened in a state other than ROOJ in the envelope state, an OR gate 64, and an OR gate 65 in synchronization with the addition timing when the J block address signal is generated. The cassette is set in the set register 53 to perform a high release operation. The above describes the core configuration of this system.

Next, we will discuss the timing relationships for controlling the circuit configurations in Figures 7A, B, C, and D, various clock signals for envelope control, ensemble control signals, performance key groups, key input control, etc., and the connection state shown in Figure 26. This will be explained using the circuit configuration diagrams shown in FIGS. 27A and 27B. Basic clock signal φ output from original clock generator 100.

(for example, 272,510 Hz) is supplied to a line counter 101 that performs counting corresponding to one cycle of the eight line memories forming the registers 20, 21, 34, 53, and 54 of FIG. 7A and D. This line counter 101 is 3
It performs an octal binary counting operation using bits, and the output of each bit stage (see FIG. 28a) is supplied to a control timing generation circuit 102. The control timing generation circuits 1 and 02 are supplied with respective instruction signals from the ensemble instruction switch W at the contact positions of W1 (non-accompanied instruction), W2 (double instruction), and W3 (quartet instruction), Therefore output 5
The output signal shown in FIG.
-4 to output 5 through r1 signal and OR gate 102
The 11J signal is output to output 6 via -5 and 102-6. Also, in the duet instruction, and gate 102-7,
The output signal shown in FIG.
-5 and 102-6, the output signal shown in FIG. 28C is obtained at output 6. And gate 10 in quartet instructions
The output signal shown in FIG. As a result, the output signal shown in FIG. 28D is generated.

The octet instruction signal, the duet instruction signal from the contact point W of the ensemble instruction switch W, and the output of each bit stage of the line counter 101 are supplied to the ensemble timing signal generation circuit 103. Thus, the OR gate 103-1 outputs a septet instruction signal or an octet instruction signal, and the OR gate 103-2 outputs a duet presence signal (which is output for any instruction of 2, 4, or octet). be done. Since the overlap presence signal of the OR gate 103-2 is supplied to the AND gate 103-3 and the inhibit gate 103-4, the line counter 101
The output signal of the weight RlJ is outputted from each gate as a P signal and an F signal as shown in FIG. 28e, and applied to the inhibit gates 80 and 81 in FIG. 7C. In addition, since the overlap presence signal output from the ORG 103-2 is supplied to the AND gate 103-5, the weight RlJ of the line counter 101 is determined from the output of the AND gate 103-5.
The output signal of
+1 is output as a command signal. Also, or gate 1
Since the output of 03-1 is supplied to AND gate 103-6, the output signal from weight R2J of line counter 101 is output, and is supplied to OR gate 103-8 via OR gate 103-7. Further, the duet instruction signal is supplied to the inhibit gate 103-9, and the inverted signal of the line counter 101 is extracted from the output thereof and applied to the OR gate 103-8 via the OR gate 107. Furthermore, the overlap presence signal output from OR gate 103-2 is applied to OR gate 103-8 as an inverted output signal via OR gate 103-10. Further, the operation signal of the vibrato designation switch B is applied to this OR gate 103-10. That is, the output of the OR gate 103-8 is outputted via the OR gate 105 as the output signal shown in FIG. 28B(7)G, i in response to a duet or quartet instruction. Also, the octet instruction signal is the AND gate 103-
11, the weight R of the line counter 101
The output signal of 4 is outputted from this AND gate 103-11, and is outputted through the OR gate 106 as shown in FIG. 28B(7)k.
The signal is output as shown in . Therefore, Figure 28B (7
) The timing signals shown in F and g are output from OR gates 104 and 105, respectively, when a duet is specified, and are shown in FIG. 28B.
(7) The timing signals shown in H and l are output from the OR gates 104 and 105, respectively, when a quartet is specified, and the timing signals shown in FIG.
When specifying a duet, the AND gates 97-1 to 97- are output from the OR gates 104 to 106, respectively, and are shown in FIG. 7A.
3 is applied to the RO program. It is supplied to the adder 40 as an additional addend value in synchronization with the address signal. That is, the additional addend value in the overlap instruction is used to add a slight difference in frequency to each line memory. Output from the control timing generation circuit 102. The timing signals of the outputs 5, ◎, and 6 are supplied to the input control circuit 107, and the timing signals from the output 5 are also supplied to the octave counter 108 in FIG. 27B.

That is, this octave counter 108 is a 3-bit octal binary counter that is advanced by a number of steps every 8 line times of 8φo, and the lower 2 bits (weight Rl
J, l2J) becomes the octave input chord in FIG. 7A as a four-octave chord state (see a in FIG. 29A). The 3-bit output from each stage of the octave counter 108 is supplied to a synchronizing signal generating circuit 109 and also to a decoder 110. Therefore, this 3-bit all R
Oyo counting state is inverted and gate 109-1
, and the timing signal shown in FIG. 29A(7)b is extracted as the detection output 4 and applied to the scale counter 110 as a counting step signal. This scale counter 111 is the lower 2
The bits function as a ternary binary counter, and the carry operates the binary counter of the upper bit (see FIG. 29A(7)c). Incidentally, in reality, the scale counter is composed of 4 bits in combination with the most significant bit of the counter 108, and therefore, this 4-bit output becomes the scale input code shown in FIG. 7A. This counter 111 is supplied to the synchronization signal generation circuit 109 and also to the decoder 112. Decoder 110
Different timing signals as shown in d of FIG. 29B are outputted from the 8 outputs 1 to 8 of
is applied to eight vertical lines. This performance key group 113
48 performance keys are arranged in a matrix, and six output lines are supplied to AND gates 114-1 to 114-6 of the key operation timing detection circuit 114, respectively. Six different timing signals (see FIG. 29B(:I)e) generated from outputs 3 to [F] of the decoder 112 are sequentially coupled to the AND gates 114-1 to 114-6, respectively. Therefore, and gate 114
-1 to 114-6 outputs are OR gates 114-7 to 11
The key input timing signal corresponding to the operated one of the 48 performance keys is extracted from the output by the serial circuit 4-11, and is sent to the key input F/F of the input control circuit 107.
It is input to lO7-1. The timing signal output from the synchronization signal generation circuit 109 is detected according to the counting state of the counters 108 and 111, and the timing signal shown in FIG. 29B(7)f is output from the output 6 to the inhibit gate 109- 3 to 109-5, and from the output 1, a timing signal shown in FIG. 7,109-8
Detected using

Further, from output 4, a timing signal shown in FIG. 29B(7)h is sent to AND gate 109-9 and inhibit gate 1.
09-10 and 109-11, the output signal of S4 of the counter 111 is output from output 5, and the timing signal shown in FIG. From the output 1, the timing signals shown in FIG. 29B(7)j are detected using the AND gate 109-13 and the inhibit gate 109-14 and outputted, respectively. The shift register 115-1 of the various clock time generation circuits 115 operates dynamically with 24 bits, and is shifted by the clock signal every 8 line times from the output 5 of the control timing generation circuit 102.

Therefore, one cycle of the shift register 115-1 is synchronized with two systems, the octal of the counter 108 and the ternary of the counter 111. This shift register 115-1 has independent counting sections of a first counting section, a second counting section, and a third counting section in 8-bit units, and the first counting section and the second counting section are used for vibrato and envelope. It is used to generate a time clock signal, and the third counting section is used to count a predetermined period of time when a new key is present, which will be described later. Basically, the first counting section is an 8-bit binary counter that operates on the timing signal from output 1 of the synchronization signal generation circuit 109 (see FIG. 29B), and the second counting section operates on the timing signal from output 5. It is an 8-bit binary counter whose lower two bits operate as a ternary counter, and the third counting section is an 8-bit binary counter which operates with a timing signal from the output 6. Therefore, the output d of this shift register 115-1
The output signal from 1 is passed through an OR gate to adder 115-
3, and its output is further supplied to shift register 115-
1 input side. Also, adder 11
The carry signal from 5-3 is applied to inhibit gate 115-4 via carry F/F1O 7-2. This inhibit gate 115-4 is configured to inhibit the output 1 of the synchronization signal generation circuit 109 from being output when a timing signal is generated, and its output is output to the OR gate 115-5.
is applied to adder 115-3 via. Further, the timing signal of the output 1 is input to the inhibit gate 115-6.
It is also input to OR gate 115-5 via. The output ↓ of the shift register 115-1 is sent to the inverted AND gate 115-7 and the inhibit gate 115-8, the output peak is sent to the inhibit gates 115-9 and the AND gate 115-10, and the output D4 is sent to the inhibit gate 115.
-11 and AND gate 115-12, the output is output to inhibit gate 115-13 and AND gate 115-12.
At 14, the output peak is applied to the inhibit gate 115-15 and the AND gate 115-16, and the output D7 is applied to the AND gate 115-17. Also, invert gate 115-7, inhibit gate 115-9,
115-11, 115-13, and 115-15 are provided with AND gates 115-10, 115-12, and 115-10 in the previous stage, respectively.
15-14, 115 - 16, 115-17 are applied,
The output of each AND gate is a one-shot clock (8φ
time width of o). Further, the output d1 is applied to the inhibit gate 115-8,
Its output is provided to AND gate 115-18. The timing signal of output 1 of the synchronizing signal generating circuit 109 is applied to this AND gate 115-18, and is applied to the adder 115-3 via the OR gate 115-2.
That is, it controls the ternary count of the lower two bits of the second counting section. The output d1 of the shift register 115-1 is sent to the AND gate 115-19.
4 is applied to an AND gate 115-20, and these outputs are applied to a flip-flop 115-21 (no delay) for determining a time for preventing chattering in synchronization with the timing signal of output 4 of the synchronization signal generating circuit 109. are supplied as reset and set signals, respectively. Well, 1
16 is a vibrato clock selection circuit, in which the time clock signal from AND gate 115-10 is coupled to AND gate 116-1, the time clock signal from AND gate 115-12 is coupled to AND gate 116-2, and the time clock signal from AND gate 115-12 is coupled to AND gate 116-2. The outputs of AND gates 116-1 and 116-2 are coupled to AND gate 116-M inhibit gate 116-5 via OR gate 116-3.

Furthermore, the output of the inhibit gate 116-5 is applied to an AND gate 116-6 to which the timing signal of output 1 of the synchronization signal generation circuit 109 is applied.
The output of 4 is supplied to an AND gate 116-7 to which the timing signal of output 4 is applied, and the outputs of these AND gates 116-6 and 116-7 are fed to an OR gate 116-8.
The vibrato clock signal φB is output via the vibrato clock signal φB. That is, this vibrato clock signal φB becomes a different time clock signal depending on the selection designation of the vibrato clock selection switches SA and SB. As can be seen from FIG. 30, the SA switch specifies whether to take out the time clock signal determined by the first counting section of the shift register 115-1 or the time clock signal determined by the second counting section. The vibrato clock signal φB is applied as a counting step signal to the octal binary counter 117 in FIG. 27A. This counter 117 generates the signal shown in FIG. 31a from each output stage and is applied to the vibrato control circuit 118. Due to this counting state, the timing signal shown in FIG. 31b is detected at the output e1 by the inhibit gate 118-1 and the AND gate 118-2, and the
The timing signal shown in FIG.
-3, the timing signal shown in FIG. 31d is detected by AND gate 118-4, and the timing signal shown in FIG.
The timing signal shown in FIG. 31e is detected by the inverted AND gate 118-7 and the AND gate 118-8, and the timing signal shown in FIG. 31f is detected at the output E5 by the inhibit gate 118-9. Furthermore, the timing signal shown in FIG. 31g is detected at the output E6 by the inhibit gate 118-10. In the end, the output E7 becomes the timing signal shown in FIG. 31h, and the OR gate 118-
10, 118-11, and the timing signal shown in FIG.
OR gate 118-13, 1 that takes the logical sum of e2 and e5
18-14 in series circuit.
Therefore, the timing signals of outputs E7, e8, and e4 are output from the AND gate 11 when the vibrato designation switch B is operated.
8-15 to 118-17 and OR gates 104 to 105 to AND gates 97-1 to 97-3 to which the ROJ block signal in FIG. 7A is supplied. That is, when vibrato is specified, ΔPl and ΔP4 are output according to the count value of the counter 117. 119 is an envelope clock select circuit for selecting the envelope clock applied to the inhibit gate 63 in FIG. 7D.

RA and RB are switches for selecting the time clock signal in the release state, DA and DB are switches for selecting the time clock signal in the decay state, RO is a switch for selecting the slow release clock signal, and 0A is the switch for selecting the time clock signal in the decay state. (Steady sound) Envelope specification switch.
The time clock signal output from the AND gate 115-12 is sent to the AND gates 119-1 to 119-3.
The time clock signal output from AND gate 115-14 is sent to AND gates 119-4 to 119-6, and the time clock signal output from AND gate 115-16 is sent to AND gates 119-7 to 119-9. The time clock signal output from AND gate 115-17 is applied to AND gates 119-10 and 119-11. Furthermore, AND gate 11 no 9-1, 119-4, 1
The selection contact output of the RB switch is applied to each of 19-7 and 119-10, and the outputs of these AND gates are supplied to a series circuit of OR gates 119-12 to 119-14, which take an OR, and the output is applied to the AND gate 119. -15, coupled to inhibit gate 119-16. The timing signal of the output f of the synchronization signal generation circuit 109 is applied to AND gates 119-17 to 119-19, and the timing signal of output g is applied to AND gates 119-20 to 119-22. The AND gate 119-15 and the inhibit gate 119-16 are each connected to the AND gate 119-2.
0,119-17 and its output is OR gate 1
The release state detection signal of FIG. 7D is applied via AND gates 119-24 through 19-23, and is output as a release clock signal φR. As can be seen from Fig. 30, the RA switch is connected to the shift register 115-1.
This designates whether to extract the time clock signal determined by the first counting section or the time clock signal determined by the second counting section. ANDGATE 119-2
, 119-5, 119-8 are applied with the selection contact output of the DB switch, and the outputs of these AND gates are supplied to a series circuit of OR gates 119-25, 119-26, which take an OR. 119-27,
are supplied to each of the inhibit gates 119-28.
Further, the outputs of the AND gate 119-27 and the inhibit gate 119-28 are connected to the AND gate 119-2, respectively.
1,119-18 is supplied to an AND gate 119-30 via an OR gate 119-29, and outputs a decay clock signal when the decay state detection signal shown in FIG. 7D is received. Next, AND gate 119-6, 119-9
, 119-11 are applied with the selection contact output of switch Rc, and the outputs of these AND gates are supplied to a series circuit of OR gates 119-31 and 119-32, which take an OR, and the output is supplied from FIG. 7D. AND gate 119-33,1 when a slow release state detection signal is generated.
Slow release clock signal φSr via 19-19
Take out. ANDGATE 119-3 is ORGATE 11
It is output when the high release state detection signal or attack state detection signal supplied from FIG.
Output as 9. Therefore, and gate 119-2
Release clock signal φ output from 4. , Decay clock signal φD1 output from AND gate 119-30 Slow release clock signal φSrl output from AND gate 119-19
Each time clock signal of the high release clock signal φHr outputted from the OR gate group 119-34
, 119-35, 119-36 are supplied as an envelope clock signal to the inhibit gate 63 in FIG. 7D. Reference numeral 120 designates an addition value specifying circuit which is supplied to the envelope adder 55 in FIG. By controlling 0+, r-, it is possible to rapidly control the rise and fall times of the envelope as time passes.

That is, the Aa switch is a 5-contact selection switch, and each contact output is 1+1jr+ through AND gates 120-1 to 120-5 to which attack state detection signals are applied.
The addition value command signals of 2JJ+4jr+8 and 1+32J are outputted via OR gates 120-6 to 120-10. The Da switch is a 5-contact selection switch, and each contact output is connected to AND gates 120-11 to 120-15 and OR gates 120-6 to which a decay state detection signal is applied.
120-10, 1+1jr+2, r+4, r+8, and r+32j are output as additional value command signals, respectively. Further, when a release state detection signal is generated, a 1+ addition command signal is sent through the OR gate 120-16, and when a slow release state detection signal is generated, an OR gate 120-1
1+1J addition value command signal is sent via OR gate 120-18 when a high release state detection signal is generated. A J addition value command signal is obtained, and this addition value is sent to the adder 55 in FIG.
67-5. In the end, andgate 11
5-10, 115-12, 115-14, 115-16
, 115-17, the different time clock signals in the first counting section and the second counting section are outputted from the vibrato clock selection circuit 116 and the envelope clock selection circuit 119 according to their respective instructions, as shown in FIG. The location indicated by the O mark is selected, and the addition value for the envelope adder 55 can be selected in synchronization with the selected time clock signal. FIGS. 32, 33, and 34 show examples of changes over time in envelope coefficient values in attack, decay, and release states, respectively.

Next, the timing signal (time width of 8φo) corresponding to the operated performance key outputted from the key operation timing detection circuit 114 described above is the key input synchronization F/FlO7-
1, and its output is applied to AND gate 107-3.

This AND gate 107-3 is output in synchronization with the set output of the flip-flop 115-21 for preventing chattering, and is supplied to the inhibit gate 107-4 to generate a key-on signal. That is, the inhibit gate 107-4 will be described in detail later, but the number of performance keys (
In this case, when the output of the 48-bit shift register 107-5 corresponding to the 48-bit shift register 107-5 is '40', a key-on signal is obtained by the first new key operation and is supplied to the AND gate 107-6. This AND gate 107-6 responds to the reset signal (indicating the cleared empty line memory in the envelope register 54) output from the inhibit gate 68 shown in FIG. 7A to update the empty line memory. The above-mentioned input instruction signal is generated to set the pitch input data of the key and the attack state of the envelope. Moreover, it becomes an input instruction signal that specifies a plurality of line memories according to the overlap instruction state. That is, the reset signal output from inhibit gate 68 in FIG. 7A is supplied to AND gate 107-7 and inhibit gate 107-8 of input control circuit 107. and gate 10
The output of 7-7 is held via an OR gate 107-9 and an inhibit gate 107-10, and is coupled as an input to an inhibit gate 107-11 whose output is prohibited by the inhibit gates 107-8. . Further, the AND gate 107-7 and the inhibit gate 107-8 receive the output 6 from the control timing generation circuit 102, that is, 2
The signals shown in Figure 28 A (7) C and d for ensemble designation and quartet designation, the constant RlJ signal for designation without duet designation, and the signal shown in Figure 28 A (7) b for octet designation are the gates. It is applied as a signal. Further, the signal shown in FIG. 28 AOb is transmitted from output 5 to inhibit gate 107-12 to inhibit the output of inhibit gate 107-10 and release the hold. Therefore, the inhibit gate 107-
11 generates a signal synchronized with the signal of output 6 corresponding to each ensemble instruction, and is outputted from AND gate 107-6 when a key-on signal is generated. Therefore, the output signal of the AND gate 107-6 is input to the inhibit gate 107.
-13 and AND gate 107-14. AND gate 107-14 is control timing generation circuit 10
It is output in synchronization with the signal of output 5 of 2, and the OR gate 10
7-15 to a flip-flop 107-16 that provides a 1-bit delay (delay time of 1φo), and its output is supplied again to the OR gate 107-15 via an inhibit gate 107-17, allowing circulation. ing.
That is, the inhibit gate 107-17 receives the output signal from the output of the control timing generation circuit 102 (FIG. 28A).
7) It is held until the gate output is prohibited in (see b).
Therefore, the output signal from inhibit gate 107-13 is generated from the time when the output of AND gate 107-6 is generated until the gate is inhibited by the output of inhibit gate 107-17. Therefore, during the 8φo time width of the key-on signal, the inhibit gate 107-13 outputs 1φo time width (in the case of no ensemble instruction), 2φo time width (in the case of duet instruction),
4φo time width (in case of quartet instruction), 8φ. An input instruction signal with a time width (in the case of an octet instruction) is generated. In this case, in the duet instruction, line memory! and Ll
, L2 and L3, L4 and L5, L6 and L7, and L in the quartet instruction. Above 3, two combinations of L4 to L7, L in octet instruction. The same pitch input code is input to the plural line memories of the scale code register 20 and octave code register 21 of FIG. 7A, and the plural lines of the envelope register 54 of FIG. The memory is placed in an attack state, and each register is activated by a plurality of line memories. Thus, the output of the AND gate 107-16 is output from the 1-bit delayed flip-flop 107-16.
The signal is applied to the AND gate 107-20 through the OR gates 107-18, and through the OR gate 107-19 to which the output signal of the shift register 107-5 is input. The OR gates 107-18 are taken out in synchronization with the input instruction signal, and the output signal is sent from the AND gate 107-20 to the shift register 107 by a timing signal corresponding to the pressed key output from the OR gates 107-21. -5 as a write signal. When the RlJ signal is written to the shift register 107-5, the shift register 107-5 is sequentially shifted in synchronization with the timing signal from the output 5 of the control timing generating circuit 02 (see b in Fig. 28A), and the shift register 107-5 continues to cycle while the performance key is pressed. It is canceled when the held performance key is released. ANDGATE 107-20
The output of is supplied to the inhibit gate 107-22 as a gate inhibit signal. On the other hand, a key-on signal output from inhibit gate 107-4 when a performance key is pressed sets flip-flop 107-24 via OR gate 107-23, and the set output is output from inhibit gate 107-25. It is maintained in circulation through the .

This cyclical holding is carried out by an AND gate 107-26 which takes the AND of the timing of the output 6 of the synchronizing signal generating circuit 109 (see FIG. 29f) and the output of the carry flip-flop (F/F) 107-2. It is released in synchronization with the generation of output. That is, the set output of the flip-flop 107-24 is applied to the inhibit gate 115-22 in the various clock time generation circuits 115, and causes the third snare number section of the shift register 115-1 to start counting operation. Since the holding time can be determined by the third counting section of the lever, this system uses approximately 4 seconds after pressing the performance key.
It is set to be 5rns. The set output signal of the flip-flop 107-24 is sent to the OR gate 1 of the switch 0A for specifying the organ sound volume.
07-27 through the inhibit gate 107-2.
2 and its output is supplied to AND gate 107-28. A coincidence detection signal from the coincidence circuit 121 is further applied to the AND gate 107-28, and a high release set (Hr
SET) signal is taken out from the high release synchronization set register 9 through the OR gate 92 in FIG. 7D.
It is set to 1. The matching circuit 121 is 019029S19S29S49S8 of the counter 1089111.
Pitch input codes output from each stage and the scale code register 20 and octave code register 21 in FIG. 7A.
It is checked to see if it matches the pitch output code output from the . That is, when the switch 0A is set to OFF, the pitch code has already been input to the line memories of the scale code register 20 and the octave code register 21 during the holding time of the flip-flop 107-24 (approximately 45rT1S), and The one whose performance key is released is AND gate 1
A high release set signal is output from 07-28 and placed in a high release state. As mentioned above, the high release state is a state in which the sound rapidly disappears when the performance key is released. In addition, when the switch 09 is set to ON, when the performance key is released (AND gate 107-2
The line memory of the same pitch output code as the released performance key is set to the high release state (no output of 0). As a result, it is possible to realize an OFF state of the performance keys without a click sound. As described above, according to the configuration of the present invention, it is possible to simultaneously instruct and synthesize multiple waveforms, and between each waveform there are differences in the volume rise,
Since the falling edges can be varied, it is possible to obtain musical tones with extremely varied and effective tones.

Of course, in the above embodiment, the volume curve format can be specified as two different types, α and β, but this is not limited to two types, and it is also possible to combine two or more waveforms. be. Note that the waveform program designation section 35 for each block in FIG. 7A described above is designated by a switch as shown in FIG. The information may be stored in a fixed storage device.

Also, store the necessary instructions on a magnetic card,
Various methods are conceivable, such as reading it out at the time of use and storing it in a buffer in a memory such as a flop-flop. Further, the number of blocks in one period of the musical sound waveform is not limited to 16, and the differential coefficient value for each block is also 1, and the design is not limited to R2J and r4J, and can be arbitrarily changed. Furthermore, a filter circuit can be provided after the D/A conversion circuit, and in that case, for example, multiple types of digital filters may be prepared and selected arbitrarily using a switch. It is possible to obtain sound effects with different resonance characteristics and reverberation characteristics of a held musical instrument, or transmission characteristics of a wind instrument. It goes without saying that various other circuit configurations may be used without departing from the gist of the present invention. As detailed above, according to the present invention, there is provided a waveform change value generating means for generating a change value between adjacent addresses of a musical sound waveform at a speed corresponding to the frequency of the musical tone to be generated, and controlling the envelope of the musical tone. an envelope means for generating at least two different envelope data; and each address obtained by dividing one period of the musical sound waveform into a plurality of groups is divided into at least two groups, and the envelope data generated from the envelope means for each group is One of the at least two different envelope data is associated with the timbre of the musical tone to be generated, and the envelope between each address is controlled based on the change value generated by the waveform change value generating means. An apparatus comprising an output means for outputting a change value, and a waveform amplitude value generation means for accumulating the envelope-controlled change values obtained from the output means to generate an amplitude value at the address. Therefore, with a simple configuration, it is possible to obtain a musical sound waveform with an envelope whose timbre changes over time.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle configuration based on the basic concept of this system, Fig. 2 is a diagram of the envelope mode used in Fig. 1, Fig. 3 is a basic explanatory diagram of the musical sound waveform generator in Fig. 1,
Figures 4A, B, and C are diagrams showing relative changes in musical sound waveforms according to envelope coefficient values, and Figures 5A, B, C, D, E, and F.
6 is a diagram explaining the logical symbols used in this embodiment, FIG. 6 is a diagram showing the connection state of FIGS.
Figures A, B, C, and D are specific circuit configuration diagrams of the heart of this system, and Figure 8 is a time diagram showing selected output states according to scales related to the block address states in Figures 7 A and B. 9 is a time chart showing the addition timing output for each octave related to the synchronization register in FIG. 7A, FIG. 10 is a diagram explaining the number of scale steps in FIGS. 7A and B, and 11th Figures A, B, and C are time charts explaining the waveform period for each scale in this system, Figure 12 is a detailed diagram of the shift memory in Figure 7C, and Figure 13 is the volume level used in this system. Figure 14 is a diagram showing the types of curve formats, Figure 14 is a diagram explaining the combination of volume curve formats for α and β in this system, and Figure 15 is block addresses for α and β of tone waveforms in this system. 16 is a detailed diagram of the waveform program designation section in FIG. 7A, FIG. 17 is a diagram explaining the output addition value in FIG. 7C, and FIG. 18 is a diagram explaining the output addition value in FIG. Figure A is the time chart of the cycle number counter, Figure 19 is a diagram explaining the basic relationship between the number of cycles and duty used to explain Figure 7B, and Figure 20 is the cycle mode designation for each αβ in this system. FIG. 21 is a detailed diagram related to the αβ period mode in this system. FIGS. 22, 23, and 24 are waveform diagrams explaining tremolo control used in this system. Figures 25A and 25B are waveform diagrams explaining the plucked sound tremolo control used in this system, Figure 26 is a diagram explaining the connection state of Figures 27A and B, and Figure 27A.
, Bl is a specific circuit diagram of the control unit that controls A, B, C, and D in FIG. 7, FIG. 28 A, B is a time chart related to the ensemble in FIG. is the 27th
Figure B is a time chart related to key input timing and synchronization signals, Figure 30 is a diagram explaining the selection state of time clocks based on various clock time generation circuits, and Figure 31 is a diagram of vibrato control in this system. Time chart, Figure 32 is a diagram explaining the rising states of various volume levels as the time changes during attack, Figure 33 is a diagram explaining various volume change states as the time changes during decay, and Figure 34 is a diagram explaining the various volume change states as the time changes during the decay stage. FIG. 3 is a diagram illustrating a change in volume due to a change in time. 1... Pitch input code register, 2...
・Clock control circuit, 3... waveform period counting circuit, 5... waveform program specification section for each block,
6... Multiplier circuit, 7... Volume curve forming counter, 8... Adder, 9... Accumulator, 1
1...Speaker, S1-S6...No...α,
β volume curve format indication switch, 72.α, β volume curve format control circuit, 73...Envelope state detection circuit.

Claims (1)

[Claims] 1. A waveform change value generating means for generating a change value between adjacent addresses of a musical sound waveform at a speed corresponding to the frequency of the musical sound to be generated, and generating at least two different envelope data for controlling the envelope of the musical sound. an envelope means, each address obtained by dividing one period of the musical sound waveform into a plurality of groups into at least two groups, and one of the at least two different envelope data generated from the envelope means for each group; an output means for associating envelope data according to the timbre of the musical tone to be generated and outputting an envelope-controlled change value between each address based on the change value generated by the waveform change value generating means; A musical sound waveform generation device for an electronic musical instrument, comprising waveform change value generation means for accumulating the envelope-controlled change values obtained from the means to generate an amplitude value at the address.