JPS6044671B2 - Musical sound waveform generator for electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a musical sound waveform generator for an electronic musical instrument that digitally generates and outputs musical sound waveforms.

In conventional digital electronic musical instruments, for example, one period of a waveform is divided into a plurality of steps, and this waveform information is sequentially read out using a clock according to the musical scale frequency. Therefore, the above-mentioned waveforms are repeatedly output in each cycle, and each waveform has a duty of 1 and changes like a sine wave. Such a sine wave musical tone does not contain many harmonic components, and as the range gets lower, the output characteristics of the speaker worsen (the output level of low frequency components decreases), and the output level of the musical tone decreases. As I progressed, I discovered some shortcomings. Further, in conventional electronic musical instruments, when outputting musical tones in an octave relationship, it is necessary to variably control the waveform readout clock, which has the disadvantage of requiring a complicated circuit configuration.

This invention was made in view of the above points, and it is possible to vary the pitch cycle (period) of a musical tone by an octave with a simple configuration, and furthermore, the generation of a musical sound waveform during the pitch cycle of a musical tone can be reduced to one unit cycle. It is an object of the present invention to provide a musical sound waveform generating device for an electronic musical instrument that generates a limited sound waveform.

Hereinafter, one embodiment of the present invention will be described in detail, but prior to that, explanations of logic symbols used in the following drawings are shown in FIGS. 1A, B, C, D, and E. Inside, logical formulas, truth tables, and general logical symbols corresponding to each logical symbol are described, as well as examples of combinational circuits. What must be particularly noted here is that the inverter symbol attached to the input line of an OR gate and an AND gate is valid only for that gate.For details, please refer to the combinational circuit examples in each figure. Figure 2 is Figure 3A
, B, C, and D are shown in the combined state.

In Figure 3A, 20 is 4 bits ("1, p, "
2", "4j, "8" weight), and is composed of eight line memories that shift 4 bits in parallel in the direction of the arrow; 21 is a 2-bit (rl9 "2") It is an octave code register consisting of eight line memories that shift 2 bits in parallel in the direction of the arrow, and has an input/output terminal for weights. Start remembering. That is, in synchronization with the generation of input instruction signals related to the operation of performance keys, which will be described later, the corresponding scale input codes and octave input codes are AND gates 22 to 27 and OR gates 28-1 to 28-4.
, are input to the scale code register 20 and octave code register 21 via OR gates 29 and 30, respectively. The input scale code, octave chord (hereinafter referred to as pitch code), is a shift palace φ. (which is the basic clock of this system) is sequentially shifted in parallel in the direction of the arrow, and after a shift time of 8φo, from each output terminal via inhibit gates 31-1 to 31-4 and inhibit gates 32 and 33, respectively. This is to perform a so-called dynamic shift operation in which the signal is input in a circular manner.
Then, in synchronization with the new input instruction signal, the inhibit gates 31-1 to 31-4 and the inhibit gates 32,
33, the pitch codes in each register 20, 21 are controlled to be erased. In addition, the scale code register 20 and octave code register 21 are 8
Because it has a book line memory, for example, even if you operate up to 8 performance keys at the same time, the corresponding scale input chords and octave input chords will be input in sequence according to the timing order in synchronization with the input instruction signal. The dynamic shift cycle can be held.

In other words, eight sounds are controlled in a time-division manner. The scale codes and octave codes in this system are listed in Tables 1 and 2. One period (cycle) of the 1-7 blue i sound waveform is stored in the scale code register 20,
This is a period counting register that counts periods according to the pitch codes stored in circulation in the octave code register 21, and similarly to the scale code register 20 and octave code register 21 described above, shifts pulses φ in the direction of the arrow.

The memory is comprised of eight line memories which are sequentially and dynamically shifted according to the following. This period count register 3
4 is a block count register 34-1 which basically consists of a 4-bit multiplication that stores a count value corresponding to the address of each block in order to divide one cycle of a musical waveform into 116J blocks according to the time transition. The fourth pin 6 controls the number of steps for each block, which will be described later, in order to take out the addition timing signal that commands this block counting step.
It consists of a 3-bit octal cycle number register 34-3 which is counted and incremented every cycle of the block count register 34-1. The count contents of each line memory generated from each output of the block count register 34-1 and the cycle number register 34-3 are directly passed through the waveform program specifying section 35 for each block (to be described later), and are passed through the adder 36 in FIG. 3B.
In addition, there is an inhibit gate 37-1 which is a circulation gate.
.about.37-7, and the adder 86, which performs binary counting steps in this circulation cycle, is incremented by 1+L when the above-mentioned addition timing signal is generated. Also, 4 bits Cl. of the block count register 34-1. j. r2yo, R4, R8J
The wait) output (see FIG. 4a) is supplied to a block state detection circuit 38 for detecting a specific block address among the block addresses of Rl6J, and its output 9
The ROJ block address signal shown in FIG. 4b is taken out from outputs 1, 2, 3, and 4, and the output signals shown in FIG. 4c are taken out from outputs 1, 2, 3, and 4, respectively. Among them, outputs 1 to 4 are supplied to a scale step matrix circuit 39 which determines the number of step corrections for each scale, which will be described later. That is, the output 9 of the block state detection circuit 38 has weights r1, 12, 14 and 18 by connecting the inverted AND gate 38-1 and the inhibit gates 38-2 and 38-3 in series. Both are ゜゜0゛. Output 1 takes the output of weight RL as it is and outputs the pars block address signal under the conditions of (D, Σ, T-T). Output 2 outputs the weight r1 when it is "0" and Weight R2J is “
R2J. ．． l6, RlO, 114 block address signals, output 3 is wait R4
゜1゛ and weight R2J. , rlJ are both ``0゛1
In order to obtain the condition (4.].T), inhibit gates 38-5 and 38-6 are successively connected in series to obtain R4. 1
2 block address signal, output 4 is wait R8 is 4F, wait R4 is R2, and so on.

In order to satisfy the condition that 1 is '6013 (8.end.].〒), inhibit gates 38-7 to 38-9 are successively connected in series and R8 block address signals are outputted respectively.

On the other hand, synchronous count register (TC register) 34-2-4
The output of each stage of bits is input to the adder 40, and this adder 4
The output of each stage of 5 bits of 0 is subtractor (subtractor) 4
1, and the 4-bit output of the subtractor 41 is connected to inhibit gates 42-1 to 42-1, which are circulation control gates.
42-4, the signals are fed back to the input side of the corresponding bit stage.

Further, each stage output of the synchronous counting register 34-2 is an addition timing generation circuit 43 and an r
The 3-bit output of weights 1, 12 and R4 is supplied to a weight shaft circuit 44, which will be described later. Furthermore, this addition timing generation circuit 43 and weight shift circuit 44
An output signal of an octave code decoder 45 that generates first to fourth octave signals 01 to 04 according to the output state of the 2 bits output from the octave code register 21 is coupled to the octave code decoder 45 . That is, the inverted AND gate 45-1 of the octave code decoder 45 receives the first octave signal 01, the inhibit gate 45-2 receives the second octave signal 02, and the inhibit gate 45-3 receives the second octave signal 02.
and AND gate 45-4 output the third octave signal 03 and the AND gate 45-4 output the fourth octave signal 04 by detecting the chord states shown in Table 2 above, respectively. Octave signals 01 to 03 are supplied to AND gates 43-1, 43-2, and 43-3 of addition timing generation circuit 43, octave signal 02 is supplied to AND gate 44-1 of weight shift circuit 44, and octave signal 03 is supplied to AND gate 44-1 of weight shift circuit 44. Octave signal 0 to AND gates 44-2 and 44-3
4 is supplied to AND gates 44-4, 44-5 and 44-6. The AND gate 43-1 of the addition timing generation circuit 43 has 11, R2 .
, the output signal of R4J weight is OR gate 43-43
12, which is coupled via -5 and output from orcate 43-5. The output signal of the 4-way weight is coupled to an AND gate 43-2, and the output signal of the R8J weight is coupled to an AND gate 43-3.

In addition, the outputs of these AND gates are input to inhibit gates 43-6, 43-7, and inverted AND gate 43.
-8, respectively, and the output signal of the weight 78 is further coupled to the inverted AND gate 43-8. And these inverted and gate 43-
The output of 8 is sent to inhibit gate 43-7, and the output of inhibit gate 43-7 is sent to inhibit gate 43-7.
-6 and inhibit gate 43-6.
The above-mentioned addition timing signal is obtained from the output of . That is, as can be understood from FIG. 5, which shows the counting state (FIG. 5a) of the synchronous counting register 34-2 in one line memory, the addition timing generation circuit 43
FIG. 5b is output on output lines 5 and 56 respectively in
The output signals shown in FIG.
It is taken out as an output signal. In other words, the first
When the octave signal is 01, the second octave signal is 0 only when the synchronous counting register 34-2 is counting 0J. Teha ROJ
The third octave signal 03 is used only when counting ROJ-R3, and the fourth octave signal 04 is used only when counting ROJ-R3.
Then, only when counting ROJ-R7J, the addition timing generation circuit 43 outputs the addition timing signal. The addition timing signal obtained in this way is supplied to the adder 40 as a 1+8J addition command signal, and to the AND gates 46-1 to 46-4 as a gate opening signal, and is also supplied to the adder 36 in FIG. 3B for 1+L addition. It is also applied as a command signal. On the other hand, an octave signal 010 is output from the octave code decoder 45.

0304 passes through the addition timing generation circuit 43 and is sent to the subtractor 41 in FIG.
It is supplied as a command signal for 1-4 and J-8.

Therefore, in the cycle count register 34-2 → adder 40 → subtractor 41 → synchronous count register 34-2, the adder is basically applied to the count storage value output from the synchronous count register 34-2. 40, 1+8J is added in synchronization with the addition timing signal, and the addition result is a numerical value corresponding to octave signals 01 to 04 (0 for octave signal 01 and 1- for 1 octave signal 02).
2. j. 1-4 for octave signal 03, 0-8 for octave signal 04. ), the subtraction operation is performed. The adder 40 has AND gates 46-1 to 4 which are opened in synchronization with the generation of the addition timing signal.
6-4, a step correction number corresponding to the scale is supplied from the scale step matrix circuit 39 in accordance with the block count state of the block count register 34-1. That is, one cycle of the musical tone waveform consists of R16 block addresses as time progresses, and each block address corresponds to the basic clock φ. (8 times or more the period of the basic clock period).
This basic clock φ. One shot corresponds to one step of the musical sound waveform, and each block address ends up being more than eight steps. The highest note in this system is when each of the Rl6 block addresses in one cycle of the musical waveform is 8 steps, making a total of 128 steps (actually, in this system, the highest note (C+7) is 130 steps).
). Therefore, by increasing the number of steps between each scale from the highest note step number to one octave below so that the relationship is 121Σ, the period becomes longer and lower pitches are obtained according to the scale. . The number of step corrections corresponding to this scale is incorporated into a scale step matrix circuit 39, which will be described next. The output signals 1, 2, 3, and 4 of the aforementioned block state detection circuit 38 and the 4-bit output of the scale code register 20 are input to the scale step matrix circuit 39 of FIG. 3B. And this scale step matrix circuit 39
is provided with an AND function matrix circuit 39-1 that detects the chord status of each of the scales shown in Table 1, and outputs 12 output lines 1 to 2 (shown in the figure) corresponding to the scale. C scale detection line to C+ scale detection line) are taken out, and the first OR function matrix circuit 39-2
, and are coupled to AND gates 39-4 to 39-14 through a second OR function matrix circuit 39-3.
The first OR function matrix circuit 39-2 performs RO, 0, 1, 1, 2, 2, 3, 4, 5 in the order of C to C+ for each scale.
, 6, 7J step addends are output on lines X1, X2, X
It outputs a chord consisting of three chords, and its step addend is added to each of the 116 steps for each scale. That is, as shown in Table 3. Second
The OR function matrix circuit 39-3 is a circuit for giving a step correction 1 positive addend to each scale of one cycle of the musical sound waveform, and the step correction addend value is applied to multiple block addresses. The outputs 1 to 4 outputted from the block state detection circuit 38 are selected according to each scale in order to smooth and add them on average. The block address indicated by is selected.

The selection signal is the AND gate 39-4 according to the musical scale.
~39-14 will be supplied. Furthermore, the outputs of AND gates 39-4 to 39-14 are output to OR gate 39-1.
It is connected to the series circuit of 5 to 39-25, and from the output line
A 5+1 correction signal is output to a selected block address among the 5 blocks. That is, the step correction number output from the scale step matrix circuit 39 is (step addend+step correction addend). In addition, or gate 39
Since the "゜0゛" signal is supplied to one end of the -15, the output of the AND gate 39-4 can be obtained directly from the OR gate 39-15.
The output signals from the 9 output lines X1, X2, X3, and X4 are output from the block state detection circuit 38.
The signal is supplied to inhibit gates 47-1 to 47-4 whose gates are opened except when a block address signal is generated.
Inhibit gates 47-1 to 47-3 are supplied to AND gates 46-2 to 46-4 via corresponding OR gates 48-1 to 48-3, respectively, and the output of inhibit gate 47-4 is The signal is supplied to the AND gate 46-1. Therefore, in addition to the JO block address signal, the step addend for each block address and the step correction addend that is J+L for the selected block address are added in synchronization with the generation of the addition timing signal. 40 as an addition signal. Further, when the RO block address signal outputted from the block state detection circuit 38 is generated, the 0+2 correction value is applied via the OR gate 48 and the AND gate 46-2, and the 1+8 block address signal is applied in synchronization with the generation of the addition timing signal. It will be added together with addition. In the end, the added value for each block address based on the scale supplied to the adder 40 becomes the highest octave (fourth octave signal 04) as shown in FIG. The number of steps in one cycle of the musical sound waveform of each scale is also shown in the right column of FIG. That is, the number of steps between each scale has a relationship of ゛゜V. Of course, the above-mentioned addition timing supplied to the adder 40 differs depending on the octave signals 01 to 04, and the value subtracted by the subtractor 41 also depends on the octave signals 01 to 04.
04, and as the octave becomes lower (in the direction of octave signal 01), the period of one cycle of the musical sound waveform becomes longer. Therefore, the period counting register 3
4, the scale code register 20, and the octave code register 21 have eight line memories, and one cycle of each register in the direction of the arrow is a shift pulse of 8φo, so the musical waveform can only be controlled every cycle. The usual idea is that it cannot be controlled, but according to this system, by using the shift memory described below, it becomes possible to control the registers arbitrarily within one cycle.

That is, in this system, eight line memories are provided in the direction of the arrow on the output sound generation section side (immediately before the D/A conversion circuit) in FIG. Become. This shift memory 49 stores the 3 bits (r1, R2J, l4j weight) output from the weight shift circuit 44 described above in FIG. 3A.
One of the eight line memories is addressed by the code represented by , and the addresses RO to R7J are arranged in order from the line memory closest to the output side. That is, this address designation allows a maximum delay of 8φo shift time. Further, the address of this shift memory 49 is determined by the addition timing signal outputted from the addition timing generation circuit 43 of FIG. 3A.
It is specified only when it is supplied via AND gates 50 and 51 in FIG. C, and the output signal of AND gate 51 applied to this shift memory 49 is called an enable signal. In FIG. 3A, the output of weight 01J of the synchronous counting register 34-2 is applied to AND gates 44-1, 44-3, and 44-6 of the weight shift circuit 44, and the output of weight 01J of the synchronous counting register 34-2 is applied to is applied with the output of weight R2J, the output of weight R4J is applied with AND gate 44-4, and AND gate 44-6 is applied with output line Y1, AND gates 44-3 and 44-5 are applied with OR gate 44-7. to output line Y2 through AND gate 44
-4 and 44-2 are supplied to an OR gate 44-8, and an OR gate 4 to which the output of an AND gate 44-1 is supplied.
4-9 to output line Y4.

That is, 3 represented by these output lines Y1, Y2, Y4
The bit output is now supplied to the shift memory 49 as an addressing code, and the synchronous counting register 34-2
The output has the address designation shown in Table 4 in accordance with the octave signals 01 to 04. As will be described later, from the line memory at this specified address, the adder 5 is
The output values from the shift memory 49 are sequentially shifted up by the φo pulse and taken out from the output of the shift memory 49.

In this way, one cycle of the musical sound waveform for each scale is the reference clock φ.

The number of steps is different for each scale, and the operation will be explained using FIG. 7A in order to better understand how to create a cycle for each scale. 7th
The operation shown in FIG. A is for the case where the highest octave is 04 shown in FIG. 6 and the scale name is ゜゜C゛. Period counting register 34
Since the addition timing signal is output from the addition timing generation circuit 43 when ROJ is in the initial state, the OR gate 48-4 and the AND gate 46- are synchronized with the 10 block address signal from the block state detection circuit 38. 3
The 1+2J correction value is given together with the 1+8J addition command via the adder 40, so (0+10)
is added. This additional value of 10 is the subtractor 4
1, 1-8J is subtracted by the fourth octave signal 04,
The subtracted output value R2J is fed back to the synchronous count register 34-2. Also, the addition timing signal is sent to the adder 36 by 1+1.
It is supplied as a J addition command and also as an enable signal to the shift memory 49 in FIG. 3C. At this time, the address of the shift memory 49 is ROJ, and the output timing state is such that the output value of the adder 52, which will be described later, can be immediately output from the line memory ROJ of the shift memory 49.
Next, after 8φo shift time, the synchronous count register 34-
R2J is output from block count register 34-
RlJ is output from 1 (see B and e in FIG. 7A, respectively). At this point, the output of the block count register 34-1 is r1, so the scale step matrix circuit 39
1 output of the block state detection circuit 38 is applied to the scale ゜゜C゛, but no output signal is generated from this matrix circuit 39 in the scale ゜゛C゛. Therefore, the step correction number is not given to the adder 40, and the addition timing signal is Only the 1+8 command is supplied in synchronization, and in the end, addition of (2+8) is performed. Furthermore, 1-8J is subtracted by the subtractor 41, and the subtracted output value R2 is finally fed back to the synchronous count register 34-2. Further, the 0+L output is supplied to the adder 36 in synchronization with the addition timing signal, and the added value 12 is fed back to the output count register 34-1. Furthermore, this addition timing signal is applied to the shift memory 49 as an enable signal, and the output value R2J of the synchronous counting register (TC) 34-2 is supplied to the weight shift circuit 44.
The "1" signal is taken out from the output Y2, and as seen from Table 4, it specifies the address 12 of the shift memory 49. As a result, the output timing of the block address r1 is as shown in FIG. (7) As seen from i, 2φ
o The state is such that the output from the shift memory 49 is delayed by the shift time. That is, block address 10. There are 10 steps between and RL. Thereafter, the same operation is repeated, and in the scale ゛ "C", the intervals between the following block addresses are 8 steps, and one cycle of the musical sound waveform has 130 steps, as shown in Fig. 6.
7B and 7C respectively show the operation explanation for the scale "B゛゛C+''' in the fourth octave signal 04 as shown in FIG. 7A.
It is shown in the same way as the state diagram of . FIG. 8 shows the details of the shift memory 49 and adder 52 in FIG. is omitted in the drawing) and is shifted using the basic clock φo.

Input control circuits 49-1 to 49-16 are provided on the input side of each line memory 49-1 to 49-8, and the gate circuit for only one bit is shown in the drawing for simplification. However, all bits are made up of similar gate circuits. Also, the decoder 49- of this shift memory 49
17 are Y1 and Y of the weight shift circuit 44 of FIG. 3A.
A 3-bit addressing signal of 2 and Y4 is applied, and addressing of RO to R7 is performed here. That is,
Address ROJ~R7. Line memory 49-1 in the order of J
.about.49-8 are associated with each other. Thus, the designation signals of addresses RO to R7 are applied to AND gates 49-18 to 49-25 to which enable signals are supplied, and their outputs are supplied to input control circuits 49-9 to 49-16. . The input control circuits 49-9 to 49-16 input the output of the adder 52 from the line memory at a designated address and sequentially shift it to the output side. Then, from the output of the line memory 49-1, the output AC 49-
26, it is supplied to the D/A conversion circuit via latch circuits 49-27. Also, the output of the latch circuit 49-27. is accumulated by being circulated to the output adder 49-26. Furthermore, the output of the immediately preceding line memory corresponding to the designated address of line memories 49-1 to 49-8 is applied to the corresponding wait stage of adder 52 via OR gate 49-28 (only one bit is shown).
Next, 53 in FIG. 3A is a synchronous set register, which consists of eight 1-bit line memories connected in series, and 53 in FIG.
54 is an envelope register with 7 bits (r1, R2
J. ．． l4. JSl8yo, 116yo, -U'32yo, 1
Eight (64 weight) line memories are connected in parallel in the direction of the arrow, and all of them are sequentially shifted in the direction of the arrow in synchronization with the shift pulse φo.

In short, the scale code register 20, octave code register 21, period count register 34, period set register 53, and envelope register 54 are associated with respective line memories, that is, from the scale code register 20, octave code register 21 to For each pitch code to be output, a corresponding control output is generated from the cycle count register 34, cycle set register 53, and envelope register 54. r1-R of the envelope”-pre-register 54
2J. ．． The envelope coefficient value is specified by the 32 count values of ROJ-R3lJ represented by the 5-bit output of r4JNr8Jlrl6 weight, and R32
The two bits of the 1L weight indicate four envelope states: attack, decay, release, and clear of the envelope. Thus, the 7-bit output of each stage of the envelope register 54 is applied to the corresponding weight input terminal of the adder 55. Each bit output of the adder 55-1 that counts the envelope control value in the adder 55 is transmitted to envelope registers 11J, . 12JNr4J. ．． 18a1
16 weights are circulated to the corresponding input side. Also,
The carry output signal generated from the adder 55-1 is the state detection weight R32J of the envelope register 54. ．． r
It is applied to the carry input terminal of an adder 55-3 for state counting through an inhibit gate 55-2 whose gate is inhibited by the output of an inverted AND gate 57 which detects a clear state of 100 J at 64 J. That is, the adder 55-3 accepts the carry output signal except when the envelope is in the clear state. And adder 55-3
The output of envelope register 54 is 132J. ．． r6
An inhibit gate 58-1 is connected to the weight input terminal of 4J.
58-2. Further, the input instruction signal of the performance key shown in FIG. The envelope will now be placed in the attack state immediately. Here, the envelope state and R32W. ．． Table 5 shows the relationship between the r64j weight and the 2-bit code state. The output of the synchronous set register 53 in FIG.
0 is applied to one input terminal of the inhibit gate 61.

The other input terminal of the AND gate 60 is supplied with the output of an AND gate 62 which takes the logical product of the RO block address signal and the addition timing signal outputted from the addition timing generation circuit 43. Furthermore, the synchronous set register 58 is set when a clock signal (collectively referred to as an envelope clock) output from the inhibit gate 63 is applied to the input side after passing through the OR gates 64 and 65 according to the state of the envelope, which will be described later. done by being done. Incidentally, since the series-connected output signals of the inhibit gates 66-1 to 66-5 and the inverted AND gate 66-5, which detect the all RO state of the envelope register 54, are applied to the inhibit gate 63, all R.O. In this state, the envelope block is controlled not to pass through this inhibit gate 63. When the RlJ signal is set in the synchronous set register 53, the AND gate 60 is opened in synchronization with the addition timing signal of the 10J block by the AND gate 62, and the addition timing signal to the adder 55 is generated. At the same time, since the output of the inhibit gate 61 is inhibited, a ``0'' signal is written in the period set register 53, and the setting is canceled. The addition timing signal output from the anchor 60 is then output from the AND gates 67-1 to 67-1.
67-5 as a gate open signal, and an addition value is supplied to the envelope adder 55, which will be described later, so that the envelope time changes in the attack, decay, and release states. Become. That is, the synchronization set register 53 is provided for synchronizing the addition value applied to the envelope adder 55 with the musical sound waveform RO block address. Also, the output of the synchronous set register 53 is ROJ and the envelope register 54
When all ROs are present, the inhibit gate 68 outputs a reset signal, which will be described later. Rlj. of the envelope register 54. r2J. ．． r4a18yo, Rl6J
The 5-bit weight output is output from the exclusive OR gates 69-1 to 69- of the weight shift circuit 69 in FIG. 3C.
5, respectively. Switch S1 in FIG. 3C,
S2, S3, S4, turtle, and S6 are α and β volume curve type instruction switches, and the set of S1, S3, and turtle switches is α
The volume curve type attack A1, decay D1, release R are respectively designated, and the set of switches S2, S4, and S6 are respectively designated as A, D, and R of the β volume curve format.

That is, as shown in Figure 9, seven types of volume curve formats can be specified using three switches, and in this example, two types of volume curve formats can be selected at the same time, and one can be set to α(
The other one is called β (selected using switches S2, S4, S6).
Therefore, the types of combination instructions for α and β volume curve formats are as shown in FIG. Now, the waveform program specifying section 35 of the block address mentioned above in FIG. is specified with 1+1 (up) and 1-J (down), and it is also possible to specify α or β in the previously specified volume curve format for each block address. In the case of the β instruction, the RL signal is output, and in the case of the α instruction, the 10j signal is output. That is, an example of the designation is shown in FIG.
Differential coefficient value 11 for each block. j. 12. j. 14-yo, 1+yo, 1-yo instructions are given, and further α, β
It is now possible to select the volume curve format. The details of the waveform program specification section 35 are as follows.
As shown in Figure 2, block addresses 1L to Rl5
For each block address of J, the differential coefficient value is 1, and R
Switches A1 to Al5 specifying the absolute values of 2 and R4.
, B1 to Bl5, α/β volume curve format instruction switch C1
~Cl5, +/1 instruction switches D1 to Dl5 are provided, and the count value 1L-R of the block count register 34-1 is provided on the common line of the switch group for each block address.
The block state detection signals of 15 and 15 are combined. Furthermore, differential count value designation switches A1 to Al5 for each block,
2 to Bl5 receive differential coefficient values r1 and 12J.2 through decoders E1 to El5, respectively. 14 instructions are output as three instruction signals, and each corresponding instruction signal is eventually taken out via an OR gate. Note that since the block address RO is always set at the ROJ level, there is no switch specification, and therefore block addresses r1 to Rl5 can be specified. Therefore, the waveform program specification section 35
The (-) command signal specified for each block address is supplied to the adder 52 in FIG. 3C, and the differential count value is 01.
．． j. 12J. The command signal 14J is applied to the weight shift circuit 69 of FIG. 3C, and the β command signal is applied to the exclusive OR gates 70 and 71 of FIG. 3B.

Then, this β command signal normally passes through an exclusive OR gate 70 and is passed through an αβ volume curve type control circuit 7.
2 inhibit gates 72-1 to 72-3 and AND gates 72-4 to 72-6. Therefore, the AND gates 72-4 to 72-6 are synchronized with the β instruction signal (“1”), and the inhibit gates 72-1 to 72-3 are synchronized with the α instruction signal (“C”), and the αβ It will be output in accordance with α and β selected and instructed by the separate volume curve format designation switches S1 to S6, and the inhibitor 72-
1 and the output of AND gate 72-4 is OR gate 72-7
Inhibit gate 72-2 and AND gate 72-
The output of 5 is sent to OR gate 72-8, and the output of inhibit gate 72-3 and AND gate 72-6 is sent to OR gate 7.
It is connected to 2-9. The output of the OR gate 72-7 is the AND gate 72-10 and the inhibit gate 72-1.
1, 72-12 and AND gates 72-13, and the output of ORKATE 72-8 is supplied to AND gate 72-14.
Furthermore, the output of the inhibit gate 72-12 and the OR gate 72-9 is supplied to an AND gate 72-15. Further, the output of the AND gate 72-14 is applied to the inhibit gate 72-11 and the AND gate 72-13. Further, the AND gate 72-10 and the inhibit gate 72-11 are connected to the OR gate 72-17 via the OR gate 72-16, and the inhibit gate 72-12 is connected to the OR gate 72-17 via the OR gate 72-16.
The output of ORK7 is passed through AND gate 72-18.
2-19, AND gates 72-13 and 72-15 are supplied to OR gate 72-20, and one more OR gate 72
-17, 72-19, and 72-20 are connected in series and are eventually supplied to the AND gate 50 as the output of the OR gate 72-17. the AND gate 72-10,
72-14, 72-15, and 72-18 are connected to the detection signal from the envelope state detection circuit 73. That is, normally, the inverted AND gate 73-1 is in the clear state of the envelope, and the inhibit gate 73 is in the clear state of the envelope. -2 detects the attack state, inhibit gate 73-3 detects the decay state, AND gate 73-4 detects the release state,
Inhibit gate 73-2 is AND gate 72-10
Then, the inhibit gate 73-3 is the AND gate 72-
14, 72-18 as a gate open signal. Further, the inverted AND gate 73-1 is supplied to the inhibit gate 73-5 together with the detection signal of the all RO state of the envelope register 54 (see FIG. gate 7
The output of 3-5 is further supplied to AND gate 72-15 as a gate open signal through AND gate 73-4 and OR gate 73-6. Therefore, the OR gate 72-16 of the αβ-specific volume curve format control circuit 72 is in the attack state when the volume curve format is in the instructions 4 to 7 in FIG. 9, and in the decay state when the volume curve format is in the instructions 2 and 3 in FIG. The AND gate 72-18 is for taking out the R3L command signal in the case of instructions 4 and 5 in FIG. 9, which are in the decay state and there is no decay instruction when there is an attack instruction. . In addition, the or gate 72-20 is the descending instruction for Decay and Release, 1, 3, 5, etc. in Figure 9.
In the case of 7, it is taken out as a signal indicating a complementary value obtained by inverting the envelope coefficient value. On the other hand, Oraketo 72-
17 is output in each attack, decay, and release state only when a switch instruction for attack A1 decay D1 release R is given, and outputs the addition timing signal at that time as an enable signal to the shift memory 49.
The R3L command signal output from the AND gate 72-18 is sent to the OR gates 69-6 to 69-6 of the weight shift circuit 69.
The complement command signal supplied to 69-10 and output from the OR gate 72-20 is supplied to the exclusive OR gate 69.
Exclusive or gate 6 via 11
9-1 to 69-5. That is, when the R3L command signal and the complement command signal are not present, the weight shift circuit 69 inputs the signals 11 and 12 of the envelope register 54.
J. ．． r4J. ．． The envelope register coefficient value assigned by the r8-116 weight passes through exclusive OR gates 69-1 to 69-5, and becomes the differential coefficient value 01, R2-R4 for each block address specified by the waveform program designation section 35. A weight shift (in this case, the differential coefficient value x the envelope coefficient value E) is performed in accordance with the specified coefficient value, and the multiplied value thereof is supplied to the adder 52.

That is, the command signal with a differential coefficient value of 1 is the AND gate 69-
12 to 69-16, and the instruction signal of 12 to one input terminal of ANDKates 69-17 to 69-21.
The instruction signal for R4 is AND gate 69-22 to 69-2.
It is supplied to one input end of 6. And gate 6
The other input terminals of AND gates 69-12, 69-17, and 69-22 receive a signal corresponding to the weight RL of the envelope coefficient value, and the other input terminals of AND gates 69-13, 69-18, and 69-23 receive a signal corresponding to the weight RL of the envelope coefficient value. The signal corresponding to the weight 14j is input to the other input terminal of the AND gates 69-14, 69-19, and 69-24.
-15, 69-20, 69-25, a signal corresponding to weight R8 is input to the other input terminal of
, 69-21, 69-26 have a weight R at the other input terminal.
A signal corresponding to l6j is now supplied. Furthermore,
AND gate 69-12 is weight RlJ of adder 52
AND gates 69-13 and 69-17 are connected to the input side of weight 12 through OR gates 69-27, and AND gates 69-14, 69-18, and 69-22 are connected to OR gates 69-28 and 69. Weight 1 by 29
AND gate 69-15, 69-19 on the input side of 4-jo
, 69-23 are connected to the input side of the weight R8J by OR gates 69-30, 69-31, and the AND gate 69-1
6, 69-20, 69-24 is or gate 69-32,
69-33 is connected to the input side of weight 116, AND gates 69-21 and 69-25 are connected to OR gate 69-3.
The AND gate 69-26 is coupled to the input side of the weight R32 through the gate 4, and the AND gate 69-26 is coupled to the input side of the weight R64. Therefore, this weight shift circuit 69 changes the differential count value Rlj. The multiplication value shown in FIG. 13 is obtained according to r2Jlr4J. Therefore, when the R3 command signal output from the αβ volume curve type control circuit 72 is supplied to the OR gates 69-6 to 69-10, the envelope coefficient value becomes R3lJ regardless of the output of the envelope register 54. Becomes forced. Furthermore, when the complement command is supplied to the exclusive OR gate 69-11, the envelope coefficient value represented by 5 bits of the envelope register 54 is inverted, and the multiplication value shown in FIG. 13 becomes the inverse count value. It is. Therefore, as can be seen from FIG. 11, the multiplication for each block address follows the volume curve format specified for α and β, and in the end, the multiplication is
The envelope coefficient value is E (however, E is Eα when following the α volume curve format, and Eβ when following the β volume curve format).

The multiplication value input to the adder 52 in this manner is supplied to the shift memory 49. That is, by specifying the two volume curve formats α and β, it is possible to simultaneously specify the waveform according to α and the waveform according to β, and in the end, the rise and fall curves of the volume can be changed between different waveforms. By combining them, it is possible to make a synthesized musical sound waveform rich in variety. For this reason, the harmonic structure changes noticeably over time, making it possible to generate musical tones with effective timbre, and expressing the unique characteristics of the instrument, especially when producing sounds seen in brass instruments and plucked string instruments. It is perfect for. In FIG. 3B, switch SlO. Sll and Sl2 are for specifying cycle mode by β, and each switch SlO, . Sl, Sl. is supplied to the cycle (referred to as duty) control circuit 74, and depending on the on/off state of these three switches, a mode designation signal indicated by eight numbers from 10 to 17 is output from the AND function matrix circuit 74-1. removed from the line,
The output line is the OR function matrix circuit 74-2.
is input.

On the other hand, 3 bits (Rl6JN
r32 yo, j are also wait) outputs are also supplied to this duty control circuit 74, and the 14th output from the inverted AND gate 74-3 is
The output state of FIG.
? +16・32・? ), the output state shown in FIG. 14c is obtained. The signal in the hole of the cycle number register 34-3 shown in FIG.
17 and 74-8, and the output of the inverted AND gate 74-3 is supplied to AND gates 74-9 and 74-8.
-10, and the output of the OR gate 74-4 is supplied to AND gates 74-11 and 74-12. Here, the basic relationship between duty and cycle counting status will be described as shown in FIG. 15.

That is,. At 0? 1 indicates a cycle with no waveform output, and 1 indicates a cycle with waveform output.

Duday 11J. r112yo and Rll4J each time,
The waveform output is taken out every 1゛ cycle, every 2゛ cycle, and every 4゛ cycle.
This can be obtained by setting the cycle state. That is, the periodic mode designation switch SlO. Sll
, 50 specified by a combination of 3 bits of Sl2
OR function matrix circuit 7 when specifying modes R6 and R7J among the modes associated with numbers from y to R7.
The output K1 output signal is generated from 4-2, and the AND gate 74-1 is generated together with the output signal of the weight 164 of the adder 36.
3, and its output signal is supplied to the weight 132J of the cycle number register 34-3 via the ORKATE 74-14.
and skips the cycle state of ゜゜4゛"5゛. Also, K2 of the OR function matrix circuit 74-2
The output goes to OR gate 74-15, the K3 output goes to OR gate 74-16, the output goes to OR gate 74-15 through inhibit gate 74-7, the K5 output goes to OR gate 74-15 through inhibit gate 74-8. To 16, K
6 output is sent to OR gate 74 via AND gate 74-9.
-17, K7 output goes through AND gate 74-10 to OR gate 74-18, K3 output goes to AND gate 74-18.
-11 to the OR gate 74-9, the 4 outputs are connected to the OR gate 74-20 via the AND gate 74-12, and the OR gates 74-15, 74-17, 74-
19 are connected in series to output the output X1α, and the OR gate 74-
16,74-18,74-20 are connected in series to output X
2β is extracted. Therefore, the outputs X1α, X2β
The output signal generated is the number RO that specifies the cycle mode for αβ.
It becomes as shown in FIG. 16 corresponding to R7J. That is, the period M is extracted from the output X1α based on the waveform specified by the α instruction, and the period N based on the waveform specified by the β instruction is extracted from the output X2β. Therefore, periodic mode RO
In yo~R5yo, the period M. ．． Both N are integers, but the periodic mode R6. In J and r7, if one of the periods M and N is an integer, the other is periodically controlled in a non-integer relationship.
Furthermore, the outputs X1α and X2β are respectively inhibited by the inhibit gate 7.
5. It is supplied to the AND gate 76, and is normally synchronized with the α/β instruction signal from the exclusive OR gate 71. When the α instruction signal (゜゜0゛) is supplied, the inhibit gate 75
With the instruction signal (“1”), the AND gate 76 is opened, and the output thereof is further input to the inhibit gates 77, 7, which will be described later.
8 from the OR gate 79 and supplied to the AND gate 51 in FIG. 3C. Here, the switch R1 is connected to the exclusive OR gate 71, and is provided to invert the α/β instruction signal for each block address output from the waveform program specifying section 35 when operated. Therefore, the AND gate 76 inputs the α instruction signal,
Since the inhibit gate 75 outputs in synchronization with the β instruction signal, the output X1 has a duty of β and the output/output X2 has a duty of α.

The switch R2 is connected to the inhibit gates 80 and 81 to which the P signal and its inverted signal F are respectively supplied, and is used to instruct whether to separate αβ or not. The output is obtained. figure,
Therefore, from the inhibit gates 77 and 78, signals X1α and
β (However, when switch R1 is set, it becomes X1β and X2α)
A signal is extracted. When the switch R2 is not operated, the P signal and the F signal (however, they are generated only when a multiplayer instruction is issued) are output from the inhibit gates 80 and 8, respectively, and the even line memory of each register is α, and the odd line memory is α. is now indicated by β, and FIG. 17 shows this in an easy-to-understand list. In this case, the swing R1
Also, a case is shown in which the switch designation of R3, which will be explained next, is not made. Further, the non-separation instruction by the switch R2 is valid only when there is a duet. Switch R3 is connected to exclusive or gate 70,
When this is operated, the α/β instruction signal designated for each block by the waveform program designation section 35 is inverted. That is, even in the table shown in FIG. 17, the α/β relationships are all reversed. In this way, octave operation can be performed by specifying the cycle mode for each αβ, which is an effective function because the duty of the musical sound waveform can be changed and the timbre can also be made different for each octave.

Also, referring to the α/β non-separation operation in Figure 17, in the case of mode specification R6, α: β has a period of 1:1.5, β is a perfect fourth lower than α, and the mode Designation R7
In the case of , the period of β is twice that of α, but the waveform of β is considered to be a composite of the period of 213 times the period of α and twice the period of α, and β is a component that is a perfect fifth higher than α. This results in a sound with components an octave lower. In FIG. 3D, switch T1 is a normal tremolo (called tremolo flat) instruction switch,
T2 is a touch tremolo instruction switch that applies tremolo only during operation, and when instructing touch tremolo, the tremolo flat instruction switch is left open.

Switches T3, T4, and T5 are switches that indicate the depth of the tremolo (referred to as the amplitude value), and in order, the maximum 0L (100
% depth), Rll2! (50% depth) and Rll4yo (25% depth) can be specified. Since the designation signal of the switch T1 or T2 is supplied to the AND gates 83-1 to 83-3 via the ORKATE 82, the output designation signal of the designated amplitude value is taken out and supplied to the tremolo control circuit 84. Thus, AND Kates 83-1 to 83-3 are given to AND Kates 84-3 and 84-4 via OR gate 84-1 or 84-2. Further, when the switch T4 is turned on, the output of the AND gate 83-2 connected to the switch T4 is output from the R of the envelope register 54.
AND gate 84-5 to which 64 weight outputs are combined
The signal is supplied to an OR gate 84-6 and an AND gate 84-7.

Therefore, when the switch T4 is turned on, the weight 1 of the envelope register 54 is set in the decay state and the release state.
16J always becomes '6r1. Further, the output of the AND gate 84-8 for detecting the release state is given to the AND gate 84-3, which is opened in response to a tremolo instruction.
The output is taken out as an output signal from the OR gate 84-10 via an inhibit gate 84-9 which can be opened other than when specifying a mandolin, which will be described later. Therefore, the inhibit gate 84-7 is not opened in the released state, and as a result, the inhibit gate 84-7 is not opened in the released state. Bit gate 84-11 can now be opened. Therefore, in the released state, the output of the weight Rl6J of the envelope register 54 is output to the inhibit gate 84-11.
will pass through. On the other hand, in the tremolo instruction, the output of the R64J weight of the envelope register 54 is supplied to the AND gate 84-4, and the output is sent to the R64J weight of the envelope register 54 via the OR gate 84-12.
In order to always supply the 01yo signal to the J weight, ROOJ
The clear state does not occur, and the decay state and release state repeat. When the switch T5 is turned on, the output of the AND gate 83-3 connected to the switch T5 is connected to the OR gates 84-14 and 84-13 via the AND gate 84-13 to which the output of the weight R64J of the envelope register 54 is applied. 15 and also to inhibit gate 84-16.

This inhibit gate 84-16 is not opened in the released state like the inhibit gate 84-7, and in this state, the inhibit gates 84-17, 84-18 are closed.
can be opened. Therefore, in the release state, the outputs of the weights Rl6., R8j of the envelope register 54 pass through the inhibit gates 84-17, 84-18.The outputs of the weights R32 of the envelope register 54 will be explained later. The AND gate 84-19, which is valid only when the tremolo play instruction switch T6 is on, is further applied to the inhibit gate 84-21 via the coupled inhibit gate 84-20. Since the gate output prohibition signal from the AND gate 84-4 is applied to the gate, it is not opened in response to a tremolo instruction and always outputs "゜0゛". Therefore, the envelope state detection circuit 73 inhibits the inhibit gate 73.
Only the output signal in the -3 decay state is taken out. That is, in the tremolo instruction switches T1 and T2, the envelope coefficient value of the envelope register 54 is set to the amplitude value 111, 112, 112, etc. according to the volume curve format (see Figure 9).
With the depth instruction 114, the examples shown in FIGS. 18 to 20 are obtained. In addition, 1 of the volume curve format in Fig. 9,
For numbers 4 and 5, no tremolo is applied. T6
is a tremolo repelling instruction switch, and when this is operated, the output signal of the inhibit gate 84-22, which is output from the AND gate 84-19 under the condition that it is in the released state and the envelope register 54 is 116 J or more, is passed through. become. Furthermore, the envelope register 54 RO
When the cleared state of O is detected by the separated AND gate 73-1 of the state detection circuit 73, it is output as a release instruction signal to the AND gate 72-15 via the inhibit gate 73-5 and the OR gate 73-6. It will be done. Therefore, the first half of the released state is operated by the decay clock signal described later, and as shown in FIG. This makes it an effective function. The touch tremolo instruction switch T2 is effective when the flat tremolo instruction switch T1 is previously turned off, and the tremolo effect is obtained only during operation.

Depending on the output state of the wait stage R32 and R64 of the envelope register 54, the inhibit gate 85 outputs the attack state detection signal 5, the inhibit gate 86 outputs the decay state detection signal 4, and the series circuit of the AND gate 87 and the inhibit gate 88 outputs the attack state detection signal 5. Release detection signal?
・The high release detection signal O is output from the above-mentioned inverted gate 66-6 to the AND gates 89 and 90.
The slow release detection signal O is taken out by the series circuit.

Further, 91 is a synchronous set register for high release designation, which has eight 1-bit line memories and performs a shift operation in response to a shift pulse φo. Thus, high release ◎ means relatively fast attenuation to prevent click sounds when the performance key is off (especially when specifying a steady sound such as an organ sound). For this purpose, when an O set signal, which will be described later, is output, that signal is passed through an OR gate 92 to an inhibit gate 93, which is opened when there is no input instruction signal, and a third
The signal is input to the high release synchronization set register 91 via the inhibit gate 94 which is opened by the inverted signal of the AND gate 62 in FIG. The output signal of the inhibit gate 93 is synchronized with the output signal of the AND gate 62 (the addition timing when the RO! block address signal is generated), and the AND gate 95 is an inhibit gate that is opened in a state other than the envelope state r'00J. The signal is input to the synchronous set register 53 for the envelope clock via the gate 96, the OR gate 64, and the OR gate 65 to perform a high release operation. As described above, according to the configuration of the present invention, as shown in FIGS. 14 to 17, particularly in FIG. In other words, it is possible to extremely easily generate musical tones in octave relationships with different duties.

In the above embodiment, the volume curve format can be specified as two different types, α and β, but this is not limited to two types, and it is also possible to combine two or more waveforms. .

In addition, although the waveform program designation section 35 for each processor in FIG. 3A described above is designated by a switch as shown in FIG. It may be stored in a fixed storage device such as.

Also, store the necessary instructions on a magnetic card,
Various methods are conceivable, such as reading out the data when it is used and storing it in a buffer in a memory such as a flip-flop. Further, the number of blocks in one period of the musical sound waveform is not limited to 16, and the differential coefficient value for each block is also RlJ. ．． r2. ．． , R4, etc., and the design can be changed arbitrarily. Furthermore, D/A
A filter circuit can be provided after the conversion circuit, and in that case, multiple types of filters may be prepared and selected arbitrarily using a switch. It is possible to obtain different effects such as the characteristics and reverberation characteristics or the transmission characteristics of wind instruments. It goes without saying that various other circuit configurations may be employed without departing from the gist of the present invention. As described in detail above, according to the present invention, there is provided a waveform information supply means for supplying waveform information for generating a musical sound waveform at a speed corresponding to the frequency of the musical sound to be generated, and a comprising a period number counting means for counting, and an output control means for controlling whether or not to output the waveform information supplied from the waveform information supply means according to the count content of the period number counting means, Since the musical sound waveform is generated in only one cycle among multiple musical sound waveform cycles, it has a simple configuration and contains many harmonic components rather than a waveform with a duty ratio of 1, that is, a waveform that is not a sine wave. There is an advantage that the waveform can be obtained, and even if the output characteristics of the speaker deteriorate in the low frequency range, the volume level of the output musical tone will not decrease much.

Another advantage is that waveforms having different duties in octaves can be obtained very easily.

[Brief explanation of the drawing]

Figure 1 A, B, C, D, E, F is a diagram explaining the logic symbols used in this embodiment, Figure 2 is Figure 3 - A, B, C,
Figure 3 A, B, C, and D are specific circuit configuration diagrams of the heart of this system. Figure 4 is related to the block address status in Figures 3 A and B. Figure 5 is a time chart showing the addition timing output for each octave related to the synchronization register in Figure 3A, Figure 6 is Figure 3A and B. Diagram explaining the number of scale steps in , Figure 7A
, B, and C are time charts explaining the waveform period for each scale in this system, Figure 8 is a detailed diagram of the shift memory in Figure 3C, and Figure 9 is the volume curve format used in this system. Figure 10 is a diagram explaining the combination of volume curve formats for α and β in this system, and Figure 11 is a diagram for specifying block addresses for α and β of musical sound waveforms in this system. 12 is a detailed diagram of the waveform program designation section in FIG. 3A, and FIG. 13 is a detailed diagram of the waveform program designation section in FIG.
A diagram explaining the output addition value in Figure C, Figure 14 is the third
Figure A is the time chart of the cycle number counter, Figure 15 is a diagram explaining the basic relationship between the number of cycles and duty used to explain Figure 3B, and Figure 16 is the cycle mode designation for αβ in this system. FIG. 17 is a detailed diagram related to the αβ period mode in this system. FIGS. 18, 19, and 20 are waveform diagrams explaining the tremolo control used in this system. 21A and 21B are waveform diagrams illustrating the plucked sound tremolo control used in this system. 20... Scale code register, 21... Octave code register, 34... Period count register, 35... Waveform program specification section, 36,
40...Adder, 41...Subtractor,
74...Duty control circuit, 74-1...AND function matrix circuit, 74-2...OR function matrix circuit, SlO, Sll, Sl.

Claims (1)

[Claims] 1. A waveform information supply means for supplying waveform information for generating a musical sound waveform at a speed corresponding to the frequency of the musical sound to be generated; a period number counting means for counting each cycle of the musical sound waveform; and output control means for controlling whether or not to output the waveform information supplied from the waveform information supply means according to the count content of the number counting means, the output control means for controlling whether or not to output the waveform information supplied from the waveform information supply means, the output control means for controlling whether or not to output the waveform information supplied from the waveform information supply means, the output control means for controlling whether or not to output the waveform information supplied from the waveform information supply means according to the count contents of the number counting means. 1. A musical sound waveform generator for an electronic musical instrument, characterized in that the musical sound waveform is generated only by the user.