FR2473173A1 - Electronic musical instrument with progressive digital counter - has volume control and period counter dividing period into blocks with stages and accumulates volume and tone signals for output loudspeaker - Google Patents

Abstract

The electronic musical instrument uses digital techniques with the counter couting progressively. The digital circuits are suitable for mfg. by large-scale integration techniques. The time variation of the higher harmonic structure is digitally processed to give a more attractive tone. The volume control uses a digital technique. It has a period counted to convert the musical sound wave into digital pulses. This is performed by dividing the period into blocks with several counting stages. The musical notes in each block are characterised by a positive or a negative sign. The major components are an input key signal decoder (1), time interval circuit(2), wave-form distributor(3), decoder(5), volume control(7), folding circuit(6), signal counter(8), accumulator(9), analogue converter (10) and loudspeaker (11).

Description

 The present invention relates to an electronic musical instrument using a new technique for constituting the major part of the generating section of musical sounds by a digital circuit.

 So-called analog technology has so far been used dominantly in the field of electronic musical instruments such as electronic organs, electronic pianos, musical synthesizers but digital technology, which has recently taken a marked development, has also been used. partially used in this area.

A dreadfully complicated command is needed to make the main part (the unit of formation of the musical sound wave, the unit of formation of the period of the note, the unit to form the curve delimiting positive variations and variations volume and the like) in the musical sound production stage of an electronic musical instrument using large-scale integrated circuit technology when using digital technology
This is why no electronic music instrument of simple construction, resulting from a full application of nmSric technology to the construction of the musical instrument, has been developed successfully.

 In electronic musical instruments, the formation of various musical sound waves is of great importance to produce musical sounds with varied timbres. For this purpose, many proposals have been made to define musical sound waves. According to one of these proposals, sinusoidal waves from the fundamental wave to higher harmonics with given order are stored in a plurality of memories in the form of digital signals representing the amplitudes of the waves.

When a musical sound is defined, the sinusoidal waves having the corresponding orders are read selectively and simultaneously, and then the thus-read sinusoidal waves are synthesized to form a definite waveform of the musical sound. Another proposal permanently stores digital signals representing fundamental waves such as the triangle wave, the sine wave, the rectangular wave and the sawtooth wave in a memory unit of the waveform. An additional proposition is to permanently store signals representing numerically or analogously given waves of musical sounds in a fixed memory.

 In order to obtain an artificial musical sound wave that is perfectly analogous to the original natural musical sound, not only is a similar musical sound used but also a volume envelope including factors such as wave elevations and waveforms. falls of the wave which must be superimposed on the analog musical sound. However, there is no proposal to effectively overlay the volume envelope to the sound wave by digital technology. The conventional overlay of the volume envelope has been carried out by analog technology or by using a complex control circuit. This is how the technique of forming the musical sound wave by digital technology is well suited for the Large-scale integrated circuit manufacturing has not yet been introduced in this area. The waveform depending on the frequency spectrum (for example the harmonic structure in the usual state) and the volume envelope from the rise of the wave to the descent of the wave or damping are generally the essential factors for determining the timbre of a musical sound produced by a natural musical instrument. However, the particular timbre of the natural musical instrument is strongly influenced by various other factors, for example by ~ -ia ~ -väiA tion time function of the harmonic structure resulting from the delay in the appearance of the higher harmonic components which is observed at the moment of sound production by the brass, the subtle variation of the higher harmonics, the superposition of the noise which is observed at when we pinch the strings, by the rapid disappearance of the higher harmonics during damping.

As a result, the variation over time of the harmonic structure must be taken into account, in addition to the waveforms and the volume envelope, in order to eliminate the sensation of its dull and choppy tone produced by electrical signals of the electronic musical instrument and in order to obtain a natural feeling of sound for the electronic musical sound.

 In a conventional electronic musical instrument, for example an electronic organ, the structure of the harmonics is not modified for each sound and a volume envelope is simply superimposed on the simple musical sound waves. In another example in which the musical sounds of the piano or cymbals are pre-selected, the musical sound wave produced is a simple wave previously set. A synthesizer, which is a unique instrument, modifies the filtering frequency band as a function of time by an analog filtering operation using a voltage control type (VCF) filter or the like. the frequency band is relatively simple, for example "low frequency to high frequency" or "high frequency to low frequency". As a result, units giving additional sound effects are further needed to ensure a more natural sounding feel. A synthesizer of this type for performing a chord requires a filter and a sound effect means for each execution key. This leads to a complexity and a very large volume of the circuit constitution of the musical sound instrument and raises its manufacturing cost.

 The conventional electronic musical instrument uses analog technology for the problem of time variation of the structure in high order hannniques.

The direct application of technology for the execution of an agreement leads to many problems to be solved. Thus, the current state of this technique does not allow to obtain the formation of a satisfactory musical sound wave by a digital technology which is suitable for the constitution by large scale integrated circuit and with a variable harmonic structure according to the time for each sound.

 We will first consider the formation of the periods of the notes. In electronic musical instruments, the frequencies of the sound source corresponding to the execution keys are determined on the basis of the tempered range. A so-called frequency division sound source system is generally used for the formation of the frequencies of the sound source.

In this system, a reference clock frequency is frequency divided by a plurality of frequency divider circuit stages. The respective sound source frequencies are formed by choosing suitable combinations of the frequency division ratios among the frequency divider circuits. A desired waveform is read from a musical sound waveform memory for example by the frequency of the sound source corresponding to the executed execution key. The conventional electronic music instrument is designed primarily for pure or unique sound. executing an agreement by simultaneous action on several execution keys, consequently requires control circuits of the period of the note to the number of one for each execution key in order to ensure a parallel processing . This results in a considerably important circuit construction. A modification is conceivable in which a single control circuit of the period of the note is used in common for a number of execution keys and is used in a time-shared form. In this case, since the resolution is lXn for n execution keys, the time processing control is performed for a unit of time for actions on n execution keys. As a result, when the note period is set for each execution key and when a musical sound is produced, the constitution of the resulting circuit is considerably complex. Thus, no control device of the period of the note practical by a digital technology which is of a simple construction and which adapts well for the execution of agreements has been proposed. This is also true for the digital processing system allowing the execution of agreements by actuating a plurality of keys and the dynamic time-sharing processing in such a case.

 Accordingly, an object of the present invention is to provide an electronic musical instrument using a new musical sound generation technique using digital technology.

 Another object of the present invention is to provide an electronic musical instrument in which the major part of the circuit for producing the musical sounds consists essentially of a digital circuit suitable for large scale integrated circuit realization.

 Another additional object of the present invention is to provide an electronic musical instrument that can form musical sound waves by a digital circuit implementing a new technique.

 A further object of the present invention is to provide an electronic musical instrument in which the variation over time of the high order harmonic structure of the musical sound is processed by digital technology to produce a musical sound with a nice stamp.

 Another object of the invention is to provide an electronic musical instrument using a new technique capable of simultaneously controlling different waveforms.

 A further object of the present invention is to provide an electronic musical instrument with a novel technique by which different waveforms can be controlled simultaneously and synthesized and not only the different waveforms but also the periods of the different waves can be controlled to have a relationship M: N.

 Yet another object of the invention is to provide an electronic musical instrument with a novel technique that provides different volume envelope curves for different waveforms so as to form a wide variety of synthesized musical sound waves.

 Another object of the invention is to provide an electronic musical instrument with a new technique in which the period of the note can be set by a digital counting system.

 Yet another object of the invention is to provide an electronic musical instrument in which the performance of an agreement is possible by a digital dynamic processing technique.

 In order to achieve the above objects, and other objects of the present invention, the subject of the present invention is an electronic musical instrument comprising volume control means for increasing or decreasing the volume of the performance in accordance with the invention. time flow from the action on an execution key, a counting means of the period for counting a cycle of the musical sound wave by a plurality of counting stages to digitally produce a musical sound wave, means for dividing a cycle into m blocks each having one or more counting steps and a musical waveform control means for controlling the rise and fall of the musical sound wave in each block from a value to which is assigned + or "-", which value is an integer multiple of the control value of the volume control means, means in which a single cycle of the musical sound wave is divided into m blocks and these blocks are controlled from way suitable while at the same time can be done a volume control.

 With such a constitution, an electronic musical instrument or system for forming a musical sound is produced by digital technology in which the musical sound wave can be formed on the basis of an instruction corresponding to an introduced musical sound wave. in each block, a volume control is also possible simultaneously.

The system is also applicable for digital volume control of different volume rise and fall curves as seen in pianos, guitars and the like. A change in the volume as well as a variation of the waveform can be adjusted appropriately so that the high order harmonic structure can be greatly modified as a function of time so as to provide musical sounds with pleasant timbres. .

 For the implementation of chord execution, a unique dynamic way of adjusting the note period can be used for a number of execution keys with independent control of the note periods. This simplifies the construction of the circuit relating thereto.

 With these useful features of the invention, the main control part of the electronic musical instrument with the exception of the output sound stage can be manufactured in the large-scale integrated circuit technique. Accordingly, the invention can provide a.

universal and simple electronic musical instrument with a high security of operation.

The invention will be better understood on reading the detailed description given below with reference to the accompanying drawings in which
Fig. 1 is a block diagram of an electronic musical instrument constructed according to the basic concept of the present invention.
Fig. 2 is a graph for explaining an envelope mode used in the instrument shown in Figure 1;
Fig. 3 is a graph for explaining the basic operation of the instrument shown in FIG. 1 to arrive at the definition of a musical sound wave
Figs. 4A, 4B and 4C represent the modifications
relative of musical sound waves according to the value of the envelope coefficient
Figs. 5A, 5B, 5C, 5D, 5E and 5F represent the logical symbols used in the embodiments of the invention
Fig. 6 is a diagram showing the relative positions of FIGS. 7A, 7B, 7C and 7D.
Figs. 7A, 7B, 7C and 7D show a circuit diagram for a real circuit arrangement of the main part of the instrument of the present invention.
Fig. 8 is a time function graph illustrating the time distribution of the selective output state in accordance with a note relating to the state of the block address shown in FIGS. 7A and 7B
Fig. 9 is a time-based graph illustrating the time distribution of the synchronized outputs at the add-on for the respective octaves relating to the operation of the synchronization register illustrated in FIG. 7A;
Fig. 10 illustrates the relationship between the number of steps and the notes with the circuit shown in FIGS. 7A and 7B;
Figs. 11A, 11B, and 11C are time-dependent graphs for explaining the waveform period timing system of the respective notes used in one embodiment of the present invention.
Fig. 12 is a block diagram of a circuit illustrating the detailed constitution of a shift memory illustrate in FIG. 7C
Fig. 13 shows the various types of volume envelopes used in the present invention
Fig. 14 is a representation illustrating the contents of the instructions for combining volume curves defined by a and;
Fig. 15 is a musical sound wave defined by the addresses of the blocks defined by a and ss;
Fig. 16 illustrates the program definition section of FIG. 7A waveform
Fig. 17 shows the output addition values used throughout the circuit shown in FIG. 7C;
Fig. 18 is a time-dependent graph illustrating the operation of the counter for counting the number of cycles of FIG. 7A;
Fig. 19 represents the basic relation between the number of cycles and the value of the working cycle of FIG. 7B
Fig. 20 illustrates the modes of definition of the modes a and B of a period
Fig. 21 is a representation for explaining in detail the operation of the instrument of the present invention with respect to mode a and mode ss;
Figs. 22, 23 and 24 illustrate waveforms for illustrating the operation of the tremolo control of the present invention.
Figs. 25A and 25B illustrate waveforms for representing the operation of the tremolo control of a pinched chord
Fig. 26 is a diagram for illustrating the relative positions of Figs. 27A and 27B;
Figs. 27A and 27B illustrate a circuit diagram of an example of a real control section for controlling the circuitry shown in FIGS. 7A, 7B, 7C and 7D.
Figs. 28A and 28B are time-dependent graphs showing the operation corresponding to the duet, the quartet and the like with respect to the circuit illustrated in FIG. 27A
Figs. 29A and 29B are time-based graphs illustrating the relationship between the time-dependent programming of the input of the execution keys and a synchronization signal
Fig. Illustrates the operation of selecting the clock pulse from a plurality of clock pulse generating circuits;
Fig. 31 is a time-dependent graph for explaining the operation of the vibrato control of the invention;
Fig. 32 is a graph of volume envelopes representing variations with respect to the time flow during the attack;
Fig. 33-illustrates the variations of volume envelopes with respect to the flow of time during damping; and,
Fig. 34 illustrates the modification of the volume with respect to the passage of time during extinction.

 The principle of an electronic musical instrument according to the invention will first be explained with reference to Figure 1 which illustrates, in the form of a block diagram, the overall system of the instrument.

 In the figure, an input code register of the height 1 stores the corresponding height input codes generated during the depression of the execution keys (not shown) among the 48 height keys, which allows example a basic range of four octaves each of 12 notes. The input code of the pitch of the sound recorded in the register 1 is applied to a period adjustment circuit of the note 2 to control the clock frequency of the note.

Upon receipt of the sound pitch input code, the tuning circuit 2 produces a note clock frequency signal corresponding to the input code of the pitch of the applied sound which, in turn, is applied as a signal. of counting to a counting circuit of the period of the waveform 3 which counts the period of a basic cycle of the musical sound waveform during a plurality of counting steps.A binary counter is preferable as counting circuit 3 of the period.
The period counter 3 used in this example is constituted by 8 bit positions each having the weight "1", "2", "4", "8", "16", "32", "64", and "128". "and can count" 256 "decimal numbers ranging from troll to" 255 ". The use of such a counter allows a basic cycle of the musical sound wave to be expressed by 256 count steps corresponding to 256 counts of the note. Counting steps of "256" are grouped together in m blocks each having one or more counting stages. In this example m = 16, which means that a cycle of the musical sound is divided into 16 blocks. Each block is expressed by "16" counting stages (corresponding to the decimal numbers "0" to "15"). the count values of the period counting circuit 3 which are represented by 4-digit binary codes having weights of "16", "32", "64", "128" can be assigned to "16" step blocks in time, block addresses, as shown in Table 1.

Table 1

<tb><SEP> Tenants <SEP><SEP><SEP><SEP> Tenets <SEP><SEP> Addresses <SEP> Addresses
<tb> of <SEP> count <SEP> of <SEP><SEP> of <SEP> blocks <SEP> of <SEP> count <SEP> of <SEP><SEP> of <SEP> blocks
<tb> period <SEP> period
<tb><SEP> 16 <SEP> 32 <SEP> 64 <SEP> 128 <SEP> 16 <SEP> 32 <SEP> 64 <SEP> 128
<tb><SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 8
<tb><SEP> 1000 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 1 <SEP> 9
<tb><SEP> 0 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 2 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 10
<tb><SEP> 1 <SEP> 1 <SEP> 0 <SEP> 0 <SEP> 3 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 11
<tb><SEP> 0 <SEP> 0 <SEP> 1 <SEP> 0 <SEP> 4 <SEP> 0 <SEP> 0 <SEP> 01 <SEP> 1 <SEP> 12
<tb><SEP> 1010 <SEP> 5 <SEP> 1 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 13
<tb><SEP> O <SEP> i <SEP> i <SEP> O <SEP> 6 <SEP> 0 <SEP> 1 <SEP> 1 <SEP> 1 <SEP> 14
<tb><SEP> 1 <SEP> 1 <SEP> 1 <SEP> 0 <SEP> 7 <SEP> 1 <SEP> i <SEP> 1 <SEP> 1 <SEP> 15
<Tb>
The 8-bit outputs from the respective stages of the period counting circuit 3 are applied to the timing circuit 2 of the note to control the frequency of the frequency clock signal of the note corresponding to the input code. The four upper bit positions (having the weights "16", "32", "64" and 11l2811) of the counting circuit 3 of the period are applied as an address signal. of the block, among the 16 blocks, to a section 5 for defining the program of the waveform for each block, via a decoder 4. The section 5 for defining the program of the waveform is represented by 0 "to" 15 of a musical sound waveform cycle. The amount of modification (of absolute value "0", "1", "2", or "4" in this example) of the amplitude of the rising or falling waveform in each block address is expressed by a digit with a sign "+" (amount) or F (descending) applied to it. The amount of the change (differential value) of the amplitude is called differential coefficient. The signals representing a differential coefficient and llull or which are defined for each block address by the program definition section 5 of the waveform, are successively output in synchronism with a block address signal transferred from the decoder 4 for transmission to a multiplier circuit 6. The multiplier circuit 6 is supplied with a control quantity (counter count) from a volume curve forming counter 7 (called envelope counter 7) to execute numerically a volume control to increase or decrease the volume of the execution with the passage of time from the depression of an execution key.Thus, the multiplication circuit 6 multiplies the differential coefficient from section 5 defining the program of the waveform by the control quantity in accordance with the designation of "+" or "-" and in synchronism with the address of the block. The envelope counter 7 counts or counts a definition clock pulse (referred to as an envelope clock pulse) along a volume control curve having leading, damping and attenuation sections which will be described below. after in agreement with the selected one of the different modes of volume curves (called envelopes) which will also be described later.The content of the envelope counter 7 is constituted by an integer whose value goes from "0" to "31 "and all these contents are called envelope coefficient (represented by E). An example of the envelope mode is shown in Figure 2.

 The differential coefficient previously defined for each block address by the program definition section 5 of the waveform is represented by an integer number of times the corresponding envelope coefficient E illustrated in FIG. 2, to which the symbols are attached. "+" or "-".

For this reason, the multiplication circuit 6 executes the operation + or the operation - (differential coefficient x envelope coefficient E). An example of this is illustrated schematically in FIG. 3. As shown, the relationship between the value of the envelope coefficient E and the differential values of the blocks at block addresses 0 "a" 15 "during a period of the musical sound waveform.

The relative amplitudes of the musical sound waveforms including the volume control values at times when the values of the envelope coefficient E in the envelope mode shown in Fig. 2 are "5", "10", "20", and "30" vary correspondingly as illustrated in Figures 4A, 4B and 4C. These moments correspond to the points indicated by the symbols x in FIG. 2. The relative variation of the musical sound waveform naturally changes later with the envelope coefficient value E which also changes with time. In this example, it is only in the block address "0" that no designation of the differential coefficient, "+" and "-", is made and the relative variation of the musical sound waveform is always zero.

 The output signal of the multiplier circuit 6 is applied to one of the input sides of an adder 8 whose output signal is fed back to the other input side of the adder 8 via a accumulator 9.

With this circuit connection, a quantity of variation which is the output value of the multiplier of the block in question is added to the output value of the multiplier of the previous block. The musical sound waveforms shown in FIG. 3 and FIGS. 4A, 4B and 4C are taken from the accumulator 9. The output signal of the accumulator 9 is applied by a digital-to-analog converter (DA) to a speaker 11 which, in turn, emits a sound with the pitch of its corresponding to the executed execution key.

 Before going into the detailed description of the present invention the logical symbols used in the description of the invention to be made hereinafter will first be presented in FIGS. 5A, 5B, 5C, 5D and 5E in which are represented logical formulas, true value tables, general logic symbols, and combined circuits. It may be noted here that the inverter symbols attached to the input lines of the OR gates and AND gates are effective only for gates to which such symbols are attached. For more details on this subject, reference will be made to the combined circuits in the respective drawings concerned.

 Fig. 6 shows the overall arrangement of the drawings of Figs. 7A, 7B, 7C and 7D. In Fig. 7A, a note code register designated by the reference numeral 20 has 4-bit input terminals (with weights "1", "2", "4", "8") and 8 memories. in line allowing the 4 bit positions to be shifted in parallel in the direction of the arrow. The octave code register 21 has input terminals with two bit positions (of weight "1" and "2") and 8 on-line memories allowing the two bit positions to be shifted in parallel in the direction of the arrow.

These registers store note entry codes and octave input codes provided by the executed execution keys. More specifically, in synchronism with the generation of an input instruction signal corresponding to the action on an execution key which will be described hereinafter, the note input code and the code Corresponding octave input signals are input into the note code register 20 and the octave code register 21 by AND gates 22 to 27, OR gates 28-1 to 28-4 and OR gates 29 and 30. The note code and the octave code (which is referred to as the pitch code of the sound) are shifted successively and in parallel in the direction of the arrow in response to an offset pulse +0 (a clock pulse of the present system) .After 8 offset times +0, these codes are returned to the corresponding registers by inhibition gates 31-1 to 31-4 and 32 and 33. In this way, these codes are submitted to a so-called dynamic shift operation In synchronism with a new input indication signal, these gate Inhibition s 31-1 to 31-4 and 32 to 33 are closed so that note pitch codes stored in respective registers 20 and 21 are erased.

 As described above, the note code register 20 and the octave code register 21 each have 8 on-line memories. Accordingly, if 8 different execution keys are depressed simultaneously, these registers accept the note input codes and the corresponding octave input codes with appropriate synchronizations in synchronism with the input instruction signal and enable dynamic shift recirculation of these codes. This means that eight sounds are controlled according to a time-sharing method. The note code and the octave code in this system are shown in Tables 2 and 3.

Table 2
Name of the note Code of the note
8421
Do 1 1 1 1
Re 1 1 1 0
Mi l O 1 1
Mi 1 0 1 0
Fat "1 0 0 1
Fa 1 0 0 0
Sol O 1 1 1
Sol O 1 1 0
O 0 1 1
If oo 1 o
If o 0 0 1
Dot O 0 0 0
Table 3
Octave Order Octave Code
2 1
OO
02 OO
02 0 l
03 l 0
04 1 1
A count register of the period period 34 counts a cycle of a musical sound wave according to the pitch codes of its stored by recirculation in the registers 20 and 21. In the same way as the registers 20 and 21, the counting register of the period 34 is provided with 8 on-line memories to perform the successive dynamic shift by an offset pulse +0 in the direction of the arrow.The register 34 is constituted by a block count register 34-1, a synchronization count register (TC register) 34-2 and a cycle number register 34-3. In order to divide a cycle of a musical sound wave into "16" blocks according
time, the register 34-1 is of the hexadecimal type with four bit positions (corresponding to block addresses ds "16" blocks ranging from "0" to "15" shown in Table 1) to store the address of each block The timing counter register (TC register) 34-2 is of the hexadecimal type with four bit positions for controlling the number of count steps for each block, which will be described in detail, so as to produce a synchronization signal of summation for
control the clock counting. The cycle number register 34-3 is of the eight bit type with three bit positions which acts on each cycle of the block count register 34-1.

The counting content of each on-line memory generated from each output of the cycle number register 34-3 passes directly through the program definition unit of the waveform for each block which will be described below. after and is recirculated in an adder 36 shown in FIG. 7B through recirculation gates such as inhibition gates 37-1 to 37-7. In the recirculation cycle, the adder 36 which operates in the binary mode, is subjected to a counting step of "+1" upon generation of an addition timing signal mentioned above.

The four bit position output (weight "1", "2", "4", and "8") (see FIG. 8A) is applied to a state detection circuit of the block 38 to detect a block address. The circuit 38 produces from the output an address signal "0" shown in FIG. 8B and from the outputs 01, 0, Q3, and z, the signals are obtained from the output of the "16" block addresses. 8C The output signals (1) to (4) are applied to a note pitch matrix circuit 39 to determine a pitch correction number for each note, to which reference will be made herein. After the output signal from the output (h) is an address signal of the block Q under the condition "1,2,4,8" in which the weights "1", "2", "4" , "8" are all "0" with a serial connection of a reverse AND gate 38-1 and inhibition gates 38-2 and 38-3 The output signal from the output 0 is taken directly from the circuit 38 and is an odd-numbered block address signal Output (2) provides block address signals "2", "6", "10", and "14" through an inhibit gate 38-4 with a condition "1.2" in which the weight "1" is "O" and the weight "2" is "1" .The output (i) provides the block address signals "4" and "12" with a serial connection of inhibition gates 38-5 and 38-6 to satisfy the condition "4.2.i" in which the weight of "4" is "1" and the weights of "2" and "1" are both "0 ". The output (i) provides the block address signal "8" with a serial connection of the inhibit gates 38-7 to 9 to satisfy the condition "8 4 2 1" in which the weight of "8" is " 1 "and the weights of" 4 "," 2 "and" 1 "are" 0 ".

 The outputs of the four bit positions of the sync count register (TC register) 34-2 are coupled with the input of an adder 40. The outputs with five respective bit positions of the adder 40 are coupled with a subtracter 41 The four bit positions of the subtractor 41 are returned to the corresponding inputs by recirculation control gates such as the inhibit gates -42-1 to 42-4. The outputs of the timing count register 34-2 are coupled with the addition timing generator 43 which provides the addition timing signal to the adder 36 in accordance with the respective octaves. The three binary positions of weights "1," 2 "and" 4 "of the register 34-2 are applied to a weight shift circuit 44. In the generator circuit of the addition timing 43 and the shift circuit of the weight 44 are applied the output signals of an octave decoder 45 which produces the first to fourth octave signals (O1 to 4) as a function of the state of the outputs of the two bit positions transmitted from the register Specifically, an AND gate 45-1 of the octave decoder 45 generates a first octave signal when it detects the state of the code shown in Table 3. Similarly, the gate Inhibition 45 = 2 produces a second octave signal 02, the disable gate 45-3, a third octave signal 03 and the AND gate 45-4, a fourth octave signal 04O. octaves l 1 03 are fed to the AND gates 43-1 to 43-3, the octave signal 0> 2 to a p andte 44-1 of the weight shift circuit 44; the octave signal 03 at the AND gates 44-2 and 44-3 the octave signal 04 at the AND gates 44-4 to 44-6.The output signals of weight "l", 2 "," 4 "from synchronization count register 34-2 are supplied to the AND gate 43-1 of the addition timing synchronization circuit 43 by the OR gates 43-4 and 43-5 The output signal of weight "2" and 11411 derivative of the OR gate 43-4 is applied to the AND gate 43-2, the weight output signal 11811 is coupled to the AND gate 43-3.

The outputs of these AND gates are coupled with the inhibit gates 43-6 and 43-7 and an AND gate 43-8. The weight output signal "8" is additionally applied to the door
AND inverted 43-8. The output of the AND gate 43-8 is coupled to the inhibit gate 43-7 whose output is connected in series to the inhibit gate 43-6. The addition timing signal is derived based on the output of the inhibit gate 43-6. As seen from the drawing illustrating a count state (FIG. 9a) of the count register 34-2. in FIG. 9, the output signals shown in FIG. 9b delivered on the output lines (a), (b) and (c) in the circuit 43 generating the addition synchronization are removed. in the form of the signals illustrated in FIG. 9C in synchronism with the generation of the octave signals O1 to 04 from the octave code decoder 45. Specifically, the addition timing signal is generated from the signal generator addition synchronization circuit 43 only when the synchronization count register 34-2 gives "0" for the first octave signal 01, only when it counts "0" and I for the second octave signal 02, only when he counts "0" to "3" for the third octave signal 03 and only when it counts NOII at "7" for the fourth octave signal 04. The addition timing signal thus obtained is applied as an addition control signal "+8" to the adder 40 and acts as a gate release signal on the AND gates 46-1 to 46-4 ', as an addition control signal "+1" on the adder 36 shown in Fig. 7B-.

 The octave signals 1 to 04 transmitted from the octave code decoder 45 are applied as control signals "-1", "-2", "-4" and "-8i" to the subtractor 41 shown in FIG. FIG. 7B by the circuit 43 generating the addition synchronization Thus, in the recirculation loop comprising the synchronization count register 34-2 <the adder 40, <the subtractor 41 e the synchronization count register 34- 2, the adder 40 adds "+8" to the contents of the timing count register 34-2, in synchronism with the addition timing signal. The result of the addition is subtracted a value ("-1" for the octave signal Oii "-2" for the octave signal 02, "-4" for the octave signal 03 and "-8" for the octave signal 04) in agreement with the octave signals 0 to 04. A pitch correction number is fed to the adder 40, a number corresponding to the note from the AND gates 46-1 to 46-4 which are open in synchronism with the generation of the addition timing signal from the pitch step matrix circuit 39 in accordance with the block count state of the block count register 34-1.

Namely, the cycle of a musical sound wave is constituted by "16" blocks with respect to time and each block address is constituted by clock pulses (more than eight times the basic clock period) which corresponds to eight times or plus the base clock pulse 0.. A single basic pulse corresponds to one step of the musical sound wave and therefore each clock address has eight steps or more. When each of the addresses of the "16" blocks of a cycle of the musical sound wave has 8 steps and when a total of 128 steps is included in a cycle, the total number of steps corresponds to the highest pitch in this system (in fact, 130 steps corresponds to the highest note (Do *) in this system, as will be seen from the description which will be given below). By increasing the number of steps between the adjacent notes from the highest note pitch to the lower note pitch of an octave, so as to have the relation l2 2 between them, the period of the wave becomes more large in accordance with the note, so that a rave sound is obtained.The number of step correction for the adjustment of the period according to the note is calculated in the note step matrix circuit 39.

The note pitch matrix circuit shown in FIG. 7B stores a control value at the base for period control based on the note in the form of coarse and fine numbers, whereupon a setting value of the period by the positive count sign (+) in the period counting register 34. The circuit 39 is supplied with output signals from the outputs O1, 2, 3, and 4 of the circuit 38 for detecting the state of the block and the four-bit output of the note code register 20. The note step matrix circuit 39 has an AND function circuit 39-1 for detecting the code states of the twelve notes shown in Table 2. The circuit 39 -1 is provided with output lines ei to 0 (from the line detecting the note Do to the line detecting the note Do * represented in the drawing) corresponding to the notes. These output lines are coupled with AND gates 39-4 to 39-14 through a first OR function matrix circuit 39-2 and a second OR function matrix circuit 39-3. The first function matrix circuit
OR 39-2 produces a code addition number, by the output lines X1 to X3 to control the fine numbers "0, 0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7 ", in the order from C to C * for each note. The step addition number is added to each of the "16" blocks as shown in Table 4.

Table 4
Note Release Code Added Digit
in the not
Xl X2 X3
1 Do OOO 0
2 re 0 0 0 0
3 Mi 1 0 0 1
4 Mi l O 0 1
5 Fat O 1 0 2
6 Fa ol 0 2
7 Solt 1 l 0 3
8 Sol O 0 1 4
9 The 1 0 1 5
10 If 1 0 1 5
11 If O 1 1 6
12 Dot 1 l 1 7
The second OR function matrix circuit 39-3 is used to apply a pitch correction addition value, in agreement with the coarse number, to the respective note in a cycle of the musical sound wave. In this case, in order to uniformly apply the step correction addition number with the block address synchronization, the output signals derived from the outputs 1 to 4 of the block state detection circuit 38 are selected in accordance with the notes. respective ones and the block addresses with the "0" marks are chosen according to the note, as illustrated in Figure 8D. These addresses of several selected blocks serve as control timing for the coarse number. The selected signal is applied to the AND gates 39-4 to 39-14 in accordance with the note. The outputs of the AND gates 39-4 to 39-14 are coupled with the series circuit of OR gates 39-15 to 39-25, and the output line X4 of the final OR gate 39-25 provides for each note a correction signal "+ 1" at the block address selected from addresses n1 "to" l5 ". In other words, the number of pitch correction issued from the matrix circuit of the note pitch 39 becomes a control value of the period (digit to be added to the step to control the end number + digit to be added to the step in accordance with the coarse number) the signal output signal from the output lines X11 Xz, X3 and X4 of the note pitch matrix circuit 39 is applied to the inhibit gates 47-1 to 47-4 which are made conductive at a time other than the signal generation. block address to 'I transmitted through the output lines X1, X2, X3 and X4 of the pitch matrix circuit 39 The output signals p Inhibition gates 47-1 through 47-3 are respectively applied through the OR gates 48-1 to 48-3 to the gates 46-2 through 46-4 to the output signal from the gated gate. 47-4 inhibition is coupled to the AND gate 46-1.

Accordingly, at a time other than the generation of the block address signal 1101, the step-change number for each block address and the step-correction addition number by which "+ 1" is applied to the selected block address, together with "+8", are applied as addition signals to the adder 40, in synchronism with the generation of the addition timing signal. block "0" transmitted from the block address status detection circuit 38, a correction value "+2" is applied through the OR gate 48-4 and the AND gate 46-2 at the gate. adder 40 and is added in synchronism with the generation of the add sync signal together with the addition "+8". Consequently, the addition value per note, for each address, supplied to the adder 40 is the highest octave (the fourth octave signal 04) as illustrated in FIG. 10, and this value corresponds to the number step (number of base clock pulses) in each block address. The step number of a cycle of the musical sound wave of each note is shown in the right-hand column of Figure 10.

As illustrated, the step numbers of two adjacent notes have the relation l2f2 between them. Naturally, different add-on synchronizations supplied to the adder 40 are used for the respective octave signals 01 to 04, and the value subtracted in the subtractor 41 is also different for octave signals 1 to 04. When the octave becomes lower (in the direction of the octave signal 01), the period of one cycle of the musical sound wave becomes longer
The count register of the period 34, the codebook register 20, the octave code register 21, are each provided with eight on-line memories. An operation cycle in the direction of the arrow of each register is completed for eight offset pulses 0. For this, the waveform of the sound is controlled on the basis of this single circulation. Since the system of the invention uses a shift memory which will be described hereinafter, it is possible to control the waveforms in a position suitable for the flow of the register.

More specifically, the system is provided with eight on-line memories in the direction of the arrow at the output of the sound production stage (preceding a digital / analog conversion circuit) illustrated in FIG. 7C and with a memory The shift memory 49 is designed such that one of the eight on-line memories is addressed by the code expressed by three binary digits (of weight "1", " 2 "," 4 ") transmitted from the weight shift circuit 44 in FIG. 7A The addresses 11011 to" 7 "are assigned to the on-line memories such that the" 0 "address is assigned to the memory in line closest to the output side of the shift memory 49 and the address "7" to the line memory furthest from the output side. By this address designation, an offset delay of up to 8 ti0 is possible.

The address of the shift memory 49 is specified only when the addition timing signal sent from the addition timing generator circuit 43 is applied through the AND gates 50 and 51 shown in Fig. 7C.

The output signal of the AND gate 51 applied to the shift memory 49 is called the permission signal.

The weight signal "1" from timing count register 34-2 is applied to AND gates 44-1, 44-3 and 44-6 in the weight shift circuit 44 shown in FIG. 7A, the output of FIG. weight "4" at AND gate 44-4, weight output "2" at AND gates 44-2 and 44-5. The AND gate 44-6 is coupled with the output line Y1, the AND gates 44-3 and 44-5 at the output line Y2 through the OR gate 44-7, the AND gates 44-2 and 44 -4 to the Y4 exit line through the door
OR 44-9 to which the output signals of the OR gate 44-8 and the AND gate 44-1 are applied. Thus, three-bit outputs fed through the output lines Y1, Y2 and Y4 are fed as address designation code to the shift memory 49. The output signal from the timing count register 34-2 becomes the address designation signal shown in Table 5 as a function of the octave signals O to 04. As will be described hereinafter, the output signal from the adder 52 is shifted upward by the impulse # 0 by the addressed line memory and is extracted from the shift memory 49.

Table 5
Register output Address designation of the memory
counting offset synchronization O 4 03 2 1
l 2 4 8 l 2 4 l 2 4 l 2 4 l 2 4 0 0 0 0 0 0 0 0 0 0 0 OQO 0 0 0 0 0 0 0 0 0 0 0
11000 1 1 0 0 2 0 1 0 4 0 0 1
20100 2 0 l 0 4 0 0 l OOOO
31100 3 ll 0 6 0 ll 4 0 0 l
40010 4 0 0 l OOOOOOOO 51010 5 l O l 2 0 l 0 4 0 0 l
60110 6 0 ll 4 OO l OOOO
7 lll 0 7 lll 6 0 ll 4 OO l
8 0 0 0 1 0 0 OOO 0 0 O 0 0 0 0
9 1 O 0 1 1 1 0 0 2 0 l 0 4 0 0 1
10 0 1 O 1 2 0 1 0 4 0 0 1 OOOO
He 1 l O 1 3 l 1 0 6 0 ll 4 0 0 1
12 0 0 1 1 4 0 0 1 OOOOOOOO
13 1 O 1 1 5 1 0 1 2 0 1 0 4 0 0 1
14 0 1 1 1 6 0 1 1 4 0 0 1 OOOO
15 1 l 1 1 7 1 l- l 6 0 1 1 4 0 0 0 0 0 0 0
As described above, a cycle of the musical sound wave for each note is cut into steps each corresponding to a basic clock pulse "0, with a different number of steps for the respective notes." For a better understanding of the formation of the period for each note, the operation will be described with reference to FIG. 11A.

The operation shown in FIG. 1IA relates to a case in which the highest octave is 04 and the name of the note "C". At the moment when the period counting register 34 is in the 0 "initial state, the addition timing signal is generated from the summing timing generator circuit 43. Accordingly, in synchronism with the signal of block address "0" produced from the block state detection circuit 38, the correction value "+2" together with the "+8" addition command is applied to the adder 40 and then the addition (0 + 10) is carried out in the adder 40.

In the subtractor 41 "-8" is subtracted from the summation value "10 in response to the fourth octave signal 04. The output value" 2 "of the subtraction is fed back to the synchronization register 34-2. The addition timing signal is fed as an add command "+1" to the adder 36 and as a permission signal to the shift memory 49 shown in Fig. 7C. The shift memory 49 is "0." Under this condition, the line memory "0" of the shift memory 49 is, in an output synchronization state, ready to allow the output value of the adder 52 to change. as follows: After the shift period 8 + or the synchronization register 34-2 produces "2" and the block count register 34-1 produces 1 (see FIGS. 11A, 11B and 11E). at this time, the output signal from the block count register 34-1 is 1 so that the signal of 0 of the block state detection circuit 38 is supplied to the matrix circuit of the note pitch 39. In the case of the note "C", the matrix circuit 39 produces no output signal and thus no value of step correction is applied to the adder 40. Only the "+8" command is applied to the adder 40, in synchronism with the addition timing signal with the result that the addition (2 + 8) is performed in this one. In addition, the subtractor 41 performs a subtraction "-8" and finally the value resulting from the subtraction "2" is fed back to the timing counter 34-2. In synchronism with the addition timing signal, a "+ 1" signal is applied to the adder 36 and the summation value "2" is fed back to the block count register 34-1.

The addition timing signal is applied as an open signal to the shift memory 49 and the output value "2" from the timing count register (TC) 34-2 is supplied to the shift circuit. Accordingly, a signal 1 is extracted through the output line Y2. As can be seen from Table 5, this designates the address "2" of the shift memory 49. As a result, the output synchronization signal of the block address "1" has come out of the shift memory 49, being shifted by a lag time 2tot as seen from (i) of Figure 11A. Namely, when the block addresses are "O" and "1", the space between them is divided into ten steps. Then, a similar operation is repeated. In the case of the note "C" the addresses of adjacent blocks are spaced eight steps apart and, as shown in FIG. 10, a cycle of the musical sound wave comprises 130 steps. the operations for the "If" notes and for the fourth octave signal 04 are illustrated in FIGS. 11B and 11C, similarly to the diagram of FIG. 11A.

 The details of the shift memory 49 and the adder 52 shown in Fig. 7C are illustrated in Fig. 12. References 49-1 to 49-8 designate eight in-line memories (memories 49-4 to 49). -7 are omitted in the drawing), each of ten bit positions. These in-line memories are shifted by the basic clock signal Z or input control circuits 49-9 to 49-16 are provided on the input sides of line memories 49-1 to 49-8. In the drawing, only a gate circuit for a bit position is illustrated for the purpose of simplification. In fact, similar gates are used for all remaining bit positions. A three-bit address designation signal provided by lines Y1, Y2 and Y4 from the weight shift circuit 44 shown in FIG. 7A is applied to the decoder 49-17 of the shift memory 49 when the addresses "0" to "7" are specified. Online memories 49-1 to 49-8 are assigned correspondingly to addresses "O" to "7" respectively.

The address designation signals "0" to "7" are applied to the AND gates 49-18 to 49-25 to which an opening signal is applied, the outputs of these gates are coupled with the input control circuits 49-9. 49-16 The circuits of.

input control 49-9 to 49-16 allow the output from adder 52 to enter the specified line memory and cause the signal to be shifted into it. The output signal from on-line memory 49-1 is applied to a digital-to-analog converter (see FIG. 1) via an output adder 49-26 and a trigger circuit 49. 27. The output signal from the trigger circuit 49-27 is recirculated through the output adder 49-26 so that it is accumulated. The output signal from the line memory immediately preceding the output from the outputs specified in-line memories 49-1 to 49-8 is applied to the corresponding weight stage of the adder 52 via the OR gate 49-28 (illustrated only for a binary position)
A sync adjustment register 53 shown in Fig. 7A is constituted by eight in-line memories, each at a bit position, connected in series. An envelope register 54 is constituted by eight in-line memories which are connected in parallel in the direction of the arrow and each is in the form of a line memory with 7 bit positions (having weights of "1", " 2 "," 4 "," 8 "," 16 "," 32 "and" 64 "). During operation, the two registers 53, 54 are offset in the direction of the arrow in synchronism with the pulse of offset 0. The note code register 20, the octave code register 21, the count register of the period 34, the timing adjustment register 53 and the envelope register 54 are made to correspond to the memories online. For the pitch code from the octave code register 21 and the note code register 20, the control output signals corresponding thereto are generated from the period count register 54, the register. The envelope coefficient is indicated by 32 count values from "0" to "31" which are expressed by five bit positions with the weights "1", "2" and "2". "," 4 "," 8 "and" 16 "from the envelope register 54. Two weight positions" 32 "and" 64 "indicate four states of the envelope, namely the attack, the damping, attenuation and erasure.

Thus, the outputs on the seven-bit output stages of the envelope register 54 are applied to the corresponding weight input terminals of the adder 55. The outputs of the respective bit positions from the adder 55 to count the value of. control of the envelope in the adder 55 are applied so as to flow to the input terminals "1", "2", "4", "8" and "16" of the envelope register 54 by the inhibition gates 56-1 to 56-5 to inhibit the output when a carry signal from the adder 55-1 appears, respectively. The carry signal output from the adder 55-1 is applied to the terminal-d. the input of the report of an adder 55-3 for counting the state, through the inhibition gate 55-2 driven by the output signal from the inverted AND gate 57 which detects the erasure state "00" by the state detection weights 113211, "64" of the envelope register 54. In other words, the adder 55-3 accepts the carry output signal when the state of the envelope is in states other than that of erasure. The output signal of the adder 55-3 is held in circulation on the weight input terminals "32", "64" of the envelope register 54 by the inhibition gates 58-1 and 58-2. The indication signal of the input of the execution key shown in FIG. 7A is supplied to the input side of the weight stage "32" of the envelope register 54 via the OR gate 59 of FIG. so that when the input indication signal is produced, the state of the envelope immediately becomes the state of attack. The relationship between the state of the envelope and the code state of the "32" and "64" weight stages of the two bit positions is shown in tabular form in Table 6.

Table 6

<tb> Weight <SEP> Status <SEP> of <SEP> Envelope
<tb> 32 <SEP>: <SEP> 64
<tb><SEP> 0 <SEP> 0 <SEP><SEP> key released <SEP> erase
<tb><SEP> 1 <SEP>: <SEP> o <SEP> Attack
<tb><SEP> O <SEP> | <SEP> l <SEP> 1 <SEP> Depreciation
<tb><SEP> 1 <SEP> s <SEP> 1 <SEP> Attenuation
<Tb>
The output signal from the timing adjustment register 53 shown in FIG. 7A is applied to one of the input terminals of each port 60 and 61.

The other input terminal of the AND gate 60 is connected in receiving relation of the output of the AND gate 62 to obtain the logical product of the block address signal 1g0ll and the addition synchronization signal transmitted from the addition synchronization generator 43. The synchronization adjustment register 53 is set by applying on the input side thereof the clock signal (designated as envelope clock) produced from the inhibit gate 63 which will be described below through the OR gates 64 and 65. The inhibit gate 63 is powered with the output signal from a series connection of the gating gates 66-1 to 66-5 to detect the state at all. "0" of the envelope register 54 and the AND gate 66-6. For this, in the all state 101, the envelope clock pulse can not pass through the inhibit gate 63. When a signal "1" is set in the synchronization adjustment register 5 3, the AND gate 60 is made conductive in synchronism with the block addition timing signal "0" from the AND gate 62. Then, the addition timing signal is output to the adder 55 while at the same time the output of the inhibition gate 61 is inhibited. As a result, a "0" signal is loaded into the timing adjustment register 53 to release the tilted state thereof. The addition timing signal transmitted from the AND gate 60 is applied as a signal. door opening to AND gates 67-l to 67-5, which allows the passage of an adition value to the adder 55 for the envelope which will be described below. As a result, the envelope shifts over time in attack, damping, and attenuation states. That is, the sync adjustment register 53 is used to synchronize the summation value applied to the adder 55 for the wrapped with the block address "0" of the musical sound waveform. When the output of the synchronization register 53 is "0" and the envelope register 54 is in the "0" state, the inhibition gate 68 produces a reset signal which will be described below. The five bit weight signals "1", "2", "4", "8" and "16" produced from the envelope register 54 are respectively applied to the exclusive OR gates 69-1 to 69. 5 of the weight shift register 69.

 The switches S1 to S6 shown in Fig. 7C are used to define the types of individual volume curves a and ss. The group of switches S1, S3 and indicates the attack (A), the damping (D) and the attenuation (R) on the volume curve a. The group of switches S2, S4 and S6 indicates the states A, D and R of the volume curve ss. As shown in Figure 13, three switches can indicate seven types of volume curves. In this example, two types of volume curves can be selected simultaneously.

One type is called a volume curve a (selected by the switches S1, S3 and Sg) and the other type is called the ss volume curve (selected by the switches S2, S4 and S67) The combinations of these curves a and ss as illustrated in Fig. 14. As described with reference to Figs. 1 to 3, the program definition unit of the waveform 35 shown in Fig. 7A designates a period of a musical sound wave as a value. of the differential officer with "+" (ascending) or "-" (descending) of the rise of the wave or the descent of the wave for each block address of a period. The unit of definition 35 can also define the types of the volume curve, curves a and ss by producing a signal "0" for the definition of a curve a and a signal "l" for the definition of a curve ss An example of the definition is represented in figure 15. As can be seen from the figure, the indicator indicates the value The differential coefficient is given by numbers "1", "2", "4" and the symbols "+" and "-" and the volume curve para and ss. The details of the waveform program definition unit 35 are illustrated in FIG. 16. As can be seen, switches A1 to A15 and B1 to B15 for specifying the absolute values "1", "2" and "4", switches C1 to C15 to specify the volume curves a and ss and switches D1 to
D15 to indicate "+" and "-" are provided for each block address "1" to "15", respectively. A line common to the respective switch groups for each block address is coupled with the block state detection signals having count values from "1" to "15" from the count register of block 34-1. The switches A1 to A15, B1 to B15 of each block produce three signals defining the values of the differential coefficient "1", "2", "4" via the decoders E1 to E15. The block address "0" is always set to the level "0" and therefore is not indicated by the switch and, in oenseauenoe, only the block addresses "1" to "15". are indicated by the switch. The control signal (-) indicated by the waveform program definition unit 35 for each address is applied to the adder 52 illustrated in FIG. 7C, the control signal of "1", "2", or "4" is applied to the weight shift circuits 69 represents in Figure 7B and the control signal ss is applied to the doors
OR exclusive 70 and 71 shown in Figure 7B. The control signal ss generally passes through the exclusive OR gate 70 to reach the inhibition gates 72-1 to 72-3 and the AND gates 72-4 to 72-6 in a control circuit 72 of the volume curve. / B. As a result, the AND gates 72-4 to 72-6 produce output signals in synchronism with a ss ("1") definition signal, the inhibition gates 72-1 to 72-3 produce an output signal of synchronism with a definition signal a ("0") in accordance with a or ss indicated selectively by the switches S1 to S. The outputs of the door of inhibi
6 tion 72-1 and the ET 72-4 door are coupled with the door
OR 72-7; the outputs of muting gate 72-2 and AND gate 72-5 with OR gate 72-8, outputs of muting gate 72-3 and AND gate 72-6 with gate OR 72-9.

The output of the OR gate 72-7 is applied to the AND gate 72-10, the inhibition gates 72-11 and 72-12 and the AND gate 72-13
The output of the OR gate 72-8 is connected to the AND gate 72-14 and the inhibition gate 72-12 and the output of the OR gate 72-9 is supplied to the AND gate 72-15. The exit of the door
ET 72-14 is applied to the inhibition gate 72-11 and the AND gate 72-13. The AND gate 72-10 and the inhibit gate 72-11 are connected to the OR gate 72-17 through the OR gate 72-16. The output of the inhibit gate 72-12 is connected by the AND gate 72-18 to an OR gate 72-19. The doors
AND 72-13 and 72-15 are connected to the OR gate 72-20. The OR gates 72-17 to 72-20 are connected in series and the output of the OR gate 72-17 is supplied to the AND gate 50. A detection signal from the envelope condition detection circuit 73 is coupled in a feed relationship with AND gates 72-10, 72-14, 72-15 and 72-18. Usually the door
AND inverted 73-1 detects an erase state "00" of the envelope, the inhibition gate 73-2, the state of attack, the inhibition gate 73-3, the stationary state and the ET 73-4 door the state of attenuation. The inhibition gate 73-2 is coupled with the AND gate 72-10, the inhibition gate 73-3 with the gates
And 72-14 and 72-18. The output signals from these gates serve as gate-open signals. The output signal from the AND gate 73-1 together with the all-O state signal (symbol-in Figure 7D) from the envelope register 54 is applied to the inhibition gate 73-5. The output signal from the inhibit gate 73-5, together with the output signal from the AND gate 73-4, is applied as a gate-open signal to the AND gate 73-15 via an OR gate 73-6.

As a result, the OR gate 72-16 in the volume curve control circuit 72 a / ss produces an output signal when the envelope is in the attack state and the volume curve is indicated by 4 to 7 as illustrated in FIG. 13 and when the first is in the stationary state, the second is indicated by (g and 03 in FIG. 13. The AND gate 72-18 produces a control signal "31" in the case of 4 in figure 13 which
indicates that there is no damping when the state of the envelope is the state of damping.lent and an indication of attack is given.The OR gate 72 produces a signal to indicate a value of complement which is the value of the inverted envelope coefficient in the case of 1, 3, 5, 6, 7, in Figure 13 which is a downward indication for the attenuating and attenuating states of the envelope. The door
OR 72-17 produces signals representing the attack (A), the damping (D) and the attenuation (R), only when these states are indicated by the corresponding switches. The addition timing signal is at this time produced as an opening signal to the shift memory 49.

The control signal "31" generated from the AND gate 72-18 is supplied to the OR gates 69-6 to 69-10 and the complementary control signal from the OR gate 72-20 is supplied by the exclusive OR gate 69-11 to the exclusive OR gates 69-1 to 69-5.

In the weight shift circuit 69, when the control signal "31" and the complementary control signal are not present, the value of the envelope coefficient weighted by "1", "2", "4", " 8 ", and" 16 "from the envelope register 54 passes through exclusive OR gates 69-1 to 69-5 and is subjected to a weight shift operation (in this case, the value of the differential coefficient + x value of the envelope coefficient E) as a function of the difference coefficient values indicated "1", "2", and "4" for each clock address indicated from the designation unit of the waveform program And the value of the multiplication is applied to the adder 52. A differential indication signal "1" of the differential coefficient is supplied to one of the input terminals of each of the AND gates 69-12 to 69. 16, an indication signal of "2" at one of the input terminals of each of the AND gates 69-17 to 69-21, an indication signal of e "4" at one of the input terminals of each AND gate 69-22 through 69-26. The other input terminal of each of the AND gates 69-12, 69-17 and 69-22 is supplied with a signal corresponding to the weight "1" of the value of the envelope coefficient. The other input terminal of each of the AND gates 69-13, 69-18 and 69-23 is supplied with a signal corresponding to the weight "2". The other input terminal of each of the AND gates 69-14, 69-19 and 69-24 receives a signal corresponding to the "4" weight. The signal corresponding to the weight "8" is applied to the other input terminal of each of the AND gates 69-15, 69-20 and 69-25.The signal corresponding to the weight "16" is applied to the other terminal of each of the AND gates 69-16, 69-21 and 69-26. As illustrated, the AND gate 69-12 is connected to the input terminal of weight "1" of the adder 52, the doors
AND 69-13 and 69-17 at the weight input terminal "2" through the door
OR 69-27, AND gates 69-14, 69-18 and 69-22 on the weight entry side "4" by OR gates 69-28 and 69-29, AND gates 69-15, 69-19 and 69-23 at the weight entry side "8" via OR gates 69-30 and 69-31, AND doors 69-16, 69-20 and 69-24 at the "16" weight entry OR gates 69-32 and 69-33, AND gates 69-21 and 69-25 at the weight side "32" via OR gate 69-34 and AND gate 69-26 at input side of weight "64".

With this connection, the weight shift circuit 69 produces the multiplication values shown in Fig. 17 as a function of the "1", "2" and "4" values of the differential coefficient. When the control circuit 72 of the volume curve a / ss produces a control signal "31" and supplies it to the OR gates 69-6 to 69-10, the value of the envelope coefficient must have "31" regardless of the output signal from the envelope register 54. When the complement control is applied to the exclusive OR gate 69-11, the envelope coefficient at five bit positions from the envelope register 54 is inverted and the multiplication shown in Figure 17 become the inverse values.

As can be seen from Figure 15, the difference from the case illustrated in Figures 3 and 4 is that the multiplication for each block address is performed in
function of a curve of volume a or ss, that is to say of the value of the differential coefficient + x by the value of the envelope coefficient E (E is Ea when it follows the curve of volume a and is Ess when it follows the volume curve ss). In this way, the multiplication value entered in the adder 52 is fed to the shift memory 49.

 Thus, by defining two curves of volume a and ss, the system can simultaneously define the waveforms of eut ss.

As a result, when the waveforms are different, the ups and downs of the volume curves can be modified so that a suitable combination of these curves provides a wide variety of synthesized musical sound waveforms. As a result, the variation over time of the harmonic structure of the waveform is remarkable for producing a musical sound wave with a rich timbre.

 As a result, the musical instrument thus constructed in accordance with the invention can produce a musical sound with the particular characteristics of the sound produced in particular by brass and strings.

 In FIG. 7B, the contactors S10, S11 and S12 are used to define period modes a and ss and the output signals of these contactors are fed to the period control circuit 74 (work cycle call). By the on and off states of these three contactors, a mode-defining signal represented by eight digits "0" to "7" is generated from the AND function matrix 74-1 through the output lines and is then entered into the OR function matrix 74-2.The three bit position output (with weights of "16", "32" and "64") from the cycle number register 34-3, shown in FIG. FIG. 7A, which is counted for each period of the waveform, is also sent to the work cycle control circuit 74. Depending on the counting state of the cycle, the reverse AND gate 74-3 produces the state the output state shown in Fig. 18 (a) having the condition (16g32 + 16-32-64), depending on the state of the AND gate 74-5, the inhibition gate 74-6 and the reverse AND gate 74-3.

The signal (16) of the cycle number register 34-3 shown in Fig. 18 (a) is fed to the inhibition gates 74-7 and 74-8. The output of the reverse AND gate 74-3 is fed to AND gates 74-9 and 74-10. The output of the OR gate 74-4 is fed to AND gates 74-11 and 74-12.

The basic relationship between the duty cycle and the cycle count state will be described with reference to Fig. 19. In the figure, 20te indicates a cycle with no output of a waveform and "1 "indicates a cycle with an output of a waveform. Working cycles "1", "1/2" and "1/4" mean that the output of the waveform is extracted every cycle, every two cycles and every four cycles. The operating cycle "1/3" is obtained by directly setting the counting state of the cycle to the counting state of cycle "6" without counting the cycles "4" and "5" .In the designation of the modes "6 "and" 7 "among these modes specified by the numbers" 0 "to" 7 "according to
combinations of the three bit positions of the period mode / ss mode contactors S10 to S12, the OR function matrix 74-2 produces an output signal
K1 which is applied, together with the weight output signal "64" from the adder 36, to the AND gate 74-13 whose output signal is supplied by the OR gate 74-14 to the "32" weight of the register 34-3 of the number of cycles. Thus, the count values of the states of the cycles "4" and "5 are skipped. The output K2 of the OR function matrix 74-2 is applied to the OR gate 74-15, the output K3 to the OR gate 74. 16, the output K4 to the OR gate 74-15 through the inhibition gate 74-5, the output K6 to the OR gate 74-17 through the AND gate 74-9 the output K5 is applied to the gate OR 74-16 through the inhibition gate 74-8, the output K7 at the gate 74-18 through the gate
ET 74-10; the output K8 is applied to the OR gate 74-19 by the AND gate 74-11; the output Kg is applied to the OR gate 74-20 by the AND gate 74-12. The OR gates 74-15, 74-17 and 7.4-19 are connected in series to produce an output X1 (a). OR gates 74-16, 74-18 and 74-20 are connected in series to produce an output X2 - (B). As a result, the output signals produced on the output lines X1 (a) and X2 (ss) correspond to the numbers "0" and "7" for the designation of the period mode a and B, as illustrated in FIG. As shown, the line X1 (a) provides a period M on the basis of the waveform by the designation a and the output line X2 (ss) provides a period N on the basis of the waveform. Therefore, in the period modes "0" to "S", the periods M and N are both integers, but in the period modes "6" and t 7, t if one of the work cycles M and N is an integer, the other is not an integer. The output signals X1 (a) and X2 (ss) are applied to the inhibit gate 75 and to the AND gate 76. Usually in synchronism with a designation signal a / ss derived from the exclusive OR gate 71, the inhibition gate 75 is made conductive for an indication signal ("0") and the gate
AND 76 is made conductive for a designation signal ss ("1"). These output signals pass through the inhibition gates 77 and 78 which will be described later and the OR gate 79 to reach the AND gate 51 shown in FIG. 7C.

 The contactor R1 is connected to the exclusive OR gate 71 and reverses by its implementation the designation signal a / B for each block address outputted from the program definition unit 35 of the form. waveform, with the result that the AND gate 76 produces an output signal in synchronism with the definition signal a and the inhibit gate 75 produces an output signal in synchronism with the definition signal B.

As a result, the output X1 becomes a work cycle ss and the output X2 a work cycle a. The contactor R2 is connected to the inhibition gates 80 and 81 to which are respectively provided a signal P which will be described later and its inverted signal P and it indicates if a and ss are separated or not. In operation, muting gates 80 and 81 produce no output and thus muting gates 77 and 78 produce signals X1 (a) and X2 (3) (when the contactor
R1 is actuated, the signals X1 (B.) and X2 (a) are extracted).

When the contactor R2 is not actuated, the inhibition gates 80 and 81 produce a signal P and a signal P (these signals are produced only in the definition of the duet execution) and the memory-line pair is designated by a and the odd line memory by ss. This is tabulated in FIG. 21. In preparing the table shown in FIG. 21, no designation is made by the contactor
R2 and a contactor R3 which will be described below. The indication of the non-separation by the contactor R2 is effective only for the dual execution. The contactor R3 is connected to the door
OR exclusive 70 and, when actuated, the a / B signal specified for each block by the waveform program designation unit is inverted. This means that the relations of a and ss are all reversed. In this way, the operation of an octave can be effected by the designation of the work cycle mode a and ss and the working cycle of the musical sound wave is changed and the tone can also be changed for each octave. Referring to the operation with non-separation a, ss shown in Fig. 21, in the case of a mode designation "6", a: ss is 1: 15 and ss is a lower sound of four major intervals than a. In the mode designation "7" it has a work cycle twice as long as that of a. We can conceive that the waveform of ss is a wave consisting of waves having periods 2/3 and twice that of of the wave a ss is a sound that includes a higher component of five major intervals at a and another lower component of an octave at a. The periods between the different waveforms can be controlled to be M: N. For this, the harmonic structures of these waves can be modified and moreover, when these waves with modified harmonic structures are combined, the structure in harmonics of the combined wave is further modified differently.

As a result, such a combined or composite wave exhibits an effective musical sound sensation with a more natural variation in time.

 In FIG. 7, the contactor T1 is a conventional tremolo designation contactor (called a flat tremolo). T2 is a touch tremolo designation contact by which a tremolo is applied only during the action on that contact.

To designate a key tremolo, the flat tremolo designation contactor is released The contactors T3, T4 and T5 indicate the depth (called amplitude) of the tremolo and give the maximum amplitude "1" (depth of 100%) , "1/2" (50%) and "1/4" (25%), respectively. The designation signal from the contactor T1 or T2 is applied to the AND gates 83-1 to 83-3 by the OR gate 82.As a result, an output indication signal with a specified amplitude is generated and applied to a control circuit. control of the tremolo 84. The ET outputs 83-1 and 88-3 are applied to the AND gate 84-3 and 84-4 via an OR gate 84-1 or 84-2. The output of the AND gate 83-2 is applied to the OR gate 84-6 and to the AND gate 84-7 through the AND gate 84-5 coupled to the "64" gate weight output of the gate. Accordingly, in the damping state and in the attenuating state the weight "16" of the envelope register 54 is always 111in. Furthermore, the output of the AND gate 84-8 for detecting the attenuation state is applied to the AND gate 84-3 whose output is extracted to the OR gate 84-10 via an inhibition gate 84-9 which is made conductive by a designation other than the mandolin designation. For this purpose, the inhibition gate 84-7 is not made conductive in the state of attenuation while the inhibition gate 84-11 is ready to lead. In the designation of the tremolo, the weight output "64 of the envelope register 54 is applied to the AND gate 84-4 and the output thereof always provides a signal "1" at the weight "64" of the envelope register 54 via the OR gate 84 -12. As a result, the state of the envelope does not become the erased state "00" but the damping state and the attenuation state are alternately repeated. The output of the AND gate 83-3 is applied to the OR gates 84-14 and 84-15 through an AND gate 84-13 to which the weight output "64" of the envelope register 54 is applied. and it is also applied to the inhibition gate 84-16. Like the inhibition gate 84-7, the inhibition gate 84-16 is not made conductive in the attenuation state while the inhibition gates 84-17 and 84-18 are made conductive. weight output "32" of the envelope register 54 is further applied to the inhibition gate 84-21, via the inhibition gate 84-20 coupled with the AND gate 84-19 which is effective only when the T6 tremolo cord contactor, which will be studied hereinafter, is actuated. Since the inhibit signal of the gate output from the AND gate 84-4 is applied to the inhibit gate 84-21, it is not made conductive by the tremolo indication and its output is always " O ". As a result, the envelope state detection circuit 73 produces only the damping state signal from the inhibit gate 73-3. In the tremolo designation switches T1 and T2, the value of the envelope coefficient of the envelope register 54 is, as shown in FIGS. 22 to 24, as a function of the depth indication of the amplitude 1/1, 1/2 or 1/4 and the volume curves (FIG. 13). With respect to the volume curves 1, 4, 5 shown in FIG. 13, no tremolo is applied. T6 is a pinch tremolo designation contactor. When the contactor is actuated, the output signal of the inhibition gate 84-22 which is produced under the condition that the envelope is in the attenuation state and the envelope register 54 is above "16", passes through the AND gate 84-19.When the erase state "00" of the envelope register 54 is detected by the AND gate 73-1 in the state detection circuit 73, an attenuation designation signal is applied to the door
ET 72-15 via the inhibition gate 73-5 and the OR gate 73-6. Consequently, in the first half of the attenuation state, a damping clock signal is used which will be described below and a tremolo similar to the pinching of a chord is obtained along the volume curve. Horn shown in Figures 25A and 25B (in this case the designated tremolo depth is 1/1)
The tremolo designation switch T2 is effective when the tremolo designation switch T1 is previously switched off and the tremolo is effective only during actuation of the contactor.

In accordance with the weight output states "32" and "64" of the envelope register 54, the inhibit gate 85 generates a drive state detection signal Q; the muting gate 86 produces a damping state detecting signal of the AND gate 87 and reverse AND series 88 produces an attenuation detection signal # &commat;; the inverted inhibition gate 66-6 produces a fast attenuation detecting signal &commat;Q; the series circuit of AND gates 89 and 90 produces a slow attenuation detection signal. Qr. Reference 91 designates a timing adjustment register for defining the fast attenuation which is provided with eight line memories at a bit position. These memories each shift during operation in response to the +0 shift pulse. . The fast attenuation Qr means a relatively fast damping of the envelope to prevent the sounds of the clock pulses occurring when an execution key is cut (especially when a stationary sound is specified as an organ sound ). Accordingly, when a setting signal Qh, which will be described hereinafter, is transmitted, the signal is applied by an OR gate 92 to an inhibit gate 93 which is made conductive when a non-indicating signal. Come in
exists, and is applied to the fast attenuation timing control register 91 by an inhibit gate 94 which is made conductive by an inverted signal from the AND gate 62. The output signal from the gate of FIG. Inhibition 93 sets the timing register 53 of the envelope clock pulse through an AND gate 95 of an inhibit gate 96 which is made conductive in a state other than the state of the envelope. "envelope" 00 ", an OR gate 64 and an OR gate 65, in synchronism with the output signal (an addition timing when the block address signal" 0 "is generated) 1 from the AND gate 62. After the switchover, the register 53 performs a fast attenuation operation.

 The description made so far concerns the main part of the electronic musical instrument according to the invention. The synchronization signals for controlling the circuit constituted as shown in Figs. 7A, 7B, 7C and 7D, different clock signals for controlling the envelope, the multiple execution control signals such as the duet control signals, the Execution keys, control of the key input will be described using the circuit diagrams illustrated in Figures 27A and 27B which are combined as shown in Figure 26 to form a complete circuit diagram.

 A base clock signal 40 (for example at 272510 Hz) transmitted from an original clock generator 100 is applied to an on-line counter 101 which makes counts corresponding to a circulation of the eight line memories which each constitute registers 20, 21, 34, 53 and 54 illustrated in FIGS. 7A-7D. The counter 101 is a capacity counter 8.

The generator circuit of the control synchronization 102 is supplied with indication signals in the contact positions W1 (no indication of multiple execution), W2 (dual execution), W3 (quartet execution) of a contactor W multiple execution indication. Accordingly, the output signal illustrated in Fig. 28B is output on the output line through a muting gate 102-1 and a gate
AND inhibition 102-2. In the case where there is no indication of a multiple execution, a signal "1" is transmitted on the output line z through the OR gates 102-3 and 102-4. A signal "1" is sent on the output line &commat; to through the doors
OR 102-5 and 102-6.In the case of a duet indication, the output signal shown in Figure 28 (c) is outputted to the output line z via the AND gates 102- 7 and OR gates 102-3 and 102-4. The output signal shown in Fig. 28 (c) is sent on the output line Q through an inhibit gate 102-8 and OR gates 102-9, 102-5 and 102-6,
In the case of the indication of a quartet, an output signal illustrated in Fig. 28 (d) is output from the output line z by the AND gates 102-10 and 102-11 and an OR gate 102 The output signal illustrated in Fig. 28 (d) is output from an output line Q through muting gates 10242 and 102-13 and an OR gate 102-6.

The outputs of the respective bit stage of the indication signal of an octet, the indication signal of a quartet, the indication signal of a duet on the contact W4. the indication switch W and the on-line counter 101 are fed to a synchronization signal generator 103 for a multiple execution. With this connection, an OR gate 103-1 produces an indication signal of a quartet-or an indication signal of an octet and an OR gate 103-2 produces a multiple execution signal (which is produced by answer to the indication of a duet, a quartet or an octet). The signal from the OR gate 103-2 is fed to an AND gate 103-2 and an inhibit gate 103-4.As a result, the output signal of weight "1" of the on-line counter 101 is output under forms signals P and P from the respective gates and is applied to the inhibition gates 80 and 81 of FIG. 7C. The signal coming from the door
OR 103-2 is fed to an AND gate 103-5 from which is extracted the weight output signal "1" from the on-line counter 101 which is output as a "+1" command signal through a gate
OR 104.The output of the OR gate 103-1 is fed to a gate
AND 103-6 so that the weight "2" of the in-line counter 101 provides an output signal which, in turn, is applied to the gate 103-8 through an OR gate 103-7. indication of the duo is supplied to an inhibit gate 103-9 from which the inverted signal of the on-line counter 101 is extracted and is applied by an OR gate 107 to an OR gate 103-8. The multiple execution signal output from the OR gate 103-2 is applied as an inverted signal to the OR gate 103-8 via an OR gate 103-10. The OR gate 103-10 is powered with the vibrato designation switch B operating signal. The output of the OR gate 103-8 provides the output signals illustrated in FIGS. 28 (B), (g) and (i). ) for duo and quartet indications through an OR gate 105.

When an octet indication signal is applied to a door
ET 103-11, the weight output signal "4" from the line counter 101 is output from an AND gate 103-11 and is transmitted as a signal represented by (k) in Fig. 28B by an OR gate 106. The synchronization signals represented by (f) and (g) illustrated in FIG. 28B are produced from the gates
OR 104 and 105 when the duo is indicated. The timing signals shown in (h) and (i) in Fig. 28B are produced from the OR gates 104 and 105 when a quartet is indicated. The synchronization signals shown in (j), (k) and (1) in Fig. 28B are produced from OR gates 104 to 106 when an octet is designated, and are applied to AND gates 97-1 to 97. 3 and then are fed to the adder 40 in synchronism with the block address signal "0". The additional value in the multiple execution such as the duet indication is used to provide fine frequency differences to the respective line memories. The sync signals on the lines i, and O output from the control sync generator 102 are fed to an input control circuit 107 and the timing signal from the output line is supplied to an octave counter 108 illustrated in Fig. 27B. The octave counter 108 is a three-bit capacity counter 8 which is driven every eight lines of 8 + o. The two lower bit positions in the counter (weight 1 and "2") serve as the input code of the octave represented in FIG. 7A of the fourth octave code state. See (a) in Fig. 29A. The output stages at three respective bit positions of the octave counter 108 are fed to the timing signal generator 109 and to the decoder 110. The "0" state of all three bit positions is detected by an AND gate 109-1 and an inhibition gate 109-2. As the sense output, the synchronization signal shown in (b) in Fig. 29A is extracted and is applied as a step counter to the counter counter.
111. The note counter 111 has a constitution such that the two lower bit positions function as a capacity counter 3 and its carry causes the binary counter constituted by the upper bit position ((c) of FIG. 29A).

In reality, the note counter is constituted by four bit positions obtained by combining it with the most significant bit position of the counter 108, therefore the four bit position output serves as the note input code shown in Fig. 7A. The output of the counter 111 is fed to the synchronization signal generator 109 and to a decoder 112. The eight outputs &commat; 1 to z of the decoder 110 provide different timing signals as shown in FIG. 29B (d) and are applied to the eight
Execution key columns 113. The execution key group 113 has 48 execution keys arranged in a matrix with 6 output lines terminating at the AND gates 114-1 to 114-6 of a signal detection circuit 114. synchronization of the action on the keys. The AND gates 114-1 to 114-6 are fed with six different synchronization signals ((e) in Fig. 29B) produced from the output lines # to O of the decoder 112.

From the AND gates 114-1 to 114-6, key input synchronization signals corresponding to the execution keys actuated among the 48 keys are extracted by a series circuit of OR gates 114-7 to 114-11. and are applied to a key input latch register 107-1 of a control circuit of the input terminal.

 The synchronization signal outputted from the synchronization signal generator 109 is detected in accordance with the contents of the counters 108 and 111. The synchronization signal illustrated in (f) in Fig. 292 from the output g is detected by the gates. inhibition 109-3 to 109-5. The synchronization signal illustrated in (g) in Fig. 29B from an output line O is detected by an AND gate 109-1 and the inhibition gates 109-2 and 109-6 through 109-8. synchronization signal -represented in (h) in Fig. 29B from an output is detected by an AND gate 109-9 and the inhibition gates 109-10 and 109-11 The output signal S4 of the counter 111 from an output 0 and a synchronization signal shown in (i) in Fig. 29B from an output 0 are detected by an inhibit gate 109-12.

The synchronization signal illustrated in (j) in Fig. 29B from the output Qi is detected using an AND gate 109-13 and an inhibition gate 109-14. The shift register 115-1 of the clock pulse signal generator 115 operates dynamically with 24 bit positions and is shifted by a clock signal produced all. the 8 lines from the Q output line of the control timing generator 102. Accordingly, a shift of the shift register 115-1 provides synchronization with a total capacity of 24 which is the sum of the counter capacitance 8. 108 and the capacitance 3 of the counter 111. The shift register 115-1 has first to third counting parts, each with eight bit positions. The first and second counting portions are used to generate the time clock signals of the vibrato and the envelope. The third counting part is used to count a given time when a new execution key is operated as will be described hereinafter. Basically the first counting part is an eight-bit binary counter implemented by the synchronization signal from the Q output line of the synchronization signal generator 109 (Fig. 29B) .The second counting part is a binary counter at eight bit positions with the two lower bit positions providing a three capacity count which is implemented in response to a timing signal outputted from the output line Qh. The third counting part is a binary counter implemented by a synchronization signal coming from the output line 0e. The output signal coming from an output d1 of the shift register 115-1 is supplied to an adder 115-3. via an OR gate whose output is applied to be recirculated on the input side of the shift register 115-1. The carry signal from the adder 115-3 is applied to an inhibit gate 115-4 by a transfer latch 107-2. The output signal of the inhibit gate 115-4 is inhibited at the time of transmission. generation of the synchronization signal from the output (i) of the synchronization signal generator 109. The output signal is also applied to the adder 115-3 by an OR gate 115-5. The synchronization signal from the output (i) is also applied to OR gate 115-5 through an inhibit gate 115-6. The output d2 of the shift register 115-1 is applied to an AND gate 115-7 and an inhibition gate 115-8; output d3 to an inhibit gate 115-9 and an AND gate 115-10; output d4 to an inhibit gate 115-11 and an AND gate 115-12, the output d5 to an inhibit gate 115-13 and an AND gate 115-14; output d6 to an inhibit gate 115-15 and an AND gate 115-16; the output d7 to an AND gate 115-17.The AND gate 115-7 and the inhibition gates 115-9, 115-11, 115-13 and 115-15 are cut with the AND gates 115-10, 115 -12, 115-14, 115-16 and 115-17. The output signals from the respective AND gates are extracted as one-pulse pulses (each with a width 8 + o). The output d1 is applied to the inhibit gate 115-8 whose output is coupled with a pulse. AND gate 115-18.

A timing signal from the output Qj of the timing signal generating circuit 109 is applied to the AND gate 115-18, and also to the adder 115-3 via an OR gate 115-2. This means that it controls a three capacity counter constituted by the two lowest bit positions in the second counting part. The output d1 from the shift register 115-1 is applied to a gate
ET 115-19 and the output of the AND gate 115-14 is applied to an ET.115-20 gate. The exits. of these are applied as reset and toggle signals to a 115-21 flip-flop circuit (without delay) to determine a time to prevent the beat in synchronism with the timing signal from the Qg output.
Reference 116 designates a circuit for selecting the vibrato pulse-clock. In this circuit, a time clock signal from the AND gate 115-10 is applied to an AND gate 116-1, and a time clock signal from the AND gate 115-12 to an AND gate 116-2. output signals from these AND gates 116-1 and 116-2 are applied through an OR gate 116-3 to an AND gate 116-4 and an inhibition gate 116-5. The output of the inhibit gate 116-5 is applied to an AND gate 116-6 to which a synchronization signal is applied from the output of the synchronization generator 109. The output of the AND gate 116-4 is fed to an AND gate 116-7 to which is applied a timing signal from the output &commat; . The outputs of the AND gate are output in the form of a vibrato clock signal B by an OR gate 116-8.The vibrato clock signal QB is converted into different clock signals as a function of the SA selection contacts SB and SB. pulse vibrato clock chosen. As can be seen from FIG. 30, the SA contact indicates whether the time clock signal determined by the first counting section of the shift register 115-1 is extracted or whether the time clock signal determined by the second part of count is extracted. The vibrato clock signal fB is applied as a counter signal to the counter 117 of capacitance eight. The counter 117 produces the signals illustrated in (a) in FIG. 31 at the respective stages, which signals, in turn, are applied to a control circuit of the vibrato 118.

In accordance with this counting state, the synchronization signal shown in Fig. 31b is detected by an inhibit gate 118-1 and an AND gate 118-2 on an output el. The synchronization signal shown in Fig. 31c is detected by an inhibition gate 118-3 and an AND gate 118-4 on an output e2. The synchronization signal shown in Fig. 31d is detected by the AND gates 118-5 and 118-6 on an output e3.

The synchronization signal shown in FIG. 31e is detected by an AND gate 118-7 and an AND gate 118-8 on an output e4. The synchronization signal shown in Fig. 31f is detected by an inhibit gate 118-9 on an output e5. The synchronization signal shown in Fig. 31g is detected by an inhibit gate 118-10 on an output e6. A series of OR gates 118-11 and 118-12 to obtain the logical sum of the outputs e1, e3 and e6 detects the synchronization signal shown in FIG. 31h and sends it to an output e7. A series circuit comprising gates OR 118-13 and 118-14 to obtain the logical sum of the outputs el, e2 and e5 detects the synchronization signal illustrated in (i) in FIG. 31 and sends it to an output e 8
As a result, the signals of. Synchronization e7, e8 and e4 are output on the AND gates 97-1 to 97-3 to which the block signal "0" illustrated in FIG. 7A is applied by the AND gates 118-15 to 118-17 and the OR gates 104 and 105 when operation is determined by the vibrato determination contact B. This means that at the moment of designation of the vibrato, the outputs AP1, bP2, AP4 are output in agreement with the contents of the counter 117.

Reference 119 designates an envelope clock pulse selection circuit for selecting the envelope clock pulse applied to the inhibit gate 63 illustrated in FIG. 7D. RA and R B are contactors for selecting the time clock signal in the attenuation state. DA and DB are contactors for selecting the time clock signal in the state of.

damping.RC is a contactor for selecting the slow attenuation clock signal. OA is a contactor for an organ envelope (stationary sound). A clock signal output from AND gate 115-12 is applied to AND gates 119-1 to 119-3. A clock signal from an AND gate 115-14 is applied to the AND gates 119-4 to 119-6. A clock signal transmitted by an AND gate 115-16 is applied to the AND gates 119-7 to 119-9. A clock signal output from AND gate 115-17 is applied to AND gates 119-10 and 119-11. A select contact output signal from the RB contactor is applied to the gates
And 119-1, 119-4, 119-7 and 119-10. The outputs of these AND gates are applied to the series circuit of OR gates 119-12 to 119-14.The output signal from the series circuit is coupled with an AND gate 119-15- and an inhibition gate 119-16 .

The timing signal from. of the output 0 of the synchronization signal generator 109 is applied to the gates
AND 119-17 to 119-19, the timing signal from the Qg output to the AND gates 119-20 to 119-22. The AND gate 119-15 and the inhibit gate 119-16 are coupled with the gates
And 119-20 and 119-17. The outputs of these gates are output as a QR attenuation clock signal through a gate
AND 119-24 at which the attenuation state detection signal shown in Fig. 7D is applied by an OR gate 119-23.As seen from Fig. 30, the contactor
RA indicates whether the time clock signal determined by the first counting part of the shift register 115-1 is extracted or whether the time clock signal determined by the second counting part is extracted. The output of the switch contact of the DB contactor is applied to the AND gates 119-2, 119-5 and 119-8. The outputs of these AND gates are fed to a series circuit of OR gates 119-25 to 119-26. The output of the series circuit is applied to an AND gate 119-27 and an inhibition gate 119-28. The outputs of the AND gate 119-27 and the inhibition gate 119-28 are applied via of AND gates 119-21 and 119-18 and an OR gate 119-29 to a gate
ET 119-30 which produces a damping clock signal when the damping state detection signal shown in Fig. 7D appears. The output signal of the RC contactor select contact is applied to AND gates 119-6, 119-9 and 119-11 whose outputs are applied to a series of OR gates 119-31 and 119-32. The output signal of the series circuit causes the AND gates 119-33 and 119-19 to produce a slow attenuation clock signal fsr when the slow attenuation signal fed from the circuit of Fig. 7D is generated. The AND gate 119-3 produces an output at the time when the fast attenuation state detection signal or a drive state detection signal fed from the circuit of Fig. 7D through an OR gate 119 -37 is generated and, upon receiving the output from the AND gate 119-3, the AND gate 119-22 generates a fast attenuation clock signal hr or a signal
driving clock A The attenuation clock signal XB transmitted from the AND gate 119-24 the damping clock signal transmitted from the AND gate 119-30, the slow attenuation clock signal transmitted from the AND gate 119-19, the fast attenuation signal transmitted from the AND gate 119-22 are applied, such as an envelope clock signal transmitted from a series of OR gates 119-34, 119-35 and 119-36 to the gated gate. inhibition 63 illustrated in FIG. 7D.

An addition value designation circuit 120 specifies the value added to the adder 55 for the envelope illustrated in FIG. 7C in the states of attack, damping, attenuation, slow attenuation and fast attenuation. The rise time and the fall time can be quickly controlled with respect to time by adding (+) or subtracting (-) an addition value with a specified envelope coefficient value. The contactor
Aa is a five-contact selection contactor. The output signals of the contacts cause the AND gates 120-1 to 120-5 to produce addition control signals "+1", +2, "+4", "+8" and "+32" by the doors OR 120-6 to 120-10. Da denotes a five-contact selection contactor. The output signals of the contacts cause the AND gates 120-11 to 120-15 and the OR gates 120-6 to 120-10 to produce the +1 addition control signals. "," +2 "," +4 "," +8 "and" +32 ". When a signal detecting the attenuation state is generated, an addition control signal "+1" is generated by the OR gate 120-16. When the slow attenuation state detection signal is generated, an addition control signal "+1" is generated through the OR gate 120-17. When a fast attenuation state detection signal is generated, an addition control signal "+8" is generated through the OR gate 120-18. These addition value signals are fed to the adder 55 shown in FIG. 7C via AND gates 67-1 to 67-5.

 The clock signals in the first and second counting sections transmitted from the AND gates 115-10, 115-12, 115-14, 115-16 and 115-17 are selected as indicated by the circular symbols O in FIG. in agreement with the indications provided by the vibrato clock signal selection circuit 116 and the envelope clock signal selection circuit 119. In addition, the value to be added to the adder 55 for the envelope may be selected in synchronism with the clock signal selects.

Figures 32, 33, and 34 show the time-dependent changes in envelope coefficient values during attack, damping, and damping.
The synchronization signal (with a width of corresponding to an execution key implemented, transmitted from the circuit 114 for detecting the synchronization of the action on the key is applied to a synchronization switch of the input by key 107-1 whose output is coupled to an AND gate 107-3 AND gate 107-3 produces an output signal in synchronism with the flip-flop output signal 115-21 to prevent oscillation, signal that is applied to the inhibit gate 107-4 which, in turn, produces a signal corresponding to a depressed key. The inhibit gate 107-4 provides an output signal on the AND gate 107-6, when it receives a first signal at a pulse corresponding to a key pressed by action on a new key, when the output signal from the 48-bit shift register 107-5 corresponding to the number
(48) execution keys is "0" as will be described below. ET gate 107-6 responds to a reset signal
(representing a vacant line memory in the envelope register 54) transmitted from the inhibit gate 68 shown in FIG. 7A and produces the input indication signal mentioned above for setting the input data. the pitch of the new key and the state of attack of the envelope in the vacant memory.The input indication signal also specifies a plurality of on-line memories in accordance with the designation state of multiple execution. The reset signal transmitted from the muting gate 68 shown in FIG. 7A is applied to the AND gate 107-7 and the inhibition gate 107-8 of the input control circuit 107. The gate exit AND 107-7 is held by the OR gate 107-9 and the inhibit gate 107-10 and is coupled with a disable gate 107-11, the output of which is inhibited by the inhibit gate 107-8. ET gate 107-7 and gate 107-8 receive as a gate signal the output c Q, namely the designation of a duo signal from the control synchronization generator circuit 102, the signals indicated by (c) and (d) shown in Fig. 28A denoting a quartet and a constant signal "1" without any indication of multiple execution, and a signal shown in (b) in Fig. 28A denoting an octet.

The signals shown in Fig. 28A (b) prohibit the output of the inhibit gate 107-10 by an inhibit gate 107-12 from the Q output and release the hold.

Accordingly, the inhibit gate 107-11 produces a signal in synchronism with the output signal Qc corresponding to a multiple execution designation and the AND gate 207-6 produces an output signal upon generation of the key signal. actuated. The output signal from the AND gate 107-6 is supplied to the inhibit gate 107-13 and the AND gate 107-14. The AND gate 107-14 produces an output signal in synchronism with the output signal Qb from the control sync generating circuit 102. The output is then applied to the flip-flop 107-16 to provide a delay of a bit position. (lfo delay) through the OR gate 107-15. The output of the flip-flop is applied by an inhibit gate 107-17 to the OR gate 107-15. Through this connection, it is recirculated. The recirculation is maintained until the inhibit gate 107-17 is inhibited by an output signal ((b) of Fig. 28A) from the output of the control timing generator circuit 102. Accordingly, the signal The output from the inhibit gate 107-13 continues to be issued following the generation of the output of the AND gate 107-6 until it is inhibited by the output signal from the gate. inhibition 107-17. Accordingly, the inhibit gate 107-13 produces input designation signals with a width of 10 (in the case where there is no multiple execution designation), a width of 2o (in the case the designation of a duet), a width 4 + 0 (designation of a quartet) and a width 8 (designation of an octet.In the case of a designation of a duet, four combinations of memory lines LOet L11 L2 and L3, L4 and L5 and L6 and L7 are used, in the case of the designation of a quartet r two combinations of memory lines Lg to L3 and L4 to L7 are used: in the case of the designation of an octet a simple combination Lg to L7 is used The same input code of the pitch of the sound is applied to the plurality of memory-lines of the code register of the notes 20 and the octave code register 21, and at the same time time the plurality of in-line memories of the envelope register 54 illustrated in FIG. 7D are in the attack state and the registers respec In this case, the output signal of the AND gate 107-6 together with the output signal of the flip-flop 107-16 with a delay of a bit position is applied to the AND gate. 107-20 through the OR gate 107-18 and the OR gate 107-19 to which the output signal from the shift register 107-5 is applied. The OR gate 107-18 produces an output signal in synchronism with the input designation signal and its output signal is supplied as a write signal to the shift register 107-5 by the synchronization signal corresponding to the depressed key and issued from the OR gate 107-21.When receiving a signal "1", the shift register 107-5 is shifted in synchronism with the synchronization signal ((b) in Fig. 28A) from the output z of the control synchronization generator 102. The charged signal is kept in recirculation as long as the execution key is depressed, but the circulation ceases when the key is released.

The output of the AND gate 107-20 is supplied as a gate inhibit signal to the inhibit gate-107-22.

alimentée avec un signal descoincidence provenant d un circuit à coincidence 121. La porte ET 107-28 produit un signal de positionnement de l'atténuation rapide (positionnement 8 ) qui à son tour est introduit dans le registre de réglage de la synchronisation d'atténuation rapide 91 par la porte OU 92 illusw trdedans la figure 7D.Le circuit à coincidence 121 est utilisé pour vérifier si le code d'entrée de hauteur de son sorti des étages respectifs 1' 02, S1, S2, S4, et S8 des compteurs 108 et 111 coincide avec le code de sortie de hauteur de son émis depuis le registre de code de notes 20 et le registre de code d'octave 21 illustrés dans la figure 7A. Lorsque le contacteur A désigne hors service', un code de hauteur de son est chargé dans les mémoires en ligne du registre de code de note 20 et du registre de code d'octave 21, pendant le temps de maintien (approximativement 45 ms) de la bascule 107-24.Dans le cas où une touche d'exécution est relâchée, la porte ET 107-28 produit un signal de positionnement d'atténuation rapide et il est dans l'état d'atténuation rapide. Comme décrit ci-dessus, l'état d'atténuation rapide indique un état dans lequel, lorsque la touche d'exécution est relâchée, le son disparait rapidement.Upon pressing the execution key, an operating key signal transmitted from the inhibit gate 107-4 toggles the flip-flop 107-24 through the OR gate 107-23. The tilted output is circulated through the inhibit gate 107-25. Floating is released when generating the output signal from an AND gate 107-26 to perform L ut; . logic logic of the synchronization signal ((f) in Fig. 29) from the output 0e of the generator circuit of the synchronization signal 109 and the output signal from the transfer latch 107-2.The flip-flop output of the flip-flop 107-24 is applied to the inhibit gate 115-22 in the generator circuit of the clock pulse 115, so as to bring the third count section into the shift register; to start his counting operation. Accordingly, the dwell time can be obtained from the third counting section. In this system, hold time is chosen to be about 45 ms after the key. execution was depressed. The flip-flop output signal of the flip-flop 107-24, together with the output signal from the contactor 0A for designation of an organ-like volume, is applied to the inhibit gate 107-22 through the door
OR 107-27.The output from gate 107-22 is applied to AND gate 107-28. ET gate 107-28 has been

supplied with a coincidence signal from a coincidence circuit 121. The AND gate 107-28 produces a fast attenuation positioning signal (positioning 8) which in turn is inputted into the attenuation timing adjustment register. The coincidence circuit 121 is used to check whether the pitch input code is output from the respective stages 1 '02, S1, S2, S4, and S8 of the counters. 108 and 111 coincides with the pitch output code outputted from the note code register 20 and the octave code register 21 shown in FIG. 7A. When the contactor A designates out of order, a pitch code is loaded into the on-line memories of the note code register 20 and the octave code register 21 during the hold time (approximately 45 ms) of the flip-flop 107-24.In the event that an execution key is released, the AND gate 107-28 produces a fast attenuation positioning signal and is in the fast attenuation state. As described above, the fast attenuation state indicates a state in which, when the execution key is released, the sound rapidly disappears.

In the case where the contact 0A designates "in service", if the execution key is released (the AND gate 107-20 produces no output), the on-line memory with the same output code of sound height as that the released execution key is set to be in the fast attenuation state. By this operation, a satisfactory off key state is realized.

 As described above, with the constitution according to the invention, a plurality of waveforms can be defined and composed simultaneously-, and, in the different waveforms, the ups and downs of the volume can to be made different. As a result, the resulting musical sound has a natural and rich timbre. In the example mentioned above, we limit ourselves to two types of volume curves a and ss. However, two or more volume curves can be used without departing from the scope of the present invention.

 In the control system of the period of the note according to the invention, the adjustment control value of the period of the adjustment means of the period for setting the period of the counting means, corresponding to the note, is divided into coarse and fine values, taking into account the dynamic shift flow of each of the online memories (a total of 8). With such divided values, the count (+) of a counter can be controlled numerically in accordance with the respective notes. In addition, the control value is stored by a matrix circuit so that circuit construction is very simple and suitable for large scale integrated circuit fabrication. In the embodiment, counter count control is described with respect only to a progress check. However, a delay control (-) is possible by removing clock pulses from those counted by the counter means at a given clock frequency, in agreement with the note.

 Also, in the above embodiment, the program definition unit of the waveform 35 for each block shown in Fig. 7A is a contactor designation as shown in Fig. 16. Alternatively, the previously selected definition states are stored permanently in a fixed memory such as a single read memory (ROM). The definition states can be stored on a magnetic card, and in use, these are read and stored in a temporary memory such as a toggle memory. The number of blocks of a period of a musical sound wave is not limited to 16. The values of the differential coefficient for each block are not limited in number to "1li," 2 "," 4 ". The filter can be added to the stage following the digital / analog converter.In this case, a plurality of filters can be used with contactor selection.This scheme provides sound effects with different resonance characteristics and echo characteristics of the instruments. with the acoustic or brass, or different transmission characteristics of the brass, and the note code register 20, the octave code register 21, the period count register 34 and the envelope register 54 may be constituted by random access memory (RAM) Many other modifications of the constitution of the circuit are possible within the scope of the present invention.

Claims (4)

CLAIM I CA-T IONS  An electronic musical instrument including volume control means for numerically controlling the increase or decrease in the volume of the performance in accordance with the passage of time from the operation of a performance key period counting means for counting a cycle of a musical sound waveform as a plurality of count steps to numerically produce a musical sound wave means for dividing the single cycle into m blocks each having one or more count steps and means for defining a musical sound wave to define the rise and fall of the musical sound wave dai-js each block by a value with "4" or t ~ attached to said value which is an integer twice as large as the control value of the volume control means, wherein the single cycle of the musical sound wave is divided into m blocks and these blocks are suitably defined while in m At the same time, a volume control can be performed.  2. An electronic musical instrument characterized in that it comprises a volume control means for controlling the increase or decrease of the volume of the performance according to the lapse of time from the actuation of a key method of counting the period to count a single cycle of a musical sound waveform as a plurality of count steps to digitally produce a musical sound wave, a means for dividing the cycle single in m blocks each comprising one or more count steps and means for defining the musical sound wave in which, in order to define different waveforms simultaneously, one of the waveforms is defined and the rise and fall of the musical waveform in each block is defined by a value with "+" or "-" attached to said value which is an integer of times as large as the camBnde value of the volume control device.  An electronic musical instrument according to claim 2, characterized in that it comprises a device which meets the definition of the waveform by said waveform-defining device, for controlling the periods in different forms. wave so as to have the relationship M N.  4. An electronic musical instrument for producing musical sound waves when an electronic counting device progressively comprises characterized in that it comprises a device for adjusting the period to adjust the period of the counting device corresponding to the note of the execution key and a device in which the control value of the adjustment of the period of said period adjustment device is divided into coarse and fine values, the period control being carried out by means of a running count or of a delay count with several synchronizations of the given count state of the period setting device and means for period control by means of a running count or a counting of delay by selecting the given count value of the counting device corresponding to said fine value.