KR830000498B1 - High Power Amplifier / Switch Using Gate Diode Switch - Google Patents

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Description

High Power Amplifier / Switch Using Gate Diode Switch

1 and 2 are circuit diagrams in accordance with a schematic embodiment of the present invention.

3 is a circuit diagram according to another schematic embodiment of the present invention.

4 is a circuit diagram according to another schematic embodiment of the present invention.

5 is a circuit diagram according to another schematic embodiment of the present invention.

6 is a circuit diagram according to another schematic embodiment of the present invention.

The present invention relates to solid state devices, and more particularly to high voltage and high current switches, amplifiers and tube separator circuits. In particular, the present invention is useful for circuits capable of controlling relatively high voltages and high currents using amplifiers that are relatively low voltage but capable of only high current operation as control devices. Many applications require relays and other types of switches to operate at high voltage and current levels. Instead of mechanical relays, many attempts have been made to use photoactive optical separators that constitute bipolar transistors. In general, supplying very high voltages and currents to bipolar transistors has been known to be economically inadequate due to the limited voltage regulation capability.

In a paper entitled Douglas E. Houston, entitled "Field Terminal Diode," published in the minutes of the electronic device of ED-23 No. 8, August 1976, it has a vertical structure and can be pinched off to provide an off state. An ideal solid state high voltage switch is described that includes an area that can be highly challenged with dual carrier injection to provide an on state. Double carrier injection refers to the injection of holes and electrons from a conductive plasma in a semiconductor. One problem with this switch is that it cannot be easily manufactured on the cavity with a switching device similar to the other. Another problem is that the spacing between the grid and the cathode must be small to limit the magnitude of the grid control voltage. However, this limits the useful voltage range since it reduces the breakdown voltage between the grid and the cathode. This limitation in turn limits the use of two devices connected in series at relatively low operating voltages, ie each cathode connected to the other's anode. Such a circuit is useful as a high voltage bidirectional solid-stage switch. Another problem is that the base area should ideally be doped high to avoid punch-through from the anode to the grid. However, it induces low voltage breakdown between the anode and the cathode.

Expansion of the base area limits the punch effect but increases device resistance in the on state.

High power amplifiers / switches that can be operated at least several hundred volts and hundreds of milliamps are desirable.

The solution to this problem is to properly combine an amplifier or switch with a low voltage / high current capability as a level transition circuit device and gate diode switch (GDS) as published in Houston et al. Preferred forms of GDS are described herein below.

In one embodiment, the amplifier / switch is a pnp type transistor having a base used as an input and a collector connected to the gate of the GDS. Transistors have relatively high current regulation but only moderate voltage control. The level transition circuit means is a p-n diode. This network is useful as a high power amplifier / switch. The combination of the high voltage and current capability of the GDS and the high current capability of the pnp transistor lead to an amplifier / switch with both high residual and high current capability.

In another embodiment, the amplifier / switch is a pnp transistor and an npn transistor or a junction field effect transistor.

In another embodiment, the network is an optical splitter circuit having an amplifier consisting of a base of photosensitive Q1 and a pair of transistors Q1, Q2 coupled in the form of Darington. The level transition circuit means are two series coupled pn diodes (D1, D2).

The collector of Q1 and Q2 and the anode of D1 are coupled to a common terminal. The emitter of Q2 is coupled to the anode of GDS and the cathode of D2 is coupled to the gate of GDS. The Darlington arrangement of transistors Q1 and Q2 has a relatively high gain and high current capability but only moderate blocking capability. These characteristics, when combined with the high current and high voltage blocking capabilities of the GDS, allow the construction of optically coupled amplifier switches that provide excellent electrical isolation, high gain and high current and high voltage regulation. This is accomplished without using high current and high voltage transistors.

Another embodiment of the invention is an optically responsive bidirectional switch composed of a combination of two optical separator circuits and two additional diodes as described above.

These or other features and advantages of the present invention will be more clearly understood from the following considerations described in detail with reference to the accompanying drawings.

Referring to Figures 1 and 2, an amplifier A consisting of transistors Q1 and Q2 (shown connected in a Darlington arrangement), and a level transition circuit L5 consisting of diodes D1 and D2 and a semiconductor cross-sectional view in Figure 1 are illustrated. Shown is a network 10 comprised of a gate diode switch GDS illustrated as an electrical code in FIG. 2 coupled between a terminal and Y. FIG. Amplifier A is represented as an amplifier / switch. Q1 is a phototransistor having a photosensitive base region. The emitter of Q1 is coupled to the base of Q2.

The semiconductor substrate 12 body 16 and a region (18,20,22, 24) are each n, p ^- is illustrated in, p ^+, n ^+, p and n ⁺ type conductivity region. Regions 18 and 24 are used as anodes and cathodes, respectively, and regions 20 and 12 are used as gates (control terminals) of the GDS, and regions 22 are used as punch throw shields. Electrode regions 28, 30 and 32 are typically aluminum and provide low ohmic contact to regions 28, 20 and 24, respectively.

The switch GDS is characterized by a relatively low resistance when the passage between the anode region 18 and the negative electrode region 24 is on (conduction) and relatively high resistance when it is off (blocking). In the on state, the potential of the gate electrode 30 is equal to or less than the potential of the anode 28. Holes are injected into the groove 16 in the anode region 18 and electrons are injected into the body 16 in the cathode region 24. These holes and electrons can be any number sufficient to form a plasma that modulates the body 16 conductively. This lowers the resistance of the body 16 so that the resistance between the anode region 18 and the cathode region 24 becomes relatively low when the GDS is operating in the N state. This mode of operation in which both holes and electrons act as current carriers is indicated by double carrier injection.

The region 22 limits the punch draw of the depletion layer formed between the region 20 and the substrate 12 and the cathode region 24 in operation and also prohibits the formation of a surface inversion layer between the region 24 and 20. . In addition, this allows the anode region 18 and the cathode region 24 to be spaced relatively close together. This results in a relatively low resistance between the anode region 18 and the cathode region 24 during the on state.

When the potential of the gate electrode 30 is much more positive than the potential of the anode electrode 28 and the cathode electrode 32, the conduction between the anode region 18 and the cathode region 24 is prohibited or blocked. The excess electrostatic potential required to inhibit or block the conduction is a function of the structure form of the structure 10 and the impurity concentration level. This positive gate potential causes a significant portion of the body 16 to be depleted so that the potential of this portion of the body becomes more positive than that of the anode 18 and cathode 24 regions. This positive potential barrier blocks the conductive plasma and prevents holes from conducting from anode region 18 to cathode region 24. It is also used to collect electrons emitted from the cathode before the electrons reach the region 18. The switch GDS was fabricated on an n-type substrate having a thickness of 457 to 559 microns and a conductivity of 10 ¹⁵ to 10 ¹⁶ impurities / cm ³ . Body 16 has a thickness of 30-40 microns, a width of 720 microns, a length of 910 microns, and an impurity concentration of 5 × 10 ¹³ impurities / cm ³ and is P ⁺ type conductive. The cathode region 24 has a thickness of 2 to 4 microns and an impurity concentration of 10 ¹⁹ impurities / cm ³ and is p ⁺ type conductive. The cathode region 24 has a thickness of 2 to 4 microns and an impurity concentration of 10 ¹⁹ impurities / cm ³ and is n ⁺ type conductive. The spacing between the cathode and anode is typically 120 microns.

The network 10 is useful as an optical separator providing a low impedance or high impedance path between terminals X and Y. The current gain and high current capability of amplifier A and the high voltage and high current capability of GDS are combined to provide a high voltage switch. In addition, the network 10 provides a relatively high electrical isolation between the input light source and the terminals X and Y.

The collector of transistors Q1 and Q2 and the anode of D1 are coupled together to terminal X. The emitter of Q2 is coupled to the anode of GDS at terminal B. The cathode of D2 is coupled to the gate of the GDS at terminal C. The cathode of the GDS is coupled to terminal Y. The cathode of D1 is coupled to the anode of D2. Transistor Q1 is a phototransistor having a photosensitive base region used as an input to network 10. Conduction may occur between the collector and emitter of Q1 when sufficient light is incident on the photosensitive base of Q1.

As will be apparent from the following description, when sufficient light is incident on the photosensitive base of Q1, there is a relatively low impedance path between X and Y, and from terminal X to terminal Y if it is more positive by a preselected amount than terminal X and terminal Y Evangelism takes place. When insufficient light signal is incident on the photosensitive base of Q1, the terminal X and Y are essentially an open circuit (high impedance passage).

During the on (conduction) state of the GDS, the potential of the anode region 18 is more positive than the potentials of the gate regions 12 and 20 and the cathode region 24 and the current is from the anode region 18 to the region 16. And 22 to the cathode region 24. The conduction between the anode region 18 and the cathode region 24 is inhibited or blocked when the potentials of the gate regions 12 and 20 are sufficiently more positive than the potentials of the anode region 18 and the cathode region 24. The excess electrostatic potential required to inhibit or block the conduction is a function of the structure type and impurity concentration level of the semiconductor region of the GDS.

The network 10 can be operated to perform a switch function and to be used as an optical separator amplifier circuit. When a light signal strikes the photosensitive base of Q1, Q1 and Q2 are biased to maintain conduction therethrough. Substrate 12 (gate of GDS) and region 24 (cathode of GDS) are respectively used as collector and emitter of vertical npn transistor and body 16 and region 22 are used as base. The conductivity from anode region 18 to cathode region 24 acts as a base current to maintain the conductivity from substrate 12 to cathode region 24. A first conduction path from terminal X to Q1, Q2, region 18 (anode of GDS), body 16, regions 22 and 24 is established. In addition, a second conductive path from terminal X to D through Y, D1, D2, region 20, substrate 12, body 16, regions 22 and 24 is established.

The operating state described above is achieved by selecting the collector emitter voltage of Q2 to be less than the combined forward bias potential of D1 and D2. This ensures that during the conduction the potential of terminal C (gate potential of GDS) is at a peak level than that of terminal B (anode potential at GDS) and conduction between anode region 18 and cathode region 24 It ensures that it can happen.

When the light emitting the photosensitive base of Q1 is removed, Q1 and Q2 are biased off and the current flowing therethrough is stopped. The potential of the terminal B falls below the potential of the terminal C so that the GDS is switched off. This cuts off all the conduction between terminals X and Y. Therefore, at this time, between the terminals X and Y becomes relatively high impedance. Almost all voltage drops between the terminals X and Y occur at both ends of the anode region 18 (terminal B) and the cathode region 24 (terminal Y), and there are relatively appropriate ends at both ends of the collector emitter of Q2. The voltage across the collector emitter of Q2 is at a sufficiently low level that the potential of terminal B is less than that of terminal C such that GDS is biased off.

As described above, it can be understood that the level transition circuit LS provides a self bias for the GDS gate without the need for a separate bias circle. Moreover, this provides an alternating current path during the on state which reduces the high current flowing through amplifier A.

Referring to FIG. 3, there is shown a network 100 coupled between terminals X1 and Y1, which is approximately the same as network 10. The network 100 constitutes an amplifier A1, a gate diode switch GDS 1, and a level transition circuit means LS1. A1 constitutes a pnp transistor Q3 and an npn transistor Q4 and is represented by an amplifier switch. The emitter of Q3 is coupled to the collector of Q4 and the collector of Q3 is coupled to the base of Q4. LS1 consists of pn diodes D3 and D4 connected in series. The photosensitivity is not the same as that of the transistor Q1 in the base of FIG. The operation of network 100 is very similar to network 10 except that the input signal is applied to the base of Q3 via an electrical connection rather than through a light path and the gain of amplifier A1 is different from the gain of amplifier A. .

Referring to FIG. 4, there is shown a network 102 coupled between terminals X2 and Y2 that is very similar to network 100. The network 102 constitutes an amplifier A2 composed of a junction field effect transistor 5 having a gate coupled to the input terminal 12. A2 is indicated as the amplifier switch. It is also composed of the level transition circuit means LS2 composed of diode D5 and also composed of gate diode switch GDS 2. The basic difference between networks 102 and 100 is that Q3 and Q4 are substituted for junction field effect transistor Q5 and a single diode D5 is used instead of diodes D3 and D4. The operation of network 102 is very similar to the network 100 of FIG. 3 except that the gain of amplifier A3 is slightly different from the gain of FIG.

Referring to FIG. 5, there is shown a network 104 composed of amplifier A5, level transition circuit means LS5 and gate diode switch GDS 5 coupled between terminals X5 and Y5. A5 is composed of pnp transistor Q5 and LS5 is composed of p-n diode D10. A5 is represented as an amplifier switch. The network 104 is very similar to the network 102 of FIG. 4 except that npn transistor Q8 is used instead of junction field effect transistor Q5 and diode D10 is used instead of diode D5. The operation of network 104 is very similar to that of network 102, but the gain of A5 is different from the gain of A2.

Referring to FIG. 6, the first and second stage directional circuit means composed of the amplifiers A3 and A4, the gate diode switches GDS and GDS4, and the level transition circuit devices LS3 and LS4 and diodes D7 and D9, respectively. There is shown a network 106 constructed and coupled between terminals X3 and Y3. A3 and A4 are represented as amplifier switches, respectively. The network 106 can be operated as a symmetrical switch that couples terminals X3 and Y3.

In the schematic embodiment of the network 106, the amplifier A3 consists of an npn transistor Q6 having a photosensitive base region and the amplifier A4 consists of an npn transistor Q7 which also has a photosensitive base region. The combination of A3 and GDS3 and D6 and the combination of D4 and GDS4 and D8 are all constructed in essentially the same way as A, GDS and LS in FIGS. 1 and 2 and apply in the same way. The collector of Q6 is coupled to the anode of D6, the cathode of D7 and terminal X3. The emitter of Q6 is coupled to the anode of GDS3, to the cathode of GDS4, and to terminal U. The collector of Q7 is coupled to the anode of D8, the cathode of D9 and terminal Y3. The emitter of Q7 is coupled to the anode of GDS4, the cathode of GDS3, and terminal Y. The gates of the cathode tubes GDS3 and GDS4 of the diodes D6 and D8 are also coupled together to the terminal W.

If the potential of terminal X3 is more level than the potential of Y3 and a light signal is incident on the photosensitive base of Q6, it is conducted from terminal X6 to the cathode of GDS3 through Q6 and D6 and through GDS3 to terminal Y3 through D9. Is inverted. When a light signal is applied to the photosensitive base of Q6, the impedance between terminals X3 and Y3 becomes relatively low.

When the potential of the terminal Y3 is more level than the terminal X3 and a light signal is applied to the photosensitive base of Q7, it is conducted from the terminal Y3 to the GDS4 through the Q7 and the D8, and then through the D7 to the terminal X3. When a light signal is applied on the photosensitive base of Q7, the impedance between terminal Y3 and X3 becomes relatively low.

Thus, it can be clearly seen that the network 106 provides a bilateral switching action that leads to gain.

The embodiments described herein are intended to illustrate the general principles of the invention. Accordingly, various modifications are possible in accordance with the spirit of the present invention. For example, the amplifier may be a single channel or P-channel MOS transistor and the level transition circuitry may be an equivalent MOS type diode. Moreover, the amplifier may be a pair of npn transistors coupled together in a Darlington arrangement. Also, the amplifier switch can be significantly more complex than just one or two transistors, and the level transition circuit means may also be more complex than just one or two diodes. Furthermore, the amplifier switch and level transition circuit means may be formed from elements other than junction transistors or deployment effect transistors or diodes.

Claims (1)

The bulk portion has a semiconductor body 16 of the first conductivity type, an anode region 18 of the first conductivity type, a cathode region 24 of the second conductivity type opposite to the first conductivity type, and a second portion. Conductive gate regions 20 and 12, wherein the anode region, the cathode region and the gate region are separated from each other by a part of the semiconductor body bulk portion 16, and the resistivity of the bulk portion is positive, shaded and gated. Relatively low compared to the resistivity of the region, the current flowing between the anode region and the cathode region when the output terminals are connected to the anode and cathode regions, the gate terminal is connected to the gate region, and the first voltage is applied to the gate region. A depletion region that substantially prevents the formation of a semiconductor body is formed, and when a second voltage is applied to the gate region and an appropriate voltage is applied to the anode region and the cathode region, a relatively low level is formed between the anode region and the cathode region by double carrier injection. that A switching circuit comprising a gate diode switch (GDS) in which a gender current path is set, wherein the amplifier (A) is connected to the output terminal of the gate diode switch and the level transition circuit means (LS) is connected to the amplifier and the gate terminal. A high power amplifier switch using a gate diode switch characterized in that.

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