KR20240091413A - Thin film transistor and display panel - Google Patents

Abstract

Embodiments of the present disclosure relate to a thin film transistor and a display panel. More specifically, the thin film transistor includes a substrate, a protruding buffer layer, an active layer, a gate insulating layer, and a gate electrode, and a protruding buffer layer. The S-Factor can be improved by making the width narrower than the width of the gate electrode.

Description

Thin film transistor and display panel {THIN FILM TRANSISTOR AND DISPLAY PANEL}

Embodiments of the present disclosure relate to thin film transistors and display panels.

Among display devices currently being developed, there is a self-luminous display device in which subpixels disposed on a display panel include light emitting elements. Each subpixel disposed on the display panel of such a self-luminous display device may include a light-emitting element that emits light on its own, a driving transistor for driving the light-emitting element, and several transistors. The transistor may be a thin film transistor.

A transistor may include a gate electrode, a source electrode, a drain electrode, etc. Depending on the voltage applied to the gate electrode, drain current (Id) may flow through the channel of the transistor. Transistor performance related to drain current (Id) can be evaluated by threshold voltage (Vth), mobility, S-Factor, etc.

S-Factor is an indicator that indicates the amount of gate voltage change required to increase the drain current (Id) by 10 times. This is also called Subthreshold Swing (SS). The larger the S-Factor of the driving transistor, the more advantageous it is for expressing gray scale.

Meanwhile, if a buffer layer and an electrode layer are disposed below the gate electrode of the transistor, the S-Factor of the transistor can be increased. The thinner the buffer layer, the higher the S-Factor can be.

As described above, the thinner the buffer layer is, the higher the S-Factor can be. However, since a minimum thickness is required to maintain the buffer layer, there is a limit to increasing the S-Factor just by forming a thin buffer layer.

Accordingly, embodiments of the present disclosure can provide a thin film transistor and a display panel capable of improving S-Factor.

Embodiments of the present disclosure can provide a thin film transistor and a display panel that can be driven at low power as the S-factor is improved.

Embodiments of the present disclosure include a substrate, a buffer layer on the substrate, an active layer on the buffer layer, and a gate insulating layer on the active layer, wherein the buffer layer includes a buffer portion and a protruding buffer protruding upward from the buffer portion by a predetermined height. A thin film transistor may be provided, including a portion, and a side surface of the protruding buffer portion is inclined.

The protruding buffer portion may have a rectangular shape.

It may further include a gate electrode formed on the buffer layer, and the width of the protruding buffer portion may be narrower than the width of the gate electrode.

Embodiments of the present disclosure include a substrate, a buffer layer on the substrate, and a plurality of transistors on the buffer layer, and each of the plurality of transistors includes an active layer on the buffer layer, a gate insulating film on the active layer, and a gate electrode on the gate insulating film. The upper surface of the buffer layer includes a plurality of protruding upper surfaces that form a predetermined angle and protrude upward by a predetermined height, each of the plurality of protruding upper surfaces overlaps the gate electrode of each of the plurality of transistors, and The angle may provide a display panel including a first tilt and a second tilt.

According to embodiments of the present disclosure, a thin film transistor and a display panel capable of improving the S-factor can be provided.

According to embodiments of the present disclosure, a thin film transistor and a display panel that can be driven at low power can be provided as the S-factor is improved.

1 is a configuration diagram of a display device according to embodiments of the present disclosure.
2 is an equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
3 is a cross-sectional view of a thin film transistor according to embodiments of the present disclosure.
4 to 6 are cross-sectional views of thin film transistors according to embodiments of the present disclosure.
7 is a graph of the S-factor of a thin film transistor according to embodiments of the present disclosure.
8 is a graph of the S-factor of a thin film transistor according to embodiments of the present disclosure.
9 to 18 are diagrams of a manufacturing process of a thin film transistor according to embodiments of the present disclosure.
19 is an equivalent circuit of a subpixel according to embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the explanation of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g. level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g. process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a system configuration diagram of a display device 100 according to embodiments of the present disclosure.

Referring to FIG. 1 , a display device 100 according to embodiments of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110 .

The display panel 110 includes signal lines such as a plurality of data lines DL and a plurality of gate lines GL, and may include a plurality of subpixels SP. The display panel 110 may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed. In the display panel 110, a plurality of subpixels (SP) for displaying an image are disposed in the display area (DA), and the driving circuits 120, 130, and 140 are electrically connected to the non-display area (NDA). The driving circuits 120, 130, and 140 may be connected or mounted, and a pad portion to which an integrated circuit or printed circuit, etc., may be connected may be disposed.

The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

The data driving circuit 120 is a circuit for driving a plurality of data lines DL and can supply data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL and can supply gate signals to the plurality of gate lines GL.

The gate driving circuit 130 may output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive a plurality of gate lines GL by sequentially supplying a gate signal with a turn-on level voltage to the plurality of gate lines GL.

The controller 140 may supply a data control signal (DCS) to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may supply a gate control signal (GCS) to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

The controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120, and produces converted image data (Data). can be supplied to the data driving circuit 120, and data driving can be controlled at an appropriate time according to the scan.

The controller 140 controls the data driving circuit 120 and the gate driving circuit 130, including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE), and a clock signal ( A timing signal such as CLK) is input, various control signals (DCS, GCS) are generated and output to the data driving circuit 120 and the gate driving circuit 130.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data Data from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit. This data driving circuit 120 may include one or more source driver integrated circuits (SDIC). Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. In some cases, each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC).

For example, each source driver integrated circuit (SDIC) is connected to the display panel 110 using Tape Automated Bonding (TAB), Chip On Glass (COG), or Chip On Panel ( It may be connected to the bonding pad of the display panel 110 using a COP (Chip On Panel) method, or may be implemented using a Chip On Film (COF) method and connected to the display panel 110.

The gate driving circuit 130 is connected to the display panel 110 using a tape automated bonding (TAB) method, or is connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method. Pad) or may be connected to the display panel 110 according to the chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be of the GIP (Gate In Panel) type and may be formed in the non-display area NDA of the display panel 110.

When a specific gate line (GL) is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (Data) received from the controller 140 into an analog data voltage to generate a plurality of data lines. It can be supplied as (DL).

The data driving circuit 120 may be connected to one side (eg, the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The gate driving circuit 130 may be connected to one side (eg, left or right) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., left and right) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The controller 140 may be a timing controller 140 (Timing Controller) used in typical display technology, or a control device that further performs other control functions including the timing controller 140 (Timing Controller). It may be a control device different from the controller 140, or it may be a circuit within the control device. The controller 140 may be implemented with various circuits or electronic components, such as an Integrated Circuit (IC), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or Processor.

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc. The controller 140 may transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, and a Serial Peripheral Interface (SPI). The controller 140 may include one or more memory locations such as registers.

The display device 100 according to the present embodiments may be a self-luminous display such as an Organic Light Emitting Diode (OLED) display, a Quantum Dot display, or a Micro Light Emitting Diode (Micro LED) display.

FIG. 2 is an equivalent circuit of a subpixel (SP) of the display device 100 according to embodiments of the present disclosure.

Referring to FIG. 2, each of the plurality of subpixels (SP) disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure includes a light emitting element (ED), a driving transistor (DRT), and a scan function. It may include a transistor (SCT), a sensing transistor (SENT), and a storage capacitor (Cst). As such, when the subpixel (SP) includes three transistors (DRT, SCT, SENT) and one capacitor (Cst), the subpixel (SP) is said to have a 3T (Transistor) 1C (Capacitor) structure. .

The light emitting device (ED) may include a pixel electrode (PE) and a common electrode (CE), and a light emitting layer (EL) located between the pixel electrode (PE) and the common electrode (CE). Here, the pixel electrode (PE) may be disposed in each subpixel (SP), and the common electrode (CE) may be commonly disposed in multiple subpixels (SP). For example, the pixel electrode (PE) may be an anode electrode, and the common electrode (CE) may be a cathode electrode. For another example, the pixel electrode (PE) may be a cathode electrode, and the common electrode (CE) may be an anode electrode. For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a micro light emitting diode (micro LED), or a quantum dot light emitting device (ED).

The driving transistor DRT is a transistor for driving the light emitting device ED and may include a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to the source node or drain node of the scan transistor SCT. The second node (N2) of the driving transistor (DRT) may be a source node or a drain node of the driving transistor (DRT), is electrically connected to the source node or drain node of the sensing transistor (SENT), and is connected to the light emitting element (ED). It can also be electrically connected to the pixel electrode (PE) of . The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL that supplies the driving voltage EVDD.

The scan transistor (SCT) is controlled by the scan signal (SCAN) and may be connected between the first node (N1) of the driving transistor (DRT) and the data line (DL). The scan transistor (SCT) is turned on or off according to the scan signal (SCAN) supplied from the scan signal line (SCL), a type of gate line (GL), and is connected to the data line (DL) and the driving transistor ( The connection between the first nodes (N1) of the DRT) can be controlled.

The scan transistor (SCT) is turned on by the scan signal (SCAN) having a turn-on level voltage, and transmits the data voltage (Vdata) supplied from the data line (DL) to the first node ( It can be passed on to N1).

The turn-on level voltage of the scan signal (SCAN) that can turn on the scan transistor (SCT) may be a high level voltage or a low level voltage. The turn-off level voltage of the scan signal (SCAN) that can turn off the scan transistor (SCT) may be a low level voltage or a high level voltage. For example, when the scan transistor (SCT) is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, when the scan transistor (SCT) is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The sensing transistor SENT is controlled by the sense signal SENSE and may be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. The sensing transistor (SENT) is turned on or turned off according to the sense signal (SENSE) supplied from the sense signal line (SENL), which is another type of gate line (GL), and is driven with the reference voltage line (RVL). The connection between the second nodes (N2) of the transistor (DRT) can be controlled.

The sensing transistor (SENT) is turned on by the sense signal (SENSE) having a turn-on level voltage, and applies the reference voltage (Vref) supplied from the reference voltage line (RVL) to the second node of the driving transistor (DRT). You can forward it to (N2).

The turn-on level voltage of the sense signal (SENSE) that can turn on the sensing transistor (SENT) may be a high level voltage or a low level voltage. The turn-off level voltage of the sense signal (SENSE) that can turn off the sensing transistor (SENT) may be a low level voltage or a high level voltage. For example, when the sensing transistor SENT is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, when the sensing transistor SENT is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

Meanwhile, the display device 100 includes a line capacitor (Crvl) formed between the reference voltage line (RVL) and the ground (GND), and a sampling switch ( It may further include a power switch (SPRE) that controls the connection between the SAM), the reference voltage line (RVL), and the reference voltage supply node (Nref). The reference voltage (Vref) output from the power supply device is supplied to the reference voltage supply node (Nref) and may be applied to the reference voltage line (RVL) through the power switch (SPRE).

In addition, the sensing transistor (SENT) is turned on by the sense signal (SENSE) having a turn-on level voltage, so that the voltage (V2) of the second node (N2) of the driving transistor (DRT) is connected to the reference voltage line ( RVL). Accordingly, the line capacitor Crvl formed between the reference voltage line RVL and the ground (GND) may be charged.

The function of the sensing transistor (SENT) to transfer the voltage (V2) of the second node (N2) of the driving transistor (DRT) to the reference voltage line (RVL) can be used when driving to sense the characteristics of the subpixel (SP). You can. In this case, the voltage transmitted to the reference voltage line RVL may be a voltage for calculating the characteristic value of the subpixel SP or a voltage reflecting the characteristic value of the subpixel SP.

In the present disclosure, the characteristic values of the subpixel (SP) may be the characteristic values of the driving transistor (DRT) or the light emitting element (ED). Characteristic values of the driving transistor (DRT) may include threshold voltage and mobility of the driving transistor (DRT). The characteristic value of the light emitting device (ED) may include the threshold voltage of the light emitting device (ED).

Each of the driving transistor (DRT), scan transistor (SCT), and sensing transistor (SENT) may be an n-type transistor or a p-type transistor. In this disclosure, for convenience of explanation, the driving transistor (DRT), scan transistor (SCT), and sensing transistor (SENT) are each n-type as an example.

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor (Cst) is charged with a charge corresponding to the voltage difference between both ends and plays the role of maintaining the voltage difference between both ends for a set frame time. Accordingly, the corresponding subpixel (SP) may emit light during a set frame time.

The storage capacitor (Cst) is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor that exists between the gate node and the source node (or drain node) of the driving transistor (DRT). ) may be an external capacitor intentionally designed outside of the capacitor.

The scan signal line (SCL) and the sense signal line (SENL) may be different gate lines (GL). In this case, the scan signal (SCAN) and the sense signal (SENSE) may be separate gate signals, and the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) Off timing can be independent. That is, the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same or different.

Alternatively, the scan signal line (SCL) and the sense signal line (SENL) may be the same gate line (GL). That is, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) within one subpixel (SP) may be connected to one gate line (GL). In this case, the scan signal (SCAN) and the sense signal (SENSE) may be the same gate signal, and the on-off timing of the scan transistor (SCT) and the on-off timing of the sensing transistor (SENT) in one subpixel (SP) may be the same.

Meanwhile, the reference voltage line RVL may be arranged in each subpixel SP column. Alternatively, the reference voltage line (RVL) may be arranged in every two or more subpixel (SP) columns. When the reference voltage line RVL is arranged in each column of two or more subpixels SP, the plurality of subpixels SP may receive the reference voltage Vref from one reference voltage line RVL.

Meanwhile, the performance of a transistor can be evaluated by the S-Factor. S-Factor is an indicator that indicates the amount of gate voltage change required to increase the drain current (Id) by 10 times. This is also called Subthreshold Swing (SS).

The larger the S-Factor of the driving transistor (DRT), the more advantageous it is for expressing gray scale.

Depending on the structure in which the transistor is formed, the S-Factor can be improved. Below, the shape of the transistor will be described in detail.

Figure 3 is a cross-sectional view of a thin film transistor 300 according to embodiments of the present disclosure.

The thin film transistor 300 may be the driving transistor (DRT), scan transistor (SCT), or sensing transistor (SENT) described above. That is, the transistor included in the subpixel SP may be formed in the structure of the thin film transistor 300.

The thin film transistor 300 includes a substrate 310, an electrode layer 320, a buffer layer 330, an active layer 340, a gate insulating layer 350, a gate electrode 360, a first interlayer insulating layer 370, and a first interlayer insulating layer 370. It may include two interlayer insulating layers 380, a source electrode 391, and a drain electrode 392.

The substrate 310 may be placed at the bottom of the thin film transistor 300.

The substrate 310 may support components to be formed on the substrate 310 .

The substrate 310 may be made of glass or a flexible plastic material. If the substrate 310 is made of a plastic material, for example, it may be made of polyimide (PI).

The substrate 310 may be formed into one substrate by bonding two or more substrates.

An insulating layer (not shown) may be formed between the substrate 310 and the electrode layer 320. The insulating layer (not shown) can prevent penetration of moisture or impurities. It may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The electrode layer 320 may be formed on the substrate 310 .

The electrode layer 320 may block electromagnetic waves or external light incident from the outside.

The electrode layer 320 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of alloy.

The buffer layer 330 may be formed on top of the electrode layer 320.

The buffer layer 330 may insulate the electrode layer 320 and the active layer 340.

The buffer layer 330 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The active layer 340 may be formed on top of the buffer layer 330.

The active layer 340 may be an area where a channel is formed when the thin film transistor 300 is driven.

The active layer 340 may be formed of any one of indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO), and indium-zinc oxide (IZO).

The active layer 340 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

The gate insulating layer 350 may be formed on top of the active layer 340.

The gate insulating layer 350 may insulate the active layer 340 and the gate electrode 360.

The gate insulating layer 350 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The gate electrode 360 may be formed on top of the gate insulating layer 350.

The gate electrode 360 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

The first interlayer insulating layer 370 may be formed on top of the gate electrode 360.

The first interlayer insulating layer 370 may insulate the gate electrode 360 and the second interlayer insulating layer 380.

The first interlayer insulating layer 370 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The second interlayer insulating layer 380 may be formed on top of the first interlayer insulating layer 370.

The second interlayer insulating layer 380 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The source electrode 391 may be formed on the second interlayer insulating layer 380.

The first contact hole C1 may be an area where the gate insulating layer 350, the first interlayer insulating layer 370, and the second interlayer insulating layer 380 are etched.

The source electrode 391 may be formed in the first contact hole C1 and electrically connected to the active layer 340.

The source electrode 391 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

Although not shown in the cross-sectional view of FIG. 3, the source electrode 391 may be electrically connected to the electrode layer 320.

The drain electrode 392 may be formed on top of the second interlayer insulating layer 380.

The second contact hole C2 may be an area where the gate insulating layer 350, the first interlayer insulating layer 370, and the second interlayer insulating layer 380 are etched.

The drain electrode 392 may be formed in the second contact hole C2 and electrically connected to the active layer 340.

The drain electrode 392 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

Meanwhile, the active layer 340 may be disposed to overlap the gate electrode 360 and the electrode layer 320. The buffer layer 330 may be formed between the electrode layer 320 and the active layer 340. A first capacitance may be formed between the gate electrode 360 and the active layer 340 by placing the gate insulating layer 350. A second capacitance may be formed with a buffer layer 330 between the active layer 340 and the electrode layer 320.

Between the first capacitance and the second capacitance, the voltage distribution law of capacitance may be applied. When compared to the voltage formed between the gate electrode 360 and the active layer 340 when the second capacitance is not formed, the voltage formed between the gate electrode 360 and the active layer 340 when the second capacitance is formed. The resulting voltage is reduced according to the voltage division principle. Accordingly, the S-Factor of the thin film transistor 300 can be increased. The thinner the buffer layer 330 is, the larger the second capacitance can be, so the S-factor of the thin film transistor 300 can be further increased.

However, there is a limit to the thickness that can make the buffer layer 330 thin, so there is a limit to increasing the S-factor of the thin film transistor 300 as a method of thinning the buffer layer 330.

Accordingly, embodiments of the present disclosure can provide a thin film transistor and a display panel capable of improving S-Factor. This will be explained in detail below.

4 to 6 are cross-sectional views of the thin film transistor 400 according to embodiments of the present disclosure.

The thin film transistor 400 may be the driving transistor (DRT), scan transistor (SCT), or sensing transistor (SENT) described above. That is, the transistor included in the subpixel SP may be formed in the structure of the thin film transistor 400.

Referring to FIG. 4, the thin film transistor 400 includes a substrate 410, an electrode layer 420, a buffer layer 430, an active layer 440, a gate insulating layer 450, a gate electrode 460, and a first interlayer insulation. It may include a layer 470, a second interlayer insulating layer 480, a source electrode 491, and a drain electrode 492.

The substrate 410 may be placed at the bottom of the thin film transistor 400.

The substrate 410 may support components to be formed on the substrate 410 .

The substrate 410 may be made of glass or a flexible plastic material. If the substrate 410 is made of a plastic material, for example, it may be made of polyimide (PI).

The substrate 410 may be composed of two or more substrates bonded together or divided into two or more layers.

An insulating layer (not shown) may be formed between the substrate 410 and the electrode layer 420. The insulating layer (not shown) can prevent penetration of moisture or impurities. It may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The electrode layer 420 may be formed on the substrate 410 .

The electrode layer 420 may block electromagnetic waves or external light incident from the outside.

The electrode layer 420 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of alloy.

The buffer layer 430 may be formed on top of the electrode layer 420.

The buffer layer 430 may insulate the electrode layer 420 and the active layer 440.

The buffer layer 430 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The upper surface of the buffer layer 430 may include a protruding upper surface that protrudes upward. The height of the non-protruding upper surface may be H1, and the height of the protruding upper surface may be H2. That is, the buffer layer 430 may include a buffer part 431 and a protruding buffer part 432.

The buffer portion 431 and the protruding buffer portion 432 are integrated and may include the same material.

The buffer portion 431 may be formed on top of the electrode layer 420.

The buffer unit 431 may be the same as the buffer layer 330 shown in FIG. 3.

The protruding buffer part 432 may be formed on the upper part of the buffer part 431. The protruding buffer part 432 may be formed between the buffer part 431 and the gate electrode 460. A protruding top surface of the buffer layer 430 may overlap the gate electrode 460. The width of the protruding top surface of the buffer layer 430 may be narrower than the width of the gate electrode 460.

Since the buffer layer 430 includes a buffer portion 431 and a protruding buffer portion 432, the shape of the buffer layer 430 may be a “ㅗ” shape or an inverted “T” shape.

The side surface of the protruding buffer portion 432 may be inclined. That is, the protruding buffer part 432 may include a flat buffer part 432a and inclined buffer parts 432b and 432c formed at a predetermined angle TA on both sides of the flat buffer part 432a. In other words, the protruding buffer unit 432 may have a positive taper shape as the side of the protruding buffer unit 432 is inclined, and may have a trapezoidal shape.

The inclined buffer unit includes a right inclined buffer unit 432b inclined from the top of the flat buffer unit 432a to the lower right direction and a left inclined buffer unit 432c inclined from the top of the flat buffer unit 432a to the lower left direction. can do.

The right inclined buffer portion 432b may be formed to be inclined at a predetermined angle TA between the bottom surface and the right side. If the side surface is formed in an “L” or “L” shape, it may have a right triangle shape, and this shape may be the shape of the right inclined buffer unit 432b.

The left inclined buffer portion 432c may be formed to be inclined at a predetermined angle TA between the bottom surface and the left side. If the sides are formed in the shape of “L” or “ㄴ” flipped left and right, it may be in the shape of a right triangle, and this shape may be the shape of the left inclined buffer unit 432c.

The buffer part 431, the protruding buffer part 432, the flat buffer part 432a, the right slope buffer part 432b, and the left slope buffer part 432c included in the buffer layer 430 are separated for convenience of explanation. Although described, it may be integral and formed of the same material.

The active layer 440 may be formed on top of the buffer layer 430.

The active layer 440 may be an area where a channel is formed when the thin film transistor 400 is driven.

The active layer 440 may be formed of any one of indium-gallium-zinc oxide (IGZO), indium-gallium oxide (IGO), and indium-zinc oxide (IZO).

The active layer 440 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

The active layer 440 may include a first active layer 441, a second active layer 442, and a third active layer 443.

The first active layer 441 may be formed on the upper surface of the buffer unit 431.

The second active layer 442 may be formed on the upper surfaces of the slope buffer parts 432b and 432c. Therefore, the second active layer 442 may be formed in a shape inclined at a predetermined angle TA.

The third active layer 443 may be formed on the upper surface of the flat buffer portion 432a. That is, the active layer 440 may be formed in a concave-convex shape.

The gate insulating layer 450 may be formed on top of the active layer 440.

The gate insulating layer 450 may insulate the active layer 440 and the gate electrode 460.

The gate insulating layer 450 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The gate electrode 460 may be formed on top of the gate insulating layer 450.

The gate electrode 460 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

The first interlayer insulating layer 470 may be formed on top of the gate electrode 460.

The first interlayer insulating layer 470 may insulate the gate electrode 460 and the second interlayer insulating layer 480.

The first interlayer insulating layer 470 may be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

The second interlayer insulating layer 480 may be formed on top of the first interlayer insulating layer 470.

The second interlayer insulating layer 480 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

The source electrode 491 may be formed on the second interlayer insulating layer 480.

The first contact hole C1 may be an area where the gate insulating layer 450, the first interlayer insulating layer 470, and the second interlayer insulating layer 480 are etched.

The source electrode 491 may be formed in the first contact hole C1 and electrically connected to the active layer 440.

The source electrode 491 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

Although not shown in the cross-sectional view of FIG. 4, the source electrode 491 may be electrically connected to the electrode layer 420.

The drain electrode 492 may be formed on top of the second interlayer insulating layer 480.

The second contact hole C2 may be an area where the gate insulating layer 450, the first interlayer insulating layer 470, and the second interlayer insulating layer 480 are etched.

The drain electrode 392 may be formed in the second contact hole C2 and electrically connected to the active layer 340.

The drain electrode 392 is made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). It can be formed as a single layer or multiple layers made of an alloy.

Meanwhile, the thin film transistor 300 includes a first area A1 in which the protruding buffer part 432 is formed, and a second area A2 that is an area to the right of the first area A1 and in which the protruding buffer part 432 is not formed. and a third area A3, which is an area to the left of the first area A1 and in which the protruding buffer portion 432 is not formed.

Since the protruding buffer portion 432 may be formed on the upper surface of the buffer portion 431, the height H2 of the buffer layer 430 in the first area A1 is equal to the height H2 of the second area A2 and the third area A3. ) may be higher than the height (H1) of the buffer layer 430 at .

The active layer 440, the gate insulating layer 450, the gate electrode 460, the first interlayer insulating layer 470, and the second interlayer insulating layer 480 each have a buffer layer 430 including a protruding buffer portion 432. ) can be formed sequentially on the upper surface of. That is, since it is laminated on the buffer layer 430 having a protruding shape, the active layer 440, the gate insulating layer 450, the gate electrode 460, the first interlayer insulating layer 470, and the second interlayer insulating layer. (480) Each may be formed to protrude toward the top of the protruding buffer portion 432.

The thickness of the first area A1 of the buffer layer 430 may be thicker than the thickness of the second area A2 of the buffer layer 430. The thickness of the first area A1 of the buffer layer 430 may be thicker than the thickness of the third area A3 of the buffer layer 430. As the thickness of the first area A1 of the buffer layer 430 is thick, the capacitance formed in the first area A1 may be relatively smaller than the capacitance formed in the second area A2 and the third area A3. Depending on the relative capacitance difference, the gate voltage (Vgs) formed in each area (A1, A2, A3) may be different. The gate voltage Vgs of the first region may be relatively the highest, and the number of carriers in the channel formed in the first region A1 may increase, thereby increasing the carrier concentration. Since the carriers of the channels formed in the second area A2 and the third area A3 are relatively smaller than those in the first area A1, the drain current (Ids) of the thin film transistor 400 ) can be reduced. Accordingly, the S-Factor of the thin film transistor 400 can be improved.

The S-Factor can be improved by thinning the thickness of the buffer layer 430, and in addition, the S-Factor can be further improved depending on the shape of the protruding buffer layer 430. You can. That is, the extent to which the S-Factor of the thin film transistor 400 is improved may be determined depending on the shape of the protruding buffer portion 432 of the thin film transistor 400. Referring to FIGS. 5 and 6 , various shapes of the protruding buffer portion 432 of the thin film transistor 400 can be seen.

Referring to FIG. 5 , an enlarged cross-sectional view of the protruding buffer portion 432 of the thin film transistor 400 shown in FIG. 4 can be seen.

Referring to FIG. 5, the height of the protruding buffer portion 432 may be designed and formed in various ways.

The height of the protruding buffer portion 432 shown in Case A shown in FIG. 5 may be H3.

The height of the protruding buffer portion 432 shown in Case B shown in FIG. 5 may be H3′.

The size of H3 can be larger than H3`. That is, the height H3' of the protruding buffer unit 432 shown in Case B may be greater than the height H3 of the protruding buffer unit 432 shown in Case A.

Referring to FIG. 6, an enlarged cross-sectional view of the protruding buffer portion 432 of the thin film transistor 400 shown in FIG. 4 can be seen.

Referring to FIG. 6, the right inclined buffer unit 432b can be confirmed. The right inclined buffer portion 432b may be formed with various designs at a predetermined angle TA.

Referring to Cases 1 to 5 shown in FIG. 6, the predetermined angle TA may be formed to be 90 degrees or less.

In Case 1, the predetermined angle TA is formed at 90 degrees, so the right inclined buffer portion 432b may not be formed. The left gradient buffer unit 432c is not shown, but may not be formed similarly to the right gradient buffer unit 432b. That is, the protruding buffer portion 432 may have a rectangular shape.

Referring to Cases 2 to 5, it can be seen that the predetermined angle (TA) can be formed to be smaller than 90 degrees. As the predetermined angle TA becomes smaller, the area of the lower surface of the right inclined buffer portion 432b can become larger.

The left slope buffer unit 432c is not shown in FIG. 6, but may have the same shape as the right slope buffer unit 432b.

Although not shown in FIG. 6, the upper surface of the buffer layer 430 may include a plurality of protruding upper surfaces that form a predetermined angle and protrude upward by a predetermined height. The above-described predetermined angle may include a first tilt and a second tilt. Each of the plurality of protruding upper surfaces may overlap the gate electrode 460 of each of the plurality of transistors. Side surfaces of the protruding upper surfaces of each of the plurality of transistors may have different slopes (TA). The plurality of transistors may include a first transistor and a second transistor. The slope (TA) of the side of the protruding top surface of the first transistor may be the first slope, and the slope (TA) of the side of the protruding top surface of the second transistor may be the second slope, and the first slope may be greater than the second slope. there is. The S-Factor of the transistor may be greater in the first slope than in the second slope.

Figure 7 is a graph regarding the S-Factor of the thin film transistor 400 according to embodiments of the present disclosure.

The graph axis shown in FIG. 7 has Vgs[V] as the x-axis and log(Ids)[A] as the y-axis.

The graph shown in FIG. 7 is a graph showing the change in log(Ids)[A] as Vgs[V] increases. As Vgs[V] rises, log(Ids)[A] may rise.

Referring to FIG. 7, you can see graphs of five experimental examples (Case71, Case72, Case73, Case74, and Case75). The five experimental examples (Case71, Case72, Case73, Case74, and Case75) are experimental examples in which the height of the flat buffer part 432a is the same, but the predetermined angle (TA) of the inclined buffer part 432b and 432c is changed. . Among the five experimental examples, the first experimental example (Case 71) is the experimental example in which the predetermined angle (TA) is the smallest. Among the five experimental examples, the fifth experimental example (Case 75) is the experimental example with the largest predetermined angle (TA). Since the predetermined angle TA may be 90 degrees or less, the predetermined angle TA in the fifth experimental example (Case 75) may be 90 degrees. If the predetermined angles (TA) in the five experimental examples (Case71, Case72, Case73, Case74, Case75) are respectively TA71, TA72, TA73, TA74, and TA75, the size of the predetermined angle (TA) is TA71 < TA72 < TA73 < TA74 < TA75.

Referring to the graphs of the five experimental examples (Case71, Case72, Case73, Case74, Case75), the degree of increase in log(Ids)[A] as Vgs[V] increases may be different. The smaller the degree of increase in log(Ids)[A] as Vgs[V] increases, the greater the S-Factor.

That is, the S-Factor of the first experimental example (Case71) may be the smallest, and the S-Factor of the fifth experimental example (Case75) may be the largest.

Therefore, referring to the five experimental examples of FIG. 7 and FIG. 6, as the predetermined angle TA of the gradient buffer unit 432b increases, the S-Factor may increase. When the predetermined angle TA of the tilt buffer unit 432b is formed at 90 degrees, the increase in S-Factor may be greatest. When the predetermined angle TA is formed at 90 degrees, the protruding buffer portion 432 may have a rectangular shape.

Referring to the five experimental examples of FIG. 7 and FIG. 6, the larger the predetermined angle TA of the gradient buffer unit 432b, the larger the S-factor of the thin film transistor 400 may be, and the gradient buffer unit 432b may have a larger S-factor. As the predetermined angle TA of 432b is smaller, the S-factor of the thin film transistor 400 may be smaller. Although not shown in FIG. 6, the upper surface of the buffer layer 430 may include a plurality of protruding upper surfaces that protrude upward by a predetermined height. Each of the plurality of protruding upper surfaces may overlap the gate electrode 460 of each of the plurality of transistors. Referring to FIG. 2 , the subpixel SP may include a driving transistor (DRT) for driving the light emitting element (ED), a scan transistor (SCT) for a switching function, and a sensing transistor (SENT). A thin film transistor with a large S-Factor may be a transistor for driving a light emitting device (ED), and a thin film transistor with a small S-Factor may be a transistor for a switching function. That is, the lateral inclination of the protruding buffer unit 432 of the driving transistor DRT may be greater than the lateral inclination of the protruding buffer unit 432 of the transistor performing the switching function.

FIG. 8 is a graph regarding the S-Factor of the thin film transistor 400 according to embodiments of the present disclosure.

The graph axis shown in FIG. 8 has Vgs[V] as the x-axis and log(Ids)[A] as the y-axis.

The graph shown in FIG. 8 is a graph showing the change in log(Ids)[A] as Vgs[V] increases. As Vgs[V] rises, log(Ids)[A] may rise.

Referring to FIG. 8, you can see graphs of five experimental examples (Case81, Case82, Case83, Case84, and Case85). Five experimental examples (Case81, Case82, Case83, Case84, Case85) are experimental examples in which the predetermined angles (TA) of the inclined buffer parts 432b and 432c are the same, but the height of the flat buffer part 432a is changed. admit. Among the five experimental examples, the first experimental example (Case81) is an experimental example in which the height of the flat buffer portion 432a is the lowest. Among the five experimental examples, the fifth experimental example (Case85) is an experimental example in which the height of the flat buffer portion 432a is the highest. If the heights of the flat buffer portion 432a in the five experimental examples (Case81, Case82, Case83, Case84, and Case85) are respectively H81, H82, H83, H84, and H85, the height sizes are H81 < H82 < H83 < H84 < Could be H85.

Referring to the graphs of the five experimental examples (Case81, Case82, Case83, Case84, Case85), the degree of increase in log(Ids)[A] as Vgs[V] increases may be different. The smaller the degree of increase in log(Ids)[A] as Vgs[V] increases, the greater the S-Factor.

That is, the S-Factor of the first experimental example (Case81) may be the smallest, and the S-Factor of the fifth experimental example (Case85) may be the largest.

Therefore, referring to the five experimental examples of FIG. 8 and FIG. 5, as the height of the flat buffer portion 432a increases, the increase in S-Factor may be greatest.

Referring to FIGS. 7 and 8 , as the height of the flat buffer portion 432a increases, the increase in S-Factor may be greatest.

9 to 18 are diagrams of the manufacturing process of the thin film transistor 400 according to embodiments of the present disclosure.

9 to 17 show a substrate 410, an electrode layer 420, a buffer layer 430, an active layer 440, a gate insulating layer 450, a gate electrode 460, and a first transistor included in the thin film transistor 400. This is a diagram relating to the manufacturing process of the interlayer insulating layer 470, the second interlayer insulating layer 480, the source electrode 491, and the drain electrode 492. Substrate 410, electrode layer 420, buffer layer 430, active layer 440, gate insulating layer 450, gate electrode 460, first interlayer insulating layer 470, second interlayer insulating layer 480 ), the characteristics of the source electrode 491 and the drain electrode 492 may be the same as those described above with reference to FIG. 4.

9 to 17, the A-A' direction is shown, which may be a horizontal direction. A direction perpendicular to the horizontal direction may be a vertical direction. And the top and bottom directions of the transistor 400 may be up and down.

Referring to FIG. 9, first, a substrate 410 may be formed.

After the substrate 410 is formed, an electrode layer 420 may be formed on top of the substrate 410. The electrode layer 420 may be formed on a portion of the substrate 410. The electrode layer 420 may be formed to expose portions of both ends of the substrate 410 in the vertical direction.

After the electrode layer 420 is formed, the buffer layer 430 may be formed on top of the electrode layer 420. The buffer layer 430 may be formed to cover both the substrate 410 and the upper portion of the electrode layer 420.

After the buffer layer 430 is formed, photo resist PR may be formed on top of the buffer layer 430. Photo resist PR may be formed to cover the entire upper portion of the buffer layer 430.

Referring to FIG. 10, a portion of the photo resist (PR) may be removed by patterning. In order for the buffer layer 430 to be formed as the protruding buffer portion 432, the photo resist PR may be removed from both sides in the horizontal direction based on the horizontal center of the buffer layer 430. The shape of the remaining photoresist (PR`) may be an “H” shape based on the horizontal direction. In other words, the remaining photoresist (PR`) may exist at both ends in the vertical direction.

After a process in which part of the photo resist (PR) is removed, a positive photo resist process may be performed. When a positive photoresist process is performed, etching may occur in areas where there is no photoresist PR′, thereby removing a portion of the buffer layer 430. That is, the buffer layer 430 may have a structure including a buffer part 431 and a protruding buffer part 432. The buffer portion 431 and the protruding buffer portion 432 are integrated and may include the same material. However, it is not limited to the photoresist method described above, and any method capable of etching the buffer layer 430 may be used.

Referring to FIG. 11, photo resist PR′ can be removed.

After the photo resist PR′ is removed, an active electrode may be formed on the entire surface of the buffer layer 430. After the active electrode is formed, the active electrode may be patterned to become the active layer 440. The active layer 440 is not formed at both ends in the vertical direction, so the buffer layer 430 may be exposed at that portion. Referring to FIG. 18 , the length covered by the active layer 440 in the vertical direction may be shorter than the length of the electrode layer 420 in the vertical direction.

Referring to FIG. 12, the gate insulating layer 450 may be formed to cover both the upper portions of the active layer 440 and the buffer layer 430.

After the gate insulating layer 450 is formed, the gate electrode layer GL may be formed on top of the gate insulating layer 450.

Referring to FIG. 13, the gate electrode layer GL may be patterned to become the gate electrode 460. Referring to FIG. 18 , the gate electrode 460 may be formed at a location that entirely covers the protruding buffer portion 432 . That is, the gate electrode 460 may be formed to overlap the protruding buffer portion 432.

After the gate electrode 460 is formed, the active layer 440 may undergo a conductive process.

Referring to FIG. 14, the first interlayer insulating layer 470 may be formed to cover both the gate electrode 460 and the upper portion of the gate insulating layer 450.

After the first interlayer insulating layer 470 is formed, the second interlayer insulating layer 480 may be formed on top of the first interlayer insulating layer 470.

Referring to FIG. 15, a first contact hole C1 and a second contact hole C2 may be formed. The first contact hole C1 may be an area where the gate insulating layer 450, the first interlayer insulating layer 470, and the second interlayer insulating layer 480 are etched. The second contact hole C2 may be an area where the gate insulating layer 350, the first interlayer insulating layer 370, and the second interlayer insulating layer 380 are etched.

Referring to FIG. 16, after the process of forming the first contact hole C1 and the second contact hole C2, the electrode layer 490 may be formed to cover the entire upper portion of the thin film transistor 400.

Referring to FIG. 17, after the electrode layer 490 is formed, the electrode layer 490 may be patterned. The electrode layer 490 may be patterned to cover the top of the first contact hole C1 and the second contact hole C2. At this time, referring to FIG. 18 , the patterned electrode layer 490 may be a source electrode 491 formed on the first contact hole C1 and a drain electrode 492 formed on the second contact hole C2.

19 is an equivalent circuit of a subpixel according to embodiments of the present disclosure.

Descriptions of the same features among the features of the equivalent circuit of the subpixel shown in FIG. 19 and the features of the equivalent circuit of the subpixel shown in FIG. 2 may be omitted.

Referring to FIG. 19 , the display panel 110 according to embodiments of the present disclosure may include a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of gate lines (GL). Each of the plurality of subpixels (SP) may include a light emitting element (ED) and a plurality of transistors.

The plurality of transistors may include a driving transistor (DRT) for driving the light emitting device (ED) and a switching transistor for switching the connection between the gate node of the driving transistor (DRT) and the data line (DL). The switching transistor may be a scan transistor (SCT).

The cross-sectional view of each of the plurality of transistors may be the same as the cross-sectional view of the thin film transistor 400 shown in FIG. 6. A plurality of transistors may be formed on the buffer layer 430 formed on the substrate 410. Each of the plurality of transistors may include an active layer 440 on the buffer layer 430, a gate insulating layer 450 on the active layer 440, and a gate electrode 460 on the gate insulating layer 450. The upper surface of the buffer layer 430 may include a plurality of protruding upper surfaces that protrude upward by a predetermined height. Each of the plurality of protruding upper surfaces may overlap the gate electrode 460 of each of the plurality of transistors.

Referring to FIG. 19, the plurality of protruding upper surfaces may include a first protruding upper surface overlapping the gate electrode 461 of the driving transistor (DRT), and a side surface of the first protruding upper surface may have a first slope TA1. You can. Referring to FIG. 19, the plurality of protruding upper surfaces may include a second protruding upper surface overlapping the gate electrode 462 of the scan transistor (SCT), and a side of the second protruding upper surface may have a second slope TA2. You can.

The first slope TA1 and the second slope TA2 may have different slopes. The first slope TA1 may be greater than the second slope TA2. As the first slope (TA1) is greater than the second slope (TA2), the S-Factor value of the driving transistor (DRT) is greater than the S-Factor value of the scan transistor (SCT). It can be big.

In other words, the plurality of transistors may include a first transistor and a second transistor. Depending on the slope of the protruding upper surface of the buffer layer 430 that overlaps each of the first transistor and the second transistor, the first transistor and the second transistor may have different S-factor values.

According to the embodiments of the present disclosure described above, a thin film transistor and a display panel capable of improving S-Factor can be provided.

According to embodiments of the present disclosure, a thin film transistor and a display panel that can be driven at low power can be provided as the S-factor is improved.

The embodiments of the present disclosure described above are briefly described as follows.

According to embodiments of the present disclosure, it includes a substrate, a buffer layer on the substrate, an active layer on the buffer layer, and a gate insulating layer on the active layer, and the buffer layer includes a buffer portion and a protruding buffer portion that protrudes upward from the buffer portion by a predetermined height. In addition, a thin film transistor having an inclined side surface of the protruding buffer portion can be provided.

The protruding buffer portion may have a positive taper shape.

The protruding buffer portion may have a rectangular shape.

The protruding buffer portion may include a flat buffer portion and an inclined buffer portion formed at a predetermined angle on both sides of the flat buffer portion.

The inclined buffer unit may include a right inclined buffer unit inclined from the top of the flat buffer unit to the lower right direction and a left inclined buffer unit inclined from the top of the flat buffer unit to the lower left direction.

It further includes a gate electrode formed on the buffer layer, and the width of the protruding buffer portion may be narrower than the width of the gate electrode.

It may include a first area where the protruding buffer unit and the gate electrode overlap, and a second area where the protruding buffer unit and the gate electrode do not overlap.

The height of the buffer layer in the first area may be higher than the height of the buffer layer in the second area.

The buffer portion and the protruding buffer portion may be integrated and include the same material.

An electrode layer is included between the substrate and the buffer layer, and the electrode layer and the source electrode may be electrically connected.

According to embodiments of the present disclosure, it includes a substrate, a buffer layer on the substrate, and a plurality of transistors on the buffer layer, and each of the plurality of transistors includes an active layer on the buffer layer, a gate insulating film on the active layer, and a gate electrode on the gate insulating film, The upper surface of the buffer layer forms a predetermined angle and includes a plurality of protruding upper surfaces that protrude upward by a predetermined height, each of the plurality of protruding upper surfaces overlaps the gate electrode of each of the plurality of transistors, and the predetermined angle is determined by the first slope and the first slope. A display panel including a second slope different from the first slope may be provided.

The plurality of transistors include a first transistor, the plurality of protruding top surfaces include a first protruding top surface that overlaps the gate electrode of the first transistor, and a side surface of the first protruding top surface may have a first slope.

The plurality of transistors include a second transistor, the plurality of protruding top surfaces include a second protruding top surface overlapping the gate electrode of the second transistor, and a side surface of the second protruding top surface may have a second slope.

The first slope may be greater than the second slope.

The first transistor may have an S-factor value greater than the S-factor value of the second transistor.

It further includes a plurality of data lines, a plurality of gate lines, a plurality of subpixels connected to the plurality of data lines and a plurality of gate lines, each of the plurality of subpixels includes a light emitting element, a driving transistor for driving the light emitting element, and a driving transistor. It may include a switching transistor that switches the connection between the gate node of the transistor and the data line, where the first transistor may be a driving transistor and the second transistor may be a switching transistor.

The above description is merely an illustrative explanation of the technical idea of the present disclosure, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but rather are for explanation, and therefore the scope of the technical idea of the present disclosure is not limited by these embodiments.

100: display device
110: display panel
120: data driving circuit
130: Gate driving circuit
140: controller

Claims (16)

Board;
a buffer layer on the substrate;
an active layer on the buffer layer; and
Comprising a gate insulating layer on the active layer,
The buffer layer includes a buffer portion and a protruding buffer portion protruding upward from the buffer portion by a predetermined height,
A thin film transistor in which a side surface of the protruding buffer portion is inclined.
According to paragraph 1,
The protruding buffer portion is a thin film transistor having a positive taper shape.
According to paragraph 1,
The protruding buffer portion is a thin film transistor having a rectangular shape.
According to paragraph 1,
The protruding buffer part is a thin film transistor including a flat buffer part and an inclined buffer part formed at a predetermined angle on both sides of the flat buffer part.
According to paragraph 4,
The gradient buffer unit includes a right gradient buffer unit inclined from the top of the flat buffer unit to a lower right direction and a left gradient buffer unit inclined from the top of the flat buffer unit to the lower left direction.
According to paragraph 1,
It further includes a gate electrode formed on the buffer layer,
A thin film transistor wherein the protruding buffer portion has a width narrower than the width of the gate electrode.
According to clause 6,
A thin film transistor including a first region where the protruding buffer portion and the gate electrode overlap, and a second region where the protruding buffer portion and the gate electrode do not overlap.
In clause 7,
A thin film transistor wherein the height of the buffer layer in the first area is higher than the height of the buffer layer in the second area.
According to paragraph 1,
A thin film transistor wherein the buffer unit and the protruding buffer unit are integrated and contain the same material.
According to paragraph 1,
It includes an electrode layer between the substrate and the buffer layer,
A thin film transistor wherein the electrode layer and the source electrode are electrically connected.
Board;
a buffer layer on the substrate; and
Includes a plurality of transistors on the buffer layer,
Each of the plurality of transistors includes an active layer on the buffer layer, a gate insulating film on the active layer, and a gate electrode on the gate insulating film,
The upper surface of the buffer layer forms a predetermined angle and includes a plurality of protruding upper surfaces that protrude upward by a predetermined height,
Each of the plurality of protruding upper surfaces overlaps the gate electrode of each of the plurality of transistors,
The predetermined angle includes a first tilt and a second tilt different from the first tilt.
According to clause 11,
The plurality of transistors include a first transistor,
The plurality of protruding upper surfaces include a first protruding upper surface that overlaps a gate electrode of the first transistor,
A side of the first protruding upper surface has the first slope.
According to clause 12,
The plurality of transistors include a second transistor,
The plurality of protruding upper surfaces include a second protruding upper surface overlapping a gate electrode of the second transistor,
A side of the second protruding upper surface has the second slope.
According to clause 13,
A display panel wherein the first slope is greater than the second slope.
According to clause 14,
The display panel wherein the first transistor has an S-factor value greater than that of the second transistor.
According to clause 13,
a plurality of data lines;
multiple gate lines; and
Further comprising a plurality of subpixels connected to the plurality of data lines and the plurality of gate lines,
Each of the plurality of subpixels includes a light-emitting element, a driving transistor for driving the light-emitting element, and a switching transistor for switching a connection between a gate node of the driving transistor and a data line,
The display panel wherein the first transistor is the driving transistor and the second transistor is the switching transistor.

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