KR20190002884A - Transistor substrate and display panel using the same - Google Patents

Abstract

According to an embodiment of the present invention, a display panel includes a driving transistor including an active layer which is curved in a plane. In order to reduce an area occupied by the active layer, the active layer includes at least one channel inclined surface. So, a driving transistor including an active layer of a long-channel can be formed in a small area, thereby realizing a high-resolution display panel.

Description

TRANSISTOR SUBSTRATE AND DISPLAY PANEL USING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor substrate and a display panel using the transistor substrate, and more particularly to a transistor substrate in which a long-channel transistor formed in a high-resolution display panel is disposed, and a display panel using the transistor substrate.

Currently, various display devices are being developed and marketed. For example, a liquid crystal display device (LCD), a field emission display device (FED), an electrophoretic display device (EPD), an electro-wetting display devices (EWDs), organic light emitting display devices (OLEDs), and quantum dot display devices (QDs).

As the era of informationization becomes full-scale, the field of display devices for visually displaying electrical information signals is rapidly developing. The display device is used not only for simple images but also for viewing, enjoying, and sharing various contents such as documents, pictures, and videos. Therefore, studies for increasing the resolution of a display device to implement a screen such as viewing an actual object through various display devices have been continued.

The display device includes a display panel in which pixels are divided into a display area in which an image is displayed and a non-display area in which no image is displayed. Sub-pixels indicating colors are arranged in the display region, and pixel driving circuits capable of driving sub-pixels are arranged for each of the sub-pixels. A part of the pixel driving circuit may be shared among sub pixels. In the non-display area, circuits for transmitting driving signals are arranged in the pixel array constituting the display area. A gate driver circuit is arranged to transfer the gate signal to the gate line of the pixel array, and a data driver circuit is arranged to transfer the data signal to the data line of the pixel array.

The area occupied by one sub-pixel is reduced because the number of sub-pixels arranged in the display area increases as the display device goes higher in resolution. The area occupied by the sub-pixel may be the sum of the areas of the light emitting portion which is substantially the light emitting region and the area of the pixel drive circuit portion which applies the light emitting signal to the light emitting portion. Alternatively, when the light emitting portion and the pixel driving circuit portion are overlapped with each other, the area of either the light emitting portion or the pixel driving circuit portion may be an area of the sub pixel.

The pixel driving circuit portion is composed of driving elements for driving sub-pixels, for example, transistors and capacitors. As the pixel driving circuit is complicated, the area occupied by one driving element is reduced as the resolution of the display panel is increased.

Accordingly, the inventors of the present invention have recognized the above-mentioned problems and have developed a technique for forming a driving device with a smaller area without deteriorating the driving device performance.

A solution according to embodiments of the present invention is to provide a transistor substrate in which transistors of the same performance are formed in a smaller area.

SUMMARY OF THE INVENTION The present invention provides a display panel in which a pixel driving circuit including a long-channel transistor is arranged in a high-resolution display panel.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

In a display panel according to an embodiment of the present invention, a display panel includes a driving transistor including a planar active layer in a curved shape, and in order to reduce an area occupied by the active layer, the active layer includes at least one channel inclined surface do. Therefore, a driving transistor including an active layer of a long-channel can be formed in a small area occupied by the transistor, thereby realizing a high-resolution display panel.

In a transistor substrate on which a transistor is disposed according to an embodiment of the present disclosure, the transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode, and the source electrode and the drain electrode contact the active layer A channel layer is formed between the source electrode and the drain electrode, and the active layer includes at least one channel inclined surface with an acute angle from the substrate. Therefore, a transistor substrate in which a transistor including an active layer of a long-channel is formed in a small area occupied by the transistor can be realized.

In a transistor substrate having a gate electrode, an active layer, a source electrode, and a drain electrode disposed on a substrate according to an embodiment of the present invention, the transistor may have a resistance to voltage difference between the source electrode and the drain electrode, When a voltage is applied to the gate electrode, a channel layer is formed on the surface of the active layer. The active layer has a channel inclined surface in a region where the channel layer is formed. Therefore, a transistor substrate in which a transistor including an active layer of a long-channel is formed in a small area occupied by the transistor can be realized.

The details of other embodiments are included in the detailed description and drawings.

According to the embodiments of the present invention, by forming the channel inclined surface in the channel layer of the transistor, the area for forming the channel layer can be reduced to form a relatively long transistor.

According to embodiments of the present invention, a buffer layer or a gate electrode having an auxiliary inclined surface formed under the active layer of the transistor is disposed to form a channel inclined surface in the channel layer, so that the channel layer has an area for forming a relatively long transistor .

Further, according to the embodiments of the present invention, the thickness of the auxiliary layer is less than 1 占 퐉 and the angle of the auxiliary inclined surface is set to 20 占 or less, whereby the auxiliary inclined surface is stably formed, and the active layer is formed on the auxiliary inclined surface Can be uniformly formed.

The scope of the claims is not limited by the matters described in the description of the specification, as the contents of the description in the problems, the solutions to the problems, and the effects described above do not specify the essential features of the claims.

1 is a diagram illustrating a display device according to an embodiment of the present invention.
2 is a circuit diagram showing a pixel driver circuit according to an embodiment of the present invention.
3A is a diagram showing the shape of a planar active layer according to a first comparative example of the present invention.
FIG. 3B is a view showing a planar active layer according to a second comparative example of the present invention. FIG.
FIG. 3C is a view showing the form of a planar active layer according to a third comparative example of the present specification. FIG.
4A is a cross-sectional view of a transistor according to a first embodiment of the present invention.
4B is a cross-sectional view of a transistor according to a second embodiment of the present invention.
4C is a cross-sectional view of a transistor according to a third embodiment of the present invention.
4D is a cross-sectional view of a transistor according to a fourth embodiment of the present invention.
5A is a diagram illustrating the shape of a planar active layer according to one embodiment of the present disclosure.
FIG. 5B is a view showing the shape of a planar active layer according to an embodiment of the present invention. FIG.
FIG. 6A is a diagram according to one embodiment of FIG.
6B is a cross-sectional view taken along line A-A 'in FIG. 6A.
FIG. 7A is a view according to another embodiment showing FIG. 5A by applying FIG. 4B. FIG.
7B is a cross-sectional view taken along the line B-B 'in FIG. 7A.
FIG. 8 is a view showing in detail FIG. 5A by applying FIG. 4A or FIG. 4C.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments herein may be combined or combined with each other, partially or wholly, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, a transistor substrate and a display panel using the transistor substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating a display device according to an embodiment of the present invention.

1, a display device 100 includes a display panel 110, a timing controller 115, a data driver 111, and a gate driver 113.

The display panel 110 includes subpixels P to which the data lines 10 and the gate lines 20 are connected. The display panel 110 is sealed to protect at least one film or substrate and subpixels formed on the film or the substrate from external air such as moisture or oxygen.

The display panel 110 includes a display area DA in which subpixels are formed and a non-display area NDA in which various signal lines, pads, and the like are formed outside the display area DA. Since the display area DA is an area for displaying an image, subpixels are located, and the non-display area NDA is an area that does not display an image, so dummy subpixels are located or subpixels are not located. In the case where the display panel 110 is a flexible display panel, the display panel 110 may be configured so that an image can be displayed in an area bending by bending the inside of the display area DA. The display panel 110 may be implemented by a top emission method, a bottom emission method, or a dual emission method depending on the configuration of the subpixel P. [

The gate driving circuit 113 is connected to the gate lines 20 to supply gate signals. Specifically, the gate driving circuit 113 receives clock signals from the level shifter and a gate control signal including a start voltage. The gate driving circuit 113 generates gate signals according to the clock signals and the start voltage and provides them to the gate lines 20. [

The level shifter shifts the level of the clock signals input from the timing controller 115 and the voltage level of the start voltage to a gate-on voltage and a gate-off voltage capable of switching transistors formed on the display panel. The level shifter supplies the level shifted clock signals to the gate drive circuit 113 through the clock lines and supplies the level shifted start voltage to the gate drive circuit 113 via the start voltage line. Since the clock lines and the start voltage line are the lines for transmitting the start signals and the clock signals corresponding to the gate control signals, the clock lines and the start voltage line can be collectively referred to as gate control lines.

The data driving circuit 111 is connected to the data lines 10. The data driving circuit 111 receives digital image data and a data control signal from the timing control unit 115. The data driving circuit 111 converts the digital image data into analog data voltages in accordance with the data control signal. The data driving circuit 111 supplies the analog data voltages to the data lines 10.

The timing controller 115 receives digital image data and timing signals from an external system board. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal.

The timing control unit 115 generates a gate control signal for controlling the operation timing of the gate drive circuit 113 and a data control signal for controlling the operation timing of the data drive circuit 111 based on the timing signals.

The data driving circuit 111, the level shifter, and the timing control unit 115 may be formed of one driving IC. Further, the driving IC integrated into one may be disposed on the display panel 110. [ The embodiment of the present invention is not limited thereto, and each of the data driving circuit 111, the level shifter, and the timing control unit 115 may be formed as a separate driving IC.

2 is a circuit diagram showing a pixel driver circuit according to an embodiment of the present invention.

The transistors constituting the pixel driving circuit may be implemented by transistors of an N type or P type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. The transistor is a three-terminal element including a gate electrode, a source electrode, and a drain electrode. The source electrode is an electrode for supplying a carrier to the transistor. In the transistor, the carrier begins to flow from the source electrode. The drain electrode is an electrode in which the carrier exits from the transistor to the outside. That is, the flow of carriers in the MOSFET flows from the source electrode to the drain electrode. In the case of the N-type transistor, since the carrier is an electron, the voltage of the source electrode is lower than the voltage of the drain electrode so that electrons can flow from the source electrode to the drain electrode. In the N-type transistor, since the electrons flow from the source electrode to the drain electrode, the direction of the current flows from the drain electrode toward the source electrode. In the case of the P-type transistor, since the carrier is a hole, the voltage of the source electrode is higher than the voltage of the drain electrode so that holes can flow from the source electrode to the drain electrode. In the P-type transistor, since the holes flow from the source electrode toward the drain electrode, a current flows from the source electrode to the drain electrode. The source electrode and the drain electrode of the MOSFET are not fixed but can be changed according to the applied voltage.

2 illustrates a P-type transistor as an example. 2 is a circuit diagram of 2T1C (2 transistors and 1 capacitor) for supplying current to the organic light emitting element, but the present invention is not limited thereto, and various circuit diagrams such as 3T1C, 4T2C, 5T1C, 6T1C, Panel. It may also be a circuit for driving a liquid crystal element or a quantum dot element as well as an organic light emitting element.

The pixel driving circuit shown in Fig. 2 includes a scan transistor ST, a driving transistor DT, and a capacitor C.

A gate electrode of the scan transistor ST is connected to a scan line, a source electrode of the scan transistor ST is connected to a data line, and a drain electrode of the scan transistor ST is connected to a gate electrode of the drive transistor DT . When the scan transistor ST is turned on by the scan signal Scan applied through the scan line, the data voltage Vdata supplied through the data line is applied to the gate electrode of the drive transistor DT.

The gate electrode of the driving transistor DT is connected to the drain electrode of the scan transistor ST and the source electrode of the driving transistor DT is connected to the high potential line. To the anode of the organic light emitting diode (OLED). When the scan transistor ST is turned on and the data voltage Vdata is applied to the gate electrode of the driving transistor DT, the driving transistor DT is turned on and the organic light emitting diode OLED is turned on. Current. The capacitor C is connected between the source electrode of the driving transistor DT and the gate electrode of the driving transistor DT and is connected to the high potential voltage VDD applied to the source electrode of the driving transistor DT and the driving transistor DT. And a data voltage (Vdata) applied to the gate electrode of the organic light emitting diode OLED, thereby providing a constant current to the organic light emitting diode OLED. A cathode of the organic light emitting diode OLED is connected to the low potential voltage line to receive the low potential voltage VSS.

3A to 3C are views showing the planar active layers according to Comparative Examples 1 to 3 of the present invention.

As mentioned above, the sub-pixel includes a light emitting portion and a pixel driving circuit portion. The transistors and capacitors included in the circuit diagram of Fig. 2 are arranged in the pixel driving circuit portion. In the case of the organic light emitting display panel, the luminance is controlled according to the magnitude of the current supplied to the organic light emitting diode. That is, the driving transistor disposed in the organic light emitting display panel provides a constant current to the organic light emitting diode and changes the current according to the voltage applied to the data line. In general, the length of the channel layer of the transistor is inversely proportional to the amount of current flowing out of the transistor, and the width of the channel layer of the transistor is proportional to the amount of current flowing out of the transistor. Since the channel layer is formed on the surface of the active layer and the carrier can move, the characteristics of the length and width of the channel layer are also applied to the active layer.

In the case of a switching transistor serving to transfer data, the on / off characteristics of the transistor can be improved by increasing the width of the channel layer. In the case of the driving transistor, the characteristic that the magnitude of the current sent from the driving transistor can be controlled to be constant is important. Therefore, the length of the channel layer of the driving transistor is lengthened, and the driving transistor has a high resistance characteristic, so that the characteristics of the driving transistor can be improved. For example, in the case of a switching transistor, the channel layer may have a length of 5 to 6 mu m, and in the case of a driving transistor, a channel layer may have a length of 20 to 30 mu m. Transistors having a channel layer length of several tens of micrometers, such as a driving transistor, may be referred to as long-channel transistors.

3A shows a long-channel transistor, which shows an area OT1 occupied by one transistor in the pixel driving circuit portion, in which the active layer 116 according to the first comparative example of the present invention is disposed. The active layer 116 is formed to be long in the 'a' shape.

FIG. 3B is a view showing an active layer 126 according to a second comparative example of the present invention. In the area OT2 occupied by one transistor, the active layer 126 is formed to be long in a 'C' shape.

FIG. 3C is a view showing an active layer 136 according to the third comparative example of the present invention, wherein the active layer 136 is formed in a long shape in the area OT3 occupied by one transistor.

The active layers 116, 126, and 136 shown in FIGS. 3A to 3C are shown as examples of an active layer in the form of a curved shape in a plane, and the form of the active layer is not limited thereto. For example, the curved portion of the active layer may be formed smoothly, or the shape of the active layer may be formed repeatedly.

As the resolution of the display panel increases, the area occupied by one transistor decreases. For example, when the active layers 116, 126, and 136 shown in FIGS. 3A to 3C have the same length, the area OT2 occupied by one transistor shown in FIG. 3B is the same as that of the one transistor And the area OT3 occupied by one transistor shown in FIG. 3C may be smaller than the area OT2 occupied by one transistor shown in FIG. 3B. In order to form an active layer having the same length in a small area occupied by the transistor, the form of the active layer is inevitably complicated.

4A to 4D are cross-sectional views of a transistor according to the first to fourth embodiments of the present invention, respectively.

The above-mentioned circuit for pixel driving and signal transmission is composed of elements such as a transistor and a capacitor. The transistor is composed of three terminals, that is, a gate electrode, a source electrode, and a drain electrode, and an active layer (or semiconductor layer) which forms a channel layer that is a passage through which electrons or holes move. The transistor has a P type and an N type depending on the doping type of the active layer, and a C type in which a P type and an N type are combined. The transistor may be classified into an amorphous silicon transistor (a-Si TFT), a polycrystalline silicon transistor (p-Si TFT), a single crystal silicon transistor (c-Si TFT), and an oxide transistor .

The transistor includes a top-gate structure in which the gate electrode is located on top of the active layer according to a method of disposing the gate electrode, the source electrode, the drain electrode, and the active layer; A staggered structure which can be divided into a bottom-gate or an inverted structure and in which a gate electrode and a source / drain electrode are separated up and down with respect to the active layer, and And a coplanar structure in which source / drain electrodes are formed in parallel with the active layer. That is, the structure of the transistor may be a staggered structure (or a top-gate staggered structure), an inverted staggered structure (or bottom-gate staggered structure), a coplanar structure (or a top- , And an inverted coplanar structure (or bottom-gate coplanar structure).

4A is a diagram showing a transistor to which an inverted staggered structure is applied. A gate electrode 145 is formed on the substrate 111 and a gate insulating layer 141 is formed on the gate electrode 145. One surface of the gate electrode 145 has a taper, and the taper forms an acute angle from the substrate 111. An active layer 146 is disposed on the gate insulating layer 141 so that the gate insulating layer 141 insulates the gate electrode 145 from the active layer 146. [ The active layer 146 is disposed obliquely along the tapered inclined surface of the gate electrode 145. Source / drain electrodes 147 are formed at both ends of the active layer 146 in the length direction. A passivation layer 142 is formed on the source / drain electrodes 147. The passivation layer 142 may protect the transistor from contamination or damage.

An etch stopper layer may be disposed on the active layer 146 before the source / drain electrodes 147 are formed to prevent damage to the active layer 146. [

The channel layer 148 is formed in the active layer 146 disposed between the source / drain electrodes 147 when a voltage is applied to the gate electrode 145 and the source / drain electrode 147 of the transistor to form a current in the transistor. . The channel layer 148 is formed on the surface of the active layer 146 in the region where the active layer 146 and the gate electrode 145 overlap. The channel layer 148 is formed by tilting along the tapered inclined surface of the gate electrode 145, like the active layer 146. In this case, the active layer 146 is not parallel to the substrate 111, and the inclined portion is referred to as a channel inclined surface. That is, the active layer 146 includes a channel inclined surface formed at the same slope as the inclined surface of the gate electrode 145. [

FIG. 4B is a view showing a transistor to which an inverted staggered structure is applied according to a modification of FIG. 4A.

A gate electrode 145 is formed on the substrate 111 and a gate insulating layer 141 is formed on the gate electrode 145. Both surfaces of the gate electrode 145 have a taper, and the taper forms an acute angle from the substrate 111. An active layer 156 is disposed on the gate insulating layer 141 so that the gate insulating layer 141 insulates the gate electrode 145 from the active layer 156. [ The active layer 156 is formed so as to cover the gate electrode 145 and is arranged to be inclined along the tapered inclined surfaces of both surfaces of the gate electrode 145. Source / drain electrodes 147 are formed at both ends of the active layer 156 in the length direction. A passivation layer 142 is formed on the source / drain electrodes 147.

4A, an etch stopper layer is disposed on the active layer 156 before the source / drain electrodes 147 are formed to prevent damage to the active layer 156 It is possible.

The channel layer 158 is formed in the active layer 156 disposed between the source / drain electrodes 147 when a voltage is applied to the gate electrode 145 and the source / drain electrode 147 of the transistor to form a current in the transistor. . The channel layer 158 is formed on the surface of the active layer 156 in the region where the active layer 156 and the gate electrode 145 overlap. The channel layer 158 is formed by tilting along the tapered inclined surface of the gate electrode 145, like the active layer 156. That is, the active layer 156 includes two channel inclined planes formed at the same slope as the inclined planes of the gate electrode 145.

4C is a diagram showing a transistor to which a coplanar structure is applied.

A buffer layer 143 is provided on the substrate 111 and an active layer 166 is provided on the buffer layer 143. One surface of the buffer layer 143 has a taper, and the taper forms an acute angle from the substrate 111. The active layer 166 is formed by tilting along the tapered inclined surface of the buffer layer 143. A gate insulating layer 141 is formed on the active layer 166. 4C, the gate insulating layer 141 is formed only on a part of the active layer 166, but the gate insulating layer 141 may be formed on the entire surface of the substrate 111 so as to cover the active layer 166. [ A gate electrode 145 is disposed on the gate insulating layer 141 and the gate insulating layer 141 insulates the gate electrode 145 from the active layer 166. An intermediate layer 144 is formed on the gate electrode 145 and source / drain electrodes 147 are formed on both ends of the active layer 166 in the length direction to contact with each other through contact holes formed in the intermediate layer 144 do. A passivation layer may be formed on the source / drain electrode 147.

A channel layer 168 is formed on the active layer 166 disposed between the source / drain electrodes 147 when a voltage is applied to the gate electrode 145 and the source / . The channel layer 168 is formed on the surface of the active layer 166 in the region where the active layer 166 and the gate electrode 145 overlap. The channel layer 168 is formed by tilting along the tapered inclined surface of the gate electrode 145, like the active layer 166. That is, the active layer 166 includes a channel inclined surface formed at the same slope as the inclined surface of the gate electrode 145.

FIG. 4D is a view showing a transistor to which a coplanar structure is applied as a modification of FIG. 4C.

A buffer layer 143 is provided on the substrate 111 and an active layer 176 is provided on the buffer layer 143. Both surfaces of the buffer layer 143 have a taper, and the taper forms an acute angle from the substrate 111. The active layer 176 is formed so as to cover the buffer layer 143 and is inclined along the tapered inclined surfaces of both surfaces of the buffer layer 143. A gate insulating layer 141 is formed on the active layer 176. 4D, the gate insulating layer 141 is formed only on a part of the active layer 176, but the gate insulating layer 141 may be formed on the entire surface of the substrate 111 so as to cover the active layer 176. [ A gate electrode 145 is disposed on the gate insulating layer 141 and the gate insulating layer 141 isolates the gate electrode 145 and the active layer 176 from each other. An intermediate layer 144 is formed on the gate electrode 145 and source / drain electrodes 147 are formed on both ends of the active layer 176 in the length direction to contact with each other through contact holes formed in the intermediate layer 144 do. A passivation layer may be formed on the source / drain electrode 147.

The channel layer 178 is formed in the active layer 176 disposed between the source / drain electrodes 147 when a voltage is applied to the gate electrode 145 and the source / drain electrode 147 of the transistor to form a current in the transistor. . A channel layer 178 is formed on the surface of the active layer 176 in the region where the active layer 176 and the gate electrode 145 overlap. The channel layer 178 is formed by tilting along the tapered inclined surface of the gate electrode 145, like the active layer 176. That is, the active layer 176 includes two channel inclined planes formed at the same slope as the inclined planes of the gate electrode 145.

The gate electrode 145 and the source / drain electrode 147 shown in FIGS. 4A to 4D may be formed of a semiconductor or a conductive metal such as silicon (Si), for example, molybdenum (Mo), aluminum (Al) ), Gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or two or more alloys thereof or multilayers thereof. In addition, the gate insulating layer 141, the buffer layer 143, the intermediate layer 144, and the passivation layer 142 may have an insulating property and may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

4C and FIG. 4D, a planarization layer may be further formed between the intermediate layer 144 and the source / drain electrode 147. In this case, For example, the planarization layer may be formed of a resin material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, But it is not limited thereto.

By having the active layers 146, 156, 166, 176 include channel inclined surfaces when designing transistors, as in the transistors shown in Figures 4A-4D, the relatively long channel layers 148, 158, 168, < RTI ID = 0.0 > 178. < / RTI > In order for the active layers 146, 156, 166, and 176 to include a channel inclined surface, a gate electrode or a buffer layer having a tapered inclined surface below the active layer is disposed. In this case, the gate electrode or the buffer layer may be referred to as an auxiliary layer, and the tapered inclined surface of the gate electrode or the buffer layer may be referred to as an auxiliary inclined surface.

Figures 5A and 5B illustrate the shape of the active layer in plan view according to one embodiment of the present disclosure, applying the embodiments of Figures 4A-4D. Although the shape of the active layer 136 of FIG. 3C is described as an example, the present invention can be applied to various types of active layers other than FIG. 3A or FIG. 3B and FIGS. 3A and 3B. Although the active layer 136 of FIGS. 5A and 5B is shown as being divided into two hatching for ease of explanation, it is an active layer 136 formed simultaneously with the same material.

5A shows a case where the horizontal resolution of the display panel is increased or the area occupied by one transistor is decreased due to an increase in the number of transistors or capacitors included in the pixel driving circuit. The area occupied by one transistor is reduced from OTb to OTa, which reduces the width of the area occupied by one transistor. In this case, since the area occupied by the active layer 136W arranged in the transverse direction in the active layer 136 is substantially reduced, the active layer 136W arranged in the transverse direction on the plane while maintaining the length of the active layer 136W arranged in the transverse direction So that the area occupied by the active layer 136W can be reduced. That is, the active layer 136W arranged in the transverse direction is formed to include the channel inclined surfaces shown in Figs. 4A to 4D.

5B shows a case where the vertical resolution of the display panel is increased or the area occupied by one transistor is decreased due to an increase in the number of transistors or capacitors included in the pixel driving circuit. The area occupied by one transistor is reduced from OTb to OTa, which reduces the vertical width of the area occupied by one transistor. In this case, since the area occupied by the active layer 136L arranged in the longitudinal direction in the active layer 136 is substantially reduced, the length of the active layer 136L arranged in the longitudinal direction is maintained in the vertical direction on the plane So that the area occupied by the active layer 136L can be reduced. That is, the active layer 136L disposed in the longitudinal direction includes the channel inclined surfaces shown in FIGS. 4A to 4D.

FIG. 6A is a diagram according to one embodiment of FIG. 5A, which is applied to FIG. 4B. Since FIG. 6A illustrates the example of FIG. 4B by way of example, FIG. 4D can be applied in the same manner as FIG. 4B. 6A shows only the gate electrode 145 and the active layer 156 for convenience. 4D, the buffer layer 143 may be disposed instead of the gate electrode 145. [

5A and 6A, in order to form the active layer 156 within the area OTa occupied by one transistor, the channel slope must be included in the transversely arranged active layer, so that the lower portion of the active layer 156 One gate electrode 145 having two auxiliary inclined surfaces to the left and right sides is disposed. The number of the gate electrodes 145 is not limited to one, but the number of the gate electrodes 145 may vary depending on the processing capability (for example, the resolution of the exposure apparatus), the area occupied by one transistor, .

6B is a cross-sectional view taken along line A-A 'in FIG. 6A.

6A and 6B, a gate electrode 145 is disposed on a substrate 111, and a gate insulating layer 141 is formed on a gate electrode 145. The gate electrode 145 has two auxiliary inclined surfaces, and each of the two auxiliary inclined surfaces forms an acute angle from the substrate 111. An active layer 156 is disposed on the gate insulating layer 141 and a gate insulating layer 141 isolates the gate electrode 145 and the active layer 156 from each other. Since three active layers arranged in the transverse direction of the active layer 156 are formed along the auxiliary inclined surface of the gate electrode 145, the three active layers each include two channel inclined surfaces. In this case, the taper formed on the left side surface of the gate electrode 145 forms the first angle 1, and the taper formed on the right side surface of the gate electrode 145 forms the second angle 2. The gate electrode 145 may be symmetrical in the left / right direction by forming the first angle 1 and the second angle 2 to be equal to each other.

For example, when the width x of the region where the active layer 156 is to be formed on the plane is 6 mu m, the first longitudinal length y and the second longitudinal length z are 2 mu m, When the thickness h of the gate electrode 145 disposed under the active layer 156 is set to 1 탆 and the first angle 1 and the second angle 2 are formed identically, ) And the second angle (2) are each about 18.4 DEG. Since the length of one channel inclined surface is about 3.16 mu m, the total length of the active layer 156 is about 23 mu m since it is 6X3.16 mu m + 2X2 mu m. When the gate electrode has no auxiliary inclined surface and the active layer has no channel inclined surface, the total length of the active layer that can be formed on the same plane is 22 占 퐉. That is, when the active layer is formed to include a channel inclined surface at the same area, the length of the active layer can be increased by about 5%.

If the thickness of the single layer formed on the substrate 111 is 1 탆 or more, a gravitational force or a tensile force is excessively generated in one direction, so that the substrate 111 may be defective or defective. Therefore, the thickness of the gate electrode 145 formed on the substrate 111 can be less than 1 mu m. 4D, the thickness of the buffer layer 143 may be less than 1 mu m. In the case of the buffer layer 143, if the thickness is 1 탆 or more, difficulties may arise in the etching process. The thickness that can be stably etched during the etching process is 4000? The thickness of the buffer layer 143 should be less than 1 mu m so that the auxiliary inclined surface can be stably formed. In addition, when the first angle 1 and the second angle 2 of the auxiliary slope of the buffer layer 143 or the gate electrode 145 exceed 20 [deg.], It may be difficult to uniformly form the active layer 156 The active layer 156 may be broken if the first angle 1 and the second angle 2 are rapidly increased. Therefore, by forming the auxiliary layer with a thickness of less than 1 占 퐉 and forming the auxiliary inclined surface with an angle of 20 占 or less, the auxiliary inclined surface can be formed stably and the active layer can be uniformly formed on the auxiliary inclined surface.

FIG. 7A is a diagram according to another embodiment showing FIG. 5A in detail by applying FIG. 4B. Since FIG. 7A is an example of FIG. 4B, FIG. 4D can be applied in the same manner as FIG. 4B. 7A shows only the gate electrode 145 and the active layer 156 for convenience. 4D, the buffer layer 143 may be disposed instead of the gate electrode 145. [

5A and 7A, in order to form the active layer 156 in the area OTa occupied by one transistor, the channel slope must be included in the active layer arranged in the transverse direction, A long gate electrode 145 is arranged in the longitudinal direction. For example, although four gate electrodes 145 are disposed, the number of gate electrodes 145 may vary depending on the processing capability (for example, the resolution of the exposure apparatus) or the area occupied by one transistor . An active layer disposed on the four gate electrodes 145 is formed so as to cover the four gate electrodes 145. It is difficult to identify in the plane, but three active layers arranged in the transverse direction of the active layer 156 are curved. In this case, the four gate electrodes 145 may be a structure connected to each other at the bottom of the active layer 156.

7B is a cross-sectional view taken along the line B-B 'in FIG. 7A.

7A and 7B, four gate electrodes 145 are disposed on the substrate 111, and a gate insulating layer 141 is provided on the gate electrode 145. [ Both surfaces of the four gate electrodes 145 each have a taper, and the taper forms an acute angle from the substrate 111. An active layer 156 is disposed on the gate insulating layer 141 so that the gate insulating layer 141 insulates the gate electrode 145 from the active layer 156. The active layer 156 is formed to cover all of the four gate electrodes 145. Thus, the active layers arranged in the transverse direction are each formed to have eight channel inclined surfaces. In this case, the taper formed on the left side surface of the gate electrode 145 forms the first angle 1, and the taper formed on the right side surface of the gate electrode 145 forms the second angle 2. The gate electrode 145 is symmetrical in the left and right direction and the first angle 1 and the second angle 2 may be equal to each other and the distance between the four gate electrodes 145 and the height of the gate electrode 145 , And the first angle (1) and the second angle (2) may be different depending on the process capability.

FIG. 8 is a view showing in detail FIG. 5A by applying FIG. 4A or FIG. 4C. Since FIG. 8A illustrates the example of FIG. 4A, FIG. 4C can be applied in the same manner as FIG. 4A. 8 shows the gate electrode 145 and the active layer 146 for convenience. 4C, the buffer layer 143 may be disposed instead of the gate electrode 145. In this case,

5A and FIG. 8, in order to form the active layer 146 in the area OTa occupied by one transistor, the channel slope must be included in the active layer disposed in the transverse direction, A long gate electrode 145 is arranged in the longitudinal direction. One surface of the gate electrode 145 has a taper and the taper forms a third angle 3, which is acute angle from the substrate 111. The active layer 146 is formed in multiple 'S' shapes along one tapered side of the gate electrode 145. 'S' is a modified example of 'd'. Accordingly, the active layer 146 is formed to have seven channel inclined surfaces, but the number of channel inclined surfaces is not limited thereto. The angle of the third angle (3) and the number of channel inclined planes are determined by the height of the gate electrode (145) and the length of the channel layer of the active layer (146).

A transistor substrate and a display panel using the transistor substrate according to an embodiment of the present invention can be described as follows.

In a display panel according to an embodiment of the present invention, a display panel includes a driving transistor including a planar active layer in a curved shape, and in order to reduce an area occupied by the active layer, the active layer includes at least one channel inclined surface do. Therefore, a driving transistor including a long-channel active layer can be formed in a small area, thereby realizing a high-resolution display panel.

Further comprising an auxiliary layer for forming a channel inclined surface, wherein the auxiliary layer may be under the active layer.

The height of the auxiliary layer may be 1 탆 or less.

The driving transistor includes a gate electrode, and the channel inclined surface may be in a region where the active layer and the gate electrode overlap.

In a transistor substrate on which a transistor is disposed according to an embodiment of the present disclosure, the transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode, and the source electrode and the drain electrode contact the active layer A channel layer is formed between the source electrode and the drain electrode, and the active layer includes at least one channel inclined surface with an acute angle from the substrate. Therefore, a transistor substrate in which a transistor including a long-channel active layer is formed in a small area can be realized.

The buffer layer further comprises a buffer layer at a lower portion of the channel inclined surface, and the buffer layer may include at least one auxiliary inclined surface having an acute angle from the substrate.

The angles formed by the channel inclined surface and the auxiliary inclined surface from the substrate may be equal to each other.

The angle between the buffer layer and the substrate may be 20 DEG or less.

The height of the buffer layer may be 1 탆 or less.

The transistor is a driving transistor, and the channel layer of the driving transistor may have a length of 20 mu m or more.

In a transistor substrate having a gate electrode, an active layer, a source electrode, and a drain electrode disposed on a substrate according to an embodiment of the present invention, the transistor may have a resistance to voltage difference between the source electrode and the drain electrode, When a voltage is applied to the gate electrode, a channel layer is formed on the surface of the active layer. The active layer has a channel inclined surface in a region where the channel layer is formed. Therefore, a transistor substrate in which a transistor including a long-channel active layer is formed in a small area can be realized.

The channel inclined surface may overlap the gate electrode.

The gate electrode may be under the channel inclined surface, and the gate electrode may include at least one auxiliary inclined surface with an acute angle from the substrate.

The channel slope and the auxiliary slope may overlap each other.

The angle between the channel inclined surface and the substrate may be 20 deg. Or less.

The height of the channel inclined surface may be 1 占 퐉 or less.

In order for the transistor to have a high resistance characteristic, the channel layer may have a length of 20 mu m or more.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

100: display device
110: Display panel
111: substrate
113: Gate driver
115: Timing control unit
OT: area occupied by one transistor
116, 126, 136, 146, 156, 166, 176: active layer
141: gate insulating layer
142: Passivation layer
143: buffer layer
145: gate electrode
147: source / drain electrode

Claims (17)

And a driving transistor including an active layer bent in a planar shape,
Wherein the active layer comprises at least one channel inclined surface to reduce the area occupied by the active layer. The method according to claim 1,
Further comprising an auxiliary layer for forming the channel inclined surface,
Wherein the auxiliary layer is at the bottom of the active layer. 3. The method of claim 2,
And the height of the auxiliary layer is 1 占 퐉 or less. The method according to claim 1,
The driving transistor further includes a gate electrode,
Wherein the channel inclined surface is in a region where the active layer and the gate electrode overlap with each other. A transistor substrate on which a transistor is disposed,
The transistor including a gate electrode, an active layer, a source electrode, and a drain electrode,
Wherein the source electrode and the drain electrode contact the active layer to form a channel layer between the source electrode and the drain electrode,
Wherein the active layer comprises at least one channel inclined surface with an acute angle from the substrate. 6. The method of claim 5,
Further comprising a buffer layer underlying the channel inclined surface,
Wherein the buffer layer comprises at least one auxiliary inclined surface with an acute angle from the substrate. The method according to claim 6,
And the angle formed by the channel inclined surface and the auxiliary inclined surface from the substrate are equal to each other. 6. The method of claim 5,
Wherein an angle between the buffer layer and the substrate is 20 DEG or less. 6. The method of claim 5,
Wherein a height of the buffer layer is 1 占 퐉 or less. 6. The method of claim 5,
Wherein the transistor is a driving transistor, and the channel layer of the driving transistor is 20 mu m or more in length. 1. A transistor substrate on which a transistor including a gate electrode, an active layer, a source electrode, and a drain electrode is disposed on a substrate,
The transistor has a high resistance characteristic to withstand a voltage difference between the source electrode and the drain electrode,
When a voltage is applied to the gate electrode, a channel layer is formed on the surface of the active layer,
Wherein the active layer has a channel inclined surface in a region where the channel layer is formed. 12. The method of claim 11,
The channel inclined surface overlapping the gate electrode. 12. The method of claim 11,
Wherein the gate electrode is below the channel inclined surface and the gate electrode comprises at least one auxiliary inclined surface with an acute angle from the substrate. 14. The method of claim 13,
The channel inclined surface and the auxiliary inclined surface overlap each other. 12. The method of claim 11,
Wherein an angle between the channel inclined surface and the substrate is 20 DEG or less. 12. The method of claim 11,
Wherein a height of the channel inclined surface is 1 占 퐉 or less. 12. The method of claim 11,
Wherein the channel layer has a length of 20 mu m or more so that the transistor has high resistance characteristics.

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