KR102651257B1 - Display apparatus - Google Patents

Abstract

Embodiments of the present specification include a first semiconductor pattern including poly-silicon, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer therebetween, and a first source connected to the first semiconductor pattern. A first thin film transistor including an electrode and a first drain electrode, a second semiconductor pattern including an oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer therebetween, and a second semiconductor layer. A second thin film transistor including a second source electrode and a second drain electrode connected to the pattern, a first storage electrode integrally connected to the first semiconductor pattern, and overlapping with the first storage electrode with the first gate insulating layer interposed therebetween. A display device may be provided including a storage capacitor including a second storage electrode, and a connection electrode integrally connected to the second drain electrode and in contact with the second storage electrode.

Description

Display device {DISPLAY APPARATUS}

This specification relates to a display device, and more specifically, to a display device having a subpixel structure that can improve image quality.

As the information society develops, various types of display devices for displaying images are being developed. Among these display devices, there is a display device in which light-emitting elements that emit light on their own are formed in the display panel without a backlight unit outside the display panel.

In addition, a display device in which light-emitting elements are formed on a display panel defines a plurality of pixels in a display area where an image is displayed, and has an array substrate on which at least one thin film transistor is installed for each subpixel in the plurality of pixels. Includes.

For example, the array substrate includes a driving thin film transistor for supplying a driving current to the light emitting device for each subpixel and a switching thin film transistor for supplying a gate signal to the driving thin film transistor.

Meanwhile, in the array substrate of such a display device, the driving thin film transistor must be designed to be advantageous for grayscale expression, and the switching thin film transistor must be designed to have a good on/off ratio. This is because the smaller the current change in relation to the voltage change, the better for grayscale expression for the driving thin film transistor, and the switching thin film transistor must be able to turn on and off quickly.

However, the driving thin film transistor and the switching thin film transistor disposed on the array substrate and including the same semiconductor material have the same characteristics. Therefore, in a conventional array substrate, it is difficult to design the characteristics of the driving thin film transistor and the switching thin film transistor to be different depending on the characteristics of the thin film transistor.

Additionally, as high resolution is required in a display area of the same size, the area of each subpixel within a plurality of pixels is gradually decreasing. In this way, it is difficult to design a storage capacitor and a plurality of transistors having different semiconductors in the small area of each subpixel.

According to an embodiment of the present specification, the second storage electrode disposed on the first gate insulating layer may overlap the first storage electrode formed by extending the first drain region of the first semiconductor pattern. Accordingly, the second storage electrode may form a first storage capacitor by overlapping the first storage electrode formed by extending the first drain region with the first gate insulating layer interposed therebetween. In this way, without forming a separate electrode pattern to form the first storage capacitor within each subpixel SP, the first storage electrode can be formed by extending the first drain region of the first semiconductor pattern.

Additionally, according to an embodiment of the present specification, a third storage electrode may be further formed by arranging the first drain lower electrode of the first drain electrode to extend. Additionally, the third storage electrode may overlap the second storage electrode with the first interlayer insulating layer interposed therebetween to further form a second storage capacitor C2. Accordingly, an additional storage capacitor can be secured without forming a separate electrode pattern to form an additional storage capacitor in each subpixel (SP) area. Therefore, in a display device that requires a high-capacity storage capacitor, the storage capacitor can be increased by forming a third storage electrode by extending the first drain lower electrode to overlap the second storage electrode.

A display device according to an embodiment of the present specification includes a first semiconductor pattern including poly-silicon, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first semiconductor pattern connected to the first semiconductor pattern. a first thin film transistor including a first source electrode and a first drain electrode, a second semiconductor pattern including an oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer therebetween, and A second thin film transistor including a second source electrode and a second drain electrode connected to the second semiconductor pattern, a first storage electrode integrally connected to the first semiconductor pattern, and a first gate insulating layer therebetween. It may include a storage capacitor including a second storage electrode overlapping the storage electrode, and a connection electrode integrally connected to the second drain electrode and in contact with the second storage electrode.

In another aspect, a display device according to an embodiment of the present specification includes a first semiconductor pattern including a first semiconductor, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first semiconductor pattern including a first semiconductor. A first thin film transistor including a first source electrode and a first drain electrode connected to a semiconductor pattern, a second semiconductor pattern including a second semiconductor different from the first semiconductor, and a second semiconductor with a second gate insulating layer therebetween. A second thin film transistor including a second gate electrode overlapping the pattern, a second source electrode and a second drain electrode connected to the second semi-doped pattern, and a second storage electrode disposed on the same layer as the first gate electrode. , and a storage capacitor including a third storage electrode overlapping the second storage electrode.

According to embodiments of the present specification, the second storage electrode disposed on the first gate insulating layer may overlap the first storage electrode formed by extending the first drain region of the first semiconductor pattern. Accordingly, the second storage electrode may form a first storage capacitor by overlapping the first storage electrode formed by extending the first drain region with the first gate insulating layer interposed therebetween. In this way, without forming a separate electrode pattern to form the first storage capacitor within each subpixel SP, the first storage electrode can be formed by extending the first drain region of the first semiconductor pattern. Accordingly, there is an advantage in that a storage capacitor and a plurality of transistors can be effectively designed within each limited subpixel (SP) area.

Additionally, according to embodiments of the present specification, a third storage electrode may be further formed by arranging the first drain lower electrode of the first drain electrode to extend. Additionally, the third storage electrode may overlap the second storage electrode with the first interlayer insulating layer interposed therebetween to further form a second storage capacitor C2. Accordingly, an additional storage capacitor can be secured without forming a separate electrode pattern to form an additional storage capacitor in each subpixel (SP) area. Therefore, in a display device that requires a high-capacity storage capacitor, the storage capacitor can be increased by forming a third storage electrode by extending the first drain lower electrode to overlap the second storage electrode. Therefore, in a high-resolution display device that requires a high-capacity storage capacitor, there is an advantage in that the storage capacitor and a plurality of transistors can be effectively designed within each limited subpixel (SP) area.

The effects according to the present invention are not limited to the details exemplified above, and further various effects are included within the present invention.

1 is a system configuration diagram of a display device according to embodiments of the present specification.
Figure 2 is an equivalent circuit of a subpixel of a display device according to embodiments of the present specification.
FIG. 3 is a diagram showing a cross-sectional structure within a subpixel of a display device according to embodiments of the present specification.

Hereinafter, some embodiments of the present specification will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present specification, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present specification, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, when describing the components of this specification, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the description of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

1 is a system configuration diagram of a display device according to embodiments of the present specification.

Referring to FIG. 1, the display device 100 according to the present embodiments has a plurality of data lines DL and a plurality of gate lines GL, and a plurality of data lines DL and a plurality of gate lines It may include a display panel 110 in which a plurality of subpixels (SP) connected to (GL) are arranged, and a driving circuit for driving the display panel 110.

The driving circuit includes a data driving circuit 120 that drives a plurality of data lines (DL), a gate driving circuit 130 that drives a plurality of gate lines (GL), a data driving circuit 120, and a gate driving circuit. It may include a controller 140 that controls 130 .

In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged to cross each other. For example, multiple data lines DL may be arranged in rows or columns, and multiple gate lines GL may be arranged in columns or rows. Below, for convenience of explanation, it is assumed that the plurality of data lines DL are arranged in rows and the plurality of gate lines GL are arranged in columns.

The controller 140 supplies various control signals (DCS, GCS) necessary for the driving operation of the data driving circuit 120 and the gate driving circuit 130, and operates the data driving circuit 120 and the gate driving circuit 130. Control.

This controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120, and converts the converted image data (DATA) ) is output, and data operation is controlled at an appropriate time according to the scan.

The above-described controller 140, along with input image data, various types of signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, a clock signal (CLK), etc. Timing signals are received from an external source (e.g., host system).

The controller 140 converts the input image data input from the outside to suit the data signal format used in the data driving circuit 120 and outputs the converted image data (DATA), and also operates the data driving circuit 120 and In order to control the gate driving circuit 130, timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal are input, and various control signals are generated to generate the data driving circuit 120. ) and output to the gate driving circuit 130.

For example, the controller 140 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE) to control the gate driving circuit 130. : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable. Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 130. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of a scan signal (gate pulse). The gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the data driving circuit 120. Outputs various data control signals (DCS: Data Control Signal) including Output Enable. Here, the source start pulse (SSP) controls the data sampling start timing of one or more source-driver integrated circuits constituting the data driving circuit 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each source-driver integrated circuit. The source output enable signal (SOE) controls the output timing of the data driving circuit 120.

This controller 140 may be a timing controller used in typical display technology, or may be a control device that can perform other control functions, including a timing controller.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data DATA from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

The data driving circuit 120 may be implemented including at least one source-driver integrated circuit (S-DIC). Each source-driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. there is. Each source-driver integrated circuit (S-DIC) may, in some cases, further include an analog to digital converter (ADC).

Each source-driver integrated circuit (S-DIC) uses a Tape Automated Bonding (TAB) method, a Chip On Glass (COG) method, or a Chip On Panel (COP) method. It may be connected to a bonding pad of the display panel 110, may be placed directly on the display panel 110, or may be integrated and placed on the display panel 110, depending on the case. Additionally, each source-driver integrated circuit (S-DIC) may be implemented using a chip-on-film (COF) method mounted on a source-circuit film connected to the display panel 110.

The gate driving circuit 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 is also called a scan driving circuit.

The gate driving circuit 130 may include a shift register, a level shifter, etc.

The gate driving circuit 130 is connected to the display panel 110 using a Tape Automated Bonding (TAB) method, a Chip On Glass (COG) method, or a Chip On Panel (COP: Chip On Panel) method. ) or may be implemented as a GIP (Gate In Panel) type and placed directly on the display panel 110. In some cases, it may be integrated and placed on the display panel 110. . Additionally, the gate driving circuit 130 may be implemented using a chip-on-film (COF) method in which a plurality of gate driver integrated circuits (G-DICs) are implemented and mounted on a gate-circuit film connected to the display panel 110. .

The gate driving circuit 130 sequentially supplies scan signals of on voltage or off voltage to a plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (DATA) received from the controller 140 into an analog data voltage to generate a plurality of data lines (DL). supplied by

The data driving circuit 120 may be located only on one side (e.g., upper or lower) of the display panel 110, and in some cases, both sides (e.g., upper or lower) of the display panel 110 depending on the driving method, panel design method, etc. For example, it may be located on both the upper and lower sides.

The gate driving circuit 130 may be located only on one side (e.g., left or right) of the display panel 110, and in some cases, both sides (e.g., left or right) of the display panel 110 depending on the driving method, panel design method, etc. For example, it may be located on both the left and right sides.

A plurality of gate lines (GL) disposed on the display panel 110 may include a plurality of scan lines (SCL) and a plurality of emission control lines (EML). Multiple scan lines (SCL) and multiple light emission control lines (EML) are gate nodes of different types of transistors (scan transistors, light emission control transistors) that transmit different types of gate signals (scan signals, light emission control signals). These are the wiring that transmits

The gate driving circuit 130 is a scan driving circuit that outputs scan signals through a plurality of scan lines, which are a type of gate line (GL), and outputs emission control signals through a plurality of light emission control lines, which are another type of gate line (GL). It may include a light emission driving circuit.

Figure 2 is an equivalent circuit of a subpixel (SP) of a display device according to embodiments of the present specification.

Referring to FIG. 2, each subpixel (SP) may include a light emitting element (ED), first to sixth transistors (T1 to T6), and a storage capacitor (Cst).

Referring to FIG. 2, each subpixel (SP) has a first node (N1) corresponding to the source node or drain node of the second transistor (T2), and a second node (N1) corresponding to the gate node of the second transistor (T2). A node N2, a third node N3 corresponding to the drain node or source node of the second transistor T2, a fourth node N4 corresponding to the pixel electrode PE of the light emitting element ED, etc. Includes major nodes of

The light emitting device (ED) may include a pixel electrode (PE), a light emitting layer (EL), and a common electrode (CE). The light emitting layer (EL) is located between the pixel electrode (PE) and the common electrode (CE). A pixel electrode (PE) and a light emitting layer (EL) are disposed in each subpixel (SP). However, the common electrode (CE) may be commonly disposed in multiple subpixels (SP). A base voltage (VSS) corresponding to the common voltage may be applied to the common electrode (CE).

Among the first to sixth transistors (T1 to T6), the second transistor (T2) is a driving transistor (DRT) that drives the light emitting device (ED).

Among the first to sixth transistors (T1 to T6), excluding the second transistor (T2), which is the driving transistor (DRT), five are connected to the gate nodes of the remaining five transistors (T1, T3, T4, T5, T6). gate lines (GL) are required.

The five gate lines GL may include first to third scan lines SCL1, SCL2, and SCL3 and first and second emission control lines EML1 and EML2.

The third transistor (T3) electrically connects the second node (N2) and the third node (N3) according to the first scan signal (Scan1(n)) applied to the gate node through the first scan line (SCL1). control.

The first transistor (T1) is a data line that supplies a data voltage (Vdata) to the first node (N1) according to the second scan signal (Scan2(n)) applied to the gate node through the second scan line (SCL2). (DL) Controls the electrical connection between

The sixth transistor (T6) is configured to apply the fourth node (N4) and the initialization voltage (Vini) according to the third scan signal (Scan2(n-1)) applied to the gate node through the third scan line (SCL3). Controls electrical connections between initialization voltage nodes (NVINI).

The fourth transistor (T4) is configured to apply the first node (N1) and the driving voltage (VDD) according to the first emission control signal (EM1(n)) applied to the gate node through the first emission control line (EML1). Controls the electrical connection between driving voltage nodes (NVDD).

The fifth transistor (T5) generates electricity between the third node (N3) and the fourth node (N4) according to the second light emission control signal (EM2(n)) applied to the gate node through the second light emission control line (EML2). Controls network connections.

Referring to FIG. 2, the storage capacitor Cst includes a first plate PLT1 and a second plate PLT2. The first plate PLT1 is electrically connected to the gate node of the second transistor T2, which is the driving transistor DRT, and the second plate PLT2 is electrically connected to the DC voltage node. Here, the DC voltage node may include, for example, a driving voltage node (NVDD).

Referring to FIG. 2 , the storage capacitor Cst may be electrically connected between the second node N2 and the driving voltage node NVDD. Here, the second node N2 corresponds to the gate node of the second transistor T2, which is the driving transistor DRT, and the driving voltage node NVDD may be a DC voltage node.

Referring to FIG. 2, the second transistor T2 among the first to sixth transistors T1 to T6 may be a P-type transistor. For example, among the first to sixth transistors T1 to T6, the second transistor T2 may be a P-type transistor, and the remaining first, third to sixth transistors T6 may be N-type transistors. However, the present invention is not limited to this, and at least one transistor among the first to sixth transistors T1 to T6 may be an N-type transistor, and all other transistors may be P-type transistors. Alternatively, the first to sixth transistors (T1 to T6) may all be N-type transistors.

As described above, by designing the second transistor T2, which is the driving transistor DRT, as a P-type transistor, the storage capacitor Cst is connected to the second node N2, which is the gate node of the second transistor T2, and the DC voltage. It can be formed between the driving voltage nodes (NVDD), which are nodes.

By connecting one of both ends of the storage capacitor (Cst) to the driving voltage node (NVDD), which is a DC voltage node, a voltage change in the second node (N2), which is the other end of the storage capacitor (Cst), can be prevented. The second node N2 corresponds to the gate node of the second transistor T2, which is the driving transistor DRT.

In addition, according to the embodiments of the present specification, the second transistor (T2), which is the driving transistor (DRT), is designed as a P-type transistor that is advantageous for operation reliability and current supply performance because operation reliability and current supply performance are most important. do. However, the remaining first, third to sixth transistors T6 may be transistors whose switching speed is more important than current supply performance. Accordingly, the first, third to sixth transistors T6 can be designed as N-type transistors with fast switching speed due to high carrier mobility. Accordingly, the driving performance of the subpixel (SP) can be greatly improved.

Meanwhile, the display device 100 according to embodiments of the present specification may be a self-emitting display such as an Organic Light Emitting Diode (OLED) display, a Quantum Dot display, or a Micro Light Emitting Diode (Micro LED) display. there is.

When the display device 100 according to embodiments of the present specification is an OLED display, each subpixel (SP) may include an organic light emitting diode (OLED) that emits light on its own as a light emitting element (ED). When the display device 100 according to the embodiments of the present specification is a quantum dot display, each subpixel (SP) may include a light emitting element (ED) made of quantum dots, which are semiconductor crystals that emit light on their own. You can. When the display device 100 according to the embodiments of the present specification is a micro LED display, each subpixel (SP) emits light on its own and uses a micro LED (Micro Light Emitting Diode) made based on an inorganic material as a light emitting element (ED). It can be included as .

FIG. 3 is a diagram showing a cross-sectional structure within a subpixel of a display device according to embodiments of the present specification.

Referring to FIG. 3, the display device 100 according to an embodiment of the present specification includes a substrate 10, a first buffer layer 20, a first gate insulating layer 30, a first interlayer insulating layer 40, Second buffer layer 50, second gate insulating layer 60, second interlayer insulating layer 70, protective layer 80, bank layer 90, spacer 91, light emitting device 500, first It may include a thin film transistor 200, a second thin film transistor 300, a storage capacitor 400, a connection electrode 610, and a shield pattern 710.

And, the first thin film transistor 200 may include a first semiconductor pattern 210, a first source electrode 220, a first drain electrode 230, and a first gate electrode 240. Additionally, the second thin film transistor 300 may include a second semiconductor pattern 310, a second source electrode 320, a second drain electrode 330, and a second gate electrode 340.

And, the storage capacitor 400 may include a first storage electrode 410, a second storage electrode 420, and a third storage electrode 430. Additionally, the light emitting device 500 may include a first electrode 510, a light emitting structure 520, and a second electrode 530.

Referring to FIG. 3 , a display device according to an embodiment of the present specification may include a substrate 10 . The substrate 10 may include a display area where subpixels SP are disposed and a non-display area disposed adjacent to the display area. The substrate 10 may include an insulating material. For example, the substrate 10 may include glass or plastic. In FIG. 3, the substrate 10 is depicted as a single-layer structure, but it is not limited to this. For example, the substrate 10 may have a multi-layer structure. The substrate 10 may have a structure in which an inorganic insulating layer is located between the first substrate layer and the second substrate layer. The second substrate layer may include the same material as the first substrate layer. For example, the first substrate layer and the second substrate layer may include plastic. The inorganic insulating layer may include an insulating material. For example, the first substrate layer and the second substrate layer may be made of polyimide (PI). Additionally, the inorganic insulating layer may be made of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. For example, an inorganic insulating layer can be formed using a silicon dioxide (Silica or Silicon Dioxide: SiO2) material.

In this way, by forming an inorganic insulating layer between the first and second substrate layers made of polyimide (PI), the reliability of the product is improved by blocking the charge on the first substrate layer disposed below. It can be improved. Additionally, by forming an inorganic insulating layer between two polyimides (PI), the reliability of the display device can be improved by blocking moisture components from penetrating the thin film transistor through the lower first substrate layer.

The substrate 10 may include a subpixel SP defined by gate lines GL and data lines DL. A first thin film transistor 200, a second thin film transistor 300, and a light emitting device 500 may be located within each subpixel SP. Each light emitting device 500 is electrically connected to the first thin film transistor 200 and can emit light representing a specific color. As another example, each light emitting device 500 may be electrically connected to the second thin film transistor 300 and emit light representing a specific color.

Referring to FIG. 3, a first buffer layer 20 may be formed on the substrate 10. The first buffer layer 20 can prevent contamination by the substrate 10 during the pixel circuit formation process. For example, the first buffer layer 20 may be formed between the substrate 10 and the first semiconductor pattern 210 of each subpixel SP. The first buffer layer 20 may include an insulating material. For example, the first buffer layer 20 may include a silicon oxide-based (SiOx) material layer and a silicon nitride-based (SiNx) material layer. The first buffer layer 20 may have a multi-layer structure. For example, the first buffer layer 20 may include a first lower buffer layer 21 and a first upper buffer layer 22.

A first buffer lower layer 21 may be disposed on the substrate 10, and a first buffer upper layer 22 may be disposed on the first buffer lower layer 21. The first lower buffer layer 21 may be formed as a multi-layer composed of a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx). For example, the first lower buffer layer 21 may be formed of multiple layers in which silicon oxide (SiOx) layers and silicon nitride (SiNx) layers are alternately formed.

Additionally, the first buffer upper layer 22 may be formed as a single layer made of a silicon oxide (SiOx)-based material. For example, the first buffer upper layer 22 may be formed as a single layer made of silicon dioxide (SiO2) material.

Referring to FIG. 3, a shield pattern 710 may be additionally disposed between the first buffer upper layer 22 and the first buffer lower layer 21. The shield pattern 710 may be a metal material layer. The shield pattern 710 may serve to block charges charged to the substrate 10 from affecting the first thin film transistor 200 by forming a back bias. Additionally, the reliability of the display device can be improved by blocking external light from passing through the substrate 10 and penetrating into the first thin film transistor 200.

The first semiconductor pattern 210 may be located on the first buffer upper layer 22 of the first buffer layer 20 . The first semiconductor pattern 210 may include a semiconductor material. For example, the first semiconductor pattern 210 may include poly-silicon (Poly-Si), a polycrystalline semiconductor material. For example, the first semiconductor pattern 210 may include low temperature poly-silicon (LTPS).

The first semiconductor pattern 210 may overlap the shield pattern 710 with the first buffer upper layer 22 interposed therebetween. Additionally, the first semiconductor pattern 210 may include a first channel region 210C, a first source region 210S, and a first drain region 210D. Additionally, the first drain region 210D of the first semiconductor pattern 210 may be extended to become the first storage electrode 410 of the storage capacitor 400. Accordingly, referring to FIG. 3 , the first drain region 210D of the first semiconductor pattern 210 may be integrated and connected to the first storage electrode 410 of the storage capacitor 400. Accordingly, the first drain region 210D of the first semiconductor pattern 210 and the first storage electrode 410 of the storage capacitor 400 may have the same stacked structure and may include the same material.

A first gate insulating layer 30 may be formed on the first semiconductor pattern 210, the first storage electrode 410, and the first buffer layer 20. The first gate insulating layer 30 may include an insulating material. For example, the first gate insulating layer 30 may include a silicon oxide-based (SiOx) material. For example, it may include silicon dioxide (SiO2) among silicon oxide-based (SiOx) materials. However, the present invention is not limited thereto, and the first gate insulating layer 30 may include a silicon nitride-based (SiNx) material. Alternatively, the first gate insulating layer 30 may be formed as a multi-layer composed of a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx).

The first gate electrode 240 of the first thin film transistor 200 and the second storage electrode 420 of the storage capacitor 400 may be formed on the first gate insulating layer 30. The first gate electrode 240 may overlap the first semiconductor pattern 210 with the first gate insulating layer 30 interposed therebetween. Additionally, the second storage electrode 420 may overlap the first storage electrode 410 with the first gate insulating layer 30 interposed therebetween. For example, the first gate electrode 240 may overlap the first channel region 210C of the first semiconductor pattern 210 with the first gate insulating layer 30 interposed therebetween. Additionally, the second storage electrode 420 may overlap the first storage electrode 410 with the first gate insulating layer 30 interposed therebetween.

Additionally, the second storage electrode 420 may overlap the first storage electrode 410 with the first gate insulating layer 30 therebetween to form the first storage capacitor C1 of the storage capacitor 400. .

The first gate electrode 240 and the second storage electrode 420 may include a conductive material. For example, the first gate electrode 240 and the second storage electrode 420 are aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), and It may contain the same metal or alloy thereof. Additionally, the first gate electrode 240 and the second storage electrode 420 may be composed of a single layer or multiple layers of a metal or alloy material.

Additionally, the first gate electrode 240 and the second storage electrode 420 are made of the same material and may be disposed on the same layer. Accordingly, the first gate electrode 240 and the second storage electrode 420 may have the same stacked structure.

A first interlayer insulating layer 40 may be formed on the first gate electrode 240, the second storage electrode 420, and the first gate insulating layer 30. The first interlayer insulating layer 40 may include an insulating material. The first interlayer insulating layer 40 may include a first interlayer insulating lower layer 41 and a first interlayer insulating upper layer 42. The first interlayer insulating lower layer 41 may include the same insulating material as the first gate insulating layer 30 . Additionally, the first interlayer insulating upper layer 42 may include an insulating material different from that of the first interlayer insulating lower layer 41 . For example, when the first gate insulating layer 30 includes a silicon oxide-based material (SiOx), the first interlayer insulating lower layer 41 may include a silicon oxide-based material (SiOx). Additionally, the first interlayer insulating upper layer 42 may include a silicon nitride-based (SiNx) material.

A contact hole exposing the first semiconductor pattern 210 may be formed by etching the first gate insulating layer 30 and the first interlayer insulating layer 40. For example, the first gate insulating layer 30, the first interlayer insulating lower layer 41, and the first interlayer insulating upper layer 42 are etched to form the first drain region 210D of the first semiconductor pattern 210. An exposed contact hole may be formed. Accordingly, the first drain region 210D of the first semiconductor pattern 210 may be exposed through the contact hole of the first gate insulating layer 30 and the first interlayer insulating layer 40.

The first drain lower electrode 231 of the first drain electrode 230 and the third storage electrode 430 of the storage capacitor 400 may be formed on the first interlayer insulating layer 40. The first drain lower electrode 231 may be connected to the exposed first semiconductor pattern 210 through a contact hole in the first gate insulating layer 30 and the first interlayer insulating layer 40. For example, the first drain lower electrode 231 of the first drain electrode 230 is a contact of the first gate insulating layer 30, the first interlayer insulating lower layer 41, and the first interlayer insulating upper layer 42. It may be connected to the first drain region 210D of the first semiconductor pattern 210 through the hole. Additionally, the third storage electrode 430 may overlap the second storage electrode 420 with the first interlayer insulating layer 40 interposed therebetween. Additionally, the third storage electrode 430 may overlap the second storage electrode 420 with the first interlayer insulating upper layer 42 and the first interlayer insulating lower layer 41 interposed therebetween. The third storage electrode 430 may overlap the second storage electrode 420 with the first interlayer insulating layer 40 therebetween to form the second storage capacitor C2 of the storage capacitor 400 .

As shown in FIG. 3 , the first drain lower electrode 231 is disposed to extend to overlap the second storage electrode 420 , thereby forming the third storage electrode 430 . Accordingly, the first drain lower electrode 231 and the third storage electrode 430 may be integrally connected to each other. Additionally, the first drain lower electrode 231 and the third storage electrode 430 have the same stacked structure and may include the same material.

The first drain lower electrode 231 and the third storage electrode 430 may be made of a conductive material. The first drain lower electrode 231 and the third storage electrode 430 are made of metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W). It may include alloys thereof. Additionally, the first drain lower electrode 231 and the third storage electrode 430 may be composed of a single layer or multiple layers of a metal or alloy material.

As the display device becomes higher resolution, the area of each subpixel (SP) area decreases. Therefore, it is difficult to design a storage capacitor and a plurality of transistors in each small subpixel (SP) area. However, in the display device according to the embodiment of the present specification, the second storage electrode 420 disposed on the first gate insulating layer 30 extends the first drain region 210D of the first semiconductor pattern 210. may overlap with the formed first storage electrode 410. Accordingly, the second storage electrode 420 overlaps the first storage electrode 410 formed by extending the first drain region 210D with the first gate insulating layer 30 interposed therebetween to form the first storage capacitor C1. can be formed. In this way, without forming a separate electrode pattern to form the first storage capacitor C1 within each subpixel SP, the first drain region 210D of the first semiconductor pattern 210 is extended to form the first storage capacitor C1. 1 Storage electrode 410 can be formed. Accordingly, there is an advantage in that a storage capacitor and a plurality of transistors can be effectively designed within each limited subpixel (SP) area.

Additionally, in the display device according to an embodiment of the present specification, the third storage electrode 430 may be formed by arranging the first drain lower electrode 231 of the first drain electrode 230 to extend. Additionally, the third storage electrode 430 may overlap the second storage electrode 420 with the first interlayer insulating layer 40 therebetween to further form a second storage capacitor C2. Accordingly, the storage capacitor 400 can be additionally secured without forming a separate electrode pattern to additionally form the storage capacitor 400 in each subpixel (SP) area. Therefore, in a display device that requires a high-capacity storage capacitor 400, the first drain lower electrode 231 is extended to overlap the second storage electrode 420 to form the third storage electrode 430, thereby forming the storage capacitor 400. ) can be increased. Therefore, according to an embodiment of the present specification, there is an advantage in that a storage capacitor and a plurality of transistors can be effectively designed within a limited area of each subpixel (SP) in a high-resolution display device that requires a high-capacity storage capacitor.

A second buffer layer 50 may be formed on the first drain lower electrode 231, the third storage electrode 430, and the first interlayer insulating layer 40. The second buffer layer 50 may be formed as a multi-layer composed of a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx). The second buffer layer 50 may be formed of multiple layers in which silicon oxide (SiOx) and silicon nitride (SiNx) are alternately formed. For example, the second buffer layer 50 may include a first lower buffer layer 51 and a second upper buffer layer 52. The first buffer lower layer 51 may include silicon nitride (SiNx). And, the first buffer upper layer 52 may include silicon oxide (SiOx).

Referring to FIG. 3, the second semiconductor pattern 310 of the second thin film transistor 300 may be formed on the second buffer layer 50. The second semiconductor pattern 310 of the second thin film transistor 300 may include a material different from the first semiconductor pattern 210 of the first thin film transistor 200. The second semiconductor pattern 310 may include an oxide semiconductor. For example, the second semiconductor pattern 310 is IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, ITZO (InSnZnO)-based IGTO (InGaSnO)-based )-based, GO (GaO)-based, GZTO (GaZnSnO)-based, and GZO (GaZnO)-based oxide semiconductor materials. However, the embodiments of the present specification are not limited to this, and the second semiconductor pattern 310 may be made of other oxide semiconductor materials.

The second semiconductor pattern 310 includes a second channel region 310C overlapping the second gate electrode 340, a second source region 310S connected to the second source electrode 320, and a second drain electrode ( It may include a second drain region 310D connected to 330).

A second gate insulating layer 60 may be formed on the second semiconductor pattern 310 and the second buffer layer 50. The second gate insulating layer 60 may overlap the first gate electrode 240, the first drain lower electrode 231, and the third storage electrode 430. However, the present invention is not limited to this, and the second gate insulating layer 60 may be disposed to overlap only the second semiconductor pattern 310 . For example, the second gate insulating layer 60 may be disposed to overlap only the second channel region 310C of the second semiconductor pattern 310. The second gate insulating layer 60 may include at least one of a silicon oxide-based (SiOx) material and a silicon nitride-based (SiNx) material. The second gate insulating layer 60 may have a single-layer or multi-layer structure.

The second gate electrode 340 of the second thin film transistor 300 may be formed on the second gate insulating layer 60. The second gate electrode 340 may overlap the second semiconductor pattern 310 with the second gate insulating layer 60 interposed therebetween. The second gate electrode 340 may include a conductive material. For example, the second gate electrode 340 includes metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W), or alloys thereof. can do. And the second gate electrode 340 may be formed as a single layer or multiple layers. For example, when formed as a multi-layer, the second gate electrode 340 may be formed as a multi-layer consisting of a molybdenum (Mo) metal layer and a titanium (Ti) metal layer. When the second gate electrode 340 is a multilayer consisting of a molybdenum (Mo) metal layer and a titanium (Ti) metal layer, based on the cross-sectional view, the width of the titanium (Ti) metal layer may be larger than the width of the molybdenum (Mo) metal layer. .

A second interlayer insulating layer 70 may be formed on the second gate electrode 340. The second interlayer insulating layer 70 may include at least one of a silicon oxide-based (SiOx) material and a silicon nitride-based (SiNx) material. The second interlayer insulating layer 70 may have a single-layer or multi-layer structure.

Referring to FIG. 3, the second interlayer insulating layer 70, the second gate insulating layer 60, the second buffer layer 50, the first interlayer insulating layer 40, and the first gate insulating layer 30. A contact hole exposing the first semiconductor pattern 210 of the first thin film transistor 200 may be formed by etching. For example, the second interlayer insulating layer 70, the second gate insulating layer 60, the second buffer layer 50, the first interlayer insulating layer 40, and the first gate insulating layer 30 are etched. 1 A contact hole exposing the first source region 210S of the semiconductor pattern 210 may be formed. As another example, when the second gate insulating layer 60 overlaps only the second semiconductor pattern 310, the second interlayer insulating layer 70, the second buffer layer 50, the first interlayer insulating layer 40, The first gate insulating layer 30 may be etched to form a contact hole exposing the first source region 210S of the first semiconductor pattern 210.

Then, the second interlayer insulating layer 70, the second gate insulating layer 60, and the second buffer layer 50 are etched to expose the first drain lower electrode 231 of the first drain electrode 230. A hole can be formed. As another example, when the second gate insulating layer 60 overlaps only the second semiconductor pattern 310, the second interlayer insulating layer 70 and the second buffer layer 50 are etched to form the first drain electrode 230. A contact hole exposing the first drain lower electrode 231 may be formed.

In addition, the second interlayer insulating layer 70, the second gate insulating layer 60, the second buffer layer 50, and the first interlayer insulating layer 40 are etched to form the second storage electrode ( 420) can be formed to expose the contact hole. As another example, when the second gate insulating layer 60 overlaps only the second semiconductor pattern 310, the second interlayer insulating layer 70, the second buffer layer 50, and the first interlayer insulating layer 40 A contact hole exposing the second storage electrode 420 can be formed by etching.

Then, the second interlayer insulating layer 70 and the second gate insulating layer 60 may be etched to form a contact hole exposing the second semiconductor pattern 310 of the second thin film transistor 300. For example, the second interlayer insulating layer 70 and the second gate insulating layer 60 are etched to expose the second source region 310S and the second drain region 310D of the second semiconductor pattern 310. A contact hole can be formed. As another example, when the second gate insulating layer 60 is disposed to overlap only the second channel region 310C of the second semiconductor pattern 310, the second interlayer insulating layer 70 is etched to form a second source region ( A contact hole exposing the second drain region 310S) and the second drain region 310D may be formed.

A second source electrode 320, a second drain electrode 330, a connection electrode 610, a first drain upper electrode 232, and a first source electrode 220 are formed on the second interlayer insulating layer 70. It can be.

Referring to FIG. 3, the second source electrode 320 and the second drain electrode 330 of the second thin film transistor 300 are contact holes of the second interlayer insulating layer 70 and the second gate insulating layer 60. It may be connected to the exposed second semiconductor pattern 310 through . For example, the second source electrode 320 may be connected to the second source region 310S of the second semiconductor pattern 310. And, the second drain electrode 330 may be connected to the second drain region 310D of the second semiconductor pattern 310.

The first source electrode 220 of the first thin film transistor 200 includes a second interlayer insulating layer 70, a second gate insulating layer 60, a second buffer layer 50, a first interlayer insulating layer 40, And it may be connected to the exposed first semiconductor pattern 210 through the contact hole of the first gate insulating layer 30. And, the first drain upper electrode 232 of the first drain electrode 230 is exposed through the contact hole of the second interlayer insulating layer 70, the second gate insulating layer 60, and the second buffer layer 50. It may be connected to the first drain lower electrode 231. Accordingly, the first drain upper electrode 232 may be electrically connected to the first semiconductor pattern 210 through the first drain lower electrode 231.

The connection electrode 610 is a second storage exposed through the contact hole of the second interlayer insulating layer 70, the second gate insulating layer 60, the second buffer layer 50, and the first interlayer insulating layer 40. It may be connected to the electrode 420.

Referring to FIG. 3, the connection electrode 610 and the second drain electrode 330 may be integrated and connected to each other. As another example, the connection electrode 610 and the second source electrode 320 may be integrated and connected to each other.

The second source electrode 320, the second drain electrode 330, the first source electrode 220, the first drain upper electrode 232, and the connection electrode 610 may be formed of the same material and have the same layer. can be placed in Accordingly, the second source electrode 320, the second drain electrode 330, the first source electrode 220, the first drain upper electrode 232, and the connection electrode 610 may have the same stacked structure. And, they are made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. It can be formed as a single layer or multiple layers. For example, the second source electrode 320, the second drain electrode 330, the first source electrode 220, the first drain upper electrode 232, and the connection electrode 610 are formed in a multi-layer structure. In this case, the second source electrode 320, the second drain electrode 330, the first source electrode 220, the first drain upper electrode 232, and the connection electrode 610 may be formed as a triple layer. . When the second source electrode 420, the second drain electrode 330, the first source electrode 220, the first drain upper electrode 232, and the connection electrode 610 are formed in a triple layer, the lower layer and the upper layer It may be composed of an aluminum (Al) metal layer. And, the intermediate layer located between the lower layer and the upper layer may be composed of a titanium (Ti) metal layer.

The first drain upper electrode 232 and the first drain lower electrode 231 may include at least one different metal material layer.

A protective layer 80 may be formed on the second source electrode 430, the second drain electrode 330, the first source electrode 220, the first drain upper electrode 232, and the connection electrode 610. . A contact hole may be formed in the protective layer 80 to expose the first drain electrode 230 of the first thin film transistor 200. For example, a contact hole may be formed in the protective layer 80 to expose the first drain upper electrode 232 of the first drain electrode 230. However, the present invention is not limited to this, and a contact hole may be formed in the protective layer 80 to expose the second drain electrode 330 or the second source electrode 320 of the second thin film transistor 300. The protective layer 80 may be a single layer or a multi-layer made of at least one of an inorganic material and an organic material. When the protective layer 80 includes an inorganic material, it may be a silicon oxide (SiOx)-based material or a silicon nitride (SiNx)-based material. And, when the protective layer 80 contains an organic material, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. ), etc. may be organic substances.

And, when the protective layer 80 is made of multiple layers, the protective layer 80 may be made of a first organic layer and a second organic layer. Additionally, the first organic layer and the second organic layer may be made of different materials or the same material. As another example, the protective layer 80 may be composed of a first inorganic layer and a second inorganic layer. And, the first inorganic layer and the second inorganic layer may be made of different materials. Alternatively, the protective layer 80 may be composed of an inorganic layer and an organic layer. At this time, the inorganic insect may be single-layered or multi-layered.

The first electrode 510 of the light emitting device 500 may be formed on the protective layer 80. The first electrode 510 may be connected to the first drain electrode 230 of the first thin film transistor 200 through a contact hole in the protective layer 80. For example, the first electrode 510 may be connected to the first drain upper electrode 232 of the first drain electrode 230 through a contact hole in the protective layer 80.

Accordingly, the light emitting device 500 of each subpixel (SP) may be electrically connected to the first thin film transistor 300 of the corresponding subpixel (SP). For example, the first electrode 510 of each subpixel SP may penetrate the protective layer 80 and be electrically connected to the first drain electrode 230 of the first thin film transistor 200. Accordingly, the first electrode 510 of each subpixel SP may be electrically connected to the first thin film transistor 200. However, the present invention is not limited to this, and the first electrode 510 of the light emitting device 500 may be connected to the second thin film transistor 300.

The first electrode 510 may be formed in a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). And, the opaque conductive film has a single-layer or multi-layer structure containing aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. It can be done. For example, the first electrode 510 may be sequentially formed of a transparent conductive film, an opaque conductive film, and a transparent conductive film. However, the present invention is not limited to this, and for example, a transparent conductive film and an opaque conductive film may be formed sequentially.

Since the display device according to the embodiment of the present specification is a top emission display device, the first electrode 510 may be an anode electrode. When the display device is bottom emitting, the first electrode 510 disposed on the protective layer 80 may be a cathode electrode.

The light emitting device 500 of each subpixel SP may be driven independently. For example, the first electrode 510 of each subpixel SP may be insulated from the first electrode 510 of an adjacent subpixel SP. The edge of each first electrode 510 may be covered by the bank layer 90. The bank layer 90 may be located on the protective layer 80. The light emitting layer 520 and the second electrode 530 of each subpixel SP may be stacked on the corresponding first electrode 510 exposed by the bank layer 90. The bank layer 90 may include an insulating material. For example, the bank layer 90 may include an organic insulating material. The bank layer 90 may include the same material as the protective layer 80 or a different material. Since the bank layer 90 can define the light emitting area of the display device, it can also be called a pixel defining layer. A spacer 91 may be further disposed on the bank layer 90. And, the spacer 91 may be formed of the same material as the bank layer 90.

Additionally, the light emitting layer 520 of the light emitting device 500 may be further disposed on the first electrode 510. The light emitting layer 520 may be formed on the first electrode 510 by forming a hole layer (HL), an light emitting material layer (EML), and an electron layer (EL) in that order or in the reverse order.

At least a portion of the light emitting layer 520 of each subpixel SP may extend onto the bank layer 90. For example, the hole layer HL and the electron layer EL of each subpixel SP may be connected to the hole layer HL and the electron layer EL of the adjacent subpixel SP. The light emitting material layer (EML) of each subpixel (SP) may be spaced apart from the light emitting material layer (EML) of an adjacent subpixel (SP). The second electrode 530 of each subpixel SP may extend onto the bank layer 90 . For example, the second electrode 530 of each subpixel SP may be connected to the second electrode 530 of an adjacent subpixel SP.

A sealing member that suppresses moisture penetration may be further disposed on the second electrode 530. The encapsulation member may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The second encapsulation layer may include a material different from the first encapsulation layer and the third encapsulation layer. For example, the first encapsulation layer and the third encapsulation layer may be an inorganic insulating film formed of an inorganic insulating material, and the second encapsulation layer may be an organic insulating film formed of an organic insulating material. The first encapsulation layer of the encapsulation member may be disposed on the second electrode 530 . And, the second encapsulation layer may be disposed on the first encapsulation layer. Additionally, the third encapsulation layer may be disposed on the second encapsulation layer.

The first and third encapsulation layers of the encapsulation member may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second encapsulation layer of the encapsulation member is made of organic materials such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. can be formed.

A display device according to an embodiment of the present specification includes a first semiconductor pattern including poly-silicon, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first semiconductor pattern connected to the first semiconductor pattern. a first thin film transistor including a first source electrode and a first drain electrode, a second semiconductor pattern including an oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer therebetween, and A second thin film transistor including a second source electrode and a second drain electrode connected to the second semiconductor pattern, a first storage electrode integrally connected to the first semiconductor pattern, and a first gate insulating layer therebetween. It may include a storage capacitor including a second storage electrode overlapping the storage electrode, and a connection electrode integrally connected to the second drain electrode and in contact with the second storage electrode.

According to an embodiment of the present specification, it may further include a first interlayer insulating layer disposed on the first gate electrode and the second storage electrode. Additionally, the first drain electrode may include a first drain lower electrode disposed on the first interlayer insulating layer and a first drain upper electrode disposed on the first drain lower electrode.

According to an embodiment of the present specification, the storage capacitor may further include a third storage electrode that overlaps the second storage electrode with the first interlayer insulating layer interposed therebetween.

According to an embodiment of the present specification, the third storage electrode is connected to the first drain lower electrode and may be configured as one piece.

According to an embodiment of the present specification, the second storage electrode may have the same stacked structure as the first gate electrode.

According to an embodiment of the present specification, the first drain upper electrode and the first drain lower electrode may include at least one different metal material layer.

According to an embodiment of the present specification, the first source electrode, the first drain upper electrode, the connection electrode, the second source electrode, and the second drain electrode are disposed on the same layer and may have the same stacked structure.

A display device according to an embodiment of the present specification includes a first semiconductor pattern including a first semiconductor, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first semiconductor pattern connected to the first semiconductor pattern. a first thin film transistor including a first source electrode and a first drain electrode, a second semiconductor pattern including a second semiconductor different from the first semiconductor, and a second semiconductor pattern overlapping with the second gate insulating layer therebetween. A second thin film transistor including a second gate electrode and a second source electrode and a second drain electrode connected to the second anti-doped pattern, a second storage electrode disposed on the same layer as the first gate electrode, and a second It may include a storage capacitor including a third storage electrode that overlaps the storage electrode.

According to an embodiment of the present specification, it may further include a first interlayer insulating layer disposed on the first gate electrode and the second storage electrode. The third storage electrode may overlap the second storage electrode with the first interlayer insulating layer interposed therebetween.

According to an embodiment of the present specification, the first drain electrode may include a first drain lower electrode disposed on the first interlayer insulating layer and a first drain upper electrode disposed on the first drain lower electrode.

According to an embodiment of the present specification, the third storage electrode is connected to the first drain lower electrode and may be configured as one piece.

According to an embodiment of the present specification, the first drain upper electrode and the first drain lower electrode may include at least one different metal material layer.

According to an embodiment of the present specification, the storage capacitor may further include a first storage electrode. Additionally, the first storage electrode is integrally connected to the first semiconductor pattern and may be connected to the second storage electrode with the first gate insulating layer interposed therebetween.

According to an embodiment of the present specification, it is integrally connected to the second drain electrode and may further include a connection electrode in contact with the second storage electrode.

100: display device
10: substrate
20: first buffer layer
30: first gate insulating layer
40: first interlayer insulating layer
50: second buffer layer
60: second gate insulating layer
70: second interlayer insulating layer
80: protective layer
90: Bank layer
91: spacer
500: Light emitting device
610: connection electrode
710: Shield pattern
200: first thin film transistor
300: Second thin film transistor
400: storage capacitor

Claims (14)

A first semiconductor pattern including poly-silicon, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer therebetween, and a first source electrode and a first drain connected to the first semiconductor pattern. A first thin film transistor including an electrode;
A second semiconductor pattern including an oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer interposed therebetween, and a second source electrode and a second drain electrode connected to the second semiconductor pattern. A second thin film transistor including;
a storage capacitor including a first storage electrode integrally connected to the first semiconductor pattern, and a second storage electrode overlapping the first storage electrode with the first gate insulating layer interposed therebetween; and
It is integrally connected to the second drain electrode and includes a connection electrode in contact with the second storage electrode,
Further comprising a first interlayer insulating layer disposed on the first gate electrode and the second storage electrode,
The first drain electrode includes a first drain lower electrode disposed on the first interlayer insulating layer and a first drain upper electrode disposed on the first drain lower electrode,
The storage capacitor further includes a third storage electrode overlapping the second storage electrode with the first interlayer insulating layer interposed therebetween,
The third storage electrode is connected to the first drain lower electrode and is integrally formed,
The first source electrode, the first drain upper electrode, the connection electrode, the second source electrode, and the second drain electrode are disposed in contact with each other on the same layer and have the same stacked structure.
delete delete delete According to paragraph 1,
The display device wherein the second storage electrode has the same stacked structure as the first gate electrode.
According to paragraph 1,
The first drain upper electrode and the first drain lower electrode include at least one different metal material layer.
delete A first semiconductor pattern including a first semiconductor, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer therebetween, and a first source electrode and a first drain connected to the first semiconductor pattern. A first thin film transistor including an electrode;
A second semiconductor pattern including a second semiconductor different from the first semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer interposed therebetween, and a second source connected to the second semiconductor pattern. a second thin film transistor including an electrode and a second drain electrode; and
A storage capacitor including a second storage electrode disposed on the same layer as the first gate electrode, and a third storage electrode overlapping the second storage electrode,
Further comprising a first interlayer insulating layer disposed on the first gate electrode and the second storage electrode,
The third storage electrode overlaps the second storage electrode with the first interlayer insulating layer interposed therebetween,
The first drain electrode includes a first drain lower electrode disposed on the first interlayer insulating layer and a first drain upper electrode disposed on the first drain lower electrode,
The third storage electrode is connected to the first drain lower electrode and is integrally formed,
The first source electrode, the first drain upper electrode, the second source electrode, and the second drain electrode are disposed in contact with each other on the same layer and have the same stacked structure.
delete delete delete According to clause 8,
The first drain upper electrode and the first drain lower electrode include at least one different metal material layer.
According to clause 8,
The storage capacitor further includes a first storage electrode,
The first storage electrode is integrally connected to the first semiconductor pattern and overlaps the second storage electrode with the first gate insulating layer interposed therebetween.
According to clause 8,
The display device further includes a connection electrode integrally connected to the second drain electrode and in contact with the second storage electrode.

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