KR20210086276A - Display apparatus - Google Patents

Abstract

An embodiment of the present specification provides a display apparatus including: a first buffer layer on a substrate; a first semiconductor pattern disposed on the first buffer layer and including poly-silicon; a first thin film transistor including a first gate electrode overlapping the first semiconductor pattern with the first gate insulating layer interposed therebetween, and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a second buffer layer including a first buffer lower layer on the first gate electrode and a second buffer upper layer on the first buffer lower layer; a second semiconductor pattern disposed on the second buffer upper layer and including an oxide semiconductor; a second thin film transistor including a second gate electrode overlapping the second semiconductor pattern with the second gate insulating layer interposed therebetween, and a second source electrode and a second drain electrode connected to the second semiconductor pattern; and a storage capacitor including a first storage electrode disposed on the first gate insulating layer and overlapping the second semiconductor pattern, and a second storage electrode overlapping the first storage electrode with the first interlayer insulating layer interposed therebetween. In addition, in the display apparatus according to the embodiment of the present specification, the second gate insulating layer is disposed only in a region overlapping the second semiconductor pattern, and a width of the second gate insulating layer is greater than a width of the second gate electrode.

Description

display device {DISPLAY APPARATUS}

The present specification relates to a display device, and more particularly, to a display device having a sub-pixel structure capable of improving image quality.

As the information society develops, various types of display devices for displaying images have been developed. Among such display devices, there is a display device in which light emitting elements emitting light by themselves are formed on the display panel without a backlight unit outside the display panel.

And, in a display device in which light emitting elements are formed on a display panel, a plurality of pixels are defined in a display area where an image is displayed, and at least one thin film transistor is disposed for each sub-pixel in the plurality of pixels. includes

For example, the array substrate includes a driving thin film transistor for supplying a driving current to the light emitting device for each sub-pixel and a switching thin film transistor for supplying a gate signal to the driving thin film transistor.

On the other hand, in the array substrate of such a display device, the driving thin film transistor should be designed to be advantageous in gradation expression, and the switching thin film transistor should be designed to have a good On/Off Ratio. This is because, in the driving thin film transistor, the smaller the amount of current change with respect to the voltage change, the more advantageous the grayscale expression is, and the on-off of the switching thin film transistor must be fast.

However, the driving thin film transistor and the switching thin film transistor including the same semiconductor material disposed on the array substrate have the same characteristics. Therefore, in the conventional array substrate, it is difficult to design the characteristics of the driving thin film transistor and the switching thin film transistor differently according to the characteristics of the thin film transistor.

In addition, when a plurality of transistors having different semiconductors are designed, the process may be complicated and the production cost may increase.

According to the exemplary embodiment of the present specification, the second semiconductor pattern, the second gate insulating layer, and the second gate electrode may be formed by a single photolithography process in the same chamber. Accordingly, it is possible to reduce production costs by simplifying the process of forming the second semiconductor pattern, the second gate insulating layer, and the second gate electrode.

Also, according to the embodiment of the present specification, the second semiconductor material layer and the second gate insulating material layer may be etched using the same photoresist as a mask to form the second semiconductor pattern and the second gate insulating layer. Accordingly, the slope of both side surfaces of the second semiconductor pattern may be the same as the slope of both side surfaces of the second gate insulating layer. In addition, the second gate insulating layer may be formed only in the second channel region, the second source region, and the second drain region of the second semiconductor pattern. Also, the second gate insulating layer may be disposed to cover only the second channel region, the second source region, and the second drain region of the second semiconductor pattern.

In order to achieve the above object, a display device according to an exemplary embodiment of the present specification includes a first buffer layer on a substrate, a first semiconductor pattern disposed on the first buffer layer and including poly-silicon, and a first gate insulating layer interposed therebetween. a first thin film transistor including a first gate electrode overlapping the first semiconductor pattern, and a first source electrode and a first drain electrode connected to the first semiconductor pattern, a first buffer lower layer and a second layer on the first gate electrode A second buffer layer including a second buffer upper layer on the lower buffer layer, a second semiconductor pattern disposed on the second buffer upper layer and including an oxide semiconductor, and a second overlapping second semiconductor pattern with a second gate insulating layer interposed therebetween a second thin film transistor including a gate electrode and a second source electrode and a second drain electrode connected to the second semiconductor pattern, a first storage electrode disposed on the first gate insulating layer and overlapping the second semiconductor pattern, and The storage capacitor may include a storage capacitor including a second storage electrode overlapping the first storage electrode with the first interlayer insulating layer interposed therebetween. In addition, the second gate insulating layer is disposed only in the region overlapping the second semiconductor pattern, and the width of the second gate insulating layer may be greater than the width of the second gate electrode.

In another aspect, the display device according to the exemplary embodiment of the present specification includes a first semiconductor pattern including a first semiconductor, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first A first thin film transistor including a first source electrode and a first drain electrode connected to a semiconductor pattern, a second semiconductor pattern including a second semiconductor different from the first semiconductor, and a second semiconductor with a second gate insulating layer therebetween It may include a second thin film transistor including a second gate electrode overlapping the pattern, and a second source electrode and a second drain electrode connected to the second semiconductor pattern. In addition, the second gate insulating layer may be disposed only on the second semiconductor pattern, and the slope of both sides of the second gate insulating layer may be the same as that of both sides of the second semiconductor pattern.

According to the embodiments of the present specification, the second semiconductor pattern, the second gate insulating layer, and the second gate electrode may be formed by a single photolithography process in the same chamber. Accordingly, it is possible to reduce production costs by simplifying the process of forming the second semiconductor pattern, the second gate insulating layer, and the second gate electrode.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a system configuration diagram of a display device according to embodiments of the present specification.
2 is an equivalent circuit of a sub-pixel of a display device according to embodiments of the present specification.
3 is a diagram illustrating a cross-sectional structure in a sub-pixel of a display device according to embodiments of the present specification.
4A to 4F are diagrams illustrating a process of forming a thin film transistor positioned in region A of FIG. 3 .

Hereinafter, some embodiments of the present specification will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present specification, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present specification, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in a singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present specification, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when two or more components are described as being "connected", "coupled" or "connected", the two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal flow relation related to the components, the operation method, the manufacturing method, etc., for example, a temporal precedence relationship such as "after", "after", "after", "before", etc. Or, when a flow precedence relationship is described, it may include a case where it is not continuous unless "immediately" or "directly" is used.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

1 is a system configuration diagram of a display device according to embodiments of the present specification.

Referring to FIG. 1 , in the display device 100 according to the present exemplary embodiment, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of data lines DL and a plurality of gate lines are disposed. The display panel 110 may include a display panel 110 in which a plurality of sub-pixels SP connected to the GL are arranged, and a driving circuit for driving the display panel 110 .

Functionally, the driving circuit includes the data driving circuit 120 driving the plurality of data lines DL, the gate driving circuit 130 driving the plurality of gate lines GL, and the data driving circuit 120 . ) and the controller 140 for controlling the gate driving circuit 130 , and the like.

In the display panel 110 , the plurality of data lines DL and the plurality of gate lines GL may be disposed to cross each other. For example, the plurality of data lines DL may be arranged in rows or columns, and the plurality of gate lines GL may be arranged in columns or rows. Hereinafter, for convenience of description, it is assumed that the plurality of data lines DL are arranged in rows and the plurality of gate lines GL are arranged in columns.

The controller 140 supplies various control signals DCS and GCS necessary for driving operations of the data driving circuit 120 and the gate driving circuit 130 to control the data driving circuit 120 and the gate driving circuit 130 . Control.

The controller 140 starts scanning according to the timing implemented in each frame, and converts the input image data input from the outside to match the data signal format used by the data driving circuit 120 to convert the converted image data DATA ) and control the data drive at an appropriate time according to the scan.

The above-described controller 140, along with the input image data, includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal (CLK), including various Receive timing signals from the outside (eg host system).

The controller 140 converts the input image data input from the outside according to the data signal format used by the data driving circuit 120 to output the converted image data DATA, and the data driving circuit 120 and In order to control the gate driving circuit 130 , the data driving circuit 120 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, an input DE signal, and a clock signal, and generates various control signals. ) and the gate driving circuit 130 .

For example, in order to control the gate driving circuit 130 , the controller 140 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable). Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 130 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, in order to control the data driving circuit 120 , the controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Various data control signals (DCS: Data Control Signal) including output enable) are output. Here, the source start pulse SSP controls the data sampling start timing of one or more source-driver integrated circuits constituting the data driving circuit 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source-driver integrated circuits. The source output enable signal SOE controls the output timing of the data driving circuit 120 .

The controller 140 may be a timing controller used in a conventional display technology or a control device capable of further performing other control functions including a timing controller.

The controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 drives the plurality of data lines DL by receiving the image data DATA from the controller 140 and supplying data voltages to the plurality of data lines DL. Here, the data driving circuit 120 is also referred to as a source driving circuit.

The data driving circuit 120 may be implemented by including at least one source-driver integrated circuit (S-DIC). Each source-driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, and the like. have. Each source-driver integrated circuit (S-DIC) may further include an analog-to-digital converter (ADC) in some cases.

Each source-driver integrated circuit (S-DIC) is a Tape Automated Bonding (TAB) method, a Chip On Glass (COG) method, or a Chip On Panel (COP) method. As a result, it may be connected to a bonding pad of the display panel 110 , or may be directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. In addition, each source-driver integrated circuit (S-DIC) may be implemented in a chip-on-film (COF) method mounted on a source-circuit film connected to the display panel 110 .

The gate driving circuit 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 is also referred to as a scan driving circuit.

The gate driving circuit 130 may include a shift register, a level shifter, and the like.

The gate driving circuit 130 may be configured for the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method. ) may be connected to a bonding pad of , or may be implemented as a GIP (Gate In Panel) type and disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. . In addition, the gate driving circuit 130 may be implemented in a chip-on-film (COF) method that is implemented as a plurality of gate driver integrated circuits (G-DICs) and is mounted on a gate-circuit film connected to the display panel 110 . .

The gate driving circuit 130 sequentially supplies a scan signal of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller 140 .

When a specific gate line is opened by the gate driving circuit 130 , the data driving circuit 120 converts the image data DATA received from the controller 140 into an analog data voltage to form a plurality of data lines DL. supplied with

The data driving circuit 120 may be located only on one side (eg, upper or lower side) of the display panel 110 , and in some cases, both sides (eg, on both sides of the display panel 110 ) according to a driving method, a panel design method, etc. For example, it can be located on both the upper side and the lower side).

The gate driving circuit 130 may be located only on one side (eg, left or right) of the display panel 110 , and in some cases, both sides (eg, left or right side) of the display panel 110 according to a driving method or a panel design method For example, it can be located on both the left and right side).

The plurality of gate lines GL disposed on the display panel 110 may include a plurality of scan lines SCL and a plurality of light emission control lines EML. The plurality of scan lines SCL and the plurality of emission control lines EML are gate nodes of different types of transistors (scan transistors, emission control transistors) and transmit different types of gate signals (scan signals, emission control signals) to each other. wires that carry them.

The gate driving circuit 130 outputs emission control signals to a scan driving circuit that outputs scan signals to a plurality of scan lines that are one type of the gate line GL and a plurality of emission control lines that are different types of the gate line GL. It may include a light emitting driving circuit that

2 is an equivalent circuit of a sub-pixel SP of a display device according to embodiments of the present specification.

Referring to FIG. 2 , each subpixel SP may include a light emitting device ED, first to sixth transistors T1 to T6 , and a storage capacitor Cst.

Referring to FIG. 2 , each subpixel SP has a first node N1 corresponding to a source node or a drain node of the second transistor T2 and a second node N1 corresponding to the gate node of the second transistor T2 . The node N2, the third node N3 corresponding to the drain node or the source node of the second transistor T2, and the fourth node N4 corresponding to the pixel electrode PE of the light emitting device ED, etc. includes the main nodes of

The light emitting device ED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE. The light emitting layer EL is positioned between the pixel electrode PE and the common electrode CE. The pixel electrode PE and the light emitting layer EL are disposed in each subpixel SP. However, the common electrode CE may be commonly disposed in the plurality of subpixels SP. A ground voltage VSS corresponding to the common voltage may be applied to the common electrode CE.

The second transistor T2 among the first to sixth transistors T1 to T6 is a driving transistor (DRT) for driving the light emitting device ED.

Five transistors connected to the gate nodes of the remaining five transistors T1 , T3 , T4 , T5 , and T6 except for the second transistor T2 which is the driving transistor DRT among the first to sixth transistors T1 to T6 gate lines GL of

The five gate lines GL may include first to third scan lines SCL1 , SCL2 , and SCL3 and first and second emission control lines EML1 and EML2 .

The third transistor T3 is electrically connected between the second node N2 and the third node N3 according to the first scan signal Scan1(n) applied to the gate node through the first scan line SCL1 . to control

The first transistor T1 is a data line that supplies the first node N1 and the data voltage Vdata according to the second scan signal Scan2(n) applied to the gate node through the second scan line SCL2. Controls the electrical connection between (DL).

In the sixth transistor T6 , the fourth node N4 and the initialization voltage Vini are applied according to the third scan signal Scan2(n-1) applied to the gate node through the third scan line SCL3. Controls the electrical connection between the initialization voltage nodes NVINI.

The fourth transistor T4 receives the first node N1 and the driving voltage VDD according to the first emission control signal EM1(n) applied to the gate node through the first emission control line EML1. Controls the electrical connection between the driving voltage nodes NVDD.

The fifth transistor T5 is electrically connected between the third node N3 and the fourth node N4 according to the second emission control signal EM2(n) applied to the gate node through the second emission control line EML2. control the connection.

Referring to FIG. 2 , the storage capacitor Cst includes a first plate PLT1 and a second plate PLT2 . The first plate PLT1 is electrically connected to the gate node of the second transistor T2 serving as the driving transistor DRT, and the second plate PLT2 is electrically connected to the DC voltage node. Here, the DC voltage node may include, for example, a driving voltage node NVDD.

Referring to FIG. 2 , the storage capacitor Cst may be electrically connected between the second node N2 and the driving voltage node NVDD. Here, the second node N2 may correspond to the gate node of the second transistor T2 serving as the driving transistor DRT, and the driving voltage node NVDD may be a DC voltage node.

Referring to FIG. 2 , the second transistor T2 among the first to sixth transistors T1 to T6 may be a P-type transistor. For example, the second transistor T2 among the first to sixth transistors T1 to T6 may be a P-type transistor, and the remaining first and third to sixth transistors T6 may be an N-type transistor. However, the present invention is not limited thereto, and at least one of the first to sixth transistors T1 to T6 may be an N-type transistor, and all other transistors may be a P-type transistor. Alternatively, all of the first to sixth transistors T1 to T6 may be N-type transistors.

As described above, by designing the second transistor T2 serving as the driving transistor DRT as a P-type transistor, the storage capacitor Cst is connected to the second node N2 that is the gate node of the second transistor T2 and the DC voltage. It may be formed between the driving voltage node NVDD, which is a node.

One of both ends of the storage capacitor Cst is connected to the driving voltage node NVDD, which is a DC voltage node, thereby preventing a voltage change of the second node N2, which is the other one of both ends of the storage capacitor Cst. The second node N2 corresponds to the gate node of the second transistor T2 serving as the driving transistor DRT.

In addition, according to the embodiments of the present specification, the second transistor T2 serving as the driving transistor DRT is designed as a P-type transistor advantageous in the operation reliability and current supply performance because operation reliability and current supply performance are most important. do. However, the remaining first, third to sixth transistors T6 may be transistors whose switching speed is more important than current supply performance. Accordingly, the first, third to sixth transistors T6 may be designed as N-type transistors having a fast switching speed due to high carrier mobility. Accordingly, the driving performance of the sub-pixel SP may be greatly improved.

Meanwhile, the display device 100 according to the embodiments of the present specification may be a self-luminous display such as an organic light emitting diode (OLED) display, a quantum dot display, and a micro light emitting diode (LED) display. have.

When the display device 100 according to the embodiments of the present specification is an OLED display, each subpixel SP may include an organic light emitting diode (OLED) emitting light as a light emitting device ED. When the display device 100 according to the embodiments of the present specification is a quantum dot display, each subpixel SP may include a light emitting device ED made of quantum dots, which are semiconductor crystals that emit light by themselves. can When the display device 100 according to the embodiments of the present specification is a micro LED display, each sub-pixel SP emits light by itself and uses an inorganic-based micro LED (Micro Light Emitting Diode) as a light emitting device (ED). can be included as

3 is a diagram illustrating a cross-sectional structure in a sub-pixel of a display device according to embodiments of the present specification.

Referring to FIG. 3 , the display device 100 according to the embodiment of the present specification includes a substrate 10 , a first buffer layer 20 , a first gate insulating layer 30 , a first interlayer insulating layer 40 , The second buffer layer 50 , the second gate insulating layer 60 , the second interlayer insulating layer 70 , the protective layer 80 , the bank layer 90 , the spacer 91 , the light emitting device 500 , the first It may include a thin film transistor 200 , a second thin film transistor 300 , a storage capacitor 400 , a connection electrode 810 , and an auxiliary electrode 610 .

In addition, the first thin film transistor 200 may include a first semiconductor pattern 210 , a first source electrode 220 , a first drain electrode 230 , and a first gate electrode 240 . Also, the second thin film transistor 300 may include a second semiconductor pattern 310 , a second source electrode 320 , a second drain electrode 330 , and a second gate electrode 340 .

In addition, the storage capacitor 400 may include a first storage electrode 410 , a second storage electrode 420 , a third storage electrode 430 , and a fourth storage electrode 440 . In addition, the light emitting device 500 may include a first electrode 510 , a light emitting structure 520 , and a second electrode 530 .

Referring to FIG. 3 , the display device according to the embodiment of the present specification may include a substrate 10 . The substrate 10 may be made of double polyimide (PI) in order to prevent the performance of the display device 100 from being deteriorated due to moisture permeation. And, by forming an inorganic film between the two polyimides (PI), it is possible to block the moisture component from passing through the lower polyimide (PI), thereby improving product performance reliability.

By arranging an inorganic film between the two polyimides (PI) to form a substrate, the electric charge charged on the substrate 10 is prevented from affecting the first thin film transistor 200 to improve product reliability. can In addition, since the process of forming the metal layer in order to block the electric charge charged to the polyimide (PI) can be omitted, the process can be simplified and the production cost can be reduced.

The display device 100 according to the embodiment of the present specification may implement a display device for securing environmental reliability performance of a product by using double polyimide (PI) as a substrate. For example, as shown in FIG. 3 , the substrate 10 of the display device 100 includes a first substrate 11 , a second substrate 13 , and the first substrate 11 and the second substrate 13 . ) may include an inorganic insulating layer 12 formed between them. Inorganic insulating layer 12, when the first substrate 11 is charged with charge (charge), the charged charge to block the effect on the first thin film transistor 200 through the second substrate (13) can play a role In addition, the inorganic insulating layer 12 formed between the first substrate 11 and the second substrate 13 may block moisture components from penetrating and penetrating the first substrate 11 .

The first substrate 11 and the second substrate 13 may be a plastic material layer such as polyimide (PI). The inorganic insulating layer 12 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. In the display device 100 according to the exemplary embodiment of the present specification, a silicon oxide (SiOx) material may be formed as the inorganic insulating layer 12 of the substrate 10 . For example, a silicon dioxide (Silica or Silicon Dioxide: SiO ₂ ) material may be formed as the inorganic insulating layer 12 . However, the present invention is not limited thereto, and the inorganic insulating layer 12 _{may be formed of a double layer of silicon dioxide (SiO 2} ) and silicon nitride (SiNx).

The substrate 10 may include a sub-pixel SP defined by gate lines GL and data lines DL. A first thin film transistor 200 , a second thin film transistor 300 , a storage capacitor 400 , and a light emitting device 500 may be positioned in each sub-pixel SP. Each light emitting device 500 may be electrically connected to the first thin film transistor 200 to emit light having a specific color. As another example, each light emitting device 500 may be electrically connected to the second thin film transistor 300 to emit light having a specific color.

Referring to FIG. 3 , a first buffer layer 20 may be formed on the substrate 10 . The first buffer layer 20 may prevent contamination by the substrate 10 in the process of forming the pixel circuit. For example, the first buffer layer 20 may be formed between the substrate 10 and the first semiconductor pattern 210 of each sub-pixel SP. The first buffer layer 20 may include an insulating material. For example, the first buffer layer 20 may include a silicon oxide-based (SiOx) material layer and a silicon nitride-based (SiNx) material layer. The first buffer layer 20 may have a multi-layer structure. For example, the first buffer layer 20 may include a first lower buffer layer 21 and a first buffer upper layer 22 .

The first buffer lower layer 21 may be disposed on the substrate 10 , and the first buffer upper layer 22 may be disposed on the first buffer lower layer 21 . The first buffer lower layer 21 may be formed as a multilayer including a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx). For example, the first buffer lower layer 21 may be formed as a multilayer structure in which a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer are alternately formed.

In addition, the first buffer upper layer 22 may be formed as a single layer made of a silicon oxide (SiOx)-based material. For example, the first buffer upper layer 22 may be formed of a single layer made _{of a silicon dioxide (SiO 2 ) material.}

The first semiconductor pattern 210 may be positioned on the first buffer upper layer 22 of the first buffer layer 20 . The first semiconductor pattern 210 may include a semiconductor material. For example, the first semiconductor pattern 210 may include poly-silicon (Poly-Si), which is a polycrystalline semiconductor material. For example, the first semiconductor pattern 210 may include low temperature poly-silicon (LTPS).

The first semiconductor pattern 210 may include a first channel region 210C, a first source region 210S, and a first drain region 210D.

A first gate insulating layer 30 may be formed on the first semiconductor pattern 210 and the first buffer layer 20 . The first gate insulating layer 30 may include an insulating material. For example, the first gate insulating layer 30 may include a silicon oxide-based (SiOx) material. For example, silicon dioxide (SiO2) may be included among the silicon oxide-based (SiOx) materials. However, the present invention is not limited thereto, and the first gate insulating layer 30 may include a silicon nitride-based (SiNx) material. Alternatively, the first gate insulating layer 30 may be formed of a multilayer including a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx).

The first gate electrode 240 of the first thin film transistor 200 and the first storage electrode 410 of the storage capacitor 400 may be formed on the first gate insulating layer 30 . The first gate electrode 240 may overlap the first semiconductor pattern 210 with the first gate insulating layer 30 interposed therebetween. For example, the first gate electrode 240 may overlap the first channel region 210C of the first semiconductor pattern 210 with the first gate insulating layer 30 interposed therebetween.

The first gate electrode 240 and the first storage electrode 410 may include a conductive material. For example, the first gate electrode 240 and the first storage electrode 410 may include aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). It may include a metal such as, or an alloy thereof. Also, the first gate electrode 240 and the first storage electrode 410 may be formed of a single layer made of a metal or an alloy material or a multilayer thereof.

In addition, the first gate electrode 240 and the first storage electrode 410 may be made of the same material and disposed on the same layer. Also, the first gate electrode 240 and the first storage electrode 410 may have the same stacked structure.

The first storage electrode 410 may overlap the second semiconductor pattern 310 .

A first interlayer insulating layer 40 may be formed on the first gate electrode 240 , the first storage electrode 410 , and the first gate insulating layer 30 . The first interlayer insulating layer 40 may include an insulating material. The first interlayer insulating layer 40 may be a single layer including a silicon oxide-based (SiOx) material layer or a silicon nitride-based (SiNx) material layer. In the display device according to the embodiment of the present specification. The first interlayer insulating layer 40 is illustrated as a single layer, but is not limited thereto. As another example, it may be a multilayer including a silicon oxide-based (SiOx) material layer and a silicon nitride-based (SiNx) material layer. For example, when the first interlayer insulating layer 40 is formed of multiple layers, the first interlayer insulating layer 40 may include a first interlayer insulating lower layer and a first interlayer insulating upper layer. The first interlayer insulating lower layer may include the same insulating material as the first gate insulating layer 30 . In addition, the first interlayer insulating upper layer may include an insulating material different from that of the first interlayer insulating lower layer. For example, when the first gate insulating layer 30 includes a silicon oxide-based material (SiOx), the first interlayer insulating lower layer may include a silicon oxide-based material (SiOx). In addition, the first interlayer insulating upper layer may include a silicon nitride-based (SiNx) material.

A second storage electrode 420 of the storage capacitor 400 may be formed on the first interlayer insulating layer 40 . The second storage electrode 420 may overlap the first storage electrode 410 with the first interlayer insulating layer 40 interposed therebetween. The second storage electrode 420 may overlap the first storage electrode 410 with the first interlayer insulating layer 40 interposed therebetween to form the storage capacitor 400 . The second storage electrode 420 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W) or an alloy thereof. . The second storage electrode 420 may be formed of a single layer made of a metal or an alloy material or a multilayer thereof.

The second storage electrode 420 may overlap the second semiconductor pattern 310 .

A second buffer layer 50 may be formed on the second storage electrode 420 and the first interlayer insulating layer 40 . The second buffer layer 50 may be formed as a multi-layer including a silicon nitride (SiNx)-based material layer and a silicon oxide-based (SiOx) material layer. The second buffer layer 50 may be formed as a multi-layer in which silicon oxide (SiOx) and silicon nitride (SiNx) are alternately formed. For example, the second buffer layer 50 may include a first buffer lower layer 51 disposed on the first interlayer insulating layer 40 and a second buffer upper layer 52 disposed on the first buffer lower layer 51 . may include The first buffer lower layer 51 may include silicon nitride (SiNx). In addition, the first buffer upper layer 52 may include silicon oxide (SiOx). The thickness of the second buffer upper layer 52 may be greater than the thickness of the second buffer lower layer 51 . The first buffer including silicon nitride (SiNx) by forming the thickness of the first buffer upper layer 52 including silicon oxide (SiOx) to be greater than the thickness of the first buffer lower layer 51 including silicon nitride (SiNx) Hydrogen (H) generated or emitted from the lower layer 51 may be prevented from flowing into the second semiconductor pattern 310 of the second thin film transistor 300 .

A second buffer lower layer 51 of the second buffer layer 50 may be formed on the second storage electrode 420 and the first interlayer insulating layer 40 . Then, the second buffer lower layer 51 , the first interlayer insulating layer 40 , and the first gate insulating layer 30 are etched to expose the first semiconductor pattern 210 of the first thin film transistor 200 . holes can be formed. For example, by etching the second buffer lower layer 51 , the first interlayer insulating layer 40 , and the first gate insulating layer 30 , the first source region 210S of the first semiconductor pattern 210 and the second 1 A contact hole exposing the drain region 210D may be formed.

Then, the first buffer lower layer 51 may be etched to form a contact hole exposing the second storage electrode 420 .

Referring to FIG. 3 , a first source electrode 220 , a first drain electrode 230 , and a third storage electrode 430 may be disposed on the second buffer lower layer 51 . The first source electrode 220 and the first drain electrode 230 are the second buffer lower layer 51 , the first interlayer insulating layer 40 , and the first drain electrode exposed through the contact hole of the first gate insulating layer 30 . 1 may be connected to the semiconductor pattern 210 . For example, the first source electrode 220 may include a first semiconductor pattern exposed through a contact hole of the second buffer lower layer 51 , the first interlayer insulating layer 40 , and the first gate insulating layer 30 . It may be connected to the first source region 210S of the 210 . In addition, the first drain electrode 230 includes a first semiconductor pattern 210 exposed through a contact hole of the second buffer lower layer 51 , the first interlayer insulating layer 40 , and the first gate insulating layer 30 . may be connected to the first drain region 210D of

The third storage electrode 430 may be connected to the exposed second storage electrode 420 through a contact hole of the second buffer lower layer 51 .

The first source electrode 220 , the first drain electrode 230 , and the third storage electrode 430 may include aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and a metal such as tungsten (W) or an alloy thereof. And, they may be formed in a single layer or in multiple layers. The first source electrode 220 , the first drain electrode 230 , and the third storage electrode 430 are made of the same material and may be disposed on the same layer. In addition, the first source electrode 220 , the first drain electrode 230 , and the third storage electrode 430 may have the same stacked structure.

Referring to FIG. 3 , the second buffer upper layer 52 is to be formed on the first source electrode 220 , the first drain electrode 230 , the third storage electrode 430 , and the second buffer lower layer 51 . can In addition, the second semiconductor pattern 310 of the second thin film transistor 300 may be disposed on the second buffer upper layer 52 of the second buffer layer 50 . The second semiconductor pattern 310 of the second thin film transistor 300 may include a material different from that of the first semiconductor pattern 210 of the first thin film transistor 200 . The second semiconductor pattern 310 may include an oxide semiconductor. For example, the second semiconductor pattern 310 may include IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, ITZO (InSnZnO)-based IGTO (InGaSnO)-based )-based, GO (GaO)-based, GZTO (GaZnSnO)-based, and GZO (GaZnO)-based oxide semiconductor materials may be included. However, the embodiment of the present specification is not limited thereto, and the second semiconductor pattern 310 may be formed of other oxide semiconductor materials known in the art.

The second semiconductor pattern 310 includes a second channel region 310C overlapping the second gate electrode 340 , a second source region 310S connected to the second source electrode 320 , and a second drain electrode ( A second drain region 310D connected to the 330 may be included.

The second semiconductor pattern 310 may overlap the second storage electrode 420 with the second buffer layer 50 interposed therebetween. In addition, the second semiconductor pattern 310 may also overlap the first storage electrode 410 . Accordingly, the first storage electrode 410 and the second storage electrode 420 disposed to overlap the second semiconductor pattern 310 may serve to prevent external light from being introduced into the second semiconductor pattern 310 . have.

A second gate insulating layer 60 may be disposed on the second semiconductor pattern 310 . The second gate insulating layer 60 may be disposed only on the second semiconductor pattern 310 . For example, the second gate insulating layer 60 may be disposed only on the second semiconductor pattern 310 to overlap the second semiconductor pattern 310 . The second gate insulating layer 60 may include at least one of a silicon oxide-based (SiOx) material and a silicon nitride-based (SiNx) material. The second gate insulating layer 60 may have a single-layer or multi-layer structure.

The second gate electrode 340 of the second thin film transistor 300 may be disposed on the second gate insulating layer 60 . The second gate electrode 340 may overlap the second semiconductor pattern 310 with the second gate insulating layer 60 interposed therebetween. The second gate electrode 340 may include a conductive material. For example, the second gate electrode 340 may be formed of a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W) or an alloy thereof. may include In addition, the second gate electrode 340 may be formed as a single layer or a multilayer. For example, when formed as a multi-layer, the second gate electrode 340 may be formed as a multi-layer including a molybdenum (Mo) metal layer and a titanium (Ti) metal layer. When the second gate electrode 340 is a multilayer including a molybdenum (Mo) metal layer and a titanium (Ti) metal layer, the width of the titanium (Ti) metal layer may be greater than the width of the molybdenum (Mo) metal layer based on the cross-sectional view. .

The second semiconductor pattern 310 , the second gate insulating layer 60 , and the second gate electrode 340 may be formed by a single photolithography process.

A process of forming the second semiconductor pattern 310 , the second gate insulating layer 60 , and the second gate electrode 340 will be described with reference to FIGS. 4A to 4F . 4A to 4F are diagrams illustrating a process of forming the second thin film transistor 300 located in region A of FIG. 4 .

Referring to FIG. 4A , a second semiconductor material layer 310a , a second gate insulating material layer 60a , and a second gate electrode material layer 340a may be sequentially stacked on the second buffer upper layer 52 . . A photoresist 700 may be formed on the structure in which the second semiconductor material layer 310a, the second gate insulating material layer 60a, and the second gate electrode material layer 340a are sequentially stacked. The photoresist 700 may include a first photoresist 710 having a first thickness h1 , and a second photoresist 720 and a third photoresist 730 having a second thickness h2 . have. The first thickness h1 may be greater than the second thickness h2. Accordingly, based on the cross-sectional view, the first photoresist 710 having a first thickness h1 may be formed to be thicker than the second photoresist 720 and the third photoresist 730 having a second thickness h2. can

Referring to FIG. 4B , an etching process for patterning the second semiconductor material layer 310a , the second gate insulating material layer 60a , and the second gate electrode material layer 340a using the photoresist 700 as a mask This can proceed. Accordingly, regions of the second semiconductor material layer 310a, the second gate insulating material layer 60a, and the second gate electrode material layer 340a that do not overlap the photoresist 700 may be removed by an etching process. have. As described above, by the etching process using the photoresist 700 as a mask, the second semiconductor material layer 310a may be patterned to become the second semiconductor pattern 310 , and the second gate insulating material layer 60a may be It may be patterned to become the second gate insulating layer 60 . In addition, a portion of the second gate electrode material layer 340a may be removed by an etching process using the photoresist 700 as a mask.

An upper surface of the first semiconductor pattern 310 and a lower surface of the second gate insulating layer 60 may face and contact each other. In addition, the length of the upper surface of the second semiconductor pattern 310 and the length of the lower surface of the second gate insulating layer 60 may be the same. Since the second semiconductor material layer 310a and the second gate insulating material layer 60a are etched using the same photoresist 700 as a mask, the length of the upper surface of the second semiconductor pattern 310 and the second gate insulating layer The length of the lower surface of (60) may be formed to be the same.

And, since the second semiconductor pattern 310 and the second gate insulating layer 60 are etched using the same photoresist 700 as a mask, the slope of both sides of the second semiconductor pattern 310 is the second gate insulating layer ( 60) may be the same as the inclination of both sides.

And, as shown in FIG. 4C , the second photoresist 720 and the third photoresist 730 of the photoresist 700 may be removed by an ashing process. The ashing process is a process of decomposing, cleaning, and removing the photoresist 700 using ultraviolet (UV) or oxygen (O _{2 ) gas.} By the ashing process, the second photoresist 720 and the third photoresist 730 having a second thickness h2 smaller than the first thickness h1 may be removed. Accordingly, only the first photoresist 710 may be disposed on the second gate electrode material layer 340a.

And, as shown in FIG. 4D , by an etching process using the first photoresist 710 as a mask, the second gate electrode material layer 340a may be patterned to become the second gate electrode 340 . Based on the cross-sectional view, the width of the second gate electrode 340 may be smaller than the width of the second gate insulating layer 60 . For example, the length of the lower surface of the second gate electrode 340 may be smaller than the length of the upper surface of the second gate insulating layer 60 .

The second semiconductor pattern 310 , the second gate insulating layer 60 , and the second gate electrode 340 may be formed by a single photolithography process in the same chamber. Accordingly, it is possible to reduce production costs by simplifying the process of forming the second semiconductor pattern 310 , the second gate insulating layer 60 , and the second gate electrode 340 .

Referring to FIG. 4E , the first photoresist 710 may be removed by a secondary ashing process. In addition, the second source region 310S and the second drain region 310D of the second semiconductor pattern 310 may be made conductive by a conductive process. For example, the conductive process of the second source region 310S and the second drain region 310D may be a doping process using the second gate electrode 340 disposed on the second semiconductor pattern 310 as a mask. have. The doping process may be a doping process using a dopant, and the dopant may include at least one of boron, phosphorus, fluorine, and hydrogen. During the doping process, the second source region 310S and the second drain region 310D of the second semiconductor pattern 310 that do not overlap the second gate electrode 340 used as a mask may be conductive. The second channel region 310C of the second semiconductor pattern 310 may overlap the second gate electrode 340 with the second gate insulating layer 60 interposed therebetween.

An upper surface of the second semiconductor pattern 310 may contact a lower surface of the second gate insulating layer 60 . For example, the second channel region 310C, the second source region 310S, and the second drain region 310D of the second semiconductor pattern 310 may overlap the second gate insulating layer 60 . . The second channel region 310C, the second source region 310S, and the second drain region 310D of the second semiconductor pattern 310 may be covered by the second gate insulating layer 60 . In addition, the second gate insulating layer 60 may be formed only in the second channel region 310C, the second source region 310S, and the second drain region 310D of the second semiconductor pattern 310 . Accordingly, the second gate insulating layer 60 may be disposed to cover only the second channel region 310C, the second source region 310S, and the second drain region 310D of the second semiconductor pattern 310 . .

3 and 4F , a second interlayer insulating layer 70 may be formed on the second gate electrode 340 , the second gate insulating layer 60 , and the second buffer upper layer 52 . The second interlayer insulating layer 70 may include at least one of a silicon oxide-based (SiOx) material and a silicon nitride-based (SiNx) material. The second interlayer insulating layer 70 may have a single-layer or multi-layer structure.

Referring to FIG. 3 , a contact hole exposing the first drain electrode 230 of the first thin film transistor 200 may be formed by etching the second interlayer insulating layer 70 and the second buffer upper layer 52 . . For example, a contact hole may be formed through the second interlayer insulating layer 70 and the second buffer upper layer 52 to expose the first drain electrode 230 . As another example, the second interlayer insulating layer 70 and the second buffer upper layer 52 may be etched to form a contact hole exposing the first source electrode 220 of the first thin film transistor 200 . Then, the second interlayer insulating layer 70 and the second buffer upper layer 52 may be etched to form a contact hole exposing the third storage electrode 430 of the storage capacitor 700 . For example, a contact hole may be formed through the second interlayer insulating layer 70 and the second buffer upper layer 52 to expose the third storage electrode 430 .

In addition, the second interlayer insulating layer 70 and the second gate insulating layer 60 may be etched to form a contact hole exposing the second semiconductor pattern 310 of the second thin film transistor 300 . For example, through the second interlayer insulating layer 70 and the second gate insulating layer 60 , the second source region 310S and the second drain region 310D of the second semiconductor pattern 310 are exposed. A contact hole may be formed.

A second source electrode 320 , a second drain electrode 330 , a fourth storage electrode 440 , and a connection electrode 810 may be formed on the second interlayer insulating layer 70 .

Referring to FIG. 3 , the second source electrode 320 and the second drain electrode 330 of the second thin film transistor 300 have contact holes of the second interlayer insulating layer 70 and the second gate insulating layer 60 . It may be connected to the exposed second semiconductor pattern 310 through the . For example, the second source electrode 320 may have the second source region 310S of the second semiconductor pattern 310 exposed through the contact hole of the second interlayer insulating layer 70 and the second gate insulating layer 60 . ) can be associated with In addition, the second drain electrode 330 includes the second drain region 310D of the second semiconductor pattern 310 exposed through the contact hole of the second interlayer insulating layer 70 and the second gate insulating layer 60 , and can be connected

The connection electrode 810 may be connected to the first drain electrode 230 of the first thin film transistor 200 exposed through the contact hole of the second interlayer insulating layer 70 and the second buffer upper layer 52 .

The fourth storage electrode 440 may be connected to the third storage electrode 430 exposed through the contact hole of the second interlayer insulating layer 70 and the second buffer upper layer 52 . Accordingly, the fourth storage electrode 440 may be electrically connected to the second storage electrode 420 through the third storage electrode 430 .

Referring to FIG. 3 , the fourth storage electrode 440 and the second drain electrode 330 may be integrally connected to each other. Accordingly, the second storage electrode 420 may be electrically connected to the second drain electrode 330 of the second thin film transistor 300 through the fourth storage electrode 440 and the third storage electrode 430 . As another example, the fourth storage electrode 440 may be integrally connected to the second source electrode 320 .

The second source electrode 320 , the second drain electrode 330 , the fourth storage electrode 440 , and the connection electrode 810 may be formed of the same material and disposed on the same layer. In addition, the second source electrode 320 , the second drain electrode 330 , the fourth storage electrode 440 , and the connection electrode 810 may have the same stacked structure. And, they are molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), any one of neodymium (Nd) or alloys thereof It may be formed as a single layer or multiple layers. For example, when the second source electrode 320 , the second drain electrode 330 , the fourth storage electrode 440 , and the connection electrode 810 are formed in a multilayer structure, the second source electrode 320 is ), the second drain electrode 330 , the fourth storage electrode 440 , and the connection electrode 810 may be formed as a triple layer. When they are formed as a triple layer, the lower layer and the upper layer may be formed of an aluminum (Al) metal layer. In addition, the intermediate layer positioned between the lower layer and the upper layer may be formed of a titanium (Ti) metal layer.

A protective layer 80 may be formed on the second source electrode 320 , the second drain electrode 330 , the fourth storage electrode 440 , and the connection electrode 810 .

3 , the passivation layer 80 may include a first passivation layer 81 and a second passivation layer 80 disposed on the first passivation layer 81 . A contact hole for exposing the connection electrode 810 may be formed in the first passivation layer 81 . The first passivation layer 81 may be a single layer or multiple layers made of at least one of an inorganic material and an organic material. When the first passivation layer 81 includes an inorganic material, it may be a silicon oxide (SiOx)-based material or a silicon nitride (SiNx)-based material. And, when the first protective layer 81 includes an organic material, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin ( It may be an organic material such as polyimide resin).

In addition, an auxiliary electrode 610 may be formed on the first passivation layer 81 . The auxiliary electrode 610 may be connected to the exposed connection electrode 810 through the contact hole of the first protective layer 81 . Accordingly, the auxiliary electrode 610 may be electrically connected to the first thin film transistor 200 through the connection electrode 810 . For example, the auxiliary electrode 610 may be electrically connected to the first drain electrode 230 of the first thin film transistor 200 through the connection electrode 810 . The auxiliary electrode 610 may include any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or these It may be formed as a single layer or multiple layers made of an alloy of The auxiliary electrode 610 may be formed of the same material and stacked structure as the connection electrode 810 .

A second passivation layer 82 may be formed on the first passivation layer 81 and the auxiliary electrode 610 . The second protective layer 82 may be an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. have. The second passivation layer 82 may include a contact hole exposing the auxiliary electrode 610 .

The first electrode 510 of the light emitting device 500 may be formed on the second passivation layer 82 of the passivation layer 80 . The first electrode 510 may be connected to the exposed auxiliary electrode 610 through the contact hole of the second protective layer 82 . Accordingly, the first electrode 510 may be electrically connected to the first thin film transistor 200 through the auxiliary electrode 610 and the connection electrode 810 . For example, the first electrode 510 is connected to the auxiliary electrode 610 through the contact hole of the second protection layer 82 , and the auxiliary electrode 610 is connected to the auxiliary electrode 610 through the contact hole of the first protection layer 81 . It may be connected to the connection electrode 810 . In addition, the connection electrode 610 may be connected to the first drain electrode 230 of the first thin film transistor 200 through the contact hole of the second interlayer insulating layer 70 and the second buffer upper layer 52 . However, the present invention is not limited thereto. For example, when the connection electrode 810 is connected to the second thin film transistor 300 , the first electrode 510 is electrically connected to the second thin film transistor 300 through the auxiliary electrode 610 and the connection electrode 810 . can be connected to

Accordingly, the light emitting device 500 of each sub-pixel SP may be electrically connected to the first thin film transistor 200 of the corresponding sub-pixel SP. For example, the first electrode 510 of each sub-pixel SP may be electrically connected to the first drain electrode 230 of the first thin film transistor 200 through the auxiliary electrode 610 and the connection electrode 810 . can Accordingly, the first electrode 510 of each sub-pixel SP may be electrically connected to the first thin film transistor 200 . However, the present invention is not limited thereto, and the first electrode 510 of the light emitting device 500 may be electrically connected to the second thin film transistor 300 .

The first electrode 510 may be formed in a multilayer structure including a transparent conductive layer and an opaque conductive layer having high reflective efficiency. The transparent conductive layer may be made of a material having a relatively large work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). In addition, the opaque conductive film has a single-layer or multi-layer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. can be done For example, in the first electrode 510 , a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer may be sequentially formed. However, the present invention is not limited thereto, and for example, a transparent conductive layer and an opaque conductive layer may be sequentially formed.

Since the display device according to the embodiment of the present specification is a top emission display device, the first electrode 510 may be an anode electrode. When the display device is bottom emission, the first electrode 510 disposed on the protective layer 80 may be a cathode electrode.

The light emitting device 500 of each sub-pixel SP may be driven independently. For example, the first electrode 510 of each sub-pixel SP may be insulated from the first electrode 510 of the adjacent sub-pixel SP. An edge of each first electrode 510 may be covered by the bank layer 90 . The bank layer 90 may be positioned on the passivation layer 80 . The emission layer 520 and the second electrode 530 of each sub-pixel SP may be stacked on the corresponding first electrode 510 exposed by the bank layer 90 . The bank layer 90 may include an insulating material. For example, the bank layer 90 may include an organic insulating material. The bank layer 90 may include the same material as the passivation layer 80 or a different material. The bank layer 90 may define a light emitting area of the display device, and thus may be referred to as a pixel defining layer. A spacer 91 may be further disposed on the bank layer 90 . In addition, the spacer 91 may be formed of the same material as the bank layer 90 .

In addition, the light emitting layer 520 of the light emitting device 500 may be further disposed on the first electrode 510 . The emission layer 520 may be formed on the first electrode 510 in the order of the hole layer HL, the emission material layer EML, and the electron layer EL or in the reverse order.

At least a portion of the emission layer 520 of each sub-pixel SP may extend onto the bank layer 90 . For example, the hole layer HL and the electron layer EL of each sub-pixel SP may be connected to the hole layer HL and the electron layer EL of the adjacent sub-pixel SP. The light-emitting material layer EML of each sub-pixel SP may be spaced apart from the light-emitting material layer EML of the adjacent sub-pixel SP. The second electrode 530 of each sub-pixel SP may extend on the bank layer 90 . For example, the second electrode 530 of each sub-pixel SP may be connected to the second electrode 530 of an adjacent sub-pixel SP.

An encapsulation member for suppressing penetration of moisture may be further disposed on the second electrode 530 . The encapsulation member may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The second encapsulation layer may include a material different from that of the first encapsulation layer and the third encapsulation layer. For example, the first encapsulation layer and the third encapsulation layer may be an inorganic insulating film formed of an inorganic insulating material, and the second encapsulation layer may be an organic insulating film formed of an organic insulating material. The first encapsulation layer of the encapsulation member may be disposed on the second electrode 530 . In addition, the second encapsulation layer may be disposed on the first encapsulation layer. Also, the third encapsulation layer may be disposed on the second encapsulation layer.

The first encapsulation layer and the third encapsulation layer of the encapsulation member may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second encapsulation layer of the encapsulation member is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. can be formed.

The display device according to the exemplary embodiment of the present specification includes a first buffer layer on a substrate, a first semiconductor pattern disposed on the first buffer layer and including poly-silicon, and the first semiconductor pattern with a first gate insulating layer interposed therebetween. a first thin film transistor including a first gate electrode, a first source electrode and a first drain electrode connected to the first semiconductor pattern, a first buffer lower layer on the first gate electrode, and a second buffer upper layer on the second buffer lower layer a second buffer layer comprising: a second semiconductor pattern disposed on the second buffer upper layer and including an oxide semiconductor; a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer interposed therebetween; and a second semiconductor A second thin film transistor including a second source electrode and a second drain electrode connected to the pattern, a first storage electrode disposed on the first gate insulating layer and overlapping the second semiconductor pattern, and the first interlayer insulating layer are interposed therebetween may include a storage capacitor including a second storage electrode disposed on the first storage electrode and overlapping the first storage electrode. In addition, the second gate insulating layer is disposed only in the region overlapping the second semiconductor pattern, and the width of the second gate insulating layer may be greater than the width of the second gate electrode.

According to the embodiment of the present specification, the first interlayer insulating layer may be disposed on the first gate electrode and the first storage electrode, and the second buffer lower layer may be disposed on the second storage electrode and the first interlayer insulating layer.

According to the embodiment of the present specification, the first source electrode and the first drain electrode may be disposed between the second buffer lower layer and the second buffer upper layer.

According to an embodiment of the present specification, the storage capacitor may further include a third storage electrode disposed between the second buffer upper layer and the second buffer upper layer and connected to the second storage electrode through a contact hole of the second lower buffer layer. .

According to the embodiment of the present specification, a second interlayer insulating layer disposed on the second buffer upper layer, the second gate insulating layer, and the second gate electrode may be further included. In addition, the second source electrode and the second drain electrode may be connected to the second semiconductor pattern through contact holes of the second interlayer insulating layer and the second gate insulating layer.

According to an embodiment of the present specification, the storage capacitor may further include a fourth storage electrode connected to the third storage electrode through a contact hole of the second interlayer insulating layer and the second buffer upper layer.

According to the embodiment of the present specification, the length of the lower surface of the second gate insulating layer may be the same as the length of the upper surface of the second semiconductor pattern.

According to the embodiment of the present specification, the second gate insulating layer may be disposed only in a region overlapping the second semiconductor pattern.

A display device according to an exemplary embodiment of the present specification includes a first semiconductor pattern including a first semiconductor, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a connection to the first semiconductor pattern a first thin film transistor including a first source electrode and a first drain electrode, a second semiconductor pattern including a second semiconductor different from the first semiconductor, and a second semiconductor pattern with a second gate insulating layer interposed therebetween. It may include a second thin film transistor including a second gate electrode and a second source electrode and a second drain electrode connected to the second semiconductor pattern. In addition, the second gate insulating layer may be disposed only on the second semiconductor pattern, and the slope of both sides of the second gate insulating layer may be the same as that of both sides of the second semiconductor pattern.

According to an exemplary embodiment of the present specification, the second semiconductor pattern includes a second channel region overlapping the second gate electrode, a second source region connected to the second source electrode, and a second drain region connected to the second drain electrode. may include In addition, the second gate insulating layer may be disposed to cover only the second channel region, the second source region, and the second drain region of the second semiconductor pattern.

According to the embodiment of the present specification, the length of the lower surface of the second gate insulating layer and the length of the upper surface of the second semiconductor pattern may be the same.

According to the embodiment of the present specification, the length of the lower surface of the second gate electrode may be smaller than the length of the upper surface of the second gate insulating layer.

According to the embodiment of the present specification, an interlayer insulating layer disposed on the second gate electrode may be further included. In addition, the second source electrode and the second drain electrode may be respectively connected to the second source region and the second drain region of the second semiconductor pattern through contact holes formed in the interlayer insulating layer and the second gate insulating layer.

According to the embodiment of the present specification, the second gate insulating layer may be disposed only in a region overlapping the second semiconductor pattern.

100: display device
10: substrate
20: first buffer layer
30: first gate insulating layer
40: first interlayer insulating layer
50: second buffer layer
60: second gate insulating layer
70: second interlayer insulating layer
80: protective layer
90: bank layer
91: spacer
500: light emitting device
610: auxiliary electrode
700: photoresist
810: connection electrode
200: first thin film transistor
300: second thin film transistor
400: storage capacitor

Claims (14)

a first buffer layer on the substrate;
a first semiconductor pattern disposed on the first buffer layer and including poly-silicon, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and connected to the first semiconductor pattern a first thin film transistor including a first source electrode and a first drain electrode;
a second buffer layer including a first buffer lower layer on the first gate electrode and a second buffer upper layer on the first buffer lower layer;
a second semiconductor pattern disposed on the second buffer upper layer and including an oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer interposed therebetween, and connected to the second semiconductor pattern a second thin film transistor including a second source electrode and a second drain electrode;
A storage capacitor comprising: a first storage electrode disposed on the first gate insulating layer and overlapping the second semiconductor pattern; and a second storage electrode overlapping the first storage electrode with a first interlayer insulating layer interposed therebetween; includes,
The second gate insulating layer is disposed in a region overlapping the second semiconductor pattern, and a width of the second gate insulating layer is greater than a width of the second gate electrode. According to claim 1,
the first interlayer insulating layer is disposed on the first gate electrode and the first storage electrode;
The second buffer lower layer is disposed on the second storage electrode and the first interlayer insulating layer. 3. The method of claim 2,
The first source electrode and the first drain electrode are disposed between the second buffer lower layer and the second buffer upper layer. 4. The method of claim 3,
The storage capacitor is
and a third storage electrode disposed between the second lower buffer layer and the second buffer upper layer and connected to the second storage electrode through a contact hole of the second buffer lower layer. 5. The method of claim 4,
Further comprising a second interlayer insulating layer disposed on the second buffer upper layer, the second gate insulating layer, and the second gate electrode,
The second source electrode and the second drain electrode are connected to the second semiconductor pattern through a contact hole of the second interlayer insulating layer and the second gate insulating layer. 6. The method of claim 5,
The storage capacitor is
and a fourth storage electrode connected to the third storage electrode through a contact hole of the second interlayer insulating layer and the second buffer upper layer. According to claim 1,
A length of a lower surface of the second gate insulating layer is the same as a length of an upper surface of the second semiconductor pattern. According to claim 1,
and the second gate insulating layer is disposed only in a region overlapping the second semiconductor pattern. A first semiconductor pattern including a first semiconductor, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first source electrode and a first drain connected to the first semiconductor pattern a first thin film transistor including an electrode;
A second semiconductor pattern including a second semiconductor different from the first semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer interposed therebetween, and a second connected to the second semiconductor pattern A second thin film transistor including a source electrode and a second drain electrode,
The second gate insulating layer is disposed on the second semiconductor pattern, and a slope of both sides of the second gate insulating layer is the same as a slope of both sides of the second semiconductor pattern. 10. The method of claim 9,
The second semiconductor pattern includes a second channel region overlapping the second gate electrode, a second source region connected to the second source electrode, and a second drain region connected to the second drain electrode,
The second gate insulating layer is disposed to cover only the second channel region, the second source region, and the second drain region of the second semiconductor pattern. 11. The method of claim 10,
A length of a lower surface of the second gate insulating layer and a length of an upper surface of the second semiconductor pattern are the same. 12. The method of claim 11,
A length of a lower surface of the second gate electrode is smaller than a length of an upper surface of the second gate insulating layer. 11. The method of claim 10,
An interlayer insulating layer disposed on the second gate electrode,
The second source electrode and the second drain electrode are respectively connected to the second source region and the second drain region of the second semiconductor pattern through a contact hole formed in the interlayer insulating layer and the second gate insulating layer. , display device. 10. The method of claim 9,
and the second gate insulating layer is disposed only in a region overlapping the second semiconductor pattern.

Images