KR20210085785A - Display device - Google Patents

Abstract

An embodiment of the present specification provides a display apparatus including: a first buffer layer including a first buffer lower layer on a substrate and a first buffer upper layer on the first buffer lower layer; a first shielding pattern between the first buffer lower layer and the first buffer upper layer; a metal pattern disposed to be spaced apart from the first shielding pattern and interposed between the first buffer lower layer and the first buffer upper layer; a first semiconductor pattern disposed on the first buffer upper layer and including poly-silicon; a first thin film transistor including a first gate electrode overlapping the first semiconductor pattern with the first gate insulating layer interposed therebetween, and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a first interlayer insulating layer on the first gate electrode; a second buffer layer on the first interlayer insulating layer; a second semiconductor pattern disposed on the second buffer layer and including an oxide semiconductor; and a second thin film transistor including a second gate electrode overlapping the second semiconductor pattern with the second gate insulating layer interposed therebetween, and a second source electrode and a second drain electrode connected to the second semiconductor pattern.

Description

display device {DISPLAY DEVICE}

The present specification relates to a display device, and more particularly, to a display device having a sub-pixel structure capable of improving image quality.

As the information society develops, various types of display devices for displaying images have been developed. Among such display devices, there is a display device in which light emitting elements emitting light by themselves are formed on the display panel without a backlight unit outside the display panel.

The display device in which light emitting elements are formed on a display panel defines a plurality of pixels in a display area where an image is displayed, and includes an array substrate on which at least one thin film transistor is installed for each sub-pixel in the plurality of pixels. include

For example, the array substrate includes a driving thin film transistor for supplying a driving current to the light emitting device for each sub-pixel and a switching thin film transistor for supplying a gate signal to the driving thin film transistor.

On the other hand, in the array substrate of such a display device, the driving thin film transistor should be designed to be advantageous in gradation expression, and the switching thin film transistor should be designed to have a good On/Off Ratio. This is because, in the driving thin film transistor, the smaller the amount of current change with respect to the voltage change, the more advantageous the grayscale expression is, and the on-off of the switching thin film transistor must be fast.

However, the driving thin film transistor and the switching thin film transistor including the same semiconductor material disposed on the array substrate have the same characteristics. Therefore, in the conventional array substrate, it is difficult to design the characteristics of the driving thin film transistor and the switching thin film transistor differently according to the characteristics of the thin film transistor.

In addition, when a plurality of transistors having different semiconductors are designed, the process may be complicated and the production cost may increase.

According to the embodiment of the present specification, a first shielding pattern, a first metal pattern, and a second metal pattern may be disposed between the first buffer upper layer and the first buffer lower layer. The first shielding pattern, the first metal pattern, and the second metal pattern may be a metal material layer. The first shielding pattern may serve to block charges charged to the substrate from forming a back bias and affecting the first channel region of the first semiconductor pattern. In addition, the first shielding pattern may block external light from penetrating the first channel region of the first semiconductor pattern through the substrate, thereby improving the reliability of the display device.

Also, according to the present specification, the first metal pattern may be disposed to be spaced apart from one side of the first shielding pattern. In addition, the second metal pattern may be disposed to be spaced apart from the other side surface of the first shielding pattern. In addition, the first metal pattern and the second metal pattern are formed on the first buffer lower layer due to over-etching when the first contact hole and the second contact hole for connecting the first source electrode and the first drain electrode and the first semiconductor pattern are formed. It can play a role in preventing etching.

In order to achieve the above object, in a display device according to an exemplary embodiment of the present specification, a first buffer layer including a first lower buffer layer on a substrate and a first buffer upper layer on the first buffer lower layer, a first lower buffer layer, and a first buffer upper layer A first shielding pattern therebetween, a metal pattern disposed spaced apart from the first shielding pattern and disposed between the first buffer lower layer and the first buffer upper layer, and a first semiconductor pattern disposed on the first buffer upper layer and including poly-silicon , a first thin film transistor including a first gate electrode overlapping a first semiconductor pattern with a first gate insulating layer interposed therebetween, and a first source electrode and a first drain electrode connected to the first semiconductor pattern, a first gate A first interlayer insulating layer on the electrode, a second buffer layer on the first interlayer insulating layer, and a second semiconductor pattern disposed on the second buffer layer and including an oxide semiconductor, a second gate insulating layer interposed therebetween The second thin film transistor may include a second gate electrode overlapping the second semiconductor pattern, and a second source electrode and a second drain electrode connected to the second semiconducting pattern.

According to the embodiment of the present specification, by configuring the first shielding pattern, charges charged to the substrate by the first shielding pattern form a back bias in the first channel region of the first semiconductor pattern. impact can be reduced. In addition, the first shielding pattern may block external light from penetrating the first channel region of the first semiconductor pattern through the substrate, thereby improving the reliability of the display device.

In addition, according to the present specification, since the first metal pattern and the second metal pattern are disposed to be spaced apart from one side and the other side of the first shielding pattern, to connect the first source electrode and the first drain electrode with the first semiconductor pattern When the first contact hole and the second contact hole are formed, it is possible to prevent the first buffer lower layer from being etched due to over-etching.

Effects according to the present specification are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a system configuration diagram of a display device according to embodiments of the present specification.
2 is an equivalent circuit of a sub-pixel of a display device according to embodiments of the present specification.
3 is a diagram illustrating a cross-sectional structure in a sub-pixel of a display device according to an exemplary embodiment of the present specification.

Hereinafter, some embodiments of the present specification will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present specification, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present specification, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in a singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present specification, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when two or more components are described as being "connected", "coupled" or "connected", the two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal flow relation related to the components, the operation method, the manufacturing method, etc., for example, a temporal precedence relationship such as "after", "after", "after", "before", etc. Or, when a flow precedence relationship is described, it may include a case where it is not continuous unless "immediately" or "directly" is used.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

1 is a system configuration diagram of a display device 100 according to embodiments of the present specification.

Referring to FIG. 1 , in the display device 100 according to the present exemplary embodiment, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of data lines DL and a plurality of gate lines are disposed. The display panel 110 may include a display panel 110 in which a plurality of sub-pixels SP connected to the GL are arranged, and a driving circuit for driving the display panel 110 .

Functionally, the driving circuit includes the data driving circuit 120 driving the plurality of data lines DL, the gate driving circuit 130 driving the plurality of gate lines GL, and the data driving circuit 120 . ) and the controller 140 for controlling the gate driving circuit 130 , and the like.

In the display panel 110 , the plurality of data lines DL and the plurality of gate lines GL may be disposed to cross each other. For example, the plurality of data lines DL may be arranged in rows or columns, and the plurality of gate lines GL may be arranged in columns or rows. Hereinafter, for convenience of description, it is assumed that the plurality of data lines DL are arranged in rows and the plurality of gate lines GL are arranged in columns.

The controller 140 supplies various control signals DCS and GCS necessary for driving operations of the data driving circuit 120 and the gate driving circuit 130 to control the data driving circuit 120 and the gate driving circuit 130 . Control.

The controller 140 starts scanning according to the timing implemented in each frame, and converts the input image data input from the outside to match the data signal format used by the data driving circuit 120 to convert the converted image data DATA ) and control the data drive at an appropriate time according to the scan.

The above-described controller 140, along with the input image data, includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal (CLK), including various Receive timing signals from the outside (eg host system).

The controller 140 converts the input image data input from the outside according to the data signal format used by the data driving circuit 120 to output the converted image data DATA, and the data driving circuit 120 and In order to control the gate driving circuit 130 , the data driving circuit 120 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, an input DE signal, and a clock signal, and generates various control signals. ) and the gate driving circuit 130 .

For example, in order to control the gate driving circuit 130 , the controller 140 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable). Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 130 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, in order to control the data driving circuit 120 , the controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Various data control signals (DCS: Data Control Signal) including output enable) are output. Here, the source start pulse SSP controls the data sampling start timing of one or more source-driver integrated circuits constituting the data driving circuit 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source-driver integrated circuits. The source output enable signal SOE controls the output timing of the data driving circuit 120 .

The controller 140 may be a timing controller used in a conventional display technology or a control device capable of further performing other control functions including a timing controller.

The controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 drives the plurality of data lines DL by receiving the image data DATA from the controller 140 and supplying data voltages to the plurality of data lines DL. Here, the data driving circuit 120 is also referred to as a source driving circuit.

The data driving circuit 120 may be implemented by including at least one source-driver integrated circuit (S-DIC). Each source-driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, and the like. have. Each source-driver integrated circuit (S-DIC) may further include an analog-to-digital converter (ADC) in some cases.

Each source-driver integrated circuit (S-DIC) is a Tape Automated Bonding (TAB) method, a Chip On Glass (COG) method, or a Chip On Panel (COP) method. As a result, it may be connected to a bonding pad of the display panel 110 , or may be directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. In addition, each source-driver integrated circuit (S-DIC) may be implemented in a chip-on-film (COF) method mounted on a source-circuit film connected to the display panel 110 .

The gate driving circuit 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 is also referred to as a scan driving circuit.

The gate driving circuit 130 may include a shift register, a level shifter, and the like.

The gate driving circuit 130 may be configured for the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method. ) may be connected to a bonding pad of , or may be implemented as a GIP (Gate In Panel) type and disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. . In addition, the gate driving circuit 130 may be implemented in a chip-on-film (COF) method that is implemented as a plurality of gate driver integrated circuits (G-DICs) and is mounted on a gate-circuit film connected to the display panel 110 . .

The gate driving circuit 130 sequentially supplies a scan signal of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller 140 .

When a specific gate line is opened by the gate driving circuit 130 , the data driving circuit 120 converts the image data DATA received from the controller 140 into an analog data voltage to form a plurality of data lines DL. supplied with

The data driving circuit 120 may be located only on one side (eg, upper or lower side) of the display panel 110 , and in some cases, both sides (eg, on both sides of the display panel 110 ) according to a driving method, a panel design method, etc. For example, it can be located on both the upper side and the lower side).

The gate driving circuit 130 may be located only on one side (eg, left or right) of the display panel 110 , and in some cases, both sides (eg, left or right side) of the display panel 110 according to a driving method or a panel design method For example, it can be located on both the left and right side).

The plurality of gate lines GL disposed on the display panel 110 may include a plurality of scan lines SCL and a plurality of light emission control lines EML. The plurality of scan lines SCL and the plurality of emission control lines EML are gate nodes of different types of transistors (scan transistors, emission control transistors) and transmit different types of gate signals (scan signals, emission control signals) to each other. wires that carry them.

The gate driving circuit 130 outputs emission control signals to a scan driving circuit that outputs scan signals to a plurality of scan lines that are one type of the gate line GL and a plurality of emission control lines that are different types of the gate line GL. It may include a light emitting driving circuit that

2 is an equivalent circuit of a sub-pixel SP of the display device 100 according to embodiments of the present specification.

Referring to FIG. 2 , each subpixel SP may include a light emitting device ED, first to sixth transistors T1 to T6 , and a storage capacitor Cst.

Referring to FIG. 2 , each subpixel SP has a first node N1 corresponding to a source node or a drain node of the second transistor T2 and a second node N1 corresponding to the gate node of the second transistor T2 . The node N2, the third node N3 corresponding to the drain node or the source node of the second transistor T2, and the fourth node N4 corresponding to the pixel electrode PE of the light emitting device ED, etc. includes the main nodes of

The light emitting device ED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE. The light emitting layer EL is positioned between the pixel electrode PE and the common electrode CE. The pixel electrode PE and the light emitting layer EL are disposed in each subpixel SP. However, the common electrode CE may be commonly disposed in the plurality of subpixels SP. A ground voltage VSS corresponding to the common voltage may be applied to the common electrode CE.

The second transistor T2 among the first to sixth transistors T1 to T6 is a driving transistor (DRT) for driving the light emitting device ED.

Five transistors connected to the gate nodes of the remaining five transistors T1 , T3 , T4 , T5 , and T6 except for the second transistor T2 which is the driving transistor DRT among the first to sixth transistors T1 to T6 gate lines GL of

The five gate lines GL may include first to third scan lines SCL1 , SCL2 , and SCL3 and first and second emission control lines EML1 and EML2 .

The third transistor T3 is electrically connected between the second node N2 and the third node N3 according to the first scan signal Scan1(n) applied to the gate node through the first scan line SCL1 . to control

The first transistor T1 is a data line that supplies the first node N1 and the data voltage Vdata according to the second scan signal Scan2(n) applied to the gate node through the second scan line SCL2. Controls the electrical connection between (DL).

In the sixth transistor T6 , the fourth node N4 and the initialization voltage Vini are applied according to the third scan signal Scan2(n-1) applied to the gate node through the third scan line SCL3. Controls the electrical connection between the initialization voltage nodes NVINI.

The fourth transistor T4 receives the first node N1 and the driving voltage VDD according to the first emission control signal EM1(n) applied to the gate node through the first emission control line EML1. Controls the electrical connection between the driving voltage nodes NVDD.

The fifth transistor T5 is electrically connected between the third node N3 and the fourth node N4 according to the second emission control signal EM2(n) applied to the gate node through the second emission control line EML2. control the connection.

Referring to FIG. 2 , the storage capacitor Cst includes a first plate PLT1 and a second plate PLT2 . The first plate PLT1 is electrically connected to the gate node of the second transistor T2 serving as the driving transistor DRT, and the second plate PLT2 is electrically connected to the DC voltage node. Here, the DC voltage node may include, for example, a driving voltage node NVDD.

Referring to FIG. 2 , the storage capacitor Cst may be electrically connected between the second node N2 and the driving voltage node NVDD. Here, the second node N2 may correspond to the gate node of the second transistor T2 serving as the driving transistor DRT, and the driving voltage node NVDD may be a DC voltage node.

Referring to FIG. 2 , the second transistor T2 among the first to sixth transistors T1 to T6 may be a P-type transistor. For example, the second transistor T2 among the first to sixth transistors T1 to T6 may be a P-type transistor, and the remaining first and third to sixth transistors T6 may be an N-type transistor. However, the present invention is not limited thereto, and at least one of the first to sixth transistors T1 to T6 may be an N-type transistor, and all other transistors may be a P-type transistor. Alternatively, all of the first to sixth transistors T1 to T6 may be N-type transistors.

As described above, by configuring the second transistor T2 serving as the driving transistor DRT as a P-type transistor, the storage capacitor Cst is connected to the second node N2 that is the gate node of the second transistor T2 and the DC voltage. It may be formed between the driving voltage node NVDD, which is a node.

One of both ends of the storage capacitor Cst is connected to the driving voltage node NVDD, which is a DC voltage node, thereby preventing a voltage change of the second node N2, which is the other one of both ends of the storage capacitor Cst. The second node N2 corresponds to the gate node of the second transistor T2 serving as the driving transistor DRT.

In addition, according to the embodiments of the present specification, the second transistor T2 serving as the driving transistor DRT is composed of a P-type transistor advantageous for operational reliability and current supply performance because operation reliability and current supply performance are most important. do. However, the remaining first, third to sixth transistors T1 , T3 , T4 , T5 , and T6 may be transistors whose switching speed is more important than current supply performance. Accordingly, the first, third to sixth transistors T1 , T3 , T4 , T5 , and T6 may be designed as N-type transistors having a fast switching speed due to high carrier mobility. Accordingly, the driving performance of the sub-pixel SP may be greatly improved.

Meanwhile, the display device 100 according to the embodiments of the present specification may be a self-luminous display such as an organic light emitting diode (OLED) display, a quantum dot display, and a micro light emitting diode (LED) display. have.

When the display device 100 according to the embodiments of the present specification is an OLED display, each subpixel SP may include an organic light emitting diode (OLED) emitting light as a light emitting device ED. When the display device 100 according to the embodiments of the present specification is a quantum dot display, each subpixel SP may include a light emitting device ED made of quantum dots, which are semiconductor crystals that emit light by themselves. can When the display device 100 according to the embodiments of the present specification is a micro LED display, each sub-pixel SP emits light by itself and uses an inorganic-based micro LED (Micro Light Emitting Diode) as a light emitting device (ED). can be included as

3 is a diagram illustrating a cross-sectional structure of a sub-pixel SP of a display device according to an exemplary embodiment of the present specification.

Referring to FIG. 3 , the display device 100 according to the exemplary embodiment of the present specification includes a substrate 10 , a first buffer layer 20 , a first gate insulating layer 30 , a first interlayer insulating layer 40 , The second buffer layer 50 , the second gate insulating layer 60 , the second interlayer insulating layer 70 , the protective layer 80 , the bank layer 90 , the spacer 91 , the light emitting device 500 , the first Thin film transistor 200 , second thin film transistor 300 , auxiliary electrode 610 , first shielding pattern 400 , second shielding pattern 500 , first metal pattern 710 , second metal pattern 720 . ), a third metal pattern 730 , and a fourth metal pattern 740 .

In addition, the first thin film transistor 200 may include a first semiconductor pattern 210 , a first source electrode 220 , a first drain electrode 230 , and a first gate electrode 240 . Also, the second thin film transistor 300 may include a second semiconductor pattern 310 , a second source electrode 320 , a second drain electrode 330 , and a second gate electrode 340 .

Referring to FIG. 3 , the display device according to the embodiment of the present specification may include a substrate 10 . The substrate 10 may include a display area in which the sub-pixel SP is disposed and a non-display area disposed adjacent to the display area. The substrate 10 may include an insulating material. For example, the substrate 10 may include glass or plastic. In FIG. 3 , the substrate 10 is represented as a single-layer structure, but is not limited thereto. For example, the substrate 10 may have a multi-layer structure. The substrate 10 may have a structure in which an inorganic insulating layer is positioned between the first substrate layer and the second substrate layer. The second substrate layer may include the same material as the first substrate layer. For example, the first substrate layer and the second substrate layer may include plastic. The inorganic insulating layer may include an insulating material. For example, the first substrate layer and the second substrate layer may be made of polyimide (PI). In addition, the inorganic insulating layer may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. For example, the inorganic insulating layer may be formed of a silicon dioxide (Silica or Silicon Dioxide: SiO _{2 ) material.}

In this way, by forming an inorganic insulating layer between the first and second substrate layers made of polyimide (PI), the charge charged to the first substrate layer disposed below is blocked to improve product reliability. can be improved In addition, by forming the inorganic insulating layer between the two polyimides (PI), it is possible to prevent the moisture component from penetrating the thin film transistor through the lower first substrate layer, thereby improving the reliability of the display device.

The substrate 10 may include a sub-pixel SP defined by gate lines GL and data lines DL. A first thin film transistor 200 , a second thin film transistor 300 , and a light emitting device 500 may be positioned in each sub-pixel SP. Each light emitting device 500 may be electrically connected to the first thin film transistor 200 to emit light having a specific color. As another example, each light emitting device 500 may be electrically connected to the second thin film transistor 300 to emit light having a specific color.

Referring to FIG. 3 , a first buffer layer 20 may be formed on the substrate 10 . The first buffer layer 20 may prevent contamination by the substrate 10 in the process of forming the pixel circuit. For example, the first buffer layer 20 may be formed between the substrate 10 and the first semiconductor pattern 210 of each sub-pixel SP. The first buffer layer 20 may include an insulating material. For example, the first buffer layer 20 may include a silicon oxide-based (SiOx) material layer and a silicon nitride-based (SiNx) material layer. The first buffer layer 20 may have a multi-layer structure. For example, the first buffer layer 20 may include a first lower buffer layer 21 and a first buffer upper layer 22 .

The first buffer lower layer 21 may be disposed on the substrate 10 , and the first buffer upper layer 22 may be disposed on the first buffer lower layer 21 . The first buffer lower layer 21 may be formed as a multilayer including a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx). For example, the first buffer lower layer 21 may be formed as a multilayer structure in which a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer are alternately formed.

In addition, the first buffer upper layer 22 may be formed as a single layer made of a silicon oxide (SiOx)-based material. For example, the first buffer upper layer 22 may be formed of a single layer made of a silicon dioxide (SiO2) material.

Referring to FIG. 3 , a first shielding pattern 400 , a first metal pattern 710 , and a second metal pattern 720 are additionally disposed between the first buffer upper layer 22 and the first buffer lower layer 21 . can be The first shielding pattern 400 , the first metal pattern 710 , and the second metal pattern 720 may be a metal material layer.

The first shielding pattern 400 blocks charges charged on the substrate 10 from forming a back bias and affecting the first channel region 210C of the first semiconductor pattern 210 . can In addition, the first shielding pattern 400 may prevent external light from penetrating the first channel region 210C of the first semiconductor pattern 210 through the substrate 10 to improve the reliability of the display device. .

The first metal pattern 710 may be disposed to be spaced apart from one side of the first shielding pattern 400 . In addition, the second metal pattern 720 may be disposed to be spaced apart from the other side surface of the first shielding pattern 400 .

The first shielding pattern 400, the first metal pattern 710, and the second metal pattern 720 are aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), It may include a metal such as tungsten (W) or an alloy thereof. In addition, the first shielding pattern 400 , the first metal pattern 710 , and the second metal pattern 720 may be formed of a single layer made of a metal or an alloy material or a multilayer thereof. The first metal pattern 710 and the second metal pattern 720 have a first contact hole CH1 for connecting the first source electrode 220 and the first drain electrode 230 to the first semiconductor pattern 210 . And when the second contact hole CH2 is formed, it may serve to prevent the first buffer lower layer 21 from being etched due to over-etching. The first metal pattern 710 and the second metal pattern 720 are spaced apart from the first shielding pattern 400 and may be formed in an island shape. Accordingly, the first metal pattern 710 and the second metal pattern 720 may be insulated from the first shielding pattern 400 .

The first semiconductor pattern 210 may be positioned on the first buffer upper layer 22 of the first buffer layer 20 . The first semiconductor pattern 210 may include a semiconductor material. For example, the first semiconductor pattern 210 may include poly-silicon (Poly-Si), which is a polycrystalline semiconductor material. For example, the first semiconductor pattern 210 may include low temperature poly-silicon (LTPS).

The first semiconductor pattern 210 may overlap the first shielding pattern 400 with the first buffer upper layer 22 interposed therebetween. In addition, the first semiconductor pattern 210 may include a first channel region 210C, a first source region 210S, and a first drain region 210D. The first channel region 210C of the first semiconductor pattern 210 may overlap the first shielding pattern 400 with the first buffer upper layer 22 interposed therebetween. In addition, the first metal pattern 710 may overlap the first source region 210S of the first semiconductor pattern 210 with the first buffer upper layer 22 interposed therebetween. Also, the second metal pattern 720 may overlap the first drain region 210D of the first semiconductor pattern 210 with the first buffer upper layer 22 interposed therebetween. A first gate insulating layer 30 may be formed on the first semiconductor pattern 210 . The first gate insulating layer 30 may include an insulating material. For example, the first gate insulating layer 30 may include a silicon oxide-based (SiOx) material. _{For example, silicon dioxide (SiO 2} ) may be included in the silicon oxide-based (SiOx) material. However, the present invention is not limited thereto, and the first gate insulating layer 30 may include a silicon nitride-based (SiNx) material. Alternatively, the first gate insulating layer 30 may be formed of a multilayer including a silicon nitride (SiNx)-based material layer and a silicon oxide-based material layer (SiOx).

The first gate electrode 240 and the second shielding pattern 500 of the first thin film transistor 200 may be formed on the first gate insulating layer 30 . The first gate electrode 240 may overlap the first semiconductor pattern 210 with the first gate insulating layer 30 interposed therebetween. For example, the first gate electrode 240 may overlap the first channel region 210C of the first semiconductor pattern 210 with the first gate insulating layer 30 interposed therebetween. The first gate electrode 240 and the second shielding pattern 500 may include a conductive material. For example, the first gate electrode 240 and the second shielding pattern 500 may include aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W) and The same metal or alloys thereof may be included. Also, the first gate electrode 240 and the second shielding pattern 500 may be formed of a single layer made of a metal or an alloy material or a multilayer thereof. For example, when formed as a multi-layer, the first gate electrode 240 may be formed as a multi-layer including a molybdenum (Mo) metal layer and a titanium (Ti) metal layer. When the second gate electrode 340 is a multilayer including a molybdenum (Mo) metal layer and a titanium (Ti) metal layer, the width of the titanium (Ti) metal layer may be greater than the width of the molybdenum (Mo) metal layer based on the cross-sectional view. .

In addition, the first gate electrode 240 and the second shielding pattern 500 may be made of the same material and disposed on the same layer. Accordingly, the first gate electrode 240 and the second shielding pattern 500 may have the same stacked structure.

A first interlayer insulating layer 40 may be formed on the first gate electrode 240 , the second shielding pattern 500 , and the first gate insulating layer 30 . The first interlayer insulating layer 40 may include an insulating material. In FIG. 3 , the first interlayer insulating layer 40 is represented as a single layer structure, but is not limited thereto. For example, the first interlayer insulating layer 40 may include a first interlayer insulating lower layer and a first interlayer insulating upper layer. The first interlayer insulating lower layer may include the same insulating material as the first gate insulating layer 30 . In addition, the first interlayer insulating upper layer may include an insulating material different from that of the first interlayer insulating lower layer. For example, when the first gate insulating layer 30 includes a silicon oxide-based material (SiOx), the first interlayer insulating lower layer may include a silicon oxide-based material (SiOx). In addition, the first interlayer insulating upper layer may include a silicon nitride-based (SiNx) material.

A third metal pattern 730 and a fourth metal pattern 740 may be formed on the first interlayer insulating layer 40 . The third metal pattern 730 and the fourth metal pattern 740 are disposed to be spaced apart from each other, and may be formed in an island shape. The third metal pattern 730 and the fourth metal pattern 740 have a third contact hole CH1 for connecting the second source electrode 320 and the second drain electrode 330 to the second semiconductor pattern 310 . And when the fourth contact hole CH2 is formed, it is possible to prevent the first interlayer insulating layer 40 from being etched due to over-etching.

The third metal pattern 730 and the fourth metal pattern 740 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W) or these may contain an alloy of In addition, the third metal pattern 730 and the fourth metal pattern 740 may be formed of a single layer made of a metal or an alloy material or a multilayer thereof.

A second buffer layer 50 may be formed on the first interlayer insulating layer 40 , the third metal pattern 730 , and the fourth metal pattern 740 . The second buffer layer 50 may include a silicon nitride (SiNx)-based material layer or a silicon oxide-based (SiOx) material layer. In FIG. 3 , the second buffer layer 50 is illustrated as a single layer structure, but is not limited thereto. For example, the second buffer layer 50 may be formed as a multilayer including a silicon nitride (SiNx)-based material layer and a silicon oxide-based (SiOx) material layer. The second buffer layer 50 may be formed as a multi-layer in which silicon oxide (SiOx) and silicon nitride (SiNx) are alternately formed. For example, the second buffer layer 50 may include a first buffer lower layer and a second buffer upper layer. The first buffer lower layer may include silicon nitride (SiNx). In addition, the first buffer upper layer may include silicon oxide (SiOx).

Referring to FIG. 3 , the second semiconductor pattern 310 of the second thin film transistor 300 may be formed on the second buffer layer 50 . The second semiconductor pattern 310 of the second thin film transistor 300 may include a material different from that of the first semiconductor pattern 210 of the first thin film transistor 200 . The second semiconductor pattern 310 may include an oxide semiconductor. For example, the second semiconductor pattern 310 may include IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, ITZO (InSnZnO)-based IGTO (InGaSnO)-based )-based, GO (GaO)-based, GZTO (GaZnSnO)-based, and GZO (GaZnO)-based oxide semiconductor materials may be included. However, the embodiment of the present specification is not limited thereto, and the second semiconductor pattern 310 may be made of another oxide semiconductor material.

The second semiconductor pattern 310 includes a second channel region 310C overlapping the second gate electrode 340 , a second source region 310S connected to the second source electrode 320 , and a second drain electrode ( A second drain region 310D connected to the 330 may be included.

The second channel region 310C of the second semiconductor pattern 310 may overlap the second shielding pattern 500 with the second interlayer insulating layer 40 and the second buffer layer 50 interposed therebetween. In addition, the second source region 310S of the second semiconductor pattern 310 may overlap the third metal pattern 730 with the second buffer layer 50 interposed therebetween. Also, the second drain region 310D of the second semiconductor pattern 310 may overlap the fourth metal pattern 740 with the second buffer layer 50 interposed therebetween.

A second gate insulating layer 60 may be formed on the second semiconductor pattern 310 and the second buffer layer 50 . The second gate insulating layer 60 may overlap the first gate electrode 240 . However, the present invention is not limited thereto, and the second gate insulating layer 60 may be disposed to overlap only the second semiconductor pattern 310 . For example, the second gate insulating layer 60 may be disposed to overlap only the second channel region 310C of the second semiconductor pattern 310 . The second gate insulating layer 60 may include at least one of a silicon oxide-based (SiOx) material and a silicon nitride-based (SiNx) material. The second gate insulating layer 60 may have a single-layer or multi-layer structure.

The second gate electrode 340 of the second thin film transistor 300 may be formed on the second gate insulating layer 60 . The second gate electrode 340 may overlap the second semiconductor pattern 310 with the second gate insulating layer 60 interposed therebetween. The second gate electrode 340 may include a conductive material. For example, the second gate electrode 340 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W) or an alloy thereof. can do. In addition, the second gate electrode 340 may be formed as a single layer or a multilayer. For example, when formed as a multi-layer, the second gate electrode 340 may be formed as a multi-layer including a molybdenum (Mo) metal layer and a titanium (Ti) metal layer. When the second gate electrode 340 is a multilayer including a molybdenum (Mo) metal layer and a titanium (Ti) metal layer, the width of the titanium (Ti) metal layer may be greater than the width of the molybdenum (Mo) metal layer based on the cross-sectional view. .

A second interlayer insulating layer 70 may be formed on the second gate electrode 340 . The second interlayer insulating layer 70 may include at least one of a silicon oxide-based (SiOx) material and a silicon nitride-based (SiNx) material. The second interlayer insulating layer 70 may have a single-layer or multi-layer structure.

Referring to FIG. 3 , the second interlayer insulating layer 70 , the second gate insulating layer 60 , the second buffer layer 50 , the first interlayer insulating layer 40 , the first gate insulating layer 30 , and the first The first contact hole CH1 exposing the first metal pattern 710 by etching the first semiconductor pattern 210 and the first buffer upper layer 22 and the second contact hole exposing the second metal pattern 720 . (CH2) can be formed. For example, the second interlayer insulating layer 70 , the second gate insulating layer 60 , the second buffer layer 50 , the first interlayer insulating layer 40 , the first gate insulating layer 30 , and the first semiconductor A first contact hole CH1 may be formed through the first source region 210S of the pattern 210 and the first buffer upper layer 22 to expose the first metal pattern 710 . In addition, the second interlayer insulating layer 70 , the second gate insulating layer 60 , the second buffer layer 50 , the first interlayer insulating layer 40 , the first gate insulating layer 30 , and the first semiconductor pattern ( A second contact hole CH2 may be formed through the first drain region 210D of the 210 and the first buffer upper layer 22 to expose the second metal pattern 720 . As another example, when the second gate insulating layer 60 is disposed only on the second semiconductor pattern 310 , the second interlayer insulating layer 70 , the second buffer layer 50 , the first interlayer insulating layer 40 , The first contact hole CH1 and the second metal pattern penetrating through the first gate insulating layer 30 , the first semiconductor pattern 210 , and the first buffer upper layer 22 to expose the first metal pattern 710 . A second contact hole CH2 exposing 720 may be formed.

The first metal pattern 710 and the second metal pattern 720 are etched up to the first buffer lower layer 21 during the dry etching process for forming the first contact hole CH1 and the second contact hole CH2 . can prevent this from happening. Since the first metal pattern 710 and the second metal pattern 720 include a metal material, an etch rate is relatively low in the dry etching process. Accordingly, during the dry etching process for forming the first contact hole CH1 and the second contact hole CH2 , it may serve as a barrier layer that prevents the first buffer lower layer 21 from being etched.

The inner surface of the first semiconductor pattern 210 may also be exposed through the first contact hole CH1 and the second contact hole CH2 . For example, an inner sidewall of the first source region 210S may be exposed through the first contact hole CH1 . In addition, an inner sidewall of the first drain region 210D may be exposed through the second contact hole CH2 .

Then, the third metal pattern 730 is exposed by etching the second interlayer insulating layer 70 , the second gate insulating layer 60 , the second semiconductor pattern 310 , and the second buffer layer 50 . A fourth contact hole CH4 exposing the contact hole CH3 and the fourth metal pattern 740 may be formed. For example, the third layer passes through the second interlayer insulating layer 70 , the second gate insulating layer 60 , the second source region 310S of the second semiconductor pattern 310 , and the second buffer layer 50 . A third contact hole CH3 exposing the metal pattern 730 may be formed. The fourth metal pattern penetrates through the second interlayer insulating layer 70 , the second gate insulating layer 60 , the second drain region 310D of the second semiconductor pattern 310 , and the second buffer layer 50 . A fourth contact hole CH4 exposing the 740 may be formed. As another example, when the second gate insulating layer 60 is disposed to overlap only the second channel region 310C of the second semiconductor pattern 310 , the second interlayer insulating layer 70 and the second semiconductor pattern 310 . , and a third contact hole CH3 exposing the second source region 310S and a fourth contact hole CH4 exposing the second drain region 310D through the second buffer layer 50 may be formed. have.

The third metal pattern 730 and the fourth metal pattern 740 are formed up to the first interlayer insulating layer 40 during the dry etching process for forming the third contact hole CH3 and the fourth contact hole CH4 . Etching can be prevented. Since the third metal pattern 730 and the fourth metal pattern 740 include a metal material, an etch rate is relatively low in the dry etching process. Accordingly, during the dry etching process for forming the third contact hole CH3 and the fourth contact hole CH4 , it may serve as a barrier layer that prevents the first interlayer insulating layer 40 from being etched.

An inner surface of the second semiconductor pattern 310 may also be exposed through the third contact hole CH3 and the fourth contact hole CH4 . For example, an inner sidewall of the second source region 310S may be exposed through the third contact hole CH3 . In addition, an inner sidewall of the second drain region 310D may be exposed through the fourth contact hole CH4 .

A second source electrode 320 , a second drain electrode 330 , a first drain electrode 230 , and a first source electrode 220 may be formed on the second interlayer insulating layer 70 .

Referring to FIG. 3 , the first source electrode 220 and the first drain electrode 230 of the first thin film transistor 200 are exposed through the first contact hole CH1 and the second contact hole CH2 . 1 may be respectively connected to the inner surface of the semiconductor pattern 210 . For example, the first source electrode 220 may contact and be connected to an inner sidewall of the first source region 210S of the first semiconductor pattern 210 exposed through the first contact hole CH1 . In addition, the first drain electrode 230 may contact and be connected to an inner sidewall of the first drain region 210D_ of the first semiconductor pattern 210 exposed through the second contact hole CH2 .

In addition, the first source electrode 220 may contact the first metal pattern CH1 exposed through the first contact hole CH1 . Also, the first drain electrode 230 may contact the second metal pattern CH2 exposed through the second contact hole CH2 .

The second source electrode 320 and the second drain electrode 330 of the second thin film transistor 300 have a second semiconductor pattern 310 exposed through the third contact hole CH3 and the fourth contact hole CH4. may be connected to the inner surface of each. For example, the second source electrode 320 may contact and be connected to an inner sidewall of the second source region 310S of the second semiconductor pattern 310 exposed through the third contact hole CH3 . In addition, the second drain electrode 330 may be connected to and in contact with the inner sidewall of the second drain region 310D of the second semiconductor pattern 310 exposed through the fourth contact hole.

In addition, the second source electrode 320 may contact the third metal pattern 730 exposed through the third contact hole CH3 . Also, the second drain electrode 330 may contact the fourth metal pattern 740 exposed through the fourth contact hole CH4 .

In this specification, the inner surface may be an inner surface of a hole formed in the first semiconductor pattern 210 and the second semiconductor pattern 310 by the contact holes CH1 , CHJ2 , CH3 , and CH4 .

The second source electrode 320 , the second drain electrode 330 , the first source electrode 220 , and the first drain electrode 230 may be formed of the same material and disposed on the same layer. Accordingly, the second source electrode 320 , the second drain electrode 330 , the first source electrode 220 , and the first drain electrode 230 may have the same stacked structure. And, they are molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), any one of neodymium (Nd) or alloys thereof It may be formed as a single layer or multiple layers. For example, when the second source electrode 320 , the second drain electrode 330 , the first source electrode 220 , and the first drain electrode 230 are formed in a multilayer structure, the second source electrode 320 , the second drain electrode 330 , the first source electrode 220 , and the first drain electrode 230 may be formed as a triple layer. When they are formed as a triple layer, the lower layer and the upper layer may be formed of an aluminum (Al) metal layer. In addition, the intermediate layer positioned between the lower layer and the upper layer may be formed of a titanium (Ti) metal layer.

A protective layer 80 may be formed on the second source electrode 320 , the second drain electrode 330 , the first source electrode 220 , and the first drain electrode 230 .

3 , the passivation layer 80 may include a first passivation layer 81 and a second passivation layer 80 disposed on the first passivation layer 81 . A contact hole for exposing the first drain electrode 230 of the first thin film transistor 200 may be formed in the first passivation layer 81 . However, the present invention is not limited thereto, and a contact hole for exposing the second drain electrode 330 or the second source electrode 320 of the second thin film transistor 300 may be formed in the first passivation layer 81 . .

The first passivation layer 81 may be a single layer or multiple layers made of at least one of an inorganic material and an organic material. When the first passivation layer 81 includes an inorganic material, it may be a silicon oxide (SiOx)-based material or a silicon nitride (SiNx)-based material. And, when the first protective layer 81 includes an organic material, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin ( It may be an organic material such as polyimide resin).

The second protective layer 82 disposed on the first protective layer 81 may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide. It may be an organic material such as polyimide resin.

The first electrode 510 of the light emitting device 500 may be formed on the second passivation layer 82 of the passivation layer 80 . The first electrode 510 may be connected to the auxiliary electrode 610 through a contact hole of the second protective layer 82 . Accordingly, the first electrode 510 may be electrically connected to the first drain electrode 230 of the first thin film transistor 200 through the auxiliary electrode 610 . However, the present invention is not limited thereto. For example, when the auxiliary electrode 610 is connected to the second thin film transistor 300 , the first electrode 510 may be electrically connected to the second thin film transistor 300 through the auxiliary electrode 610 .

Accordingly, the light emitting device 500 of each sub-pixel SP may be electrically connected to the first thin film transistor 300 of the corresponding sub-pixel SP. For example, the first electrode 510 of each sub-pixel SP passes through the second passivation layer 82 and is connected to the auxiliary electrode 610 , and the auxiliary electrode 610 is connected to the first passivation layer 81 . may be connected to the first drain electrode 230 of the first thin film transistor 200 through the Accordingly, the first electrode 510 of each sub-pixel SP may be electrically connected to the first thin film transistor 200 . However, the present invention is not limited thereto, and the first electrode 510 of the light emitting device 500 may be electrically connected to the second thin film transistor 300 .

The first electrode 510 may be formed in a multilayer structure including a transparent conductive layer and an opaque conductive layer having high reflective efficiency. The transparent conductive layer may be made of a material having a relatively large work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). In addition, the opaque conductive film has a single-layer or multi-layer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. can be done For example, in the first electrode 510 , a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer may be sequentially formed. However, the present invention is not limited thereto, and for example, a transparent conductive layer and an opaque conductive layer may be sequentially formed.

Since the display device according to the embodiment of the present specification is a top emission display device, the first electrode 510 may be an anode electrode. When the display device is bottom emission, the first electrode 510 disposed on the protective layer 80 may be a cathode electrode.

The light emitting device 500 of each sub-pixel SP may be driven independently. For example, the first electrode 510 of each sub-pixel SP may be insulated from the first electrode 510 of the adjacent sub-pixel SP. An edge of each first electrode 510 may be covered by the bank layer 90 . The bank layer 90 may be positioned on the passivation layer 80 . The emission layer 520 and the second electrode 530 of each sub-pixel SP may be stacked on the corresponding first electrode 510 exposed by the bank layer 90 . The bank layer 90 may include an insulating material. For example, the bank layer 90 may include an organic insulating material. The bank layer 90 may include the same material as the passivation layer 80 or a different material. Since the bank layer 90 can define a light emitting region of the display device, it can also be referred to as a pixel defining layer, and is not limited thereto. A spacer 91 may be further disposed on the bank layer 90 . In addition, the spacer 91 may be formed of the same material as the bank layer 90 .

In addition, the light emitting layer 520 of the light emitting device 500 may be further disposed on the first electrode 510 . The emission layer 520 may be formed on the first electrode 510 in the order of the hole layer HL, the emission material layer EML, and the electron layer EL or in the reverse order.

At least a portion of the emission layer 520 of each sub-pixel SP may extend onto the bank layer 90 . For example, the hole layer HL and the electron layer EL of each sub-pixel SP may be connected to the hole layer HL and the electron layer EL of the adjacent sub-pixel SP. The light-emitting material layer EML of each sub-pixel SP may be spaced apart from the light-emitting material layer EML of the adjacent sub-pixel SP. The second electrode 530 of each sub-pixel SP may extend on the bank layer 90 . For example, the second electrode 530 of each sub-pixel SP may be connected to the second electrode 530 of an adjacent sub-pixel SP.

An encapsulation member for suppressing penetration of moisture may be further disposed on the second electrode 530 . The encapsulation member may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The second encapsulation layer may include a material different from that of the first encapsulation layer and the third encapsulation layer. For example, the first encapsulation layer and the third encapsulation layer may be an inorganic insulating film formed of an inorganic insulating material, and the second encapsulation layer may be an organic insulating film formed of an organic insulating material. The first encapsulation layer of the encapsulation member may be disposed on the second electrode 530 . In addition, the second encapsulation layer may be disposed on the first encapsulation layer. Also, the third encapsulation layer may be disposed on the second encapsulation layer.

The first encapsulation layer and the third encapsulation layer of the encapsulation member may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second encapsulation layer of the encapsulation member is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. can be formed.

A display device according to an embodiment of the present specification may be described as follows.

The display device according to the exemplary embodiment of the present specification includes a first buffer layer including a first buffer lower layer on a substrate and a first buffer upper layer on the first buffer lower layer, and a first shielding pattern between the first buffer lower layer and the first buffer upper layer. , a metal pattern disposed spaced apart from the first shielding pattern and disposed between the first buffer lower layer and the first buffer upper layer, a first semiconductor pattern disposed on the first buffer upper layer and including poly-silicon, and a first gate insulating layer; A first thin film transistor including a first gate electrode overlapping a first semiconductor pattern with interposed therebetween, and a first source electrode and a first drain electrode connected to the first semiconductor pattern, a first interlayer on the first gate electrode an insulating layer, a second buffer layer on the first interlayer insulating layer, and a second semiconductor pattern disposed on the second buffer layer and including an oxide semiconductor, a second semiconductor pattern overlapping the second semiconductor pattern with the second gate insulating layer interposed therebetween The second thin film transistor may include a second gate electrode and a second source electrode and a second drain electrode connected to the second semiconducting pattern.

According to the embodiment of the present specification, the first semiconductor pattern includes a first channel region overlapping the first gate electrode, a first source region connected to the first source electrode, and a second drain region connected to the first drain electrode. may include. In addition, the first shielding pattern may overlap the first channel region.

According to an embodiment of the present specification, the metal pattern may include a first metal pattern disposed to be spaced apart from one side surface of the first shielding pattern, and a second metal pattern disposed to be spaced apart from the other side surface of the first shielding pattern. .

According to the embodiment of the present specification, the first metal pattern may overlap the first source region, and the second metal pattern may overlap the first drain region.

According to the embodiment of the present specification, a first contact hole penetrating through the first source region and the first gate insulating layer of the first semiconductor pattern to expose the first metal pattern, and the first drain region and the first drain region of the first semiconductor pattern A second contact hole penetrating through the first gate insulating layer and exposing the second metal pattern may be further included.

According to the embodiment of the present specification, the first source electrode may contact the first metal pattern exposed through the first contact hole, and the first drain electrode may contact the second metal pattern exposed through the second contact hole. have.

According to the embodiment of the present specification, the metal pattern includes a third metal pattern overlapping the second source region of the second semiconductor pattern with the second buffer layer interposed therebetween, and a second pattern of the second semiconductor pattern with the second buffer layer interposed therebetween A fourth metal pattern overlapping the drain region may be included.

According to the embodiment of the present specification, the third metal pattern and the fourth metal pattern may be disposed between the first interlayer insulating layer and the second buffer layer.

According to the embodiment of the present specification, a third contact hole penetrating through the second source region and the second buffer layer of the second semiconductor pattern to expose the third metal pattern, and the second drain region and the second buffer layer of the second semiconductor pattern It may include a fourth contact hole penetrating through and exposing the fourth metal pattern.

According to the embodiment of the present specification, the second source electrode may contact the third metal pattern exposed through the third contact hole, and the second drain electrode may contact the fourth metal pattern exposed through the fourth contact hole. have.

100: display device
10: substrate
20: first buffer layer
30: first gate insulating layer
40: first interlayer insulating layer
50: second buffer layer
60: second gate insulating layer
70: second interlayer insulating layer
80: protective layer
90: bank layer
91: spacer
500: light emitting device
610: auxiliary electrode
710: first metal pattern
720: second metal pattern
730: third metal pattern
740: fourth metal pattern
200: first thin film transistor
300: second thin film transistor
400: first shielding pattern
500: second shielding pattern
CH1: first contact hole
CH2: second contact hole
CH3: third contact hole
CH4: fourth contact hole

Claims (10)

a first buffer layer including a first buffer lower layer on a substrate and a first buffer upper layer on the first buffer lower layer;
a first shielding pattern interposed between the first lower buffer layer and the first buffer upper layer;
a metal pattern spaced apart from the first shielding pattern and interposed between the first buffer lower layer and the first buffer upper layer;
A first semiconductor pattern disposed on the first buffer upper layer and including poly-silicon, a first gate electrode overlapping the first semiconductor pattern with a first gate insulating layer interposed therebetween, and connected to the first semiconductor pattern a first thin film transistor including a first source electrode and a first drain electrode;
a first interlayer insulating layer on the first gate electrode;
a second buffer layer on the first interlayer insulating layer; and
a second semiconductor pattern disposed on the second buffer layer and including an oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern with a second gate insulating layer interposed therebetween, and connected to the second semiconducting pattern A display device comprising: a second thin film transistor including a second source electrode and a second drain electrode.
According to claim 1,
The first semiconductor pattern includes a first channel region overlapping the first gate electrode, a first source region connected to the first source electrode, and a second drain region connected to the first drain electrode,
and the first shielding pattern overlaps the first channel region. 3. The method of claim 2,
The metal pattern includes a first metal pattern spaced apart from one side surface of the first shielding pattern, and a second metal pattern spaced apart from the other side surface of the first shielding pattern.
4. The method of claim 3,
the first metal pattern overlaps the first source region;
and the second metal pattern overlaps the first drain region.
5. The method of claim 4,
a first contact hole penetrating through the first source region and the first gate insulating layer of the first semiconductor pattern to expose the first metal pattern; and
and a second contact hole penetrating through the first drain region of the first semiconductor pattern and the first gate insulating layer to expose the second metal pattern.
6. The method of claim 5,
The first source electrode is in contact with the first metal pattern exposed through the first contact hole,
and the first drain electrode contacts the second metal pattern exposed through the second contact hole.
6. The method of claim 5,
The metal pattern includes a third metal pattern overlapping the second source region of the second semiconductor pattern with the second buffer layer interposed therebetween, and the second drain of the second semiconductor pattern with the second buffer layer interposed therebetween. A display device comprising a fourth metal pattern overlapping the region.
8. The method of claim 7,
The third metal pattern and the fourth metal pattern are disposed between the first interlayer insulating layer and the second buffer layer.
9. The method of claim 8,
a third contact hole penetrating through the second source region and the second buffer layer of the second semiconductor pattern to expose the third metal pattern; and
and a fourth contact hole penetrating through the second drain region of the second semiconductor pattern and the second buffer layer to expose the fourth metal pattern.
10. The method of claim 9,
The second source electrode is in contact with the third metal pattern exposed through the third contact hole,
and the second drain electrode contacts the fourth metal pattern exposed through the fourth contact hole.

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