KR20230005798A - Display Apparatus - Google Patents

Abstract

The present invention provides a display device which can alleviate brightness non-uniformity by compensating for an R-C load in an area having a free-form portion. The display device of the present invention comprises: a display panel including an active area containing a first area with a free-form portion and a second area without the free-form portion, and a bezel area at an external side of the active area; gate lines and data lines disposed to intersect with each other in the active area; pixels connected to the gate lines and the data lines in the active area; a first power supply electrode supplying a first potential to the pixels; a dummy gate line disposed in the bezel area adjacent to the first area and connected to the gate line disposed on the first area to form the first power supply electrode and a first capacitance; and at least one compensation unit compensating for a load caused by a difference in the number of pixels per line in the first area and the second area.

Description

Display Apparatus

This specification relates to a display device.

As the information society develops, demands for display devices for displaying images are increasing in various forms. For example, flat panel display devices (FPDs), which are thin, light, and capable of large areas, have been rapidly developed to replace bulky cathode ray tubes (CRTs). As such a flat panel display device, a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescent display (EL), a field emission display (FED) Various flat panel display devices such as , and electrophoretic displays (EDs) have been developed and used.

These display devices include a display panel including display elements for displaying information, a driver for driving the display panel, and a power supply unit for generating power to be supplied to the display panel and the driver.

These display devices can be designed to have various designs depending on the use environment or purpose. Correspondingly, the display panel displaying the image also has a non-shaped part such as a partial curved surface or a notch from the traditional single rectangular shape. ), as well as various shapes such as round and oval.

As described above, a display device having a deformed portion or a display panel implemented in a circular shape, an oval shape, or the like has an advantage in being able to appeal to consumers who value design aspects in that it can increase the degree of freedom in product design.

However, since the number of pixels disposed on the curved or notched portion of the display panel and the other portion of the display panel is different for each line (for example, horizontal line), a difference in resistor-capacitor load (RC-C load) is generated. As a result, there is a problem in that the luminance of the display panel is non-uniform and the display quality is deteriorated.

The present specification provides a display device capable of improving luminance non-uniformity of a display panel by compensating the RC load of the irregular portion to correspond to the RC load according to the difference in the number of pixels between an area including the irregular portion and an area not including the irregular portion of the display panel. is to provide

A display device according to a first aspect of the present specification includes: a display panel including an active area including a first area having a release portion and a second area without the release portion, and a bezel area outside the active area; gate lines and data lines disposed to cross each other in the active area; pixels connected to the gate lines and the data lines in the active area; a first power supply electrode supplying power to the pixels; and a dummy gate line disposed in the bezel area adjacent to the first area of the active area, wherein the dummy gate line is connected to a gate line disposed in the first area and overlaps with the first power supply electrode. Thus, the first capacitance may be formed.

A display device according to a second aspect of the present specification includes an active area including a first area having a release portion and a second area not having a release portion, a third area corresponding to the first area, and a second area corresponding to the second area. a display panel including a bezel area disposed outside the active area; first pixels formed to correspond to the first gate line disposed in the first region; second pixels formed corresponding to the second gate line disposed in the second region, the number of which is greater than the number of pixels of the first pixels; and a power supply electrode disposed in the bezel area of the display panel and supplying power to the first pixels and the second pixels, wherein the third area of the bezel area includes a first area of the first area. It may include at least one compensation unit that is connected to one gate line or the power supply electrode to form a compensation capacitance to compensate for a load generated according to a difference in the number of pixels between the first pixels and the second pixels. .

* According to the display device of the present specification, since it is possible to increase the R-C load for each gate line by disposing at least one compensation unit in the bezel area of the display panel having the release unit, the R-C load for each gate line of the non-release unit can be compensated to be close to that of the Therefore, an effect of improving luminance non-uniformity of the display panel can be obtained.

1 is a block diagram showing a display device according to an embodiment of the present specification;
2 is a plan view schematically illustrating the shape of the display panel shown in FIG. 1;
3 is a plan view schematically illustrating a partial region R1 of the display panel shown in FIG. 2;
4 is a cross-sectional view showing structures of a thin film transistor, a storage capacitor, and a light emitting diode in the pixel P shown in FIG. 1;
5 is an enlarged plan view of a partial area of the first compensating unit of FIG. 3;
6 is a cross-sectional view taken along line A-A' and line B-B' of FIG. 4;
7 is an enlarged plan view of a partial area of the first compensating unit of FIG. 3;
8 is a cross-sectional view taken along line A-A' and line B-B' of FIG. 7;
9 is a graph showing a comparison between luminance before compensation and luminance of a display device after compensation by a compensator according to an embodiment of the present invention;

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of this specification complete, and common knowledge in the art to which this specification belongs. It is provided to fully inform the person who has the scope of the specification, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to those shown in this specification. Like reference numbers designate like elements throughout the specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', '~ below', 'next to', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

Although first, second, etc. may be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or together in a related relationship. may be

Hereinafter, a display device according to embodiments of the present specification will be described with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted or briefly described.

Hereinafter, a display device according to an exemplary embodiment of the present specification will be described with reference to FIGS. 1 to 3 .

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present specification, and FIG. 2 is a plan view schematically illustrating a shape of a display panel illustrated in FIG. 1 . FIG. 3 is a plan view schematically illustrating a partial region R1 of the display panel shown in FIG. 2 .

Referring to FIG. 1 , a display device according to an embodiment of the present specification includes a display panel 10, a data driver, a GIP (Gate In Panel) type gate driver, a power supply (PS), a timing controller (TC), and the like. can do.

The display panel 10 includes an active area AA that displays information and a bezel area BA that does not display information.

The active area AA is an area where an input image is displayed and a pixel array in which a plurality of pixels P are arranged in a matrix type is disposed.

The bezel area (BA) is the shift register (SRa, SRb) of the gate driving circuit and various link signal wires (GL1 to GLn, DL1 to DLm, ) and link power supply lines (VDL1, VDL2, VSL1, VSL2) and power This is an area where the supply electrodes VDLa and VDLb are disposed. The pixel array disposed in the active area AA includes a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn disposed to cross each other, and pixels disposed in a matrix form at each crossing area ( P) are included.

Each pixel P includes a light emitting diode (LED), a driving thin film transistor (hereinafter referred to as a TFT) (DT) controlling the amount of current flowing through the light emitting diode (LED), and a gate-source of the driving TFT (DT). A programming unit (SC) for setting the voltage between the terminals is included. The pixels P of the pixel array receive the first power source Vdd, which is a high potential voltage, from the power supply unit PS through the first power lines VD1 to VDm, and the second power lines VSLa to VSLb. The second power supply (Vss), which is a low potential voltage, is supplied through.

The first power lines VD1 to VDm include a lower first power supply electrode VDLa disposed in the bezel area BA on the side where the chip-on film 30 is attached and an upper first power supply electrode VDLa disposed in the opposite bezel area. The first power source Vdd is supplied from the power supply unit PS at both sides through the power supply electrode VDLb. Both ends of the lower first power supply electrode VDLa and the upper first power supply electrode VDLb may be connected to each other by link wires VDL1 and VDL2. However, it is not limited thereto, and in some cases may be replaced by first power lines VD1 to VDm without forming link wires VDL1 and VDL2 connecting both ends to each other. Accordingly, an effect of minimizing degradation of display quality due to an increase in RC according to positions of pixels arranged in the active area AA can be obtained.

The programming unit SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to a scan signal from the gate line GL, thereby applying a data voltage from the data line DL to one electrode of the storage capacitor. The driving TFT (DT) controls the amount of light emitting diode (LED) by controlling the amount of current supplied to the light emitting diode (LED) according to the level of the voltage charged in the storage capacitor. The amount of light emitted from the light emitting diode (LED) is proportional to the amount of current supplied from the driving TFT (DT).

The TFTs constituting the pixel may be implemented as p-type or as n-type. In addition, the semiconductor layers of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide. A light emitting diode (LED) includes an anode electrode, a cathode electrode, and a light emitting structure interposed between the anode electrode and the cathode electrode. An anode electrode is connected to the driving TFT (DT). The light emitting structure includes a light emitting layer (Emission layer, EML), a hole injection layer (HIL) and a hole transport layer (HTL) on one side with the light emitting layer interposed therebetween, and an electron transport layer (HTL) on the other side. An electron transport layer (ETL) and an electron injection layer (EIL) may be respectively disposed.

The data driver includes a chip-on-film 30 in which a data IC (SD) is mounted, one side of which is connected to one end of the source printed circuit board 20, and the other side of which is attached to the bezel area BA of the display panel 10. include

The data IC (SD) converts digital video data input from the timing controller (TC) into an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data IC (SD) is supplied to the data lines D1 to Dm.

The GIP type gate driver is formed in the level shifters LSa and LSb mounted on the source printed circuit board 20 and the bezel area BA of the display panel 10, so that the level shifters LSa and LSb are It includes shift registers (SRa, SRb) that receive supplied signals.

The level shifters LSa and LSb receive signals such as a start pulse ST, gate shift clocks GLCK, and a flicker signal FLK from the timing controller TC, and also receive a gate high voltage VGH, gate A driving voltage such as a low voltage (VGL) is supplied. The start pulse ST, gate shift clocks GCLK, and flicker signal FLK are signals that swing between approximately 0V and 3.3V. The gate shift clocks GLCK1 to n are n-phase clock signals having a predetermined phase difference. The gate high voltage (VGH) is a voltage higher than or equal to the threshold voltage of the thin film transistor (TFT) formed in the thin film transistor array of the display panel 10 and is a voltage of about 28V, and the gate low voltage (VGL) is the voltage of the thin film transistor (TFT) of the display panel 10 It is a voltage lower than the threshold voltage of the thin film transistor (TFT) formed in the transistor array and is approximately -5V.

The level shifter LS is a shift clock signal obtained by level-shifting the start pulse ST and the gate shift clocks GLCK input from the timing controller TC to a gate high voltage VGH and a gate low voltage VGL, respectively. outputs (CLK). Accordingly, each of the start pulse VST and shift clock signals CLK output from the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The level shifter LS may reduce the flicker by lowering the kickback voltage ΔVp of the liquid crystal cell by lowering the gate high voltage according to the flicker signal FLK.

The output signals of the level shifter LS are transferred to shift registers through lines formed on the chip-on-film 30 on which the source drive IC SD is disposed and Line On Glass (LOG) lines formed on the substrate of the display panel 10. SR) can be supplied. The shift register SR may be directly formed on the bezel area BA of the display panel 10 by a GIP process.

The shift register SR shifts the start pulse VST input from the level shifter LS according to the gate shift clock signals CLK1 to CLKn, thereby generating a gate pulse swinging between the gate high voltage and the gate low voltage VGL. shift sequentially. The gate pulse output from the shift register SR is sequentially supplied to the gate lines G1 to Gn.

The timing controller TC receives timing signals such as a vertical sync signal, a horizontal sync signal, a data enable signal, and a main clock input from a host system (not shown), and receives data ICs (SD) and gate drivers (LSa, LSb). , SRa, SRb) operation timing is synchronized. The data timing control signal for controlling the data IC SD may include a source sampling clock (SSC), a source output enable signal (SOE), and the like. Gate timing control signals for controlling the gate drivers (LSa, LSb, SRa, SRb) include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Output Enable, GOE), etc.

Although FIG. 1 shows a configuration in which shift registers SRa and SRb are disposed on both sides of the outer side of the active area AA to supply gate pulses to the gate lines G1 to Gn at both ends of the active area AA, this The present invention is not limited thereto, and the shift register may be disposed only on one side of the active area AA to supply gate pulses to the gate lines G1 to Gn on one side of the active area AA. When the shift registers SRa and SRb are disposed on both sides outside the active area AA, gate pulses having the same phase and the same amplitude are supplied to gate lines disposed on the same horizontal line of the pixel array.

Referring to FIG. 2 , the display panel 10 of the present invention includes an active area AA and a bezel area BA outside the active area AA.

The active area AA is an area where the pixel array is disposed, and includes a first area having a free form portion (the area from line b to line d and the area from line e to f) , a second region (region from line d to line e) not having a release portion.

The bezel area BA is an area outside the active area AA and surrounds the active area AA, and includes a third area (the area from line a to line d and the area from line f to line f) having a similar shape to that of the active area AA. It may include a region up to line g) and a fourth region (region from line d to line e) not having a release portion.

The release portion may include at least one of a curved portion RO having a round shape at a corner portion of the display panel 10 and a notch portion NO having a predetermined area removed along one side of the display panel 10 .

In the example of FIG. 2 , the curved portion RO and the notch portion NO are simultaneously included, and the notch portion NO is a deformed portion formed at the center of one side of the display panel 10 . However, the present invention is not limited thereto. not. For example, the release portion may include only a curved portion, only a notch portion, or a notch portion formed at a corner portion. Therefore, the example of FIG. 2 should not be construed as reducing the scope of the present invention.

As shown in FIG. 2 , since the first area of the active area AA has a first area including a silver release portion and a second area not including a release portion, the first area (ie, from line b to line d) The number of pixels corresponding to the horizontal line of the pixel array arranged in the area of , the area from line e to line f) is in the horizontal line of the pixel array arranged in the second area (ie, the area from line d to line e). It is bound to be less than the number of corresponding pixels. For example, the number of pixels corresponding to one gate line G4a and G4b disposed in the first region may be less than the number of pixels corresponding to the gate line G6 disposed in the second region. Therefore, a difference in R-C load (resistor-capacitor load) may occur according to a difference in the number of pixels, and thus a luminance non-uniformity problem may occur. And, accordingly, the display quality is degraded.

In the present invention, in order to solve this problem, as shown in FIG. 3 , at least one first layer is provided in the third area of the bezel area BA where pixels are not formed to compensate for the luminance non-uniformity between the first area and the second area. - 3rd load compensating units (DCA1, DCA2, DCA3) are arranged to solve the problem of luminance non-uniformity.

In FIG. 3, in order to avoid complicating the drawing and description, known components unrelated to the technical features of the present invention, for example, the configuration of the second power lines VS1 to VSn are omitted. In addition, although FIG. 3 shows that the first area includes first and second sub-active areas divided into left and right sides by the notch part NO, the present invention is not limited thereto. For example, a plurality of notches NO may be disposed on either the left side or the right side of the active area AA, or in the central portion. Accordingly, the example of FIG. 3 should not be construed as reducing the scope of protection of the present invention.

Referring to FIG. 3 , the display panel 10 according to an exemplary embodiment includes an active area AA and a bezel area BA.

In FIG. 3 , for simplicity of explanation, four gate lines constituting a pixel array are arranged along the first power line direction (eg, the arrangement direction of VD1 ) in the first area of the active area AA of FIG. 2 . A case in which it is arranged will be described as an example.

Each of the pixels in the active area AA corresponding to the first area and the second area is considered to have the same size.

The two first and second gate lines disposed above the first region include first and second gate lines G1a and G2a sequentially receiving first and second gate pulses from the left shift register SRa, and , 1b and 2b gate lines G1b and G2b sequentially receiving the first and second gate pulses from the right shift register SRb.

The first and second gate lines G1a and G2a disposed in the first sub-active area of the active area divided by the left side of the first area (ie, the notch NO) extend from the first sub-active area to the bezel area. It may extend to the first compensation area of the third area of (BA). The 1a and 2a gate lines G1a and G2a correspond to the 1a dummy gate line GD1a and the 2a dummy gate line GD2a formed on different layers in the first compensating part DCA1 of the bezel area BA. can be connected The 1a gate line G1a and the 1a dummy gate line GD1a, and the 2a gate line G2a and the 2a dummy gate line GD2a may be connected to form an “inverted c” character.

The 1b and 2b gate lines G1b and G2b disposed on the right side of the first region (that is, the second sub-active region of the active region divided by the notch NO) extend the bezel from the second sub-active region. It may extend to the second compensation area of the third area of area BA. The 1b and 2b gate lines G1b and G2b are connected to the 1b dummy gate line GD1b and the 2b dummy gate line GD2b formed on different layers in the second compensation unit DCA2 in the bezel area BA. can be connected The 1b gate line G1b and the 1b dummy gate line GD1b, and the 2b gate line G2b and the 2b dummy gate line GD2b may be connected to form a “c” shape.

The display panel 10 includes a first compensation unit formed by overlapping the first power supply electrode VDLb with the first and second dummy gate lines GD1a and GD2a disposed in the first compensation area of the bezel area BA. A second compensator formed by overlapping DCA1 and the first power supply electrode VDLb with the 1b and 2b dummy gate lines GD1b and GD2b disposed in the second compensation area of the bezel area BA ( DCA2).

Meanwhile, similar to the gate lines disposed on the upper side of the first region, the gate lines disposed on the lower side of the first region are sequentially supplied with the third and fourth gate pulses from the left shift register SRa. 4a gate lines G3a and G4a, and 3b and 4b gate lines G3b and G4b sequentially receiving the third and fourth gate pulses from the right shift register SRb.

The left third and fourth gate lines G3a and G4a and the right third and fourth gate lines G3b and G4b, which are the gate lines disposed below the first region, are divided by the notch NO. The third and fourth dummy gate lines GD3 and GD4 disposed in the third compensation area of the third area of the bezel area BA between the first subactive area and the right second subactive area are connected to each other.

The display panel 10 includes a third compensation unit formed by overlapping the first power supply electrode VDLb with the third and fourth dummy gate lines GD3 and GD4 disposed close to the horizontal line of the notch NO. (DCA3).

The first compensating unit DCA1 and the second compensating unit DCA2 of the display panel 10 will be described in detail with reference to FIGS. 5 and 6 , and the third compensating unit DCA3 will be described in FIGS. 7 and 8 . It will be described in more detail with reference to.

Since the first compensating unit DCA1 and the second compensating unit DCA2 are formed in different positions but have the same substantial structure, in the following description with reference to FIGS. 5 and 6, the first compensating unit DCA1 is represented. By explaining, it is assumed that the description of the second compensating unit DCA2 is also included.

Before describing the first to third compensating units DCA1 , DCA2 , and DCA3 , a cross-sectional structure of a pixel P constituting a pixel array in an active area will be described with reference to FIG. 4 .

FIG. 4 is a cross-sectional view illustrating structures of a thin film transistor (TFT), a storage capacitor (Cst), and a light emitting diode (LED) in the pixel P shown in FIG. 1 .

Referring to FIG. 4 , a single- or multi-layered buffer layer BUF may be disposed on the substrate SUB. The substrate SUB may be formed of a flexible translucent material. When the substrate SUB is formed of a material such as polyimide, the buffer layer BUF protects the substrate SUB from impurities such as alkali ions flowing out from the substrate SUB in a subsequent process. In order to prevent the light emitting element from being damaged, it may be formed as a single layer made of any one of inorganic and organic materials. Also, the buffer layer BUF may be formed of multiple layers made of different inorganic materials. Also, the buffer layer BUF may be formed as a multi-layer formed of an organic material layer and an inorganic material layer. The inorganic material layer may include any one of a silicon oxide layer (SiOx) and a silicon nitride layer (SiNx). The organic material may include photo acrylic.

A semiconductor layer A may be disposed on the buffer layer BUF. The semiconductor layer A may include a source region SA and a drain region DA spaced apart from each other with the channel region CA interposed therebetween. The source region SA and the drain region DA may be conductive regions. The semiconductor layer (A) may be formed using amorphous silicon or polycrystalline silicon obtained by crystallizing amorphous silicon. Alternatively, the semiconductor layer A may be formed of any one of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), or zinc tin oxide (ZnSnO). In addition, the semiconductor layer (A) may be formed of a low molecular weight or high molecular weight organic material such as melocyanine, phthalocyanine, pentacene, and thiophene polymer.

A gate insulating layer GI is disposed on the buffer layer BUF on which the semiconductor layer A is disposed to cover the semiconductor layer A. The gate insulating layer GI may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the gate insulating layer GI may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof.

On the gate insulating film GI, the gate electrode GE of the thin film transistor TFT and a gate line connected to the gate electrode GE are overlapped with the channel layer CA of the semiconductor layer A so that at least a portion thereof overlaps (not shown). ) can be placed. A first electrode C1 of the storage capacitor Cst may be disposed on the gate insulating layer GI. The gate electrode GE and the gate line, and the first electrode C1 include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). ) It may be any one selected from the group consisting of, or an alloy thereof, and may be made of a single layer or multiple layers.

A first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI on which the gate electrode GE, the gate line, and the first electrode C1 of the storage capacitor Cst are disposed to cover them. The first interlayer insulating layer INT1 may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the gate insulating layer GI may be formed of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx).

The second electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer INT1 to overlap the first electrode C1. The second electrode C2 is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be an alloy thereof, and may be composed of a single layer or multiple layers.

A second interlayer insulating layer INT2 may be disposed to cover the second electrode C2 of the storage capacitor Cst. The second interlayer insulating layer INT2 may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the second interlayer insulating layer INT2 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof.

A source electrode SE and a drain electrode DE of the thin film transistor TFT may be disposed on the second interlayer insulating layer INT2. A third electrode C3 may be disposed on the second interlayer insulating layer INT2 to overlap the second electrode C2 of the storage capacitor Cst. The source electrode SE and the drain electrode DE include a source region SA of the semiconductor layer exposed through contact holes penetrating the gate insulating layer GI and the first and second interlayer insulating layers INT1 and INT2, and the drain Each may be connected to the area DA. The third electrode C3 of the storage capacitor Cst may be connected to the second electrode C2 exposed through the contact hole of the second interlayer insulating layer INT2. The source electrode SE, the drain electrode DE, and the third electrode C3 of the storage capacitor Cst are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), or titanium (Ti). , may be any one selected from the group consisting of nickel (Ni) and copper (Cu), or an alloy thereof, and may be made of a single layer or multiple layers.

A passivation layer PAS may be disposed to cover the source electrode SE, the drain electrode DE, and the third electrode C3 of the storage capacitor Cst. The passivation layer PAS may be formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. For example, the passivation layer PAS may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof.

A first planarization layer PLN1 may be disposed on the passivation layer PAS. The first planarization layer PLN1 is for protecting the lower structure while alleviating the level difference of the lower structure, and may be formed of an organic material layer. For example, the first planarization layer PLN1 may be formed of a photo acrylic layer. A connection electrode CON for connecting an anode electrode ANO of a light emitting diode (LED) to the drain electrode DE may be disposed on the first planarization layer PLN1 . A fourth electrode C4 connected to the third electrode C3 of the storage capacitor Cst may be disposed on the first planarization layer PL1. The connection electrode CON is connected to the drain electrode DE of the thin film transistor TFT exposed through the contact hole of the first planarization layer PLN1 and the passivation layer PAS, and the fourth portion of the storage capacitor Cst. The electrode C4 may be connected to the fourth electrode C4 of the storage capacitor Cst exposed through the contact hole of the first planarization layer PLN1 and the passivation layer PAS. The connection electrode CON and the fourth electrode C4 of the storage capacitor Cst are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper. It may be any one selected from the group consisting of (Cu), or an alloy thereof, and may be composed of a single layer or multiple layers.

A second planarization layer PLN2 may be disposed on the first planarization layer PLN1 to cover the connection electrode CON and the fourth electrode C4 of the storage capacitor Cst. The second planarization layer PLN2 may be a planarization layer that additionally protects the lower structure while further mitigating a level difference between the connection electrode CON on the first planarization layer PL and the fourth electrode C4 of the storage capacitor. there is. The second planarization layer PLN2 may be formed of an organic material layer. For example, the second planarization layer PLN2 may be formed of a siloxane-based organic material.

An anode electrode ANO may be disposed on the second planarization layer PLN2 . The anode electrode ANO is connected to the exposed connection electrode CN through a contact hole penetrating the second planarization layer PLN2. The anode electrode ANO may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

A bank layer BN having an opening OL exposing the anode electrode AN may be formed on the second planarization layer PLN2 .

The opening of the bank layer BN may be an area defining the light emitting area LA. On the anode electrode ANO exposed through the light emitting region of the bank layer BL, the light emitting stacked structure LES and the cathode electrode CAT are sequentially disposed. The light emitting layered material LES may include a hole layer, a light emitting layer, and an electron layer. The cathode electrode CAT may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function. In the present invention, it has been described that the light emitting laminate (LES) is disposed on the anode electrode (ANO) and the cathode electrode (CAT) is disposed on the light emitting laminate (LES), but the light emitting laminate is placed on the cathode electrode (CAT). Water LES may be disposed, and an anode electrode ANO may be disposed on the light emitting laminate LES.

An encapsulation layer ENC may be disposed on the second planarization layer PLN2 to cover the cathode electrode CA and the bank layer BL. The encapsulation layer (ENC) is to prevent penetration of moisture or oxygen from the outside into the light emitting layered material (LES) located inside the encapsulation layer (ENC), and may be formed in a multi-layered structure in which an inorganic material layer and an organic material layer are alternately disposed. .

Next, the first compensation unit DCA1 and the second compensation unit DCA2 of the display panel 10 will be described in more detail with reference to FIGS. 3, 5, and 6 . FIG. 5 is an enlarged plan view of a partial area of the first compensating unit DCA1 of FIG. 3 , and FIG. 6 is a cross-sectional view taken along line A-A' and line B-B' of FIG. 4 .

5 and 6 , the first compensation unit DCA1 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a semiconductor layer ACT disposed on the buffer layer BUF. include The semiconductor layer ACT of the first compensation unit DCA1 may be formed by the same process as the semiconductor layer A of the thin film transistor TFT. can be formed on the same layer. Also, the semiconductor layer ACT of the first compensation unit DCA1 may be formed of the same material as the semiconductor layer A of the thin film transistor TFT. The semiconductor layer ACT of the first compensation unit DCA1 may be a layer made of a semiconductor material as a conductor. Conducting the semiconductor layer ACT of the first compensating unit DCA1 is formed by conducting both the source region SA and the drain region SA of the semiconductor layer A of the thin film transistor TFT. can The semiconductor layer ACT of the first compensation unit DCA1 includes a plurality of semiconductor layers (eg, ACT1 to ACT3). A gate insulating layer GI may be disposed on the buffer layer BUF to cover the semiconductor layer ACT.

Referring to FIGS. 5 and 7 , a 2a gate line G2a and a 1a gate line G1a may be disposed parallel to each other on the gate insulating layer GI.

A first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI to cover the first 1a gate line G2a and the 1b th gate line G1a. On the first interlayer insulating layer INT1, the 2a dummy gate line GD2a and the 1a dummy gate line GD1a are parallel to each other so that at least a portion overlaps the 2a gate line G2a and the 1a gate line G1a. can be placed. The 2a dummy gate line GD2a is connected to the 2a gate line G2a through the second contact hole CH2 penetrating the first interlayer insulating film INT1, and the 1a dummy gate line GD1a is It may be connected to the first gate line G1a through the first contact hole CH2 penetrating the interlayer insulating layer INT1.

Referring to FIGS. 5 and 6 , the first dummy gate line GD1a and the second dummy gate line GD1b are disposed to overlap a plurality of semiconductor layers (eg, ACT1, ACT2, and ACT3). To compensate for a capacitance value generated according to a difference between the number of pixels in the first area of the active area AA having the release portion and the number of pixels in the second area of the active area AA without the release portion, a plurality of The overlapping areas of the semiconductor layers ACT1 , ACT2 , and ACT3 and the first dummy gate line GD1a and the second dummy gate line GD1b may be formed differently. For example, the area overlapping the semiconductor layer ACT and the first dummy gate line GD1a and the second dummy gate line GD1b may be formed differently by using the number or size of the semiconductor layers ACT. . Alternatively, by adjusting the width or length of at least one of the 1a dummy gate line GD1a and the 2a dummy gate line GD1b, the semiconductor layer ACT and the 1a dummy gate line GD1a and the 2a dummy gate line The overlapping area of (GD1b) can be formed differently. Specifically, although the first dummy gate line GD1a and the second dummy gate line GD1b are shown as straight lines in FIG. 5 , they may be formed in a concavo-convex shape having curves. As such, when the 1a dummy gate line GD1a and the 2a dummy gate line GD1b are formed in a concavo-convex shape, as shown in FIG. 5, the lengths of the 1a dummy gate line GD1a and It can be longer than the length of the 2a dummy gate line GD1b. Accordingly, an overlapping area between the semiconductor layer ACT and the first dummy gate line GD1a and the second dummy gate line GD1b may increase. And, it is possible to increase the capacitance value for compensation.

A second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer ILD1 to cover the 1a dummy gate line GD1a and the 2a dummy gate line GD2a.

A first power supply electrode VDLb may be disposed on the second interlayer insulating layer INT2 and overlap the 2a dummy gate line GD2a and the 1a dummy gate line GD1a. The first power supply electrode VDLb is connected to the semiconductor layer through the third and fourth contact holes CH3 and CH4 penetrating the second interlayer insulating film INT2, the first interlayer insulating film INT1, and the gate insulating film GI. (ACTs).

A passivation layer PAS may be disposed on the first power supply electrode VDLb to protect the first power supply electrode VDLb.

* At least one of a first planarization layer PLN1 , a second planarization layer PLN2 , and an encapsulation layer ENC may be formed on the passivation layer PAS.

The second compensation unit DCA2 is also formed similarly to the first compensation unit DCA1 and is formed in the same manner as the first compensation unit DCA1. Therefore, further description is omitted.

Next, the third compensation unit DCA3 of the display panel 10 will be described in more detail with reference to FIGS. 3, 7, and 8 .

FIG. 7 is an enlarged plan view of a partial area of the third compensating unit 3CA1 of FIG. 3 , and FIG. 8 is a cross-sectional view taken along line A-A' and line B-B' of FIG. 7 .

7 and 8 , the third compensation unit DCA3 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a plurality of semiconductor layers disposed on the buffer layer BUF (eg, For example, ACT5, ACT6) may be included. The semiconductor layer ACT of the third compensation unit DCA1 may be formed by the same process as the semiconductor layer A of the thin film transistor TFT. can be formed on the same layer. Also, the semiconductor layer ACT of the third compensation unit DCA1 may be formed of the same material as the semiconductor layer A of the thin film transistor TFT. The semiconductor layer ACT of the third compensation unit DCA1 may be a layer made of a semiconductor material as a conductor. Conducting the semiconductor layer ACT of the third compensating unit DCA1 is formed by conducting both the source region SA and the drain region SA of the semiconductor layer A of the thin film transistor TFT. A gate insulating layer GI may be disposed on the buffer layer BUF to cover the semiconductor layers ACT5 and ACT6.

Referring to FIGS. 7 and 8 , the third gate line G3a and the third gate line G3b may be separated from each other and disposed on the same line on the gate insulating layer GI. Also, the 4a gate line G4a and the 4b gate line G4b may be disposed to be separated from each other. The 3a gate line G3a and the 4a gate line G3a may be disposed parallel to each other. Also, the 3b-th gate line G3b and the 4b-th gate line G3b may be disposed parallel to each other.

A first interlayer insulating film INT1 is disposed on the gate insulating film GI to cover the 3a gate line G3a and the 3b gate line G3b and the 4a gate line G4a and the 4b gate line G4b. can A third dummy gate line GD3 is disposed on the first interlayer insulating layer INT1 to overlap one end of the 3a gate line G3a and one end of the 3b gate line G3b, and a 4a gate line G4a. ) and the fourth dummy gate line GD4 may be disposed to overlap one end of the 4b gate line G4b.

The third dummy gate line GD3 may be connected to the 3a and 3b gate lines G3a and G3b through the fifth contact holes CH5 penetrating the first interlayer insulating layer INT1 . The fourth dummy gate line GD4 may be connected to the 4a and 4b gate lines G4a and G4b through the sixth contact holes CH6 penetrating the first interlayer insulating layer INT1 .

Referring to FIG. 8 , a second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer INT1 to cover the third dummy gate line GD3 and the fourth dummy gate line GD4 .

A first power supply electrode VDLb overlapping the third dummy gate line GD3 and the fourth dummy gate line GD4 may be disposed on the second interlayer insulating layer INT2 . The first power supply electrode VDLb has seventh and eighth contacts exposing the semiconductor layers ACT5 and ACT6 by passing through the second interlayer insulating film INT2, the first interlayer insulating film INT1, and the gate insulating film GI. It is connected to the semiconductor layers ACT5 and ACT6 through the holes CH7 and CH8, respectively.

A passivation layer PAS for protecting the first power supply electrode VDLb is disposed on the first power supply electrode VDLb.

As shown in FIGS. 5 and 6 , the first compensation unit DCA1 according to the above configuration has a first capacitance formed by each dummy gate line GD1a or GD2a and the first power supply electrode VDLb. and a second compensation component of the second capacitances C2 formed by each of the dummy gate lines GD1a or GD2a and the plurality of semiconductor layers ACT1, ACT2, and ACT2. do.

Also, like the first compensating unit DCA1, the second compensating unit DCA2 is configured to compensate for the first capacitances C1 formed by each dummy gate line GD1b or GD2b and the first power supply electrode VDLb. It includes a first compensation component and a second compensation component of the second capacitances C2 formed by each dummy gate line GD1b or GD2b and a plurality of semiconductor layers.

As shown in FIGS. 7 and 8 , the third compensator DCA3 is configured to compensate for the first capacitances C1 formed by each dummy gate line GD3 or GD4 and the first power supply electrode VDLb. It includes a first compensation component and a second compensation component of the second capacitances C2 formed by each of the dummy gate lines GD3 or GD4 and the plurality of semiconductor layers ACT5, ACT6, and ACT7.

Therefore, in the present invention, the capacitance is maximized in a narrow space through the first compensating unit DCA1 and the second compensating unit DCA2 having a double capacitor structure of the first capacitance C1 and the second capacitance C2. can do. Like the first compensating unit DCA1, the third compensating unit DCA3 also has a double capacitor structure, so that the capacitance can be maximized in a narrow space adjacent to the horizontal portion of the notch NO. Therefore, since the R-C load per pixel line can be increased through the first compensating unit DCA1, the second compensating unit DCA2, and the third compensating unit DAC3 located in the third area of the bezel area, the active area It is possible to compensate to be close to the R-C load per pixel line disposed in the second area of (AA), and thus an effect of improving luminance non-uniformity of the display panel can be obtained.

Next, a luminance improvement effect obtained by the display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 9 .

9 is a graph illustrating luminance change of a display device without a compensation unit and luminance change of a display device with a compensation unit according to an exemplary embodiment of the present invention. In FIG. 9 , a solid line represents a luminance change of a display device without a compensation unit, and a dotted line represents a luminance change of a display device with a compensation unit according to an exemplary embodiment of the present invention. In FIG. 9, the standard luminance of the display device is set to 150 nits.

In FIG. 9, the horizontal axis indicates gate lines (1st to 30th lines) corresponding to the b-c section of the first region of the display device shown in FIG. 2 and gate lines (30 to 90th lines) corresponding to the c-d section of the first region. line), and gate lines (90th to 120th lines) corresponding to the d-e section of the second region. And, the vertical axis represents the luminance change of the display device. 0% on the vertical axis indicates that there is no change in the luminance of the display device compared to the reference luminance of 150 nit.

Referring to FIG. 9 , looking at a solid line representing a change in luminance of a display device without a compensating part, there is no change in luminance in the period d-e of the second region, which is an active region without a release part, but b-c and b-c and It can be confirmed that a change in luminance occurs in the c-d section. It can be seen that the change in luminance compared to the standard luminance is about 6% to 18%.

In FIG. 9 , looking at a dotted line representing a luminance change of a display device having a compensating part according to an exemplary embodiment of the present invention, not only a period d-e of the second area, which is an active area without a release part, but also b-c and c-d, which are active areas having a release part. It can be seen that there is no change in luminance even in the section. From the above graph, the first compensating part DCA1, the second compensating part DCA2, and the third compensating part DAC3 located in the bezel area BA form the first compensation part of the active area AA including the irregular part. It can be seen that by increasing the R-C load of the gate line located in the region, compensation can be made to be close to the R-C load of each gate line located in the second region of the active area AA that does not include the release portion.

The R-C load for each gate line can be increased through the first compensating unit DCA1 and the second compensating unit DCA2 located in the first area A1 and the third compensating unit DAC3 located in the second area A2. Therefore, it is possible to compensate to be close to the R-C load for each gate line of the third region A3, so that the effect of improving the luminance non-uniformity of the display panel can be obtained.

A display device according to the present specification can be described as follows.

A display device according to a first aspect of the present specification includes: a display panel including an active area including a first area having a release portion and a second area without the release portion, and a bezel area outside the active area; gate lines and data lines disposed to cross each other in the active area; pixels connected to the gate lines and the data lines in the active area; a first power supply electrode supplying power to the pixels; and a dummy gate line disposed in the bezel area adjacent to the first area of the active area, wherein the dummy gate line is connected to a gate line disposed in the first area and overlaps with the first power supply electrode. to form a first capacitance.

The configuration may further include a semiconductor pattern connected to the first power supply electrode and overlapping the dummy gate line to form a second capacitance.

The deformed portion of the first area may include at least one of a round portion formed at a corner portion and a notch portion formed at one side of the active area.

The active region of the first region in which the notch part is formed includes first and second sub-active regions divided into left and right sides by the notch part, and first and second gate lines are disposed in the first sub-active region. and third and fourth gate lines may be disposed in the second sub-active region.

The dummy gate line may include: a first dummy gate line disposed in the bezel area adjacent to the first sub-active area; and a second dummy gate line disposed in the bezel area adjacent to the second sub-active area, wherein the first dummy gate line is connected to the first gate line of the first sub-active area and is connected to the second dummy gate line. A gate line may be connected to the third gate line of the second sub-active region.

the dummy gate line further comprises a third dummy gate line disposed in the bezel area between the first sub-active region and the second sub-active region;

The second gate line disposed in the first sub-active region and the fourth gate line disposed in the second sub-active region may be connected to each other by the third dummy gate line.

The first capacitance includes a first compensation capacitance formed by overlapping the first dummy gate line and the first power supply electrode and a second compensation capacitance formed by overlapping the second dummy gate line and the first power supply electrode. can include

The semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern, the second capacitance is a fourth compensation capacitance formed by overlapping the first dummy gate line and the first semiconductor pattern, and the second dummy gate A fifth compensation capacitance formed by overlapping a line and the second semiconductor pattern may be included.

The first and second semiconductor patterns may be connected to the first power supply electrode.

The first capacitance may further include a third compensation capacitance formed by overlapping the third dummy gate line and the first power supply electrode.

The semiconductor pattern may further include a third semiconductor pattern, and the second capacitance may include a sixth compensation capacitance formed by overlapping the third dummy gate line and the third semiconductor pattern.

The third semiconductor pattern may be connected to the first power supply electrode.

The semiconductor pattern is disposed on a substrate, the gate lines are disposed on a gate insulating layer disposed to cover the semiconductor pattern, and the data lines and the dummy gate line are disposed on a first interlayer insulating layer covering the gate lines. and the first power supply electrode may be disposed on a second interlayer insulating layer covering the dummy gate line.

The dummy gate line is connected to the gate line through a contact hole formed in the first interlayer insulating film, and the first power supply electrode is a contact penetrating the second interlayer insulating film, the first interlayer insulating film, and the gate insulating film. It may be connected to the semiconductor pattern through a hole.

*The first to third semiconductor patterns are disposed on a substrate, the gate lines are disposed on a gate insulating layer disposed to cover the first to third semiconductor patterns, and the data lines and the first to the third dummy gate lines are disposed on a first interlayer insulating film covering the gate lines, and the first power supply electrode is disposed on a second interlayer insulating film covering the first to third dummy gate lines; The first dummy gate line is connected to the first gate line through a first contact hole formed in the first interlayer insulating film, and the second dummy gate line is connected to the first gate line through a second contact hole formed in the first interlayer insulating film. The third dummy gate line is connected to the second gate line through a third contact hole formed in the first interlayer insulating film, and the fourth dummy gate line is connected through a fourth contact hole formed in the first interlayer insulating film. A contact hole connected to a gate line to connect the second gate line and the fourth gate line to each other, and the first power supply electrode passing through the second interlayer insulating film, the first interlayer insulating film, and the gate insulating film. It may be connected to the first to third semiconductor patterns through.

A display device according to a second aspect of the present specification includes an active area including a first area having a release portion and a second area not having a release portion, a third area corresponding to the first area, and a second area corresponding to the second area. a display panel including a bezel area disposed outside the active area; first pixels formed to correspond to the first gate line disposed in the first region; second pixels formed corresponding to the second gate line disposed in the second region, the number of which is greater than the number of pixels of the first pixels; and a power supply electrode disposed in the bezel area of the display panel and supplying power to the first pixels and the second pixels, wherein the third area of the bezel area includes a first area of the first area. and at least one compensation unit connected to one gate line or the power supply electrode to form a compensation capacitance to compensate for a load generated according to a difference in the number of pixels between the first pixels and the second pixels.

At least one compensation unit may further include a semiconductor pattern forming a second capacitance with the first power supply electrode.

The first compensation pattern is positioned between the power supply electrode and the second compensation pattern to form the first compensation capacitance with the power supply electrode and form the second compensation capacitance with the second compensation pattern. can

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the technical spirit of the present specification. In the example shown in the present invention, an electroluminescent display device has been described as an example, but the present invention is not limited thereto, and a liquid crystal display device (LCD), a plasma display panel (PDP), an electric field It can be applied to various flat panel display devices such as a Field Emission Display Device (FED) and an Electrophoretic Display Device (ED). Therefore, the technical scope of the present specification is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: display panel A1: first area
A2: 2nd area A3: 3rd area
AA: active area ACT: metalized semiconductor layer
BA: Bezel area D1 to Dm: Data line
GD1a, GD1b, GD2a, GD2b, GD3, GD4: dummy gate lines
G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b, G5... Gn: Gate line
DCA1: 1st compensating unit DCA2: 2nd compensating unit
DCA3: 3rd compensation part PS: power supply part
VD1~VDm: 1st power line
VDLa, VDLb: first power supply electrode

Claims (19)

An active area including a first area having a plurality of pixels and a second area including a second area having a different number of pixels per unit area from the first area, and a bezel area disposed outside the active area and including a gate driving circuit display panel;
a plurality of gate lines electrically connected to the gate driving circuit to transmit signals to the plurality of pixels;
a first power supply electrode supplying power to the plurality of pixels; and
and a dummy gate line disposed in the bezel area, one side connected to the gate driving circuit and the other side not connected to the plurality of pixels. According to claim 1,
Further comprising a data driver for transmitting data voltages to the plurality of pixels;
The first power supply electrode,
A display device disposed adjacent to the data driver. According to claim 1,
and a first power line connected to the first power supply electrode to supply a first power to the plurality of pixels. The method of claim 3, wherein the first power supply electrode,
A display device comprising: a lower first power supply electrode disposed on one side of the bezel area and an upper first power supply electrode disposed on the other side of the bezel area. According to claim 4,
The display device further comprises at least one link wire connecting the lower first power supply electrode and the upper first power supply electrode. According to claim 3,
The display device further comprises a second power line supplying a second power having a low potential voltage to the plurality of pixels. The method of claim 6, wherein the second power line,
The outermost wiring, the display device. The method of claim 1, wherein the gate driving circuit,
A display device comprising a level shifter mounted on a source printed circuit board (20). According to claim 8,
An output signal of the level shifter is supplied to a shift register through line on glass (LOG) wires formed on a substrate of a display panel. According to claim 9,
Wherein the substrate is formed of a flexible translucent material. According to claim 9,
The LOG wires have a shape in which some of the power wires are overlapped in a jumping structure. According to claim 9,
When the shift registers are disposed on both sides outside the active region, gate pulses of the same phase and the same amplitude are supplied to gate lines disposed on the same horizontal line of the pixel array. The method of claim 1, wherein the display panel,
A display device comprising at least one oxide TFT. According to claim 1,
The display device, wherein the display panel has a curved portion having a round shape at a corner portion. According to claim 1,
The number of pixels disposed in the first area is less than the number of pixels disposed in the second area. According to claim 1,
A display device, wherein a passivation film is disposed on the first power supply electrode. According to claim 16,
The passivation film is formed of a single layer made of an inorganic material or multiple layers made of different inorganic materials. The method of claim 16, wherein the passivation film,
A display device comprising a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof. An active area including a first area having a plurality of pixels and a second area including a second area having a different number of pixels per unit area from the first area, and a bezel area disposed outside the active area and including a gate driving circuit display panel;
a plurality of gate lines electrically connected to the gate driving circuit to transmit signals to the plurality of pixels;
a first power supply electrode supplying power to the plurality of pixels; and
and a dummy gate line disposed to overlap or face the first power supply electrode in the bezel area, at least a portion of which is not connected to the plurality of pixels.

Images