KR20240046447A - Display Apparatus - Google Patents

Abstract

This specification is intended to provide a display device that can improve luminance unevenness of a display panel by compensating for the R-C load in the area having the irregularities. The display device of the present specification includes a display panel including an active area including a first area with a special shape and a second area without a special shape, and a bezel area outside the active area; Gate lines and data lines arranged to cross each other within the active area; pixels connected to the gate lines and the data lines within the active area; a first power supply electrode that supplies a first potential to the pixels; and a dummy gate line disposed in a bezel area adjacent to the first region and connected to a gate line disposed in the first region to form the first power supply electrode and a first capacitance, wherein the first region and and at least one compensation unit that compensates for a load due to a difference in the number of pixels per line in the second area.

Description

Display Apparatus

This specification relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, there has been rapid development of flat panel displays (FPDs) that are thin, light, and capable of large areas, replacing bulky cathode ray tubes (CRTs). Such flat panel displays include Liquid Crystal Display (LCD), Plasma Display Panel (PDP), Electroluminescent Display (EL), and Field Emission Display (FED). , and electrophoretic displays (ED), various flat panel displays have been developed and used.

These display devices include a display panel including display elements for displaying information, a driver for driving the display panel, and a power supply that generates power to be supplied to the display panel and the driver.

These display devices can be designed to have various designs depending on the usage environment or purpose, and correspondingly, the display panel that displays the image also has unusual shapes such as a partial curve or notch from the traditional single rectangular shape. ), as well as shapes such as circular and oval.

In this way, a display device consisting of a display panel that has a special shape or is implemented in a circular or oval shape has the advantage of appealing to consumers who value design aspects in that it can increase the degree of freedom in product design.

However, since the number of pixels placed on the curved or notched display panel and other parts of the display panel varies for each line (e.g., horizontal line), a difference in R-C load (Resistor-Capacitor load) occurs. , this caused problems with uneven luminance of the display panel and deteriorated display quality.

This specification provides a display device that can improve luminance unevenness of a display panel by compensating the R-C load of the unusual part to correspond to the R-C load according to the difference in the number of pixels between the area including the unusual part and the area not containing the unusual part of the display panel. It is intended to provide.

A display device according to a first aspect of the present specification includes: a display panel including an active area including a first area with a special shape and a second area without a special shape, and a bezel area outside the active area; Gate lines and data lines arranged to cross each other within the active area; pixels connected to the gate lines and the data lines within the active area; a first power supply electrode that supplies power to the pixels; and a dummy gate line disposed in the bezel area adjacent to the first region of the active area, wherein the dummy gate line is connected to the gate line disposed in the first region and overlaps the first power supply electrode. Thus, a first capacitance can be formed.

The display device according to the second feature of the present specification includes an active area including a first area with a special shape and a second area without a special shape, a third area corresponding to the first area, and a third area corresponding to the second area. a display panel including a fourth area and a bezel area disposed outside the active area; first pixels formed corresponding to a first gate line disposed in the first area; second pixels formed to correspond to a second gate line disposed in the second area and having a larger number of pixels than the first pixels; and a power supply electrode disposed in the bezel area of the display panel and supplying power to the first pixels and the second pixels, wherein the third area of the bezel area 1 It may include at least one compensation unit connected to a gate line or the power supply electrode to form a compensation capacitance to compensate for a load generated according to a difference in the number of pixels between the first pixels and the second pixels. .

*According to the display device of this specification, it is possible to increase the R-C load for each gate line by disposing at least one compensation unit in the bezel area of the display panel with the unusual part, so compensation can be made to approach the R-C load for each gate line of the non-differential part. This can achieve the effect of improving the luminance unevenness of the display panel.

1 is a block diagram showing a display device according to an embodiment of the present specification;
Figure 2 is a plan view schematically showing the shape of the display panel shown in Figure 1;
FIG. 3 is a plan view schematically showing a partial area R1 of the display panel shown in FIG. 2;
FIG. 4 is a cross-sectional view showing the structures of the thin film transistor, storage capacitor, and light emitting diode in the pixel P shown in FIG. 1;
Figure 5 is a plan view showing an enlarged portion of a portion of the first compensation unit of Figure 3;
Figure 6 is a cross-sectional view taken along line A-A' and line B-B' of Figure 4;
Figure 7 is an enlarged plan view of a partial area of the first compensating part of Figure 3;
Figure 8 is a cross-sectional view taken along line A-A' and line B-B' of Figure 7;
9 is a graph comparing the luminance before compensation and the luminance of the display device after compensation by a compensation unit according to an embodiment of the present invention.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the specification, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative and are not limited to the matters shown in the specification. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be partially or fully combined or combined with each other, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, a display device according to embodiments of the present specification will be described with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted or explained briefly.

Hereinafter, a display device according to an embodiment of the present specification will be described with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram showing a display device according to an embodiment of the present specification, and FIG. 2 is a plan view schematically showing the shape of the display panel shown in FIG. 1. FIG. 3 is a plan view schematically showing a partial area R1 of the display panel shown in FIG. 2.

Referring to FIG. 1, a display device according to an embodiment of the present specification includes a display panel 10, a data driver, a GIP (Gate In Panel) type gate driver, a power supply (PS), and a timing controller (TC). can do.

The display panel 10 includes an active area (AA) that displays information and a bezel area (BA) in which information is not displayed.

The active area (AA) is an area where an input image is displayed and is an area where a pixel array in which a plurality of pixels (P) are arranged in a matrix type is disposed.

The bezel area (BA) contains the shift registers (SRa, SRb) of the gate driving circuit, various link signal wires (GL1~GLn, DL1~DLm, ), link power supply lines (VDL1, VDL2, VSL1, VSL2), and power This is the area where supply electrodes (VDLa, VDLb), etc. are placed. The pixel array disposed in the active area (AA) includes a plurality of data lines (D1 to Dm) and a plurality of gate lines (G1 to Gn) arranged to intersect each other, and pixels ( P) includes.

Each pixel (P) includes a light emitting diode (LED), a driving thin film transistor (hereinafter referred to as TFT) (DT) that controls the amount of current flowing through the light emitting diode (LED), and the gate-source of the driving TFT (DT). It includes a programming unit (SC) for setting the voltage between the devices. The pixels (P) of the pixel array receive the first power (Vdd), which is a high potential voltage, from the power supply unit (PS) through the first power lines (VD1 to VDm), and the second power lines (VSLa to VSLb) The second power source (Vss), which is a low-potential voltage, is supplied through .

The first power lines (VD1 to VDm) include a lower first power supply electrode (VDLa) disposed in the bezel area (BA) on the side where the chip-on film 30 is attached, and an upper first power supply electrode (VDLa) disposed in the bezel area on the opposite side. The first power source (Vdd) is supplied from the power supply unit (PS) on both sides through the power supply electrode (VDLb). Both ends of the lower first power supply electrode VDLa and the upper first power supply electrode VDLb may be connected to each other by link wires VDL1 and VDL2. However, it is not limited to this, and in some cases, the link wires (VDL1 and VDL2) connecting both ends to each other may not be formed, but may be replaced by the first power lines (VD1 to VDm). Accordingly, it is possible to minimize the deterioration of display quality due to an increase in RC depending on the positions of pixels arranged in the active area (AA).

The programming unit SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to a scan signal from the gate line GL, thereby applying the data voltage from the data line DL to one electrode of the storage capacitor. The driving TFT (DT) controls the amount of current supplied to the light emitting diode (LED) according to the level of voltage charged in the storage capacitor, thereby adjusting the amount of light emitted by the light emitting diode (LED). The amount of light emitted from a light emitting diode (LED) is proportional to the amount of current supplied from the driving TFT (DT).

TFTs constituting a pixel may be implemented as a p type or as an n type. Additionally, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide. A light emitting diode (LED) includes an anode electrode, a cathode electrode, and a light emitting structure sandwiched between the anode electrode and the cathode electrode. The anode electrode is connected to the driving TFT (DT). The light emitting structure includes an emission layer (EML), a hole injection layer (HIL) and a hole transport layer (HTL) on one side with the light emitting layer in between, and an electron transport layer (HTL) on the other side. An electron transport layer (ETL) and an electron injection layer (EIL) may each be disposed.

The data driver unit is equipped with a data IC (SD), one side of which is connected to one end of the source printed circuit board 20, and the other side of which is a chip-on-film 30 attached to the bezel area (BA) of the display panel 10. Includes.

The data IC (SD) converts digital video data input from the timing controller (TC) into an analog gamma compensation voltage and generates a data voltage. The data voltage output from the data IC (SD) is supplied to the data lines (D1 to Dm).

The GIP type gate driver is formed in the level shifters (LSa, LSb) mounted on the source printed circuit board 20 and the bezel area (BA) of the display panel 10, and receives the power from the level shifters (LSa, LSb). It includes shift registers (SRa, SRb) that receive supplied signals.

The level shifters (LSa, LSb) receive signals such as the start pulse (ST), gate shift clocks (GLCK), and flicker signal (FLK) from the timing controller (TC), and also receive the gate high voltage (VGH) and gate shift signal (FLK). It is supplied with a driving voltage such as low voltage (VGL). The start pulse (ST), gate shift clocks (GCLK), and flicker signal (FLK) are signals that swing between approximately 0V and 3.3V. Gate shift clocks GLCK1 to n are n-phase clock signals with a predetermined phase difference. The gate high voltage (VGH) is a voltage higher than the threshold voltage of the thin film transistor (TFT) formed in the thin film transistor array of the display panel 10 and is approximately 28V, and the gate low voltage (VGL) is the voltage of the thin film transistor (TFT) of the display panel 10. This is a voltage lower than the threshold voltage of the thin film transistor (TFT) formed in the transistor array and is approximately -5V.

The level shifter (LS) is a shift clock signal that level-shifts the start pulse (ST) input from the timing controller (TC) and the gate shift clocks (GLCK) to the gate high voltage (VGH) and gate low voltage (VGL), respectively. outputs (CLK). Accordingly, each of the start pulse (VST) and shift clock signals (CLK) output from the level shifter (LS) swings between the gate high voltage (VGH) and the gate low voltage (VGL). The level shifter (LS) can reduce flicker by lowering the gate high voltage according to the flicker signal (FLK) and lowering the kickback voltage (ΔVp) of the liquid crystal cell.

The output signals of the level shifter (LS) are transmitted through the shift register ( SR) can be supplied. The shift register SR may be formed directly on the bezel area BA of the display panel 10 through the GIP process.

The shift register (SR) shifts the start pulse (VST) input from the level shifter (LS) according to the gate shift clock signals (CLK1 to CLKn), thereby swinging the gate pulse between the gate high voltage and the gate low voltage (VGL). are shifted sequentially. Gate pulses output from the shift register (SR) are sequentially supplied to the gate lines (G1 to Gn).

The timing controller (TC) receives timing signals such as vertical synchronization signal, horizontal synchronization signal, data enable signal, and main clock from the host system (not shown) and controls the data IC (SD) and gate drivers (LSa, LSb). , SRa, SRb) operation timing is synchronized. The data timing control signal for controlling the data IC (SD) may include a source sampling clock (SSC), a source output enable signal (Source Output Enable), etc. Gate timing control signals for controlling the gate drivers (LSa, LSb, SRa, SRb) include gate start pulse (GSP), gate shift clock (GSC), and gate output enable signal (Gate Output). Enable, GOE), etc.

Figure 1 shows a configuration in which shift registers SRa and SRb are arranged on both sides outside the active area AA to supply gate pulses to the gate lines G1 to Gn from both ends of the active area AA. The invention is not limited to this, and the shift register may be disposed only on one side of the active area AA to supply gate pulses to the gate lines G1 to Gn from one side of the active area AA. When the shift registers SRa and SRb are disposed on both sides outside the active area AA, gate pulses of the same phase and same amplitude are supplied to the gate lines disposed on the same horizontal line of the pixel array.

Referring to FIG. 2, the display panel 10 of the present invention includes an active area (AA) and a bezel area (BA) outside the active area (AA).

The active area (AA) is an area where the pixel array is placed, and includes a first area (the area from line b to line d and the area from line e to line f) having a free form portion; , may include a second area (area from line d to line e) that does not have a special shape.

The bezel area (BA) is an area surrounding the active area (AA) outside the active area (AA), and is a third area (the area from line a to line d and the area from line f to It may include an area up to line g) and a fourth area without a special shape (area from line d to line e).

The special shape part may have at least one of a curved part RO having a round shape at a corner of the display panel 10 and a notch part NO in which a certain area is removed along one side of the display panel 10 .

In the example of FIG. 2, it has both a curved surface RO and a notch NO, and the notch NO is shown in the center of one side of the display panel 10. However, the present invention is not limited to this. no. For example, the special shape may include only a curved portion, only a notch portion, or the notch portion may be formed at a corner portion. Accordingly, the example of FIG. 2 should not be construed as reducing the scope of the present invention.

As shown in FIG. 2, the first region of the active area (AA) is the first region (i.e., from line b to line d) because there is a first region including the silver feature and a second region not including the feature. The number of pixels corresponding to the horizontal line of the pixel array disposed in the area (i.e., the area from line e to line f) is the number of pixels corresponding to the horizontal line of the pixel array disposed in the second area (i.e., the area from line d to line e). It is bound to be less than the number of corresponding pixels. For example, the number of pixels corresponding to gate lines G4a and G4b arranged in the first area may be less than the number of pixels corresponding to gate line G6 arranged in the second area. Therefore, a difference in R-C load (Resistor-Capacitor load) may occur depending on the difference in the number of pixels, resulting in a problem of luminance non-uniformity. And, the display quality deteriorates accordingly.

In the present invention, in order to solve this problem, as shown in FIG. 3, at least one first light is added in the third area of the bezel area BA where pixels are not formed to compensate for the luminance non-uniformity between the first area and the second area. By arranging the to third load compensators (DCA1, DCA2, and DCA3), the problem of brightness unevenness is solved.

In FIG. 3 , in order to avoid complicating the drawings and description, known components unrelated to the technical features of the present invention, for example, the configuration of the second power lines VS1 to VSn, are omitted. In addition, in FIG. 3, the first area is shown to include first and second sub-active areas divided into left and right by a notch NO, but the present invention is not limited thereto. For example, a plurality of notches NO may be arranged on either the left or right side of the active area AA, or in the center. Therefore, the example in FIG. 3 should not be interpreted as reducing the scope of protection of the present invention.

Referring to FIG. 3, the display panel 10 according to an embodiment of the present invention includes an active area (AA) and a bezel area (BA).

In FIG. 3 , to simplify the explanation, four gate lines constituting the pixel array are aligned in the first area of the active area AA of FIG. 2 along the first power line direction (for example, the arrangement direction of VD1). This will be explained using an example of a case where it is arranged in a similar manner.

Each of the pixels in the active area (AA) corresponding to the first and second areas is considered to have the same size.

The two first and second gate lines disposed on the upper side of the first area are 1a and 2a gate lines (G1a, G2a) that sequentially receive the first and second gate pulses from the left shift register (SRa). , 1b and 2b gate lines (G1b, G2b) that sequentially receive the first and second gate pulses from the right shift register (SRb).

The 1st and 2a gate lines (G1a, G2a) disposed in the first sub-active area of the active area divided by the left side of the first area (i.e., the notch portion (NO)) extend from the first sub-active area to the bezel area. It may extend to the first compensation area of the third area of (BA). The 1a and 2a gate lines (G1a, G2a) are connected to the 1a dummy gate line (GD1a) and the 2a dummy gate line (GD2a) formed on different layers in the first compensation part (DCA1) of the bezel area (BA). can be connected The 1a gate line G1a and the 1a dummy gate line GD1a, and the 2a gate line G2a and the 2a dummy gate line GD2a may be connected to form an “inverted C” shape.

The 1b and 2b gate lines (G1b, G2b) disposed on the right side of the first area (i.e., the second sub-active area of the active area divided by the notch (NO)) extend from the bezel from the second sub-active area. It may extend to the second compensation area of the third area of the area BA. The 1b and 2b gate lines (G1b, G2b) are connected to the 1b dummy gate line (GD1b) and the 2b dummy gate line (GD2b) formed on different layers in the second compensation part (DCA2) in the bezel area (BA). can be connected The 1b gate line G1b and the 1b dummy gate line GD1b, and the 2b gate line G2b and the 2b dummy gate line GD2b may be connected to form a “ㄷ” shape.

The display panel 10 includes a first compensation unit formed by overlapping 1a and 2a dummy gate lines (GD1a, GD2a) disposed in the first compensation area of the bezel area (BA) with the first power supply electrode (VDLb). (DCA1) and the 1b and 2b dummy gate lines (GD1b, GD2b) disposed in the second compensation area of the bezel area (BA) overlap the first power supply electrode (VDLb), thereby forming a second compensation unit ( Includes DCA2).

Meanwhile, the gate lines disposed on the lower side of the first region are the 3a and 4th gate lines that sequentially receive the third and fourth gate pulses from the left shift register SRa, similar to the gate lines disposed on the upper side of the first region. It includes 4a gate lines (G3a, G4a) and 3b and 4b gate lines (G3b, G4b) that sequentially receive the 3rd and 4th gate pulses from the right shift register (SRb).

The gate lines disposed on the lower side of the first region, the left 3a and 4a gate lines (G3a and G4a) and the right 3b and 4b gate lines (G3b and G4b), are the left gate lines divided by the notch NO. They are connected to each other by third and fourth dummy gate lines GD3 and GD4 disposed in the third compensation area of the third area of the bezel area BA between the first sub-active area and the second sub-active area on the right.

The display panel 10 includes a third compensation unit formed by overlapping the first power supply electrode VDLb with the third and fourth dummy gate lines GD3 and GD4 disposed close to the horizontal line of the notch NO. (DCA3) may be included.

The first compensation unit (DCA1) and the second compensation unit (DCA2) of the display panel 10 will be described in more detail with reference to FIGS. 5 and 6, and the third compensation unit (DCA3) will be described in FIGS. 7 and 8. It will be described in more detail with reference to .

Since the first compensation unit (DCA1) and the second compensation unit (DCA2) are different only in the positions where they are formed, their actual structures are the same, so in the following description with reference to FIGS. 5 and 6, the first compensation unit (DCA1) is represented. By explaining this, we will also include an explanation of the second compensation unit (DCA2).

Before explaining the first to third compensation units DCA1, DCA2, and DCA3, the cross-sectional structure of the pixel P constituting the pixel array in the active area will be described with reference to FIG. 4.

FIG. 4 is a cross-sectional view showing the structures of a thin film transistor (TFT), a storage capacitor (Cst), and a light emitting diode (LED) in the pixel P shown in FIG. 1.

Referring to FIG. 4, a buffer layer (BUF) of a single-layer or multi-layer structure may be disposed on the substrate (SUB). The substrate (SUB) can be formed of a flexible translucent material. When the substrate (SUB) is formed of a material such as polyimide, the buffer layer (BUF) protects against impurities such as alkali ions leaking from the substrate (SUB) in the subsequent process. In order to prevent damage to the light emitting device, it may be formed as a single layer composed of either an inorganic material or an organic material. Additionally, the buffer layer (BUF) may be formed of multiple layers made of different inorganic materials. Additionally, the buffer layer (BUF) may be formed as a multi-layer formed of an organic material layer and an inorganic material layer. The inorganic material layer may include either a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The organic material may include photo acrylic.

A semiconductor layer (A) may be disposed on the buffer layer (BUF). The semiconductor layer (A) may include a source area (SA) and a drain area (DA) spaced apart from each other with a channel area (CA) in between. The source area (SA) and drain area (DA) may be conductive areas. The semiconductor layer (A) may be formed using amorphous silicon or polycrystalline silicon obtained by crystallizing amorphous silicon. In contrast, the semiconductor layer (A) may be made of any one of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), or zinc tin oxide (ZnSnO). Additionally, the semiconductor layer (A) may be made of a low-molecular-weight or high-molecular-weight organic material such as melocyanine, phthalocyanine, pentacene, or thiophene polymer.

A gate insulating film (GI) is disposed on the buffer layer (BUF) on which the semiconductor layer (A) is disposed to cover the semiconductor layer (A). The gate insulating film (GI) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the gate insulating film (GI) may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

On the gate insulating film (GI), there is a gate electrode (GE) of the thin film transistor (TFT) such that at least a portion of the area overlaps with the channel layer (CA) of the semiconductor layer (A), and a gate line (not shown) connected to the gate electrode (GE) ) can be placed. The first electrode C1 of the storage capacitor Cst may be disposed on the gate insulating layer GI. The gate electrode (GE) and gate line, and the first electrode (C1) are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). ) may be any one selected from the group consisting of, or an alloy thereof, and may be composed of a single layer or multiple layers.

A first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI on which the gate electrode GE, the gate line, and the first electrode C1 of the storage capacitor Cst are disposed to cover them. The first interlayer insulating film INT1 may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the gate insulating layer GI may be formed of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx).

The second electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer INT1 to overlap the first electrode C1. The second electrode (C2) is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be an alloy thereof, and may be made of a single layer or multiple layers.

Additionally, the second interlayer insulating film INT2 may be disposed to cover the second electrode C2 of the storage capacitor Cst. The second interlayer insulating film INT2 may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the second interlayer insulating film INT2 may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

The source electrode (SE) and drain electrode (DE) of the thin film transistor (TFT) may be disposed on the second interlayer insulating film INT2. A third electrode C3 may also be disposed on the second interlayer insulating film INT2 to overlap the second electrode C2 of the storage capacitor Cst. The source electrode (SE) and drain electrode (DE) are connected to the source area (SA) of the semiconductor layer exposed through contact holes penetrating the gate insulating film (GI), the first and second interlayer insulating films (INT1, INT2), and the drain. Each can be connected to the area (DA). The third electrode C3 of the storage capacitor Cst may be connected to the exposed second electrode C2 through the contact hole of the second interlayer insulating layer INT2. The source electrode (SE), the drain electrode (DE), and the third electrode (C3) of the storage capacitor (Cst) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), and titanium (Ti). It may be any one selected from the group consisting of nickel (Ni) and copper (Cu), or an alloy thereof, and may be made of a single layer or multiple layers.

A passivation film (PAS) may be disposed to cover the source electrode (SE), the drain electrode (DE), and the third electrode (C3) of the storage capacitor (Cst). The passivation film (PAS) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the passivation film (PAS) may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

Additionally, a first planarization layer (PLN1) may be disposed on the passivation layer (PAS). The first planarization film (PLN1) is intended to protect the lower structure while alleviating steps in the lower structure, and may be formed of an organic material layer. For example, the first planarization film (PLN1) may be formed as a photo acrylic layer. A connection electrode (CON) may be disposed on the first planarization layer (PLN1) to connect the anode electrode (ANO) of the light emitting diode (LED), which will be described later, to the drain electrode (DE). Additionally, a fourth electrode C4 connected to the third electrode C3 of the storage capacitor Cst may be disposed on the first planarization film PL1. The connection electrode (CON) is connected to the drain electrode (DE) of the thin film transistor (TFT) exposed through the contact hole of the first planarization film (PLN1) and the passivation film (PAS), and the fourth electrode of the storage capacitor (Cst). The electrode C4 may be connected to the fourth electrode C4 of the storage capacitor Cst exposed through the contact hole of the first planarization film PLN1 and the passivation film PAS. The connection electrode (CON) and the fourth electrode (C4) of the storage capacitor (Cst) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper. It may be any one selected from the group consisting of (Cu), or an alloy thereof, and may be made of a single layer or multiple layers.

A second planarization film (PLN2) may be disposed on the first planarization film (PLN1) to cover the connection electrode (CON) and the fourth electrode (C4) of the storage capacitor (Cst). The second planarization film (PLN2) may be a planarization layer that further protects the lower structure while further alleviating the step of the lower structure caused by the connection electrode (CON) on the first planarization film (PL) and the fourth electrode (C4) of the storage capacitor. there is. The second planarization film (PLN2) may be formed of an organic material layer. For example, the second planarization layer (PLN2) may be made of a siloxane-based organic material.

An anode electrode (ANO) may be disposed on the second planarization film (PLN2). The anode electrode (ANO) is connected to the exposed connection electrode (CN) through a contact hole penetrating the second planarization film (PLN2). The anode electrode (ANO) may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

A bank layer (BN) having an opening (OL) exposing the anode electrode (AN) may be formed on the second planarization film (PLN2).

The opening of the bank layer (BN) may be an area that defines the light emitting area (LA). A light-emitting laminate (LES) and a cathode electrode (CAT) are sequentially disposed on the anode electrode (ANO) exposed through the light-emitting area of the bank layer (BL). The light emitting layer (LES) may include a hole layer, a light emitting layer, and an electron layer. The cathode electrode (CAT) may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof with a low work function. In the present invention, it has been explained that the light-emitting laminate (LES) is disposed on the anode electrode (ANO), and the cathode electrode (CAT) is disposed on the light-emitting laminate (LES). However, the light-emitting laminate is placed on the cathode electrode (CAT). Water (LES) may be disposed, and an anode electrode (ANO) may be disposed on the light emitting laminate (LES).

An encapsulation layer (ENC) may be disposed on the second planarization layer (PLN2) to cover the cathode electrode (CA) and the bank layer (BL). The encapsulation layer (ENC) is intended to prevent external moisture or oxygen from penetrating into the light-emitting laminate (LES) located inside the encapsulation layer (ENC), and can be formed in a multi-layer structure in which inorganic and organic layers are alternately arranged. .

Next, the first compensation unit DCA1 and the second compensation unit DCA2 of the display panel 10 will be described in more detail with reference to FIGS. 3, 5, and 6. FIG. 5 is an enlarged plan view of a portion of the first compensation unit DCA1 of FIG. 3, and FIG. 6 is a cross-sectional view taken along lines A-A' and B-B' of FIG. 4.

5 and 6, the first compensation unit DCA1 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a semiconductor layer ACT disposed on the buffer layer BUF. Includes. The semiconductor layer (ACT) of the first compensation unit (DCA1) may be formed through the same process as the semiconductor layer (A) of the thin film transistor (TFT). It can be formed on the same layer. Additionally, the semiconductor layer (ACT) of the first compensation unit (DCA1) may be formed of the same material as the semiconductor layer (A) of the thin film transistor (TFT). The semiconductor layer (ACT) of the first compensation unit (DCA1) may be a conductive layer made of a semiconductor material. The conductorization of the semiconductor layer (ACT) of the first compensation portion (DCA1) is formed by conducting the source region (SA) and drain region (SA) of the semiconductor layer (A) of the thin film transistor (TFT) together. You can. The semiconductor layer ACT of the first compensation unit DCA1 includes a plurality of semiconductor layers (eg, ACT1 to ACT3). A gate insulating film (GI) may be disposed on the buffer layer (BUF) to cover the semiconductor layer (ACT).

Referring to Figures 5 and 7, the 2a gate line (G2a) and the 1a gate line (G1a) may be arranged parallel to each other on the gate insulating film (GI).

Additionally, a first interlayer insulating layer INT1 may be disposed on the gate insulating layer GI to cover the 1a gate line G2a and the 1b gate line G1a. On the first interlayer insulating film INT1, a 2a dummy gate line GD2a and a 1a dummy gate line GD1a are arranged side by side so as to overlap at least a portion of the 2a gate line G2a and the 1a gate line G1a. can be placed. The 2a dummy gate line (GD2a) is connected to the 2a gate line (G2a) through the second contact hole (CH2) penetrating the first interlayer insulating film (INT1), and the 1a dummy gate line (GD1a) is connected to the first interlayer insulating film (INT1). It may be connected to the 1a gate line (G1a) through the first contact hole (CH2) penetrating the interlayer insulating film (INT1).

Referring to FIGS. 5 and 6 , the 1a dummy gate line GD1a and the 2a dummy gate line GD1b are arranged to overlap a plurality of semiconductor layers (eg, ACT1, ACT2, and ACT3). To compensate for the capacitance value generated according to the difference between the number of pixels in the first area of the active area (AA) having the irregularity and the number of pixels in the second area of the active area (AA) without the irregularity, a plurality of The overlapping areas of the semiconductor layers (ACT1, ACT2, and ACT3) and the 1a dummy gate line (GD1a) and the 2a dummy gate line (GD1b) may be formed differently. For example, the area overlapping the semiconductor layer ACT with the 1st a dummy gate line GD1a and the 2a dummy gate line GD1b can be formed differently by using the number or size of the semiconductor layer ACT. . Alternatively, the width or length of at least one of the 1a dummy gate line (GD1a) and the 2a dummy gate line (GD1b) is adjusted to adjust the semiconductor layer ACT, the 1a dummy gate line (GD1a), and the 2a dummy gate line. The overlapping area of (GD1b) can be formed differently. Specifically, in Figure 5, the 1a dummy gate line (GD1a) and the 2a dummy gate line (GD1b) are shown as straight lines, but they may also be formed in a curved, concave-convex shape. In this way, when the 1a dummy gate line (GD1a) and the 2a dummy gate line (GD1b) are formed in a concavo-convex shape, their length is equal to that of the 1a dummy gate line (GD1a) and the 1st dummy gate line (GD1a) formed straight as shown in FIG. It can be longer than the length of the 2a dummy gate line (GD1b). Accordingly, the overlapping area between the semiconductor layer ACT and the 1a dummy gate line GD1a and the 2a dummy gate line GD1b may increase. And, the capacitance value for compensation can be increased.

A second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer ILD1 to cover the 1a dummy gate line GD1a and the 2a dummy gate line GD2a.

A first power supply electrode VDLb that overlaps the 2a dummy gate line GD2a and the 1a dummy gate line GD1a may be disposed on the second interlayer insulating layer INT2. The first power supply electrode (VDLb) is connected to the semiconductor layer through the third and fourth contact holes (CH3, CH4) penetrating the second interlayer insulating film (INT2), the first interlayer insulating film (INT1), and the gate insulating film (GI). (ACT) can be accessed.

A passivation film (PAS) may be disposed on the first power supply electrode (VDLb) to protect the first power supply electrode (VDLb).

*At least one layer among the first planarization film (PLN1), the second planarization film (PLN2), and the encapsulation layer (ENC) may be formed on the passivation film (PAS).

The second compensation unit DCA2 is also formed similarly to the first compensation unit DCA1 and is formed in the same manner as the first compensation unit DCA1. Therefore, further explanation is omitted.

Next, the third compensation unit DCA3 of the display panel 10 will be described in more detail with reference to FIGS. 3, 7, and 8.

FIG. 7 is an enlarged plan view of a portion of the third compensation unit 3CA1 of FIG. 3, and FIG. 8 is a cross-sectional view taken along lines A-A' and B-B' of FIG. 7.

Referring to FIGS. 7 and 8 , the third compensation unit DCA3 of the display panel 10 includes a buffer layer BUF disposed on the substrate SUB and a plurality of semiconductor layers (e.g., For example, it may include ACT5, ACT6). The semiconductor layer (ACT) of the third compensation unit (DCA1) may be formed through the same process as the semiconductor layer (A) of the thin film transistor (TFT). It can be formed on the same layer. Additionally, the semiconductor layer (ACT) of the third compensation unit (DCA1) may be formed of the same material as the semiconductor layer (A) of the thin film transistor (TFT). The semiconductor layer ACT of the third compensation unit DCA1 may be a layer made of a conductive semiconductor material. The conductorization of the semiconductor layer (ACT) of the third compensation portion (DCA1) is formed by conducting the source region (SA) and drain region (SA) of the semiconductor layer (A) of the thin film transistor (TFT) together. A gate insulating layer GI may be disposed on the buffer layer BUF to cover the semiconductor layers ACT5 and ACT6.

Referring to FIGS. 7 and 8 , the 3a gate line G3a and the 3b gate line G3b may be separated from each other on the same line on the gate insulating film GI. Also, the 4a-th gate line (G4a) and the 4b-th gate line (G4b) may be arranged to be separated from each other. The 3a gate line G3a and the 4a gate line G3a may be arranged parallel to each other. Additionally, the 3b gate line G3b and the 4b gate line G3b may be arranged parallel to each other.

A first interlayer insulating film INT1 will be disposed on the gate insulating film GI to cover the 3a gate line G3a and 3b gate line G3b, and the 4a gate line G4a and 4b gate line G4b. You can. A third dummy gate line (GD3) is disposed on the first interlayer insulating film (INT1) to overlap one end of the 3a gate line (G3a) and one end of the 3b gate line (G3b), and the 4a gate line (G4a) ) and one end of the 4th gate line (G4b) may be disposed to overlap the fourth dummy gate line (GD4).

The third dummy gate line GD3 may be connected to the 3a and 3b gate lines G3a and G3b, respectively, through the fifth contact holes CH5 penetrating the first interlayer insulating film INT1. The fourth dummy gate line GD4 may be connected to the 4a and 4b gate lines G4a and G4b, respectively, through the sixth contact holes CH6 penetrating the first interlayer insulating film INT1.

Referring to FIG. 8 , a second interlayer insulating layer INT2 may be disposed on the first interlayer insulating layer INT1 to cover the third dummy gate line GD3 and the fourth dummy gate line GD4.

A first power supply electrode VDLb may be disposed on the second interlayer insulating layer INT2 and overlaps the third dummy gate line GD3 and the fourth dummy gate line GD4. The first power supply electrode (VDLb) penetrates the second interlayer insulating film (INT2), the first interlayer insulating film (INT1), and the gate insulating film (GI) to expose the semiconductor layers (ACT5, ACT6). They are respectively connected to the semiconductor layers (ACT5 and ACT6) through the holes (CH7 and CH8).

A passivation film (PAS) is disposed on the first power supply electrode (VDLb) to protect the first power supply electrode (VDLb).

As shown in FIGS. 5 and 6, the first compensation unit (DCA1) according to the above-described configuration has a first capacitance formed by each dummy gate line (GD1a or GD2a) and the first power supply electrode (VDLb). Includes a first compensation component of C1 and a second compensation component of second capacitances C2 formed by each dummy gate line (GD1a or GD2a) and a plurality of semiconductor layers (ACT1, ACT2, ACT2). do.

In addition, like the first compensation unit DCA1, the second compensation unit DCA2 compensates for the first capacitances C1 formed by each dummy gate line (GD1b or GD2b) and the first power supply electrode (VDLb). It includes a first compensation component and a second compensation component of the second capacitances C2 formed by each dummy gate line (GD1b or GD2b) and a plurality of semiconductor layers.

As shown in FIGS. 7 and 8, the third compensation unit (DCA3) compensates for the first capacitances (C1) formed by each dummy gate line (GD3 or GD4) and the first power supply electrode (VDLb). It includes a first compensation component and a second compensation component of the second capacitances C2 formed by each dummy gate line (GD3 or GD4) and a plurality of semiconductor layers (ACT5, ACT6, and ACT7).

Therefore, in the present invention, the capacitance is maximized in a narrow space through the first compensation unit (DCA1) and the second compensation unit (DCA2) having a double capacitor structure of the first capacitance (C1) and the second capacitance (C2). can do. Since the third compensating part DCA3 also has a double capacitor structure like the first compensating part DCA1, the capacitance can be maximized in the narrow space in the area adjacent to the horizontal part of the notch part NO. Therefore, it is possible to increase the R-C load per pixel line through the first compensation unit (DCA1), the second compensation unit (DCA2), and the third compensation unit (DAC3) located in the third area of the bezel area, so that the active area Compensation can be made to approximate the R-C load per pixel line disposed in the second area of (AA), thereby improving the luminance unevenness of the display panel.

Next, the luminance improvement effect obtained by the display device according to an embodiment of the present invention will be described with reference to FIG. 9.

Figure 9 is a graph showing the luminance change of a display device without a compensation unit and the luminance change of a display device with a compensation unit according to an embodiment of the present invention. In FIG. 9 , the solid line represents the luminance change of the display device without the compensation portion, and the dotted line represents the luminance change of the display device with the compensation portion according to an embodiment of the present invention. In Figure 9, the standard luminance of the display device is set to 150 nit.

In FIG. 9, the horizontal axis represents the gate lines (1st to 30th lines) corresponding to the b-c section of the first region of the display device shown in FIG. 2, and the gate lines (30th to 90th lines) corresponding to the c-d section of the first region of the display device shown in FIG. 2. line), and a gate line (90th-120th line) corresponding to the d-e section of the second area. And, the vertical axis represents the change in luminance of the display device. On the vertical axis, 0% indicates that there is no change in the luminance of the display device compared to the standard luminance of 150 nits.

Referring to FIG. 9, looking at the solid line showing the change in luminance of the display device in which the compensation part is not formed, there is no change in luminance in the section d-e of the second area, which is the active area without the unusual part, but the active areas b-c and It can be seen that there is a change in luminance in the c-d section. It can be seen that the change in luminance compared to the standard luminance is approximately 6% to 18%.

In FIG. 9, looking at the dotted line showing the change in luminance of the display device with the compensation unit according to the embodiment of the present invention, not only the d-e section of the second area, which is an active area without a special feature, but also the b-c and c-d active areas with a feature feature. It can be seen that there is no change in luminance even in the section. From the graph above, the first compensation part (DCA1), the second compensation part (DCA2), and the third compensation part (DAC3) located in the bezel area (BA) of the active area (AA) including the irregularity part It can be seen that by increasing the R-C load of the gate line located in the region, compensation can be made to be close to the R-C load of each gate line located in the second region of the active area (AA) that does not include the anomaly.

The R-C load for each gate line can be increased through the first compensation unit (DCA1) and second compensation unit (DCA2) located in the first area (A1) and the third compensation unit (DAC3) located in the second area (A2). Therefore, compensation can be made to approximate the R-C load for each gate line of the third area A3, thereby improving the luminance unevenness of the display panel.

The display device according to the present specification can be described as follows.

A display device according to a first aspect of the present specification includes: a display panel including an active area including a first area with a special shape and a second area without a special shape, and a bezel area outside the active area; Gate lines and data lines arranged to cross each other within the active area; pixels connected to the gate lines and the data lines within the active area; a first power supply electrode that supplies power to the pixels; and a dummy gate line disposed in the bezel area adjacent to the first region of the active area, wherein the dummy gate line is connected to the gate line disposed in the first region and overlaps the first power supply electrode. Thus, a first capacitance is formed.

In the above configuration, it may further include a semiconductor pattern connected to the first power supply electrode and overlapping the dummy gate line to form a second capacitance.

The special part of the first area may include at least one of a round part formed at a corner and a notch part formed on one side of the active area.

The active area of the first area where the notch is formed includes first and second sub-active areas divided into left and right sides by the notch, and first and second gate lines are disposed in the first sub-active area. And, third and fourth gate lines may be disposed in the second sub-active area.

The dummy gate line may include: a first dummy gate line disposed in the bezel area adjacent to the first sub-active area; and a second dummy gate line disposed in the bezel area adjacent to the second sub-active area, wherein the first dummy gate line is connected to the first gate line of the first sub-active area and the second dummy gate line. A gate line may be connected to the third gate line of the second sub-active region.

The dummy gate line further includes a third dummy gate line disposed in the bezel area between the first sub-active area and the second sub-active area,

The second gate line disposed in the first sub-active region and the fourth gate line disposed in the second sub-active region may be connected to each other by the third dummy gate line.

The first capacitance is a first compensation capacitance formed by overlapping the first dummy gate line and the first power supply electrode, and a second compensation capacitance formed by overlapping the second dummy gate line and the first power supply electrode. may include.

The semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern, and the second capacitance includes a fourth compensation capacitance formed by overlapping the first dummy gate line and the first semiconductor pattern, and the second dummy gate. It may include a fifth compensation capacitance formed by overlapping the line and the second semiconductor pattern.

The first and second semiconductor patterns may be connected to the first power supply electrode.

The first capacitance may further include a third compensation capacitance formed by overlapping the third dummy gate line and the first power supply electrode.

The semiconductor pattern may further include a third semiconductor pattern, and the second capacitance may include a sixth compensation capacitance formed by overlapping the third dummy gate line and the third semiconductor pattern.

The third semiconductor pattern may be connected to the first power supply electrode.

The semiconductor pattern is disposed on a substrate, the gate lines are disposed on a gate insulating layer disposed to cover the semiconductor pattern, and the data lines and the dummy gate line are disposed on a first interlayer insulating layer covering the gate lines. and the first power supply electrode may be disposed on the second interlayer insulating film covering the dummy gate line.

The dummy gate line is connected to the gate line through a contact hole formed in the first interlayer insulating film, and the first power supply electrode is a contact penetrating the second interlayer insulating film, the first interlayer insulating film, and the gate insulating film. It can be connected to the semiconductor pattern through a hole.

*The first to third semiconductor patterns are disposed on a substrate, the gate lines are disposed on a gate insulating film disposed to cover the first to third semiconductor patterns, the data lines and the first The first to third dummy gate lines are disposed on a first interlayer insulating film covering the gate lines, and the first power supply electrode is disposed on a second interlayer insulating film covering the first to third dummy gate lines. The first dummy gate line is connected to the first gate line through a first contact hole formed in the first interlayer insulating film, and the second dummy gate line is connected to the first gate line through a second contact hole formed in the first interlayer insulating film. Connected to a third gate line, the third dummy gate line is connected to the second gate line through a third contact hole formed in the first interlayer insulating film, and the fourth dummy gate line is connected to the fourth gate line through a fourth contact hole formed in the first interlayer insulating film. It is connected to a gate line, connecting the second gate line and the fourth gate line to each other, and the first power supply electrode is a contact hole penetrating the second interlayer insulating film, the first interlayer insulating film, and the gate insulating film. It may be connected to the first to third semiconductor patterns through .

The display device according to the second feature of the present specification includes an active area including a first area with a special shape and a second area without a special shape, a third area corresponding to the first area, and a third area corresponding to the second area. a display panel including a fourth area and a bezel area disposed outside the active area; first pixels formed corresponding to a first gate line disposed in the first area; second pixels formed to correspond to a second gate line disposed in the second area and having a larger number of pixels than the first pixels; and a power supply electrode disposed in the bezel area of the display panel and supplying power to the first pixels and the second pixels, wherein the third area of the bezel area 1 and at least one compensation unit connected to a gate line or the power supply electrode to form a compensation capacitance to compensate for a load generated according to a difference in the number of pixels between the first pixels and the second pixels.

At least one compensation unit may further include a semiconductor pattern forming the first power supply electrode and a second capacitance.

The first compensation pattern is located between the power supply electrode and the second compensation pattern, forming the first compensation capacitance with the power supply electrode and the second compensation capacitance with the second compensation pattern. You can.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present specification. In the example shown in the present invention, an electroluminescent display device is used as an example, but the present invention is not limited thereto, and includes a liquid crystal display device (LCD), a plasma display panel (PDP), and an electroluminescent display device. It can be applied to various flat panel displays such as field emission display devices (FED) and electrophoretic display devices (ED). Therefore, the technical scope of the present specification is not limited to the content described in the detailed description of the specification, but should be determined by the scope of the patent claims.

10: Display panel A1: 1st area
A2: Second area A3: Third area
AA: active area ACT: metallization semiconductor layer
BA: Bezel area D1~Dm: Data line
GD1a, GD1b, GD2a, GD2b, GD3, GD4: Dummy gate lines
G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b, G5... Gn: Gate line
DCA1: First compensation section DCA2: Second compensation section
DCA3: Third compensation section PS: Power supply section
VD1~VDm: 1st power line
VDLa, VDLb: first power supply electrode

Claims (18)

A display panel including a first area in which a plurality of pixels are arranged and a second area in which no pixels are arranged between the first areas;
a plurality of gate lines connected to the plurality of pixels in the first area and arranged symmetrically with respect to the second area; and
It includes a first gate driving circuit disposed on one side of the first area and a second gate driving circuit disposed on the other side,
A display device wherein at least one of the plurality of gate lines has one side connected to the first gate driving circuit and the other side not connected to the second gate driving circuit. The display panel of claim 1, wherein:
A display device having a curved surface with round corners. The display panel of claim 1, wherein:
A substrate on which a plurality of transistors are disposed;
the first gate driving circuit and the second gate driving circuit respectively disposed on both sides of the first area;
a data driver that supplies data signals to the plurality of transistors;
A power supply line disposed between the first area and the data driver,
Each of the plurality of transistors,
a semiconductor pattern disposed on the substrate;
a gate insulating film covering the semiconductor pattern;
a first electrode disposed on the gate insulating film;
a first interlayer insulating film covering the first electrode;
a second electrode disposed on the first interlayer insulating film;
a source electrode and a drain electrode formed on the second electrode;
a first planarization film covering the source electrode and the drain electrode;
a connection electrode disposed on the first planarization film; and
It includes a second planarization film covering the connection electrode,
The power supply line is,
a second link power supply line; and
It includes a first link power supply line formed parallel to either the gate driver or the second link power supply line,
The first link power supply line is connected to the power supply electrode. According to paragraph 3,
The display device further includes a second interlayer insulating film that covers the second electrode and is formed of multiple layers. According to paragraph 3,
The display device further includes a data line connected to the data driver and at least partially overlapping the power supply electrode. According to paragraph 3,
The first link power supply line is connected to the power supply electrode. According to paragraph 3,
The first link power supply line is disposed between the first and second gate driving circuits and the second link power supply line. The method of claim 3, wherein the plurality of transistors are:
A display device comprising at least one oxide thin film transistor. According to paragraph 3,
A display device, wherein the substrate is formed of a flexible translucent material. A display panel including a first area in which a plurality of pixels are arranged, a second area in which no pixels are arranged between the first areas, and a bezel area arranged outside the first area;
at least one gate line connected to the plurality of pixels in the first area and disposed along a boundary of the second area;
A display device comprising a dummy gate line disposed in the bezel area, one side of which is connected to the gate driving circuit, and the other side of which is not connected to the plurality of pixels. The display panel of claim 10, wherein:
A display device having a curved surface with round corners. The display panel of claim 10, wherein:
A substrate on which a plurality of transistors are disposed;
the first gate driving circuit and the second gate driving circuit respectively disposed on both sides of the first area;
a data driver that supplies data signals to the plurality of transistors;
A power supply line disposed between the first area and the data driver,
Each of the plurality of transistors,
a semiconductor pattern disposed on the substrate;
a gate insulating film covering the semiconductor pattern;
a first electrode disposed on the gate insulating film;
a first interlayer insulating film covering the first electrode;
a second electrode disposed on the first interlayer insulating film;
a source electrode and a drain electrode formed on the second electrode;
a first planarization film covering the source electrode and the drain electrode;
a connection electrode disposed on the first planarization film; and
It includes a second planarization film covering the connection electrode,
The power supply line is,
a second link power supply line; and
It includes a first link power supply line formed parallel to either the gate driver or the second link power supply line,
The first link power supply line is connected to the power supply electrode. According to clause 12,
The display device further includes a second interlayer insulating film that covers the second electrode and is formed of multiple layers. According to clause 12,
The display device further includes a data line connected to the data driver and at least partially overlapping the power supply electrode. According to clause 12,
The first link power supply line is connected to the power supply electrode. According to clause 12,
The first link power supply line is disposed between the first and second gate driving circuits and the second link power supply line. The method of claim 12, wherein the plurality of transistors are:
A display device comprising at least one oxide thin film transistor. According to clause 12,
A display device, wherein the substrate is formed of a flexible translucent material.