KR102649412B1 - Thin film transistor array substrate and electronic device including the same - Google Patents

Abstract

Embodiments of the present invention relate to a thin film transistor array substrate and an electronic device including the same, and more specifically, to a first active layer of a first transistor including a first channel region, and a thin film transistor array substrate disposed on the first active layer. A first gate electrode of the first transistor disposed on the first gate insulating film and overlapping the first channel region, and a second transistor disposed on the interlayer insulating film disposed on the first gate electrode and including a second channel region. A second active layer, a second gate insulating film disposed on a portion of the upper surface of the second active layer and a portion of the upper surface of the interlayer insulating film, and disposed on the second gate insulating film, overlap the second channel region, and contact the first active layer. By including a second gate electrode of the second transistor, a thin film transistor array substrate capable of reducing the number of mask processes and an electronic device including the same can be provided.

Description

Thin film transistor array substrate and electronic device including the same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ELECTRONIC DEVICE INCLUDING THE SAME}

Embodiments of the present invention relate to a thin film transistor array substrate and an electronic device including the same.

As the information society develops, the demand for various electronic devices such as display devices and lighting devices is increasing in various forms. Such an electronic device may include a panel on which data lines and gate lines are arranged, a data driver for driving the data lines, and a gate driver for driving the gate lines.

The panel, which is the core component of these electronic devices, can have numerous transistors arranged for various functions in order to operate them.

Because of this, the panel manufacturing process is bound to become complicated and difficult. Accordingly, when process convenience is pursued, problems may arise where the device performance of the transistor deteriorates.

Additionally, in order to realize the excellent characteristics of electronic devices, such as high resolution, the integration degree of transistors must be increased. However, since the size of the transistor cannot be reduced indefinitely due to issues such as processing and design, there is a need to provide a transistor with a structure that can provide an electronic device with high integration and simple processing without deteriorating the characteristics of the transistor. .

Embodiments of the present invention provide a thin film transistor array substrate having a structure that can reduce the area occupied by the transistors by stacking at least two transistors in a direction perpendicular to the substrate, and an electronic device including the same.

Embodiments of the present invention provide a thin film transistor array substrate having a structure that can facilitate the conduction process of the active layer by reducing the area where the conductive active layer area is disposed in the contact hole, and an electronic device including the same. I'm doing it.

Embodiments of the present invention have a structure in which the gate electrode of the second transistor disposed on the first transistor simultaneously serves as the source electrode or drain electrode of the first transistor, thereby eliminating at least one insulating film configuration and reducing the number of processes. The goal is to provide a thin film transistor array substrate that can reduce the cost and an electronic device including the same.

In one aspect, embodiments of the present invention include a panel including at least one first transistor and at least one second transistor and a driving circuit for driving the panel, the panel is disposed on a substrate, and the first transistor A first active layer of the first transistor including a channel region, a first gate insulating layer including a portion disposed on the first channel region of the first active layer, and disposed on the first gate insulating layer and overlapping the first channel region. a first gate electrode of the first transistor, an interlayer insulating film disposed on the first gate electrode, a second active layer of the second transistor disposed on the interlayer insulating film and including a second channel region, and a top surface of the second active layer. A second gate insulating film disposed on a portion of and a portion of the upper surface of the interlayer insulating film, and a second gate electrode of the second transistor disposed on the second gate insulating film, overlapping with the second channel region, and in contact with the first active layer. An electronic device that can be provided can be provided.

In another aspect, embodiments of the present invention include a substrate, a first active layer of a first transistor disposed on the substrate and including a first channel region, and a portion disposed on the first channel region of the first active layer. a first gate insulating film, a first gate electrode of the first transistor disposed on the first gate insulating film and overlapping the first channel region, an interlayer insulating film disposed on the first gate electrode, and a second interlayer insulating film, A second active layer of the second transistor including a channel region, a second gate insulating film disposed on a portion of the upper surface of the second active layer and a portion of the upper surface of the interlayer insulating film, and a second channel region are disposed on the second gate insulating film. A thin film transistor array substrate including a second gate electrode of a second transistor that overlaps and is in contact with the first active layer can be provided.

According to embodiments of the present invention, a thin film transistor array substrate having a structure that can reduce the area occupied by the transistors by stacking at least two transistors in a direction perpendicular to the substrate and an electronic device including the same can be provided.

In addition, according to embodiments of the present invention, a thin film transistor array substrate having a structure that can facilitate the conduction process of the active layer by reducing the area where the conductive active layer area is disposed in the contact hole, and including the same An electronic device that can be provided can be provided.

In addition, according to embodiments of the present invention, the gate electrode of the second transistor disposed on the first transistor has a structure that simultaneously serves as the source electrode or drain electrode of the first transistor, thereby eliminating at least one insulating film configuration. In addition, a thin film transistor array substrate capable of reducing the number of mask processes and an electronic device including the same can be provided.

1 is a system configuration diagram of a display device according to an embodiment of the present invention.
Figure 2 is an equivalent circuit of a subpixel of a display device according to an embodiment of the present invention.
Figure 3 is a plan view of a portion of the active area of a display panel according to an embodiment of the present invention.
Figure 4 is a cross-sectional view taken along lines AA' and BB' of Figure 3.
Figure 5 is a cross-sectional view taken along CD of Figure 3.
Figure 6 is a cross-sectional view taken along EF of Figure 3.
Figure 7 is a cross-sectional view cut along GH.
8 to 15 are diagrams briefly showing a manufacturing method for a partial area of a circuit unit according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the description of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

1 is a system configuration diagram of a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display device 100 according to the present embodiments has a plurality of data lines DL and a plurality of gate lines GL, and a plurality of data lines DL and a plurality of gate lines It may include a display panel 110 in which a plurality of subpixels (SP) connected to (GL) are arranged, and a driving circuit for driving the display panel 110.

Functionally, the driving circuit includes a data driving circuit 120 for driving a plurality of data lines DL, a gate driving circuit 130 for driving a plurality of gate lines GL, and a data driving circuit 120. ) and a controller 140 that controls the gate driving circuit 130.

In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged to cross each other. For example, multiple data lines DL may be arranged in rows or columns, and multiple gate lines GL may be arranged in columns or rows. Below, for convenience of explanation, it is assumed that the plurality of data lines DL are arranged in rows and the plurality of gate lines GL are arranged in columns.

The controller 140 supplies various control signals (DCS, GCS) necessary for the driving operation of the data driving circuit 120 and the gate driving circuit 130, and operates the data driving circuit 120 and the gate driving circuit 130. Control.

This controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120, and converts the converted image data (DATA) ) is output, and data operation is controlled at an appropriate time according to the scan.

The above-described controller 140, along with input image data, various types of signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, a clock signal (CLK), etc. Timing signals are received from an external source (e.g., host system).

The controller 140 converts the input image data input from the outside to suit the data signal format used in the data driving circuit 120 and outputs the converted image data (DATA), and also operates the data driving circuit 120 and In order to control the gate driving circuit 130, timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal are input, and various control signals are generated to generate the data driving circuit 120. ) and output to the gate driving circuit 130.

This controller 140 may be a timing controller used in typical display technology, or may be a control device that can perform other control functions, including a timing controller.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data DATA from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

The data driving circuit 120 may be implemented including at least one source-driver integrated circuit (S-DIC). Each source-driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. there is. Each source-driver integrated circuit (S-DIC) may, in some cases, further include an analog to digital converter (ADC).

Each source-driver integrated circuit (S-DIC) uses a Tape Automated Bonding (TAB) method, a Chip On Glass (COG) method, or a Chip On Panel (COP: Chip On Panel) method. It may be connected to a bonding pad of the display panel 110, may be placed directly on the display panel 110, or, depending on the case, may be integrated and placed on the display panel 110. Additionally, each source-driver integrated circuit (S-DIC) may be implemented using a chip-on-film (COF) method mounted on a source-circuit film connected to the display panel 110.

The gate driving circuit 130 sequentially drives a plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 is also called a scan driving circuit.

The gate driving circuit 130 may include a shift register, a level shifter, etc.

The gate driving circuit 130 is attached to the bonding pad of the display panel 110 using a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP: Chip On Panel) method. It may be connected or implemented as a GIP (Gate In Panel) type and placed directly on the display panel 110. In some cases, it may be integrated and placed on the display panel 110. Additionally, the gate driving circuit 130 may be implemented using a chip-on-film (COF) method in which a plurality of gate driver integrated circuits (G-DICs) are implemented and mounted on a gate-circuit film connected to the display panel 110. .

The gate driving circuit 130 sequentially supplies scan signals of on voltage or off voltage to the plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (DATA) received from the controller 140 into an analog data voltage to generate a plurality of data lines (DL). supplied by

The data driving circuit 120 may be located only on one side (e.g., upper or lower) of the display panel 110, and in some cases, both sides (e.g., upper or lower) of the display panel 110 depending on the driving method, panel design method, etc. For example, it may be located on both the upper and lower sides.

The gate driving circuit 130 may be located only on one side (e.g., left or right) of the display panel 110, and in some cases, both sides (e.g., left or right) of the display panel 110 depending on the driving method, panel design method, etc. For example, it can be located on both the left and right sides.

The plurality of gate lines (GL) disposed on the display panel 110 may include a plurality of scan lines (SCL), a plurality of sense lines (SCL), and a plurality of emission control lines (EML). The scan line (SCL), sense line (SCL), and emission control line (EML) are the gate nodes of different types of transistors (scan transistor, sense transistor, and emission control transistor) and transmit different types of gate signals (scan signal, These are wires that transmit sense signals and light emission control signals.

The display device 100 according to the present embodiments may be a self-luminous display such as an Organic Light Emitting Diode (OLED) display, a Quantum Dot display, or a Micro Light Emitting Diode (Micro LED) display.

When the display device 100 according to the present embodiments is an OLED display, each subpixel SP may include an organic light emitting diode (OLED) that emits light on its own as a light emitting device. When the display device 100 according to the present embodiments is a quantum dot display, each subpixel SP may include a light emitting element made of quantum dots, which are semiconductor crystals that emit light on their own. When the display device 100 according to the present embodiments is a micro LED display, each subpixel (SP) emits light on its own and may include a micro LED (Micro Light Emitting Diode) made of an inorganic material as a light emitting element. .

Figure 2 is an equivalent circuit of a subpixel (SP) of the display device 100 according to an embodiment of the present invention.

Referring to FIG. 2, in the display device 100 according to embodiments of the present invention, each subpixel (SP) includes a light-emitting element (ED) and a driving transistor ( DRT), a scan transistor (SCT) for transferring the data voltage (Vdata) to the driving transistor (DRT), a sense transistor (SENT) for initialization operation, an emission control transistor (EMT) for controlling emission, and a predetermined period of time. It may include a storage capacitor (Cst) for maintaining the voltage.

Since the subpixel (SP) illustrated in FIG. 2 has four transistors (DRT, SCT, SENT, EMT) and one capacitor (Cst) to drive the light emitting element (ED), 4T (Transistor) 1C It is said to have a (Capacitor) structure.

The light emitting device ED includes a first electrode E1 and a second electrode E2, and a light emitting layer EL located between the first electrode E1 and the second electrode E2. The first electrode E1 of the light emitting device ED may be an anode electrode or a cathode electrode, and the second electrode E2 may be a cathode electrode or an anode electrode. For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting device.

The second electrode E2 of the light emitting device ED may be a common electrode. In this case, the base voltage EVSS may be applied to the second electrode E2 of the light emitting device ED. Here, the base voltage (EVSS) may be, for example, a ground voltage or a voltage similar to the ground voltage.

The driving transistor DRT is a transistor for driving the light emitting device ED and includes a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DRT is a node corresponding to the gate node and may be electrically connected to the source node or drain node of the scan transistor SCT. The second node N2 of the driving transistor DRT may be electrically connected to the first electrode E1 of the light emitting device ED and may be a source node or a drain node. The third node (N3) of the driving transistor (DRT) is a node to which the driving voltage (EVDD) is applied, and can be electrically connected to a driving line (DVL) that supplies the driving voltage (EVDD), and is a drain node. Or it may be a source node. Below, for convenience of explanation, the second node N2 of the driving transistor DRT is a source node, and the third node N3 is a drain node.

The scan transistor (SCT) responds to the scan signal (SCAN) supplied from the corresponding scan line (SCL) among the plurality of scan lines (SCL), which are a type of gate line (GL), to the first node of the driving transistor (DRT). The connection between (N1) and the corresponding data line (DL) among the plurality of data lines (DL) can be controlled.

The drain node or source node of the scan transistor (SCT) may be electrically connected to the corresponding data line (DL). The source node or drain node of the scan transistor (SCT) may be electrically connected to the first node (N1) of the driving transistor (DRT). The gate node of the scan transistor (SCT) is electrically connected to the scan line (SCL), which is a type of gate line (GL), and can receive a scan signal (SCAN).

The scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage, and the data voltage (Vdata) supplied from the corresponding data line (DL) is connected to the first node (N1) of the driving transistor (DRT). ) can be delivered.

The scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage and turned off by the scan signal (SCAN) of the turn-off level voltage. Here, when the scan transistor (SCT) is n-type, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the scan transistor (SCT) is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The sense transistor (SENT) responds to the sense signal (SENSE) supplied from the corresponding sense line (SENL) among the plurality of sense lines (SENL), which are a type of gate line (GL), and transmits the first signal to the light emitting device (ED). The connection between the second node N2 of the driving transistor DRT electrically connected to the electrode E1 and the corresponding initialization voltage line IVL among the plurality of initialization voltage lines IVL can be controlled.

The drain node or source node of the sense transistor (SENT) may be electrically connected to the initialization voltage line (IVL). The source node or drain node of the sense transistor (SENT) may be electrically connected to the second node (N2) of the driving transistor (DRT) and may be electrically connected to the first electrode (E1) of the light emitting device (ED). The gate node of the sense transistor (SENT) is electrically connected to the sense line (SENL), a type of gate line (GL), and can receive a sense signal (SENSE).

The sense transistor (SENT) is turned on to apply the initialization voltage (Vini) supplied from the initialization voltage line (IVL) to the second node (N2) of the driving transistor (DRT).

The sense transistor (SENT) is turned on by the sense signal (SENSE) of the turn-on level voltage and turned off by the sense signal (SENSE) of the turn-off level voltage. Here, when the sense transistor (SENT) is n-type, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the sense transistor (SENT) is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The emission control transistor (EMT) responds to the emission control signal (EM) supplied from the corresponding emission control line (EML) among the plurality of emission control lines (EML), which are a type of gate line (GL), and operates the driving transistor (DRT). The connection between the third node N3 and the corresponding driving line DVL among the plurality of driving lines DVL can be controlled. That is, as shown in FIG. 2, the emission control transistor EMT may be electrically connected between the third node N3 of the driving transistor DRT and the driving line DVL.

The drain node or source node of the emission control transistor (EMT) may be electrically connected to the driving line (DVL). The source node or drain node of the emission control transistor (EMT) may be electrically connected to the third node (N3) of the driving transistor (DRT). The gate node of the emission control transistor (EMT) is electrically connected to the emission control line (EML), which is a type of gate line (GL), and can receive the emission control signal (EM).

Alternatively, the emission control transistor (EMT) may control the connection between the second node (N2) of the driving transistor (DRT) and the first electrode (E1) of the light emitting element (ED). That is, unlike shown in FIG. 2, the emission control transistor (EMT) may be electrically connected between the second node (N2) of the driving transistor (DRT) and the light emitting element (ED).

The emission control transistor (EMT) is turned on by the emission control signal (EM) of the turn-on level voltage and turned off by the emission control signal (EM) of the turn-off level voltage. Here, when the emission control transistor (EMT) is n-type, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the emission control transistor (EMT) is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and generates a data voltage Vdata corresponding to the image signal voltage or a voltage corresponding thereto. It can be maintained for the frame time.

The storage capacitor Cst is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT. It may be an external capacitor intentionally designed outside the transistor (DRT).

Each of the driving transistor (DRT), scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) may be an n-type transistor or a p-type transistor. The driving transistor (DRT), scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) may all be n-type transistors or p-type transistors. At least one of the driving transistor (DRT), scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) is an n-type transistor (or p-type transistor), and the others are p-type transistors (or n-type transistors). You can.

The 4T1C structure of the subpixel (SP) illustrated in FIG. 2 is only an example for explanation and may further include one or more transistors or, depending on the case, one or more capacitors. Alternatively, each of the multiple subpixels may have the same structure, or some of the multiple subpixels may have a different structure.

Figure 3 is a plan view of a portion of the active area of a display panel according to an embodiment of the present invention.

Referring to FIG. 3, a plurality of subpixels may be disposed in the active area of the display panel, and each of the plurality of subpixels may include a driver that drives an organic light emitting device (OLED).

Signal lines 312, 313, 313a, 315, 320, 321, and 321a that supply driving signals may be disposed in the driving unit. Additionally, it may include at least four transistors (T1, T2, T3, T4) electrically connected to at least one signal line.

Meanwhile, in Figure 3, the signal lines (312, 313, 313a, 315, 320, 321, and 321a) are shown as a single-layer configuration, but the present invention is not limited to this, and at least one signal line is multi-layered. It can be configured.

The plurality of data lines 312 may be arranged to extend in the first direction. A data voltage (Vdata) may be supplied to the data line 312. At least one of the plurality of data lines 312 may serve as a light blocking layer capable of blocking light incident on the display panel from the outside.

A plurality of driving lines 313 extending in the first direction may be disposed on the display panel. A driving voltage for driving the second transistor T2 may be supplied to the driving line 313. Here, the second transistor (T2) may be a driving transistor (DRT).

The display panel may include at least one driving connection line 313a that is electrically connected to the driving line 313. The driving connection line 313a may be arranged to extend in a second direction that intersects the first direction, but the present invention is not limited thereto.

The plurality of scan lines 320 may be arranged to extend in the second direction. A scan signal that turns the first transistor T1 on or off may be supplied to the scan line 320. Here, the first transistor (T1) may be a scan transistor (SCT).

The plurality of sense lines 321 may be arranged to extend in the second direction. A sense signal that turns the third transistor T3 on or off may be supplied to the sense line 321. The third transistor (T3) may be a sensing transistor (SENT).

Additionally, the display panel may include at least one sense connection line 321a electrically connected to the sense line 321. The sense connection line 321a may be arranged to extend in the second direction, but the present invention is not limited thereto.

The plurality of emission control lines 315 may be arranged to extend in the second direction. An emission control signal for driving the fourth transistor T4 may be supplied to the emission control line 315. The fourth transistor T4 may be an emission control transistor (EMT).

As shown in FIG. 3, the emission control line 315 may be disposed between the scan line 320 and the driving connection line 313a, but the present invention is not limited thereto.

As shown in FIG. 3, the driver of the display panel emits organic light according to the first transistor T1 connected to the scan line 320 and the data line 312, and the data voltage transmitted through the first transistor T1. The second transistor (T2) controls the size of the current output to the device (OLED), the third transistor (T3) to detect the characteristics of the second transistor (T2), and the timing of light emission of the second transistor (T2). It may include a fourth transistor (T4) for this purpose.

In a plane view, a storage capacitor Cst may be disposed between the gate electrode 340 of the second transistor T2 and the sense line 321. Additionally, a sense line 321 may be disposed between the storage capacitor Cst and the sense connection line 321a.

The storage capacitor Cst may be an area where conductive areas of the first active layer 310 and the second active layer 330 disposed on the first active layer 310 overlap. The first active layer 310 and the second active layer 330 may include at least one conductive region and at least one non-conductive region.

Meanwhile, as shown in FIG. 3, the first transistor T1 may include a first active layer 310 and a gate electrode 320 (hereinafter referred to as the first gate electrode) of the first transistor T1. .

Here, the first gate electrode 320 may have a configuration corresponding to the scan line 320. In other words, the scan line 320 may serve as a gate electrode of the first transistor T1. Accordingly, since the configuration for the gate electrode of the first transistor T1 does not need to be separately branched from the scan line 320, the area of the circuit part of the display panel can be reduced.

The area where the first active layer 310 and the first gate electrode 320 of the first transistor (T1) overlap may be the channel region (hereinafter referred to as the first channel region) of the first transistor (T1). . When the first transistor T1 is in the on state, charge moves through the area where the first active layer 310 and the first gate electrode 320 overlap, that is, the first channel area. You can.

The remaining area of the first active layer 310, excluding the first channel area, may be a conductive area. The conductive regions of the first active layer 310 may be spaced apart from each other with the first channel region 311 therebetween.

The connection electrode 322 may be connected to the first active layer 310 in an area where the first gate insulating layer 302 is not disposed.

A signal supplied from the data line 312 may be applied to the first active layer 310 of the first transistor T1. Specifically, the data line 312 and the scan line 320 may be electrically connected through the first contact hole (CNT1).

Also, the scan line 320 in contact with the data line 312 may contact a portion of the upper surface of the conductive area of the first active layer 310. In other words, the scan line 320 in contact with the data line 321 may contact a portion of the upper surface of the conductive area of the first active layer 310 without a separate contact hole.

In an embodiment of the present invention, at least three transistors may have a structure sharing one active layer.

For example, the second transistor T2, third transistor T3, and fourth transistor T4 may share the second active layer 330. In other words, each of the second transistor T2, third transistor T3, and fourth transistor T4 may include the second active layer 330.

The second transistor T2 may include a second active layer 330 and a gate electrode 340 (hereinafter referred to as a second gate electrode) of the second transistor T2 disposed on the second active layer 330. You can.

As shown in FIG. 3, the second gate electrode 340 may overlap a portion of the first active layer 310 and a portion of the second active layer 330.

The area where the second active layer 330 overlaps the second gate electrode 340 may be a channel area (hereinafter referred to as the second channel area) of the second transistor T2. When the second transistor (T2) is in the on state, charge is applied to the area where the second active layer 330 and the second gate electrode 340 overlap, that is, the second channel region 332. can be moved through.

As shown in FIG. 3, the second active layer 330 serves as an active layer for three transistors and may include at least three channel regions.

For example, the second active layer 330 includes the second channel region 332 of the second transistor T2, the third channel region 333 of the third transistor T3, and the third channel region 333 of the fourth transistor T4. It may include 4 channel areas 334. Each of the second to fourth channel regions 332, 333, and 334 may be spaced apart from each other.

As described above, the second channel region 332 of the second transistor T2 may be a region where the second active layer 330 overlaps the second gate electrode 340.

Additionally, the third channel region 333 of the third transistor T3 may be an area that overlaps the gate electrode 321a of the second active layer 330 and the third transistor T3. Here, the gate electrode 321a of the third transistor T3 may be an area branched from the sense line 321.

The fourth channel region 334 of the fourth transistor T4 may be an area that overlaps the gate electrode 315a of the fourth transistor T4 of the second active layer 330. Here, the gate electrode 315a of the fourth transistor T4 may be an area branched from the emission control line 315.

The remaining regions of the second active layer 330, excluding the second to fourth channel regions 332, 333, and 334, may be conductive regions.

This second active layer 330 may be connected to the driving connection line 313a in the area where the second gate insulating layer 304 is not disposed.

The second gate electrode 340 may be disposed on the same layer as the plurality of emission control lines 315 and the plurality of sense lines 321.

This second gate electrode 340 may be in contact with a portion of the upper surface of the first active layer 310 through the second contact hole (CNT2). The area of the first active layer 310 that is in contact with the second gate electrode 340 may be a conductive area. Here, the second gate electrode 340 may serve as either the source electrode or the drain electrode of the first transistor T1.

This structure will be examined in detail with reference to FIG. 4 as follows.

Figure 4 is a cross-sectional view taken along lines A-A' and B-B' of Figure 3.

The display panel according to an embodiment of the present invention may have at least one first transistor (T1) and at least one second transistor (T2) disposed in the active area.

Referring to FIG. 4, a data line 312 may be disposed on the substrate 400. The data line 312 is connected to aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti). It may include any one of metals or alloys thereof, but the present invention is not limited thereto.

In FIG. 4, the data line 312 is shown as having a single-layer structure, but the present invention is not limited to this, and the data line 312 may have a multi-layer structure.

At least one buffer layer 401 may be disposed on the data line 312.

The buffer layer 401 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present invention is not limited thereto.

In FIG. 4, the buffer layer 401 is shown as a single-layer structure, but the buffer layer 401 of the present invention may have a multi-layer structure.

When the buffer layer 401 has a multi-layer structure, layers containing at least two inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON) alternate. However, the present invention is not limited to this.

In the following description, for convenience, the buffer layer 401 will be described as having a single-layer structure.

The first active layer 310 of the first transistor T1 may be disposed on the buffer layer 401.

The first active layer 310 may be various types of semiconductor layers.

The first active layer 310 may be composed of an oxide semiconductor. The material forming the first active layer 620 is a metal oxide semiconductor, which is an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or molybdenum (Mo). ) It may be made of a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides.

For example, the first active layer 310 is made of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium- It may include at least one of zinc oxide (IGZO) and indium-zinc-tin oxide (IZTO), but the present invention is not limited thereto.

A first gate insulating layer 302 may be disposed on a portion of the upper surfaces of the first active layer 310 and the buffer layer 401.

The first gate insulating layer 302 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present invention is not limited thereto.

The first gate insulating layer 302 is formed by patterning the material of the first gate insulating layer 302 formed on the substrate 400 through a dry etching process, ultimately forming the first active layer 310 and the buffer layer 401. It may be formed on a portion of each upper surface.

During the process of dry etching the first gate insulating layer 302 material, the first active layer 310 located in an area corresponding to the area where the first gate insulating layer 302 material was patterned and removed may be made into a conductor.

In other words, the area of the first active layer 310 exposed by the first gate insulating layer 302 may be a conductive area.

The first active layer 310 of the first transistor T1 may include a first region 411 and a second region 412 that are conductive regions. The first and second regions 411 and 412 of the first active layer 310 may not overlap the first gate insulating layer 302.

Additionally, it may include a first channel area 413 provided between the first area 411 and the second area 412. Additionally, it may include a third area 414 that is spaced apart from the first channel area 413 and extends to one side of the second area 412. The first channel region 413 and the third region 414 are non-conductive regions and may be regions that overlap the first gate insulating layer 302.

Accordingly, the electrical resistance of the first and second regions 411 and 412 may be lower than that of the first channel region 413 and the third region 414.

A first gate electrode 320 and a first connection electrode 421 may be disposed on the first gate insulating film 302.

The first gate electrode 320 and the connection electrode 322 are disposed on the same layer and may include the same material.

The first gate electrode 320 and the connection electrode 322 are aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), and tantalum. It may include any one of metals such as (Ta) and titanium (Ti) or alloys thereof, but the present invention is not limited thereto.

In addition, in Figure 4, the first gate electrode 320 and the connection electrode 322 are shown as a single-layer structure, but the present invention is not limited to this, and the first gate electrode 320 and the connection electrode 322 ) may be a multi-layer structure.

The first gate electrode 320 may have a configuration that corresponds to the configuration of the scan line 320 described with reference to FIG. 3 .

The connection electrode 322 may be in contact with the data line 312 through the first contact hole (CNT1) provided in the first gate insulating film 302 and the buffer layer 401.

The connection electrode 322 may be in contact with a portion of the upper surface of the first active layer 310.

The connection electrode 322 may be in contact with one of the conductive areas of the first active layer 310. For example, as shown in FIG. 4, the connection electrode 322 may contact a portion of the upper surface of the second region 412 of the first active layer 310.

Accordingly, the signal supplied from the data line 312 may be applied to the first active layer 310 through the connection electrode 322. Specifically, the signal supplied from the data line 312 is transmitted to the connection electrode 322, and the signal transmitted to the connection electrode 412 is transmitted to the second region, which is one of the conductive regions of the first active layer 310. It can be authorized as (412).

In order for the signal supplied from the data line 312 to be applied to the second region 412 of the first active layer 310, it must be contacted with the connection electrode 322. However, a structure in which a first gate insulating film 302 is disposed on the first active layer 310, and a contact hole exposing the second region 412 of the first active layer 310 is provided in the first gate insulating film. In the case of forming a contact hole by dry etching the first gate insulating film 302, it may be difficult to conduct the second region 412.

Since the diameter of the contact hole is generally very small, the first active layer 310 disposed under the first gate insulating layer 302 through the contact hole of the first gate insulating layer 302 may not be conductive. Accordingly, a problem may occur in which the conductivity of the second region 412 of the first active layer 310 does not proceed, or an additional process is required to conduct the second region 412 of the first active layer 310. You can.

On the other hand, in the embodiment of the present invention, the first gate insulating layer 302 overlaps the first channel region 413 of the first active layer 310 and a portion of one end of the first active layer 310. region, that is, by being disposed to overlap the third region 414 of the first active layer 310, the upper surface of the second region 412 of the first active layer 310 is connected to the first gate insulating film 302. can be exposed by

Accordingly, compared to a structure in which the second region 412 of the first active layer 310 is exposed through the contact hole of the first gate insulating film 302, not only is it easier to conduct the second region 412, but it also has a larger area. Since the second area 412 can be provided, there is an effect that contact between the second area 412 and the connection electrode 322 is also easy.

Here, since the connection electrode 3220 is in contact with the data line 312 through the first contact hole (CNT1), the area where the connection electrode 322 is in contact with the data line 312 is the first contact hole (CNT1). It may be smaller than the area in contact with the second region 412 of the active layer 310.

The first gate electrode 320 of the first transistor T1 disposed on the same layer as the connection electrode 322 may overlap the first channel region 413 of the first active layer 310.

An interlayer insulating film 403 may be disposed on the connection electrode 322 and the first gate electrode 320.

The second active layer 330 of the second transistor T2 may be disposed on the interlayer insulating film 403. The second active layer 330 includes a fourth region 531, a fifth region 532 spaced apart from the fourth region 531, and a second region disposed between the fourth region 531 and the fifth region 532. It may include a channel area 332. Here, the fourth and fifth areas 531 and 532 may be conductive areas.

A partial area of the second active layer 330 may overlap with a partial area of the first active layer 310.

The conductive region of the second active layer 330 and the first conductive region 411 of the first active layer 310 may overlap each other to form a storage capacitor Cst.

A second gate insulating layer 304 may be disposed on the substrate 400 on which the second active layer 330 of the second transistor T2 is disposed.

The second gate insulating layer 304 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present invention is not limited thereto.

The second gate electrode 340 of the second transistor T2 may be disposed on the second gate insulating film 304 and the interlayer insulating film 403.

The second gate electrode 340 is made of aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium ( It may include any one of metals such as Ti) or alloys thereof, but the present invention is not limited thereto.

In FIG. 4, the second gate electrode 340 is shown as having a single-layer structure, but the present invention is not limited to this, and the second gate electrode 340 may have a multi-layer structure.

3 and 4, the second gate electrode 340 of the second transistor T2 is connected to the first electrode 340 of the first transistor T1 through the second contact hole CNT2 provided in the interlayer insulating film 403. It may be in contact with the active layer 310.

For example, as shown in FIG. 4, the second gate electrode 340 of the second transistor T2 is in contact with the first region 411 of the first active layer 310 of the first transistor T1. It can be.

Here, the second gate electrode 340 of the second transistor (T2) serves as the gate electrode of the second transistor (T2) and at the same time serves as either the source electrode or the drain electrode of the first transistor (T1). can do. Additionally, the second region 412 of the first active layer 310 may serve as the remaining one of the source electrode and the drain electrode.

The second gate electrode 340 of the second transistor T2 is disposed on the same layer as the sense line 321 and the emission control line 315 of FIG. 3 and may include the same material.

A passivation layer 405 may be disposed on the substrate 400 on which the second gate electrode 340 of the second transistor T2 is disposed.

Although not shown in the drawing, the passivation layer 405 exposes a portion of the upper surface of either the fourth region 531 or the fifth region 352 of the second active layer 330 of the second transistor T2. May include a contact hole.

For example, when the passivation layer 405 is provided with a contact hole exposing a portion of the upper surface of the fourth region 531 of the second active layer 330, the pixel electrode disposed on the passivation layer 405 may be in contact with the fourth region 531 of the second active layer 330 through a contact hole.

As described above, in the embodiment of the present invention, the region where the second active layer 330 of the second transistor T2 is conductive and the first active layer 310 of the first transistor T1 are conductive The areas can overlap to form one storage capacitor (Cst).

In addition, as the second active layer 330 of the second transistor T2 overlaps with the first active layer 310 of the first transistor T1, the first and second transistors T1 and T2 are aligned in a vertical direction. By having a multi-stage structure, the area of the circuit part of the display panel 110 can be reduced. As the area of the circuit part is reduced, the area of the light emitting part can be increased, which has the effect of implementing a display panel with high resolution.

As shown in FIG. 3, the connection electrode 322 required to apply a signal to the first active layer 310 is arranged to overlap the driving connection line 313a and the data line 312, thereby reducing the area of the circuit part. It can be reduced. Accordingly, a structure according to an embodiment of the present invention in which the first active layer 310 of the first transistor T1, which is a scan transistor, is disposed below the second active layer 320 of the second transistor T2, which is a driving transistor. Even so, the area of the storage capacitor (Cst) may not decrease.

Meanwhile, in the case of a structure in which the first active layer of the second transistor, which is a scan transistor, is disposed on the second active layer of the first transistor, which is a driving transistor, between the gate electrode of the first transistor and the first active layer of the second transistor. A single interlayer insulating film is required.

Additionally, in the above-described structure, the second transistor is disposed on the first gate electrode and requires a source electrode and a drain electrode that are electrically connected to the first active layer. In this structure, another interlayer insulating film is disposed between the source and drain electrodes of the second transistor and the first gate electrode. Therefore, two interlayer insulating films are required.

However, in an embodiment of the present invention, the first active layer 310 of the first transistor T1, which is a scan transistor, is disposed below the second active layer 330 of the second transistor T2, which is a driving transistor. Since the second gate electrode 340 of the two transistors T2 simultaneously functions as the source electrode or drain electrode of the first transistor T1, an interlayer insulating film can be disposed as shown in FIG. 4.

Meanwhile, there may be a number of contact holes in the interlayer insulating film to electrically connect different components. In the structure of the present invention with a reduced number of interlayer insulating films, the mask process for forming contact holes is reduced by reducing the number of interlayer insulating films. There is a possible effect.

In addition, in the embodiment of the present invention, the first active layer 310 and the connection electrode 322 have a structure that facilitates contact, so that the signal supplied from the data line 312 to the first active layer 310 Delivery has a beneficial effect.

The circuit part of a typical display panel may include a driving transistor and a scan transistor. In the circuit part of a typical display panel, the gate electrode of the driving transistor is in contact with the active layer of the scan transistor and may be disposed below the active layer of the scan transistor. The gate electrode of the driving transistor may be in contact with the active layer of the scan transistor through a contact hole provided in the interlayer insulating film between the gate electrode of the driving transistor and the active layer of the scan transistor.

However, in order to transmit signals from each transistor, the conductive area of the active layer of the scan transistor must be contacted with the gate electrode of the driving transistor.

A portion of the active layer of the scan transistor may be made into a conductor during a process of dry etching the gate insulating film disposed on the active layer of the scan transistor. At this time, in order to electrically connect the gate electrode of the driving transistor and the active layer of the scan transistor, the area of the active layer of the scan transistor disposed in the contact hole provided in the interlayer insulating film must also be made into a conductor, and the dry etching process of the gate insulating film is performed. When the active layer of the scan transistor disposed in the contact hole provided in the interlayer insulating film is made into a conductor, electrical connection between the scan transistor and the driving transistor may be difficult due to poor conduction.

In an embodiment of the present invention, the second gate electrode 340 of the second transistor T2, which is a driving transistor, and the first transistor T1 are placed on the first active layer 310 of the first transistor T1, which is a scan transistor. A source or drain electrode is disposed, and the second gate electrode 340 of the second transistor T2 and the source or drain electrode of the first transistor T1 including a conductive metal material are provided in the interlayer insulating film 403. It may have a structure in which contact is made through the second contact hole (CNT2).

In other words, the structure of the circuit unit according to an embodiment of the present invention may have a structure in which the active layer of the scan transistor is not disposed in the contact hole in the area connected to the driving transistor. Accordingly, since there is no need for a process to conduct the area of the active layer of the scan transistor disposed in the contact hole, it is possible to prevent the electrical characteristics of the circuit portion from being deteriorated due to non-uniform conductivity of the active layer.

The structures of the first and second transistors T1 and T2 disposed in the circuit section having this structure will be examined in detail as follows.

Figure 5 is a cross-sectional view taken along line C-D of Figure 3. Figure 6 is a cross-sectional view taken along line E-F of Figure 3. Figure 7 is a cross-sectional view taken along G-H.

In the description below, content (configuration, effects, etc.) that overlaps with the previously described embodiments may be omitted.

First, referring to FIG. 5 , a second transistor T2 may be disposed on the substrate 400.

The second transistor T2 may include a second active layer 330 and a second gate electrode 340.

A portion of the second active layer 330 of the second transistor T2 may overlap a portion of the first active layer 310 of the first transistor T1.

Specifically, a buffer layer 401 may be disposed on the substrate 400.

The first active layer 310 of the first transistor T1 shown in FIGS. 3 and 4 may be disposed on the buffer layer 401.

An interlayer insulating film 403 may be disposed on the first active layer 310 of the first transistor T1.

The second active layer 330 of the second transistor T2 may be disposed on the interlayer insulating film 403.

The second active layer 330 may be composed of an oxide semiconductor. The material forming the second active layer 330 is a metal oxide semiconductor, which is an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or zinc (Zn). ), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), and may be made of a combination of metals and their oxides.

For example, the second active layer 330 is made of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium- It may include at least one of zinc oxide (IGZO) and indium-zinc-tin oxide (IZTO), but the present invention is not limited thereto.

A second gate insulating layer 304 may be disposed on a portion of the upper surface of the second active layer 330.

The second gate insulating film 304 is formed by patterning the material of the second gate insulating film 304 formed on the substrate 400 through a dry etching process, and is finally formed on a portion of the upper surface of the second active layer 330. can be formed.

During the process of dry etching the material of the second gate insulating layer 304, the second active layer 330 located in an area corresponding to the area where the material of the second gate insulating layer 304 was patterned and removed may be made into a conductor.

In other words, the area of the second active layer 330 exposed by the second gate insulating layer 304 may be a conductive area.

The second active layer 330 of the first transistor T1 may include a fourth region 531 and a fifth region 532 that are conductive regions. The fourth and fifth regions 531 and 532 of the second active layer 330 may not overlap the second gate insulating layer 304.

Additionally, it may include a second channel region 332 provided between the fourth region 531 and the fifth region 532 of the second active layer 330. The electrical resistance of the second channel region 332 may be higher than that of the fourth and fifth regions 531 and 532.

Here, one of the fourth region 531 and the fifth region 532 of the second active layer 330 may serve as a source electrode of the second transistor T2, and the other may serve as a drain electrode.

As shown in FIG. 3, the fourth region 531 of the second active layer 330 is disposed between the fourth channel region 334 and the second channel region 332, and the second active layer 330 The fifth area 532 may be disposed between the second channel area 332 and the third channel area 333.

Meanwhile, as shown in FIG. 5, the fifth region 532, which is a conductive region of the second active layer 330, and the first region 411, which is a conductive region of the first active layer 310, are They may overlap each other with the interlayer insulating film 403 therebetween.

Here, the fifth region 532 of the second active layer 330 and the first region 411 of the first active layer 310 may form a storage capacitor (Cst).

That is, the circuit unit according to an embodiment of the present invention may be provided with a storage capacitor (Cst) without a separate conductive layer for forming the storage capacitor (Cst).

The second gate electrode 340 of the second transistor T2 may be disposed on the second gate insulating layer 304.

Although not shown in FIG. 5, as explained with reference to FIG. 4, the second gate electrode 340 extends in one direction to form the first region 411 of the first active layer 310 of the first transistor T1. can be contacted.

A passivation layer 405 may be disposed on the second gate electrode 340.

Additionally, as shown in FIG. 6, a first transistor T1 may be disposed on the substrate 400.

The first transistor T1 may include a first active layer 310 and a first gate electrode 320.

Specifically, a buffer layer 401 may be disposed on the substrate 400.

The first active layer 310 of the first transistor T1 may be disposed on the buffer layer 401.

The first active layer 310 includes a first region 411 and a second region 412, which are conductive regions, and a first channel provided between the first region 411 and the second region 412. It may include area 413. In addition, as shown in FIG. 7, the first active layer 310 is spaced apart from the first channel region 413 and may further include a third region 413 extending from one end of the second region 412. You can. Here, the third area 413 may be a non-conducting area.

A first gate insulating layer 302 may be disposed on the first active layer 310.

As shown in FIG. 6, the first gate insulating layer 302 may be disposed to overlap the first channel region 413 of the first active layer 310. Additionally, as shown in FIG. 7, the first gate insulating film 302 may be disposed on the third region 413 of the first active layer 310 and on a portion of the upper surface of the buffer layer 401. .

The first gate electrode 320 of the first transistor T1 may be disposed on the first gate insulating layer 302 overlapping the first channel region 413 of the first active layer 310.

A connection electrode 322 may be disposed on the third region 413 of the first active layer 310 and on the first gate insulating film 302 disposed on a portion of the upper surface of the buffer layer 401.

The connection electrode 312 may be in contact with the data line 312 disposed on the substrate 400 through the first contact hole (CNT1) provided in the first gate insulating film 302 and the buffer layer 401. Additionally, the connection electrode 312 may be disposed on the first gate insulating film 302 and in contact with a portion of the upper surface of the second region 412 of the first active layer 310 . Accordingly, the connection electrode 312 may be electrically connected to the second region 412 of the first active layer 310.

An interlayer insulating film 403 may be disposed on the connection electrode 312 and the first gate electrode 320.

As shown in FIG. 6, a second gate insulating layer 304 may be disposed on a portion of the upper surface of the interlayer insulating layer 403.

On the second gate insulating film 304, the first active layer 310 of the first transistor T1 is formed through the second contact hole CNT2 provided in the second gate insulating film 304 and the interlayer insulating film 403. A conductive layer 340 may be disposed in contact with the area 411. Here, the conductive layer 340 may serve as a source electrode or drain electrode of the first transistor T1 and at the same time serve as a gate electrode of the second transistor T2.

Generally, the source electrode or drain electrode of the first transistor (T1) and the second gate electrode of the second transistor (T2) have a separate structure. On the other hand, in an embodiment of the present invention, the source electrode or drain electrode of the first transistor T1 and the second gate electrode of the second transistor T2 are integrated, thereby reducing the mask process.

Specifically, to form the circuit part of a general display panel, a mask process to form the source electrode or drain electrode of the first transistor (T1) and a mask process to form the second gate electrode of the second transistor (T2) are required. . However, in an embodiment of the present invention, one of the mask process for forming the source electrode or drain electrode of the first transistor T1 or the mask process for forming the second gate electrode of the first transistor T1 can be deleted, so the process It has the effect of simplifying.

In an embodiment of the present invention, the number of mask processes can be reduced in the process of forming the circuit unit including the first transistor T1 having the above-described structure.

When examining this with reference to FIGS. 8 to 15, it is as follows.

8 to 15 are diagrams briefly showing a manufacturing method for a partial area of a circuit unit according to an embodiment of the present invention.

In the description below, content (configuration, effects, etc.) that overlaps with the previously described embodiments may be omitted.

Referring to FIG. 8, a data line 312 and a buffer layer material 801 may be sequentially disposed on the substrate 400.

A first active layer material 810 may be disposed on the buffer layer material 801.

A first gate insulating material 802 may be disposed on the first active layer material 810 .

A first photoresist 850 may be disposed on the first gate insulating material 802. In an embodiment of the present invention, the first photoresist 850 may be a negative photoresist or a positive first photoresist. However, the following description will focus on the configuration in which the first photoresist 805 disposed on the first gate insulating material 802 is a positive first photoresist in which the portion exposed to light is dissolved in a developer.

The halftone mask 800 may be disposed to face the substrate 400 on which the first photoresist 850 is disposed. The halftone mask 800 may include a transparent part 801, a semi-transparent part 802, and a blocking part 803.

The transmission portion 801 of the halftone mask 800 is an area where light can pass through the halftone mask 800 and reach the first photoresist 850. The semi-transmissive portion 802 of the halftone mask 800 is an area where a portion of light can pass through the halftone mask 800 and reach the first photoresist 850, and is less than the amount of light transmitted through the transmissive portion 801. It may be an area through which positive light transmits. The blocking portion 803 of the halftone mask 800 may be an area where light does not pass through and is blocked.

The first photoresist 850 disposed in the area corresponding to the transparent portion 801 of the halftone mask 800 may be removed after exposure (photolithography) and development processes.

Additionally, only a portion of the first photoresist 850 disposed in the area corresponding to the semi-transmissive portion 802 of the halftone mask 800 may remain after the exposure (photolithography) and development processes.

The first photoresist 850 disposed in the area corresponding to the blocking portion 803 of the halftone mask 800 is not removed even after the exposure (photolithography) and development process, and remains as before the exposure and development process. You can.

Here, the height of the first photoresist 850 disposed in the area corresponding to the semi-transparent portion 802 of the halftone mask 800 is greater than the height of the photoresist 850 disposed in the area corresponding to the blocking portion 803. It can be low.

Thereafter, as shown in FIG. 9, a portion of the first gate insulating material 902 and the buffer layer material 901 are etched through an ashing process (dry etching process) using the first photoresist 850 as a mask. Some of them can be removed.

Specifically, the first gate insulating material 902 provided in the area where the first photoresist 850 does not exist can be removed, and the buffer layer material provided in the area where the first photoresist 850 does not exist ( 901) may be removed.

The first active layer material 1010 disposed in the area corresponding to the area from which the first gate insulating material 902 was removed may be made into a conductor in the first gate insulating material 902 ashing process. In other words, in the step of FIG. 10, the first active layer material 1010 may include a conductive region 1010a. Here, the area where the first active layer material 1010 is conductive may later become part of the second area of the first active layer.

Thereafter, a portion of the first photoresist 850 remaining on the substrate 400 in FIG. 9 may be removed.

Accordingly, like the first photoresist 1050 shown in FIG. 10, a low-height portion of the first photoresist 950 in FIG. 9 can be removed. In other words, the first photoresist 950 disposed in the area corresponding to the semi-transparent portion 802 of the halftone mask 800 shown in FIG. 8 can be removed.

A portion of the first gate insulating layer material 1002 and a portion of the buffer layer material may be removed using the first photoresist 1050 of FIG. 10 as a mask.

The first gate insulating layer material 1002 and the buffer layer material provided in areas where the first photoresist 1050 does not exist may be removed. Specifically, the first gate insulating material 1002 may be removed from the area corresponding to the semi-transparent portion 802 of the halftone mask 800 shown in FIG. 8, and the halftone mask 800 shown in FIG. 8 may be removed. The buffer layer material disposed in the area corresponding to the transmission portion 801 may be removed.

Accordingly, the first gate insulating material 1002 and the buffer layer 401 may be disposed to expose a portion of the upper surface of the data line 312.

Thereafter, as shown in FIG. 11, the first photoresist disposed on the first gate insulating material 1002 may be removed.

Thereafter, as shown in FIG. 12 , the first gate electrode material 1220 may be formed on the substrate 400 on which the first gate insulating material 1002 is formed.

A second photoresist 1250 may be disposed on the first gate electrode material 1220. The second photoresist 1250 may be patterned to expose a portion of the top surface of the first gate electrode material 1220.

Thereafter, as shown in FIG. 13, the first gate electrode material 1220 may be patterned using the second photoresist 1250 as a mask. Specifically, the first gate electrode material 1220 disposed in the area overlapping with the second photoresist 1250 remains on the substrate 400, and is disposed in the area where the second photoresist 1250 does not exist. The first gate electrode material 1220 may be removed to form the first gate electrode 320 and the connection electrode 322.

Here, a portion of the connection electrode 322 is disposed in the area where the first gate insulating material 1220 has been removed, so that it can be in contact with the area 1010a where the first active layer material 1010 is conductive. Additionally, another part of the connection electrode 322 may be placed in an area where the first gate insulating film material 1220 and the buffer layer 401 were removed, so that it may contact a part of the upper surface of the data line 312.

Thereafter, as shown in FIG. 14 , the first gate insulating layer material may be removed through a dry etching process using the second photoresist 1250 as a mask to form the first gate insulating layer 302.

The first active layer material disposed in the area corresponding to the area from which the first gate insulating layer material was removed may be converted into a conductor in an ashing process for the first gate insulating layer material to form the first active layer 310.

Specifically, the first active layer 310 in a region corresponding to the region where the first gate insulating film 302 is disposed may be a first channel region 412 and a third region 414 that are not conductors. Additionally, a part of the first active layer 310 disposed in the area corresponding to the area where the first gate insulating film 302 was removed may become the first area 411, and the remaining part may be the first active layer in FIG. 13. It may correspond to a region extending from the conductive region 1010a of the layer material 1010. The area corresponding to the area extending from the conductive area 1010a of the first active layer material 1010 of FIG. 13 is the conductive area 1010a of the first active layer material 1010 of FIG. 13 and the first It may be the second region 412 of the active layer 310.

Thereafter, as shown in FIG. 15, the second photoresist 1250 disposed on the first gate electrode 320 and the connection electrode 322 may be removed.

As explained with reference to FIGS. 9, 10, and 14, the structure according to the embodiment of the present invention reduces the mask process by etching the first gate insulating film 302 using the first and second photoresists as masks. There is an effect that can be done.

In addition, as described with reference to FIG. 13, the first gate insulating film 302 is formed to contact the conductive region 1010a of the first active layer material 1010 present in the removed region, thereby forming the first gate. The connection electrode 322 and the second region 412, which is a conductive region of the first active layer 310, can be contacted without a separate contact hole in the insulating film 302.

Additionally, although not shown in the drawing, the second gate insulating layer may also be patterned using a halftone mask.

According to embodiments of the present invention, a thin film transistor array substrate having a structure that can reduce the area occupied by the transistors by stacking at least two transistors in a direction perpendicular to the substrate and an electronic device including the same can be provided. there is.

In addition, according to embodiments of the present invention, a thin film transistor array substrate having a structure that can facilitate the conduction process of the active layer by reducing the area where the conductive active layer area is disposed in the contact hole, and including the same An electronic device that can be provided can be provided.

In addition, according to embodiments of the present invention, the gate electrode of the second transistor disposed on the first transistor has a structure that simultaneously serves as the source electrode or drain electrode of the first transistor, thereby eliminating at least one insulating film configuration. In addition, a thin film transistor array substrate capable of reducing the number of processes and an electronic device including the same can be provided.

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

302: first gate insulating film
304: second gate insulating film
310: first active layer
312: data line
320: first gate electrode
322: Connection electrode
330: second active layer
340: second gate electrode

Claims (17)

A panel including at least one first transistor and at least one second transistor; and
Includes a driving circuit for driving the panel,
The panel is,
A first active layer of a first transistor disposed on a substrate and including a first channel region;
a first gate insulating layer including a portion disposed on the first channel region of the first active layer;
a first gate electrode of the first transistor disposed on the first gate insulating layer and overlapping the first channel region;
an interlayer insulating film disposed on the first gate electrode;
a second active layer of the second transistor disposed on the interlayer insulating film and including a second channel region;
a second gate insulating layer disposed on a portion of the upper surface of the second active layer and a portion of the upper surface of the interlayer insulating layer; and
A second gate electrode of the second transistor is disposed on the second gate insulating film, overlaps the second channel region, and is in contact with the first active layer,
An electronic device in which a first region of the first active layer is in contact with the second gate electrode of the second transistor through a first contact hole provided in the interlayer insulating layer. According to claim 1,
The first transistor is a scan transistor,
An electronic device in which the second transistor is a driving transistor. According to claim 1,
The first active layer further includes the first and second regions as conductive regions and the third region as a non-conducting region,
A first channel region of the first active layer is provided between the first region and the second region,
The third area is an electronic device extending from one side of the second area. delete According to clause 3,
The third area is an area spaced apart from the first channel area and overlaps the first gate insulating layer. According to clause 3,
It further includes a data line disposed below the first active layer and a connection electrode on a first gate insulating layer disposed on the data line,
The connection electrode is electrically connected to the data line through a first contact hole provided in the first gate insulating film. According to clause 6,
The connection electrode is disposed on the same layer as the first gate electrode,
The connection electrode is in contact with a portion of the upper surface of the second region of the first active layer. According to clause 7,
An electronic device in which an area in contact between the connection electrode and the data line is smaller than an area in contact with the connection electrode and the second region of the first active layer. According to clause 6,
Further comprising a scan line disposed on the substrate and disposed to intersect the data line,
The first gate electrode is an electronic device corresponding to the scan line. According to clause 6,
Further comprising a sense line and a light emission control line disposed on the substrate and disposed to intersect the data line,
The second gate electrode is disposed on the same layer as the sense line and the light emission control line. According to claim 10,
The panel further includes a third transistor disposed on the substrate,
The third transistor is an electronic device including a third gate electrode branched from the second active layer and the sense line. According to claim 11,
The second active layer has a third channel region in an area overlapping the third gate electrode. According to claim 10,
The panel further includes a fourth transistor disposed on the substrate,
The fourth transistor is an electronic device including a fourth gate electrode branched from the second active layer and the emission control line. In clause 13
The second active layer includes a fourth channel region in an area overlapping the fourth gate electrode. According to claim 14,
The second active layer further includes a fourth region and a fifth region that are conductive regions,
A second channel region of the second active layer is provided between the fourth region and the fifth region,
The fourth area is disposed between the fourth channel area and the second channel area,
The fifth region is disposed between the fourth channel region and the third channel region of the second active layer. According to claim 15,
the panel includes at least one storage capacitor,
The storage capacitor includes a first region that is a conductive region of the first active layer and a fifth region of the second active layer. Board;
a first active layer of a first transistor disposed on the substrate and including a first channel region;
a first gate insulating layer including a portion disposed on the first channel region of the first active layer;
a first gate electrode of the first transistor disposed on the first gate insulating layer and overlapping the first channel region;
an interlayer insulating film disposed on the first gate electrode;
a second active layer of the second transistor disposed on the interlayer insulating film and including a second channel region;
a second gate insulating layer disposed on a portion of the upper surface of the second active layer and a portion of the upper surface of the interlayer insulating layer; and
A second gate electrode of the second transistor is disposed on the second gate insulating film, overlaps the second channel region, and is in contact with the first active layer,
A thin film transistor array substrate in which a first region of the first active layer is in contact with the second gate electrode of the second transistor through a first contact hole provided in the interlayer insulating film.

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