KR20240043062A - Display panel, display device and display panel manufacturing method - Google Patents

Abstract

Embodiments of the present disclosure relate to a display panel, a display device, and a display panel manufacturing method, and more specifically, to a channel region, a first region located on a first side of the channel region, and a second side of the channel region. A first active layer including a second region, a gate insulating film disposed on the first active layer, a first electrode disposed on the gate insulating film and electrically connected to the first region, disposed on the gate insulating film, a second electrode electrically connected to the second region, a first insulating film disposed on the gate insulating film and having a first hole overlapping at least a portion of the channel region, disposed in the first hole, and within the first hole, a channel region and By including a third electrode arranged to overlap, it is possible to prevent the characteristics of the transistor from being deteriorated due to internal light.

Description

Display panel, display device and display panel manufacturing method {DISPLAY PANEL, DISPLAY DEVICE AND DISPLAY PANEL MANUFACTURING METHOD}

Embodiments of the present disclosure relate to a display panel, a display device, and a method of manufacturing a display panel.

Transistors are widely used as switching devices or driving devices in the electronic device field.

In particular, since thin film transistors can be manufactured on glass or plastic substrates, they can be driven in display devices such as liquid crystal display devices or organic light emitting display devices. It is widely used as a device or switching device.

Display devices containing such thin film transistors often experience problems such as deterioration of transistor characteristics due to internal light, increase in parasitic capacitance, and decrease in aperture ratio.

In conventional display devices, display panels, display devices, and display panels that can solve the problems of deterioration of transistor characteristics due to internal light, deterioration of driving characteristics due to parasitic capacitance, and reduction of the area of the light emitting area due to a decrease in aperture ratio. A manufacturing method was invented.

Embodiments of the present disclosure can provide a display panel, a display device, and a display panel manufacturing method that can prevent the characteristics of a transistor from being deteriorated due to internal light being incident on the active layer.

Additionally, embodiments of the present disclosure can provide a display panel, a display device, and a display panel manufacturing method that can prevent driving characteristics from being deteriorated due to an increase in parasitic capacitance.

In addition, embodiments of the present disclosure provide a display panel, display device, and display panel manufacturing method that can secure a large area of the opening (light-emitting area) by having a structure that can increase the capacity of a storage capacitor located in a small area. can be provided.

Embodiments of the present disclosure include a first active layer disposed on a substrate and including a channel region, a first region located on a first side of the channel region, and a second region located on a second side of the channel region, 1 A gate insulating film disposed on the active layer, a first electrode disposed on the gate insulating film and electrically connected to the first region, a second electrode disposed on the gate insulating film and electrically connected to the second region, and A first insulating film disposed on the first insulating film and including a first hole overlapping at least a portion of the channel region, a second insulating film disposed on the first insulating film and including a second hole overlapping at least a portion of the first hole, and a first hole. A display panel including a third electrode disposed within the first hole and overlapped with the channel region within the first hole may be provided.

Embodiments of the present disclosure include a first active layer disposed on a substrate and including a channel region, a first region located on a first side of the channel region, and a second region located on a second side of the channel region; A gate insulating layer disposed on the first active layer, a first electrode disposed on the gate insulating layer and electrically connected to the first region, a second electrode disposed on the gate insulating layer and electrically connected to the second region, and on the gate insulating layer. A display device including a first insulating film disposed in and having a first hole overlapping at least a portion of the channel region, and a third electrode disposed in the first hole and disposed to overlap the channel region within the first hole. can be provided.

Embodiments of the present disclosure include forming a light shield on a substrate, forming a buffer layer on the substrate on which the light shield is disposed, forming an active material on the buffer layer, and patterning the active material to form a first active pattern and at least Forming a second active pattern, forming a gate insulating layer material on the first and second active patterns, and forming a plurality of contact holes in the gate insulating layer material and the buffer layer through a first dry etching process to form a gate insulating layer. forming, forming an electrode material on the gate insulating film, patterning the electrode material to form first and second electrodes, forming a first insulating film material on the substrate on which the first and second electrodes are formed, 1. A method of manufacturing a display panel can be provided, including the steps of forming holes and contact holes by patterning an insulating film material, and forming a third electrode by forming and patterning a second electrode material on the first insulating film.

According to embodiments of the present disclosure, the electrode disposed on the active layer overlaps the entire channel region of the active layer and also overlaps a portion of each of the first region and the second region disposed on both sides of the channel region of the active layer. By being disposed, it is possible to provide a display panel, a display device, and a display panel manufacturing method that can prevent internal light from entering the active layer and deteriorating the characteristics of the transistor.

According to embodiments of the present disclosure, the transistor includes electrodes disposed in different layers, and by adjusting the thickness of the insulating film disposed between the electrodes, the display can prevent driving characteristics from being deteriorated due to an increase in parasitic capacitance. A panel, a display device, and a method of manufacturing a display panel can be provided.

According to embodiments of the present disclosure, a display panel including a high-capacity storage capacitor, a display device, and a display panel manufacturing method are provided by including a plurality of storage capacitor electrodes and a plurality of storage capacitors connected in parallel. You can.

1 is a system configuration diagram of a display device according to embodiments of the present disclosure.
2 is an equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
3 is another equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
FIG. 4 is a diagram illustrating a light shield within a subpixel of a display device according to embodiments of the present disclosure.
FIG. 5 is a diagram illustrating a portion of an active area in a display panel according to embodiments of the present disclosure.
FIGS. 6A to 6E are cross-sectional views taken along lines AB, CD, and EF of FIG. 5.
7A to 7C are schematic cross-sectional views of display devices according to embodiments of the present disclosure.
FIG. 8 is a diagram schematically showing the structure of storage capacitors disposed in at least one subpixel of a display device according to embodiments of the present disclosure.
9A and 9B are diagrams showing a cross-sectional structure of a display device according to embodiments of the present disclosure.
10A to 10D are diagrams illustrating the structure of a display device according to embodiments of the present disclosure.
FIGS. 11 to 21 are diagrams schematically showing the manufacturing process of the display device shown in FIG. 6C.
FIGS. 22 and 23 are diagrams schematically showing process steps for forming a third electrode, a pixel electrode, and a bank of the display device shown in FIG. 6D.
FIGS. 24 and 25 are diagrams schematically showing a process for forming a third electrode, a pixel electrode, and a bank of the display device shown in FIG. 6E.
FIGS. 26 to 36 are diagrams schematically showing the manufacturing process of the display device shown in FIG. 7A.
FIGS. 37 and 38 are diagrams schematically showing process steps for forming a third electrode, a pixel electrode, and a bank of the display device shown in FIG. 7B.
FIGS. 39 and 40 are diagrams schematically showing a process for forming a third electrode, a pixel electrode, and a bank of the display device shown in FIG. 7C.
FIGS. 41 to 44 are diagrams schematically showing the manufacturing process of the display device shown in FIG. 10A.
FIG. 45 is a diagram schematically showing the steps of forming a first electrode, a third electrode, and a pixel electrode in the display device of FIG. 10B.
FIGS. 46 and 47 are diagrams schematically showing steps for forming a first electrode, a third electrode, and a pixel electrode in the display device of FIG. 10D.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the description of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a system configuration diagram of a display device 100 according to embodiments of the present disclosure.

Referring to FIG. 1 , a display device 100 according to embodiments of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110 .

The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

The display panel 110 may include a substrate SUB and signal wires such as a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate SUB. The display panel 110 may include a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of gate lines (GL).

The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed and is located outside the display area DA. In the display panel 110, a plurality of subpixels (SP) for displaying an image are disposed in the display area (DA), and the driving circuits 120, 130, and 140 are electrically connected to the non-display area (NDA). The driving circuits 120, 130, and 140 may be connected or mounted, and a pad portion to which an integrated circuit or printed circuit, etc., may be connected may be disposed.

The data driving circuit 120 is a circuit for driving a plurality of data lines DL and can supply data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL and can supply gate signals to the plurality of gate lines GL. The controller 140 may supply a data control signal (DCS) to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may supply a gate control signal (GCS) to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

The controller 140 controls the scanning operation to start according to the timing implemented in each frame, and converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120 to produce the converted image data. (Data) can be supplied to the data driving circuit 120, and data driving can be controlled to proceed at an appropriate time according to the scanning timing.

The controller 140 uses a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC), and a gate output enable signal (GOE: Gate Output Enable signal) to control the gate driving circuit 130. ) can output various gate control signals (GCS: Gate Control Signal), etc.

The controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the data driving circuit 120. ) can output various data control signals (DCS: Data Control Signal), etc.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data Data from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

This data driving circuit 120 may include one or more source driver integrated circuits (SDIC).

For example, each source driver integrated circuit (SDIC) is connected to the display panel 110 using Tape Automated Bonding (TAB), Chip On Glass (COG), or Chip On Panel ( It may be connected to the bonding pad of the display panel 110 using a COP (Chip On Panel) method, or may be implemented using a Chip On Film (COF) method and connected to the display panel 110.

The gate driving circuit 130 may output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive a plurality of gate lines GL by sequentially supplying a gate signal with a turn-on level voltage to the plurality of gate lines GL.

The gate driving circuit 130 is connected to the display panel 110 using a tape automated bonding (TAB) method, or is connected to a bonding pad of the display panel 110 using a chip-on-glass (COG) or chip-on-panel (COP) method. Pad) or may be connected to the display panel 110 according to the chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be a gate in panel (GIP) type and may be formed in the non-display area NDA of the display panel 110. The gate driving circuit 130 may be disposed on or connected to the substrate SUB. That is, if the gate driving circuit 130 is a GIP type, it may be disposed in the non-display area NDA of the substrate SUB. The gate driving circuit 130 may be connected to the substrate SUB in the case of a chip-on-glass (COG) type, chip-on-film (COF) type, etc.

Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be arranged not to overlap the subpixels SP, and may be partially or entirely aligned with the subpixels SP. They may also be placed overlapping.

When a specific gate line (GL) is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (Data) received from the controller 140 into an analog data voltage to generate a plurality of data lines. It can be supplied as (DL).

The data driving circuit 120 may be connected to one side (eg, the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The gate driving circuit 130 may be connected to one side (eg, left or right) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., left and right) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The controller 140 may be a timing controller used in typical display technology, or a control device that can further perform other control functions, including a timing controller, and may be a control device different from the timing controller. It may be a circuit within the control device. The controller 140 may be implemented with various circuits or electronic components, such as an Integrated Circuit (IC), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or Processor.

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc.

The display device 100 according to embodiments of the present disclosure may be a display including a back light unit such as a liquid crystal display, an Organic Light Emitting Diode (OLED) display, a quantum dot display, or a micro LED ( It may be a self-luminous display such as a Micro Light Emitting Diode (Micro Light Emitting Diode) display.

When the display device 100 according to embodiments of the present disclosure is an OLED display, each subpixel (SP) may include an organic light emitting diode (OLED) that emits light as a light emitting device. When the display device 100 according to embodiments of the present disclosure is a quantum dot display, each subpixel SP may include a light emitting device made of quantum dots, which are semiconductor crystals that emit light on their own. When the display device 100 according to embodiments of the present disclosure is a micro LED display, each subpixel (SP) emits light on its own and may include a micro LED (Micro Light Emitting Diode) made of an inorganic material as a light emitting element. there is.

2 is an equivalent circuit of a subpixel (SP) of the display device 100 according to embodiments of the present disclosure, and FIG. 3 is another equivalent circuit of the subpixel (SP) of the display device 100 according to embodiments of the present disclosure. It is a circuit.

Referring to FIG. 2, each of the plurality of subpixels (SP) disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure includes a light emitting element (ED), a driving transistor (DRT), and a scanning transistor. (SCT) and a storage capacitor (Cst).

Referring to FIG. 2, the light emitting element (ED) includes a pixel electrode (PE) and a common electrode (CE), and may include a light emitting layer (EL) located between the pixel electrode (PE) and the common electrode (CE). there is.

The pixel electrode PE of the light emitting element ED may be an electrode disposed in each subpixel SP, and the common electrode CE may be an electrode commonly disposed in all subpixels SP. Here, the pixel electrode (PE) may be an anode electrode and the common electrode (CE) may be a cathode electrode. Conversely, the pixel electrode (PE) may be a cathode electrode and the common electrode (CE) may be an anode electrode.

For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting device.

The driving transistor DRT is a transistor for driving the light emitting device ED and may include a first node N1, a second node N2, and a third node N3.

The first node (N1) of the driving transistor (DRT) may be a source node (source electrode) or a drain node (drain electrode) of the driving transistor (DRT), and may also be electrically connected to the common electrode (CE) of the light emitting element (ED). can be connected The second node (N2) of the driving transistor (DRT) may be the drain node (drain electrode) or the source node (source electrode) of the driving transistor (DRT), and the driving voltage line (DVL) that supplies the driving voltage (EVDD). can be electrically connected to. The third node N3 of the driving transistor DRT may be a gate node (gate electrode) of the driving transistor DRT and may be electrically connected to the source node or drain node of the scanning transistor SCT.

The scanning transistor (SCT) is controlled by the scanning gate signal (SCAN), which is a type of gate signal, and may be connected between the third node (N3) of the driving transistor (DRT) and the data line (DL). In other words, the scanning transistor (SCT) is turned on or off according to the scanning gate signal (SCAN) supplied from the scanning gate line (SCL), which is a type of gate line (GL), and the data line (DL) The connection between the third node N3 and the driving transistor DRT can be controlled.

The scanning transistor (SCT) is turned on by the scanning gate signal (SCAN) having a turn-on level voltage, and transmits the data voltage (Vdata) supplied from the data line (DL) to the third node of the driving transistor (DRT). You can forward it to (N3).

Here, when the scanning transistor (SCT) is an n-type transistor, the turn-on level voltage of the scanning gate signal (SCAN) may be a high level voltage. When the scanning transistor (SCT) is a p-type transistor, the turn-on level voltage of the scanning gate signal (SCAN) may be a low level voltage.

The storage capacitor Cst may be connected between the third node N3 and the first node N1 of the driving transistor DRT. The storage capacitor (Cst) is charged with a charge corresponding to the voltage difference between both ends and plays the role of maintaining the voltage difference between both ends for a set frame time. Accordingly, the corresponding subpixel SP may emit light during a set frame time.

Referring to FIG. 3 , each of the plurality of subpixels SP disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure may further include a sensing transistor (SENT).

The sensing transistor (SENT) is controlled by the sensing gate signal (SENSE), which is a type of gate signal, and may be connected between the first node (N1) of the driving transistor (DRT) and the reference voltage line (RVL). In other words, the sensing transistor (SENT) is turned on or turned off according to the sensing gate signal (SENSE) supplied from the sensing gate line (SENL), which is another type of gate line (GL), to generate the reference voltage line ( The connection between RVL) and the first node (N1) of the driving transistor (DRT) can be controlled.

The sensing transistor (SENT) is turned on by the sensing gate signal (SENSE) having a turn-on level voltage, and applies the reference voltage (Vref) supplied from the reference voltage line (RVL) to the first voltage of the driving transistor (DRT). It can be delivered to node (N1).

In addition, the sensing transistor (SENT) is turned on by the sensing gate signal (SENSE) having a turn-on level voltage, so that the voltage of the first node (N1) of the driving transistor (DRT) is connected to the reference voltage line (RVL). It can be delivered to .

Here, when the sensing transistor SENT is an n-type transistor, the turn-on level voltage of the sensing gate signal SENSE may be a high level voltage. When the sensing transistor SENT is a p-type transistor, the turn-on level voltage of the sensing gate signal SENSE may be a low level voltage.

The function of the sensing transistor (SENT) to transfer the voltage of the first node (N1) of the driving transistor (DRT) to the reference voltage line (RVL) can be used when driving to sense the characteristic value of the subpixel (SP). In this case, the voltage transmitted to the reference voltage line RVL may be a voltage for calculating the characteristic value of the subpixel SP or a voltage reflecting the characteristic value of the subpixel SP.

Each of the driving transistor (DRT), scanning transistor (SCT), and sensing transistor (SENT) may be an n-type transistor or a p-type transistor. In this disclosure, for convenience of explanation, the driving transistor (DRT), scanning transistor (SCT), and sensing transistor (SENT) are each n-type.

The storage capacitor (Cst) is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor that exists between the gate node and the source node (or drain node) of the driving transistor (DRT). ) may be an external capacitor intentionally designed outside of the capacitor.

The scanning gate line (SCL) and the sensing gate line (SENL) may be different gate lines (GL). In this case, the scanning gate signal (SCAN) and the sensing gate signal (SENSE) may be separate gate signals, and the on-off timing of the scanning transistor (SCT) in one subpixel (SP) and the sensing transistor (SENT) may be different from each other. On-off timing can be independent. That is, the on-off timing of the scanning transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same or different.

Alternatively, the scanning gate line (SCL) and the sensing gate line (SENL) may be the same gate line (GL). That is, the gate node of the scanning transistor (SCT) and the gate node of the sensing transistor (SENT) within one subpixel (SP) may be connected to one gate line (GL). In this case, the scanning gate signal (SCAN) and the sensing gate signal (SENSE) may be the same gate signal, and the on-off timing of the scanning transistor (SCT) within one subpixel (SP) and the on-off timing of the sensing transistor (SENT) may be the same. The off timing may be the same.

The structure of the subpixel SP shown in FIGS. 2 and 3 is only an example and may be modified in various ways by including one or more transistors or one or more capacitors.

In addition, in FIGS. 2 and 3, the subpixel structure is explained assuming that the display device 100 is a self-luminous display device. However, when the display device 100 is a liquid crystal display device, each subpixel SP is a transistor. and pixel electrodes.

FIG. 4 is a diagram illustrating a light shield (LS) within a subpixel (SP) of the display device 100 according to embodiments of the present disclosure.

Referring to FIG. 4 , in the subpixel SP of the display device 100 according to embodiments of the present disclosure, the driving transistor DRT may have unique characteristics such as threshold voltage and mobility. When the intrinsic characteristics of the driving transistor (DRT) change, the current driving ability (current supply performance) of the driving transistor (DRT) changes, and the light emission characteristics of the corresponding subpixel (SP) may also change.

The device characteristics (e.g., threshold voltage, mobility, etc.) of the driving transistor (DRT) may change as the driving time of the driving transistor (DRT) passes. In addition, when light is irradiated to the driving transistor (DRT), especially when light is irradiated to the channel region of the driving transistor (DRT), the device characteristics (e.g., threshold voltage, mobility, etc.) of the driving transistor (DRT) may change. It may change.

Therefore, as shown in FIG. 4, in order to reduce changes in device characteristics (e.g., threshold voltage change, mobility change, etc.) of the driving transistor (DRT), a light shield (LS) is installed near the driving transistor (DRT). may be formed. For example, the light shield LS may be formed under the channel region of the driving transistor DRT.

Meanwhile, in addition to blocking light, the light shield LS may be formed under the channel region of the driving transistor DRT and serve as a body of the driving transistor DRT.

A body effect may occur in the driving transistor (DRT). In order to reduce the influence of this body effect, the light shield (LS), which serves as the body of the driving transistor (DRT), It may be electrically connected to the first node (N1). Here, the first node N1 of the driving transistor DRT may be a source node of the driving transistor DRT.

Meanwhile, the light shield LS may be disposed not only under the channel region of the driving transistor DRT, but also under the channel region of other transistors (eg, SCT, SENT).

In the display area DA of the display panel 110 according to embodiments of the present disclosure, transistors DRT, SCT, and SENT may be disposed for each subpixel SP. When the gate driving circuit 130 is formed as a GIP (Gate In Panel) type in the non-display area (NDA) of the display panel 110 according to embodiments of the present disclosure, the GIP type gate driving circuit 130 A plurality of transistors may be disposed in the non-display area NDA of the display panel 110.

As such, multiple transistors may be disposed on the display panel 110 according to embodiments of the present disclosure. Light may enter these transistors and the characteristics of the transistors may deteriorate. For example, part of the light emitted from the organic light emitting element included in the organic light emitting display device is emitted toward the front of the display panel, while the other part of the light emitted from the organic light emitting element is emitted toward the lower substrate where a plurality of transistors are arranged. It can be transmitted and flow into the interior of the transistor. In this case, bright spots or dark spots may appear on the display panel 110.

The inventors of the present specification confirmed through experiment and analysis that the characteristics of the display panel 110 deteriorate due to internal light entering the transistor, and invented a structure and process method that can prevent internal light from entering the transistor. did.

Below, a display panel and display device that can prevent light emitted from an organic light emitting device from flowing into the transistor and maintain the characteristics of the transistor will be described in more detail.

FIG. 5 is a diagram illustrating a portion of an active area in a display panel according to embodiments of the present disclosure.

Referring to FIG. 5 , at least one subpixel of the display panel according to embodiments of the present disclosure may include an emission area EA and a non-emission area divided by a bank.

In the active area of the display panel, the emission area EA may be an area that does not overlap with the bank, and the non-emission area may be an area that does not overlap with the bank.

An organic light emitting device (OLED) including an anode electrode 570, an organic layer including a light emitting layer, and a cathode electrode may be disposed in the light emitting area EA. Additionally, the color filter 580 may be arranged to overlap the light emitting area EA where the organic light emitting device (OLED) is disposed, but the present invention is not limited thereto. For example, the color filter 580 may be disposed only in some subpixels among a plurality of subpixels included in the display device 100, and the color filter 580 may not be disposed in all subpixels included in the display device 100. It may be possible.

At least one transistor may be disposed in one subpixel. For example, as shown in FIG. 5, a first transistor (T1), a second transistor (T2), and a third transistor (T3) may be disposed in one subpixel.

A first signal line 501 and a second signal line 502 that are disposed on the same layer as the light shield 510 and extend in the first direction may be disposed on the substrate. Here, the first signal line 501 may be the driving voltage line (DVL) of FIGS. 2 to 4, and the second signal line 502 may be a data line (DL of FIGS. 2 to 4), but in the present disclosure, The embodiments are not limited thereto. For example, each of the first and second signal lines 501 and 502 may be a data line.

However, for convenience of explanation, the following description will focus on the structure in which the first signal line 501 is a driving voltage line and the second signal line 502 is a data line.

The light shield 510 may be disposed on the same layer as the first and second signal lines 501 and 502.

A first active layer 520, a second active layer 530, and a third active layer 540 may be disposed on the substrate on which the first and second signal lines 501 and 502 and the light shield 510 are disposed. there is.

Here, at least one active layer may include an oxide semiconductor material. An oxide semiconductor material is a semiconductor material whose conductivity is controlled and the band gap is adjusted by doping the oxide material, and may generally be a transparent semiconductor material with a wide band gap. For example, oxide semiconductor materials include IGZO (Indium gallium zinc oxide), ZnO (zinc oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), IGZTO (Indium gallium zinc tin oxide), etc.

For example, when the first to third active layers 520, 530, and 540 include an oxide semiconductor material, the transistor TR including the first to third active layers 520, 530, and 540 It is called an oxide thin film transistor.

The first active layer 520 is included in the first transistor (T1), the second active layer 530 is included in the second transistor (T2), and the third active layer 540 is included in the third transistor (T3). may be included in

Referring to FIG. 5 , the second active layer 530 may serve as an electrode for a storage capacitor (Cst) disposed in a subpixel.

Specifically, the storage capacitor Cst may include at least two storage capacitor electrodes. For example, as shown in FIG. 5, the light shield 510 and the second active layer 530 may be included as storage capacitor (Cst) electrodes.

A plurality of signal lines 503, 504, 505 and a plurality of conductive layers 551, 552 may be disposed on the substrate on which the first to third active layers 520, 530, and 540 are disposed.

Specifically, the plurality of signal lines may include a third signal line 503, a fourth signal line 504, a fifth signal line 505, and a sixth signal line 506.

The third and fourth signal lines 503 and 504 may extend in a direction intersecting the first and second signal lines 501 and 502. The third signal line 503 may be a first gate line, and the fourth signal line 504 may be a second gate line.

The fifth signal line 505 may be arranged to overlap at least a portion of the first signal line 501. Additionally, the fifth signal line 505 and the first signal line 501 may be electrically connected through a contact hole provided in the insulating film disposed below the fifth signal line 505. Through this, the resistance of the first signal line 501 can be lowered.

Additionally, the fifth signal line 505 may include an extension portion extending in a direction intersecting the direction in which the first signal line 501 extends. A plurality of subpixels may be supplied with a driving voltage through an extension of the fifth signal line 505, but embodiments of the present disclosure are not limited thereto. For example, when the first signal line 501 is a data line, the fifth signal line 505 may not be disposed on the first signal line 501.

The sixth signal line 506 may extend in a direction crossing the first and second signal lines 501 and 502. The sixth signal line 506 may be electrically connected to the third active layer 540. Here, the sixth signal line 506 may be a signal line connected to the reference voltage line, but embodiments of the present disclosure are not limited thereto.

The third to sixth signal lines 503, 504, 505, and 506 and the plurality of conductive layers 551 and 552 disposed on the same layer may include a first electrode 551 and a second electrode 552. .

Here, each of the first electrode 551 and the second electrode 552 may function as one of the source electrode and drain electrode of the first transistor T1.

A third electrode 563 may be disposed on the substrate on which the first electrode 551 and the second electrode 552 are disposed.

The third electrode 563 may serve as a gate electrode of the first transistor T1.

The third electrode 563 may be disposed on a different layer from the first electrode 551 and the second electrode 552.

Referring to FIG. 5 , the third electrode 563 may be disposed in a contact hole provided in at least one layer of insulating film disposed below the third electrode 563.

For example, the third electrode 563 may be disposed in the first hole CH1 and the second hole CH2 of the insulating films disposed between the first active layer 520 and the third electrode 563.

Here, the third electrode 563 may overlap a portion of the first active layer 520. In particular, the third electrode 563 is connected to each of the first and second regions 521 and 521 of the first active layer 520, as well as the channel region of the first active layer 520 of the first transistor T1. It is possible to prevent light from being incident on the first active layer 520 of the first transistor T1 and deteriorating the characteristics of the first transistor T1 by overlapping at least a portion thereof.

Referring to FIG. 5 , the first transistor T1 may include a first active layer 520, a first electrode 551, a second electrode 552, and a third electrode 563.

The first electrode 551 of the first transistor (T1) is electrically connected to the light shield 510, and the first active layer 520 of the first transistor (T1) is integrated with the fifth signal line 505. It may be electrically connected to the formed second electrode 552.

The second transistor T2 may include a second active layer 530, a third electrode 563, a fourth electrode 554, and a third signal line 503. The fourth electrode 554 may be disposed on the same layer as the third signal line 503. Each of the third electrode 563 and the fourth electrode 554 included in the second transistor T2 may function as one of the source electrode and the drain electrode of the second transistor T2.

As shown in FIG. 5 , the fourth electrode 554 may be electrically connected to the second signal line 502, and the third electrode 563 may be electrically connected to the second active layer 530.

Referring to FIG. 5 , the third transistor T3 may include a third active layer 540, a fifth electrode 555, a sixth signal line 506, and a fourth signal line 504. Each of the fifth electrode 555 and the sixth signal line 506 of the third transistor T3 may serve as one of the source electrode and the drain electrode of the third transistor T3.

The first transistor T1 may be a driving transistor, and as shown in FIG. 5, at least one storage capacitor Cst may be disposed within one subpixel.

The storage capacitor Cst may include a plurality of storage capacitor electrodes. For example, as shown in FIG. 5, the storage capacitor Cst may include a light shield 510, a second active layer 530, and a pixel electrode 570 as storage capacitor electrodes.

The structure of these pixels will be examined in detail with reference to FIGS. 6A to 6E as follows.

FIGS. 6A to 6E are cross-sectional views taken along lines A-B, C-D, and E-F of FIG. 5.

6A to 6E are cross-sectional views showing transistor structures according to embodiments of the present disclosure.

The display panel 110 according to embodiments of the present disclosure may include a display area DA where an image is displayed and a non-display area NDA that is different from the display area DA. A plurality of transistors and a plurality of capacitors may be disposed in the display area DA and/or the non-display area NDA.

The transistor disposed in the display panel 110 according to embodiments of the present disclosure may be a transistor (DRT, SCT, SENT) disposed in each subpixel (SP) in the display area (DA).

Additionally, the transistor disposed on the display panel 110 according to embodiments of the present disclosure may be a transistor included in the GIP type gate driving circuit 130 formed in the non-display area NDA.

Additionally, the capacitor disposed on the display panel 110 according to embodiments of the present disclosure may be a storage capacitor (Cst) included in each subpixel (SP) in the display area (DA), or a storage capacitor (Cst) included in the non-display area (NDA). It may be a capacitor included in the GIP type gate driving circuit 130 formed in .

Hereinafter, as a transistor for explaining the transistor structure according to embodiments of the present disclosure, the driving transistor DRT in each subpixel SP in the display area DA is taken as an example, and the capacitor according to embodiments of the present disclosure is used. As a capacitor to explain the structure, the storage capacitor (Cst) within the subpixel (SP) is used as an example.

Referring to FIGS. 6A to 6E , one subpixel may include an emission area (EA) and a non-emission area (NEA).

A plurality of transistors and at least one storage capacitor (Cst) may be disposed in the non-emission area (NEA).

An organic light emitting device (OLED) including a pixel electrode 570 (or anode electrode), an organic layer 680, and a common electrode 690 (or cathode electrode) may be disposed in the light emitting area (EA).

6A to 6E, the display panel 110 of the display device 100 according to embodiments of the present disclosure includes a substrate 600, a buffer layer 601 on the substrate 600, and a first layer on the buffer layer 601. 1 active layer 520, first and second electrodes 551, 552 on the first active layer 520, gate insulating film 602 on the first active layer 520, and third electrode on the gate insulating film 602 It may include an electrode 563 and may further include a light shield 510 disposed below the first active layer 520.

6A to 6E illustrate a structure in which the light shield 510 is disposed below the first active layer 520, but the structure of the display device 100 according to embodiments of the present disclosure is not limited thereto. 1 The light shield 510 may not be disposed under the active layer 520.

The transistor TR disposed on the display panel 110 according to embodiments of the present disclosure may be a driving transistor (DRT), but is not limited thereto.

For example, the transistor described in this specification may be a scanning transistor (SCT) or a sense transistor (SENT) disposed in the display area (DA), or may be a transistor disposed in the non-display area (NDA).

Referring to FIGS. 6A to 6E , the transistor TR may include a first electrode 551, a second electrode 552, a third electrode 563, and a first active layer 520. Here, each of the first electrode 551 and the second electrode 552 may be either a source electrode or a drain electrode of the transistor TR.

Referring to FIGS. 6A and 6B , the first active layer 520 of the transistor TR may include a first region 521, a second region 522, and a channel region 523.

Specifically, the first active layer 520 includes a channel region 523 that overlaps the third electrode 563 and the gate insulating film 602, and a first region 521 located on the first side of the channel region 523. and a second area 522 located on the second side of the channel area 523.

The first and second regions 521 and 522 of the first active layer 520 may include conductive regions, and the channel region 523 may be a non-conductive region.

For example, referring to FIGS. 6A and 6B, each of the first and second regions 521 and 522 of the first active layer 520 may be an entirely conductive region.

However, the structure of the first active layer 520 according to embodiments of the present disclosure is not limited to this.

6C to 6E, the first region 521 of the first active layer 520 includes a first auxiliary region 521a and a second auxiliary region 521b, and the second region 522 is It may include a third auxiliary area 522a and a fourth auxiliary area 522b.

Here, the first auxiliary area 521a and the third auxiliary area 522a may be non-conducting areas, and the second reporting area 521b and the fourth auxiliary area 522b may be conductive areas.

Referring to FIGS. 6C to 6E, the second auxiliary area 521b is an area disposed between the channel area 523 and the first auxiliary area 521a, and the fourth auxiliary area 522b is located between the channel area 523. It may be an area disposed between and the third auxiliary area 523a.

Referring to FIGS. 6C to 6E , a portion of the upper surface of each of the second auxiliary region 521b and the fourth auxiliary region 522b may be in contact with the first insulating film 603 . In FIG. 6C, a portion of the upper surface of the second auxiliary region 521b overlaps the first electrode 551 and the gate insulating layer 602, and a portion of the upper surface of the fourth auxiliary region 522b overlaps the second electrode 552 and the gate insulating layer 602. Although a structure overlapping with the gate insulating layer 602 is shown as an example, the structure of the transistor TR according to embodiments of the present disclosure is not limited to this. For example, the entire upper surface of each of the second auxiliary area 521b and the fourth auxiliary area 522b may have a structure in contact with the second insulating film 603.

Additionally, the entire upper surfaces of the first auxiliary area 521a and the third auxiliary area 522a may be in contact with components other than the first insulating layer 603. Specifically, referring to FIG. 6C , a portion of the upper surface of the first auxiliary region 521a may be in contact with the gate insulating layer 602, and the remaining portion may be in contact with the first electrode 551. A portion of the upper surface of the third auxiliary region 522a may be in contact with the gate insulating layer 602, and the remaining portion may be in contact with the second electrode 552.

The first active layer 520 shown in FIGS. 6A to 6E may include an oxide semiconductor material. An oxide semiconductor material is a semiconductor material whose conductivity is controlled and the bandgap is adjusted through doping (or ion implantation) in an oxide material, and may generally be a transparent semiconductor material with a wide bandgap. For example, oxide semiconductor materials include IGZO (Indium gallium zinc oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO ( It may include zinc tin oxide), ZITO (zinc indium tin oxide), IGZTO (Indium gallium zinc tin oxide), etc. When the first active layer 520 is an oxide semiconductor material, the transistor TR including the first active layer 520 is called an oxide thin film transistor.

The first active layer 520 may be made into a conductor during a dry etching process of the gate insulating film 602, rather than a doping process, and the conductivity of the first active layer 520 may be changed through various processes. This can be controlled.

6A to 6E only show a structure in which the first active layer 520 is a single layer, but the structure of the transistor TR according to embodiments of the present disclosure is not limited thereto. The first active layer 520 may be a multi-layer. For example, if the first active layer 520 is a multi-layer, the multi-layer may be made of the same semiconductor material or the multi-layer may be made of two or more different semiconductor materials. You can also configure it.

Referring to FIGS. 6A to 6E , a gate insulating layer 602 may be disposed on a portion of the top surface of the first active layer 520 . The gate insulating layer 602 may include a first gate insulating layer portion 602a, a second gate insulating layer portion 602b, and a third gate insulating layer portion 602c.

Referring to FIGS. 6A to 6E, the first gate insulating layer portion 602a is disposed on the first end of the first active layer 520, among the first and second ends of the first active layer 520. For example, the first gate insulating layer portion 602a may be disposed while covering the first end of the first active layer 520.

The second gate insulating layer portion 602b may be disposed on the second end of the first active layer 520. For example, the second gate insulating layer portion 602b may be disposed on the second end of the first active layer 520. It can be arranged while covering the end.

Referring to FIGS. 6A to 6E , the first gate insulating layer portion 602a and the second gate insulating layer portion 602b may not overlap the channel region 525 of the first active layer 520 . The third gate insulating layer portion 602c may be located on the channel region 525 of the first active layer 520.

In the process of forming the first to third gate insulating film portions 602a, 602b, and 602c, a portion of the first active layer 520 may be made into a conductor.

Specifically, in the process of forming the first to third gate insulating film portions 602a, 602b, and 602c shown in FIGS. 6A to 6E, the first to third gate insulating film portions 602a, 602b, and 602c do not overlap. An area of the first active layer 520 may be conductive.

In addition, the structure of the first active layer 520 according to embodiments of the present disclosure is not limited to this, and the first active layer 520 overlaps the first to third gate insulating film portions 602a, 602b, and 602c. ) can also be made conductive.

In other words, the first active layer 520 according to embodiments of the present disclosure has a structure in which the area that does not overlap the gate insulating film 602 is conductive, or the first active layer 520 has a structure that does not overlap the gate insulating film 602. The overlapping area and a portion of the area overlapping with the gate insulating film 602 may also have a conductive structure.

The conductive area of the first active layer 520 may be made conductive through a patterning process of the gate insulating layer 602. However, the first active layer 520 according to an embodiment of the present invention may be made into a conductor through a doping (or ion implant) process rather than a patterning process.

For example, with photoresist remaining on the gate insulating film 602 patterns shown in FIGS. 6A to 6E and no photoresist remaining in the remaining areas, the photoresist is removed through a dry etching process. As the material of the gate insulating layer 602 in the missing area is removed, some areas of the first active layer 520 may become conductive.

The height of the above-mentioned photoresist can be adjusted in each area using a halftone mask, and the photoresist remaining on the substrate 600 can be removed after some areas of the first active layer 520 have been made conductive. there is.

This first active layer 520 may include a non-conductive channel region 523, and the channel region 523 overlaps the gate insulating film 602 and the third electrode 563, and the first and third electrodes 523 It may be the entire area or a partial area that does not overlap with the two electrodes 551 and 552.

The gate insulating film 602 located on the channel region 523 of the first active layer 520 may have a structure patterned on the first active layer 520 as shown in FIGS. 6A to 6E. Embodiments of the disclosure are not limited to this, and the gate insulating layer 602 may be disposed on the entire surface of the first active layer 520.

Hereinafter, for convenience of explanation, the description will focus on the patterned structure of the gate insulating film 602 disposed on the first active layer 520, as shown in FIGS. 6A to 6E.

Referring to FIGS. 6A to 6E , a first electrode 551 and a second electrode 552 may be disposed on the substrate 600 on which the gate insulating film 602 is disposed.

The first electrode 551 may be electrically connected to the first region 521 of the first active layer 520. The second electrode 552 may be electrically connected to the second region 521 of the first active layer 520.

Each of the first electrode 551, the second electrode 552, and the third electrode 563 may be a single layer or a multilayer. For example, each of the first electrode 551, the second electrode 552, and the third electrode 563 is made of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or molybdenum. It may include titanium (MoTi), etc.

When at least one of the first electrode 551, the second electrode 552, and the third electrode 563 is a multilayer, the first electrode 551, the second electrode 552, and the third electrode At least one of (563) may include a lower electrode and an upper electrode that are electrically connected to each other.

The lower electrode may include a first metal, and the upper electrode may include a second metal different from the first metal. For example, the first metal may include molybdenum (Mo), titanium (Ti), or molybdenum/titanium (MoTi). The second metal may include copper (Cu) or aluminum (Al). Hereinafter, the first metal is molybdenum titanium (MoTi) and the second metal is copper (Cu).

Referring to FIGS. 6A to 6E , the first electrode 551 may be located on at least a portion of the top surface and a portion of the side surface of the first gate insulating layer portion 602a. The second electrode 552 may be located on at least a portion of the top surface and a portion of the side surface of the second gate insulating film portion 602b.

Referring to FIGS. 6A to 6E, the buffer layer 601 disposed on the substrate 600 may be a single layer or a multilayer. For example, the buffer layer 601 may include various insulating film materials such as silicon nitride (SiNx) and silicon dioxide (SiO2).

When the buffer layer 601 is a multi-layer, the buffer layer 601 may include a first buffer layer 601a and a second buffer layer 601b disposed on the first buffer layer 601a. In this case, for example, the first buffer layer may be silicon nitride (SiNx), and the second buffer layer 601b may be silicon dioxide (SiO2). Alternatively, the first buffer layer 601a may be silicon dioxide (SiO2), and the second buffer layer 601b may be silicon nitride (SiNx).

The first active layer 520, the first electrode 551, the second electrode 552, and the third electrode 563 of the transistor (TR) may be disposed on the buffer layer 601.

6A to 6E, in the display panel 110 of the display device 100 according to embodiments of the present disclosure, the light shield 510 is located between the substrate 600 and the buffer layer 601 and is a first It may overlap the channel region 523 of the active layer 520.

The light shield 510 includes a first electrode 551, a second electrode 552, and a third electrode 563, each of which is made of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or It may include molybdenum and titanium (MoTi).

This light shield 510 may be a single layer or multiple layers.

As shown in FIGS. 6A to 6E , when the light shield 510 is multi-layered, the light shield 510 may include a lower light shield and an upper light shield on the lower light shield.

The lower light shield may include a first metal (eg, MoTi) included in the first lower electrode, the second lower electrode, and/or the third lower electrode. The upper light shield may include a second metal (eg, Cu) included in the first upper electrode, the second upper electrode, and/or the third upper electrode. For example, the first metal may include molybdenum (Mo), titanium (Ti), or molybdenum/titanium (MoTi). The second metal may include copper (Cu) or aluminum (Al).

Referring to FIGS. 6A to 6E , the first electrode 551 or the second electrode 552 may be connected to the light shield 510 through a through hole in the buffer layer 601 and the gate insulating layer 602. Accordingly, the light shield 510 may be electrically connected to the first node N1 of the driving transistor DRT (see FIG. 4). For example, the second electrode 552 may be electrically connected to the light shield 510.

A first insulating film 603 may be disposed on the substrate 600 on which the first and second electrodes 551 and 552 of the transistor TR are disposed.

The first insulating film 603 may include various insulating film materials such as silicon nitride (SiNx) and silicon dioxide (SiO2).

Referring to FIGS. 6A to 6E , the first insulating layer 603 may include a first hole CH1. The first hole CH1 may overlap the channel region 523 of the first active layer 520.

Referring to FIGS. 6A to 6E , a second insulating film 604 including a second hole CH2 may be disposed on the first insulating film 603 including the first hole CH1. The second insulating film 603 may include an organic insulating material.

However, the embodiments of the present invention are not limited to this, and the second insulating film 602 may not be disposed on the first insulating film 603 as shown in FIG. 6B.

Referring to FIGS. 6A and 6C to 6E, the second hole CH2 may overlap the first hole CH1.

For example, as shown in FIGS. 5, 6A, and 6C to 6E, the second hole CH2 may overlap the entire first hole CH1, but embodiments of the present disclosure are limited thereto. No, a portion of the second hole CH2 may overlap with a portion of the first hole CH1.

Referring to FIGS. 5, 6A, and 6C to 6E, the area of the second hole CH2 may be larger than the area of the first hole CH1. Accordingly, as shown in FIGS. 6A and 6C to 6E, there is a step between the first insulating film 603 and the second insulating film 604 in the area where the first hole CH1 and the second hole CH2 are disposed. may exist.

A third electrode 563 may be disposed on the second insulating film 602.

6A, 6C to 6E, the third electrode 563 is disposed on a portion of the upper surface of the second insulating film 604 and may be disposed in the first hole CH1 and the second hole CH2. there is.

The third electrode 563 may overlap the channel region 523 of the first active layer 520 within the first and second holes CH1 and CH2. Additionally, the third electrode 563 may contact at least a portion of the upper surface of the gate insulating layer 602 disposed on the first active layer 520.

The third electrode 563 may overlap not only the channel region 523 of the first active layer 520 but also at least a portion of the first region 521 and at least a portion of the second region 522 .

The third electrode 563 is a part of the upper surface of the second insulating film 604 around the second hole CH2, the side of the second insulating film 604 where the second hole CH2 is located, and the second hole CH2. It may be in contact with a portion of the top surface of the gate insulating layer 602 and the side of the first insulating layer 603 provided with the overlapping first hole CH1.

When a step exists between the first insulating film 603 and the second insulating film 604 in the area where the first hole (CH1) and the second hole (CH2) are disposed, the surface area of the third electrode 563 is expanded. , light passing through the first and second insulating films 603 and 604 can be effectively blocked.

This third electrode 563 may serve as a gate electrode of the transistor TR.

Referring to FIG. 6B , when the second insulating film 604 is not disposed on the first insulating film 603, the third electrode 563 may be disposed on the first insulating film 603.

Referring to FIG. 6B, the third electrode 563 is disposed on a portion of the upper surface of the first insulating film 603 and may be disposed within the first hole CH1.

The third electrode 563 may overlap the channel region 523 of the first active layer 520 within the first hole CH1. Additionally, the third electrode 563 may contact at least a portion of the upper surface of the gate insulating layer 602 disposed on the first active layer 520.

The third electrode 563 may have at least one step due to the first hole CH1 provided in the first insulating film 603. Accordingly, the surface area of the third electrode 563 can be expanded and light passing into the first insulating film 603 can be easily blocked.

Referring to FIGS. 6A to 6E , the third electrode 563 of the display device according to embodiments of the present disclosure may have various structures.

For example, as shown in FIGS. 6A to 6C, the third electrode 563 may be composed of a single layer. In this case, the single-layer third electrode 563 may include a metal material.

Additionally, as shown in FIG. 6D, the third electrode 563 may have a double-layer structure. In this case, the third electrode 563 may include a first gate electrode layer 563a disposed on the second insulating film 604 and a second gate electrode layer 563b disposed on the first gate electrode layer 563a. there is.

Here, the first gate electrode layer 563a may include a transparent conductive material, and the second gate electrode layer 563b may include a metal material. Additionally, the first gate electrode layer 563a may be formed through the same process as the pixel electrode 570 disposed on the second insulating film 604.

Additionally, as shown in FIG. 6E, the third electrode 563 may have a triple-layer structure. In this case, the third electrode 563 includes a first gate electrode layer 563a disposed on the second insulating film 604, a second gate electrode layer 563b disposed on the first gate electrode layer 563a, and a second gate electrode layer 563a. It may include a third gate electrode layer 563c disposed on the electrode layer 563b.

Here, the first gate electrode layer 563a may include a transparent conductive material, the second gate electrode layer 563b may include a metal material, and the third gate electrode layer 563c may include a transparent conductive material. there is. In addition, the triple-layer third electrode 563 can be formed through the same process as the pixel electrode 570. In this case, the pixel electrode 570 is also formed in a three-layer structure (including 570a, 570b, and 570c). It can be made of a triple-layer structure.

6A, 6C to 6E, the first insulating film 603 and the second insulating film 604 further include a contact hole exposing a portion of the upper surface of the second electrode 552 of the transistor (TR). It can be included.

Referring to FIG. 6B, the first insulating layer 603 may include a contact hole exposing a portion of the top surface of the second electrode 552 of the transistor TR.

Referring to FIGS. 6A to 6E , the first insulating film 603 may be disposed in the emission area (EA) and the non-emission area (NEA).

Referring to FIGS. 6A and 6C to 6E , the second insulating film 604 may be disposed in a portion of the emission area EA or may not be disposed in a portion of the non-emission area NEA.

A pixel electrode 570 (anode electrode) may be disposed on the first insulating film 603 and the second insulating film 604.

The pixel electrode 570 may include a reflective electrode, but embodiments of the present disclosure are not limited thereto. For example, the pixel electrode 570 may include a transparent conductive material.

Specifically, the pixel electrode 570 in FIGS. 6A to 6D is made of a single layer and may include a transparent conductive material. Additionally, the pixel electrode 570 of FIG. 6E may be made of multiple layers including a first layer 570a, a second layer 570b, and a third layer 570c. The first and third layers 570a and 570c of the pixel electrode 570 may include a transparent conductive material, and the second layer 570b may include a metal material.

Referring to FIGS. 6A to 6E, the pixel electrode 570 is connected to the transistor (TR) through the first and second insulating films 603 and 604 or a contact hole provided in the first insulating film 603 in the non-emission area (NEA). ) may be in contact with at least a portion of the upper surface of the second electrode 552. These pixel electrodes 570 may be arranged to extend from the non-emissive area (NEA) to the emissive area (EA).

A bank 670 may be disposed on the substrate 600 on which the pixel electrode 570 is disposed. The bank 670 may be disposed in the non-emissive area (NEA) of the active area and not in the emissive area (EA).

Meanwhile, FIGS. 6A to 6E illustrate a structure in which the light emitting area EA does not overlap the transistor TR and the storage capacitor Cst disposed on the substrate 600, but embodiments of the present disclosure are limited thereto. That is not the case.

For example, the light emitting area EA may be arranged to overlap at least one of the transistor TR, the storage capacitor Cst, and the wiring arranged on the substrate 600. In this case, light emitted from the organic light emitting device (OLED) may be emitted in the direction in which the buffer layer 601 is stacked on the substrate 600.

An organic layer 680 including a light-emitting layer may be disposed on the substrate 670 on which the bank 670 is disposed, and a common electrode 690 (cathode electrode) may be disposed on the organic layer 680.

The common electrode 690 may include a transparent conductive material, but embodiments of the present disclosure are not limited thereto. For example, when the pixel electrode 570 does not include a reflective electrode, the common electrode 690 may include a reflective electrode.

Additionally, in FIGS. 6A to 6E , the common electrode 690 is shown as a single-layer structure, but it may also have a multi-layer structure. In this case, at least the different layers may contain different materials.

In the emission area EA, an organic layer 680 may be disposed on the top surface of the pixel electrode 570, and a common electrode 690 may be disposed on the organic layer 680.

The light emitted from the organic light emitting device (OLED) including the pixel electrode 570, the organic layer 680, and the common electrode 690 is directed to the direction in which the light shield 510 is stacked on the substrate 600 or the substrate 600. The light may be emitted in a direction opposite to the direction in which the light shield 510 is stacked. However, the description below will focus on the structure in which light emitted from the organic light emitting device (OLED) is emitted in the direction in which the light shield 510 is stacked on the substrate 600.

In this case, a portion of the light emitted from the organic light emitting device (OLED) may pass through a plurality of insulating films disposed on the substrate 600 and reach the first active layer 520 of the transistor (TR).

When light is incident on the first active layer 520, the characteristics of the transistor TR including the first active layer 520 may deteriorate.

Referring to FIGS. 6A to 6E , in the display device according to the embodiments of the present disclosure, the third electrode 563 disposed on the first active layer 520 emits light in the direction of the first active layer 520. By blocking, there is an effect of significantly reducing the amount of light flowing into the first active layer 520.

Specifically, referring to FIGS. 6A and 6C to 6E, the third electrode 563 is formed on the upper part of the channel region 523 of the first active layer 520 within the first and second holes CH1 and CH2. In addition to overlapping, the third electrode 563 is disposed on the sides of the first and second insulating films 603 and 604 within the first and second holes CH1 and CH2, and By being disposed on a portion of the upper surface of the peripheral second insulating film 604, the third electrode 563 has the effect of blocking light traveling in the lateral direction of the first and second insulating films 603 and 604. .

Referring to FIG. 6B, the third electrode 563 overlaps the top of the channel region 523 of the first active layer 520 within the first hole CH1, and the first electrode 563 overlaps the top of the channel region 523 of the first active layer 520 within the first hole CH1. By being disposed on the side of the insulating film 603 and also on a part of the upper surface of the first insulating film 603 located around the first hole CH1, the third electrode 563 is oriented in the side direction of the first insulating film 603. It can block the light going on.

Referring to FIGS. 6A to 6E , the second active layer 530 and the light shield 510 may be disposed in the non-emission area (NEA) to overlap a portion of the common electrode 570 .

The light shield 510, the second active layer 530, and the common electrode 570 that overlap each other may serve as electrodes of the storage capacitor Cst.

Referring to FIGS. 6A to 6E, the story capacitor Cst may be disposed in the non-emission area NEA.

The storage capacitor Cst may include a first storage capacitor electrode, a second storage capacitor electrode disposed on the first storage capacitor electrode, and a third storage capacitor electrode disposed on the second storage capacitor electrode.

The first storage capacitor electrode may be the light shield 510, the second storage capacitor electrode may be the second active layer 530, and the third storage capacitor electrode may be the pixel electrode 570.

The area of the second active layer 530 that serves as the second storage capacitor electrode may be a conductive area.

Referring to FIGS. 6A to 6E, a buffer layer 601 is disposed on the first storage capacitor electrode (e.g., a light shield), and a second storage capacitor electrode (e.g., a second active layer) is disposed on the buffer layer 601. You can. A first insulating film 603 may be disposed on the second storage capacitor electrode, and a third storage capacitor electrode (eg, a pixel electrode) may be disposed on the first insulating film 603.

In this way, the storage capacitor Cst includes three storage capacitor electrodes, so the capacity of the storage capacitor can be increased.

Referring to FIGS. 6A to 6E , the first insulating film 603 may include regions having different thicknesses.

For example, the first insulating layer 603 has a first thickness T1 in at least a portion of the area overlapping the first active layer 520, and the second storage capacitor electrode (e.g., the second active layer 530) may have a second thickness T2 in at least a partial area overlapping with . The first and second thicknesses T1 and T2 may refer to the minimum length of the first insulating film 603 based on the direction in which the buffer layer 601 is stacked on the substrate 600.

Here, the second thickness T2 may be lower than the first thickness T1.

By forming the first insulating film 603 disposed on the first active layer 520 of the transistor TR to be thick, parasitic capacitance occurring between electrodes of the transistor TR can be reduced. In addition, the second thickness T2 of the first insulating film 603 disposed on the second active layer 530, which is the second storage capacitor electrode, becomes thinner than the first thickness T1, so that the storage capacitor Cst Capacity can be improved.

After forming the first insulating film 603 material on the substrate 600, the first insulating film 603 is formed into a region having a first thickness T1 and a second thickness through a dry etching process using a halftone mask. A region having (T2) may be provided.

As shown in FIGS. 6A to 6D, the third electrode 563 may overlap at least a portion of each of the first and second electrodes 551 and 552. By disposing the second insulating film 604 on the first insulating film 603 having the first thickness T1 and the first thickness T1 of the first insulating film 603, the first electrode 551 and the third electrode The distance between 563 and the second electrode 552 and the third electrode 563 may increase. Accordingly, parasitic capacitance occurring between the first electrode 551 and the third electrode 563 and between the second electrode 552 and the third electrode 563 can be reduced.

Referring to FIGS. 6A to 6E, the first thickness T1 may be thicker than 4000 Å, and the second thickness T2 may be thinner than 4000 Å, but the thickness of the first insulating film 603 according to embodiments of the present disclosure The thickness is not limited to this. Additionally, the thickness of the first insulating film 603 may be zero for gate modulation in a portion of the upper surface of the channel region 523.

In addition, referring to FIGS. 6A to 6E, the second insulating film 604 is not disposed between the second active layer 530, which is the second storage capacitor electrode, and the pixel electrode 570, which is the third storage capacitor electrode, The capacity of the storage capacitor (Cst) can be further increased.

In this way, as the capacity of the storage capacitor Cst including the first to third storage capacitor electrodes increases, the area of the storage capacitor electrodes increases to increase the capacity of the storage capacitor Cst, thereby increasing the area of the circuit area. You can prevent it from happening.

When the area of the circuit area increases, the area where the bank 670 is not placed, that is, the area of the light emitting area, may decrease. However, the display device according to embodiments of the present disclosure increases the area of the storage capacitor (Cst) electrodes. The capacity of the storage capacitor (Cst) can be increased without increasing it.

Next, with reference to FIGS. 7A to 7C and FIG. 8 , the structure of the display device according to embodiments of the present disclosure will be reviewed as follows.

7A to 7C are schematic cross-sectional views of display devices according to embodiments of the present disclosure. FIG. 8 is a diagram schematically showing the structure of storage capacitors disposed in at least one subpixel of a display device according to embodiments of the present disclosure.

In the description below, content (configuration, effects, etc.) that overlaps with the previously described embodiments may be omitted. Additionally, in the description described later, the same drawing number may be used for the drawing number of a configuration overlapping with the previously described embodiments.

7A to 7C differ only in the structure of the third electrode 563 and the pixel electrode 570, and the structures of the remaining components may be the same.

Specifically, the third electrode 563 of FIG. 7A may be made of a single layer containing a metal material, and the pixel electrode 570 may be made of a single layer containing a transparent conductive material.

The third electrode 563 in FIG. 7B may be made of a double layer, and the third electrode 563 includes a first gate electrode layer 563a containing a transparent conductive material and a second gate electrode layer 563b containing a metal material. It includes, and the pixel electrode 570 may have a single-layer structure containing a transparent conductive material.

The third electrode 563 in FIG. 7C may be made of a triple layer, and the third electrode 563 includes a first gate electrode layer 563a containing a transparent conductive material, and a second gate electrode layer 563b containing a metal material. and a third gate electrode layer 563c containing a transparent conductive material. In addition, the pixel electrode 570 is a triple layer including a first layer 570a including a transparent conductive material, a second layer 570b including a metal material, and a third layer 570c including a transparent conductive material. It can be composed of a structure of .

Referring to FIGS. 7A to 7C , an auxiliary electrode may be disposed on at least one active layer among a plurality of active layers disposed in a subpixel of a display device according to embodiments of the present disclosure.

As shown in FIGS. 7A to 7C , the transistor TR disposed on the display panel 110 according to embodiments of the present disclosure includes the first auxiliary electrode AUX1 on the first region 521 and the second region. It may further include a second auxiliary electrode (AUX2) on (522).

The first auxiliary electrode (AUX1) is located between the first area 521 and the first electrode 551 and can electrically connect the first area 521 and the first electrode 551. The second auxiliary electrode AUX2 is located between the second area 522 and the second electrode 552 and can electrically connect the second area 522 and the second electrode 552.

The conductive material included in each of the first auxiliary electrode (AUX1) and the second auxiliary electrode (AUX2) may include the metal included in the first electrode 551, the second electrode 552, or the third electrode 563. You can. For example, the metal included in the first electrode 551, the second electrode 552, or the third electrode 563 is copper (Cu), aluminum (Al), molybdenum (Mo), and titanium (Ti). , or molybdenum titanium (MoTi).

When the first electrode 551, the second electrode 552, or the third electrode 563 has a double metal structure, the conductive material included in each of the first auxiliary electrode (AUX1) and the second auxiliary electrode (AUX2) may include a first metal (eg, MoTi) included in the first lower electrode, the second lower electrode, or the third lower electrode.

7A to 7C illustrate a structure in which the first and second auxiliary electrodes AUX1 and AUX2 are a single layer, but embodiments of the present disclosure are not limited thereto.

When the first and second auxiliary electrodes (AUX1, AUX2) have a multi-layer structure, the lower layer may include a transparent conductive material, a transparent conductive oxide, nitrous oxide, or an organic material, and the upper layer may include a metal material. The embodiments are not limited thereto.

Also, referring to FIGS. 7A to 7C, the first active layer 520 is formed between the third region 524 and the second region 522 disposed between the first region 521 and the channel region 523 and the channel. It may further include a fourth area 245 disposed between the areas 523.

The third region 524 and fourth region 525 of the first active layer 520 may be conductive regions. For example, the third region 524 and the fourth region 525 may be made into conductors during the patterning process of the gate insulating film 602, but embodiments of the present disclosure are not limited thereto.

Additionally, the display device according to embodiments of the present disclosure may include a third auxiliary electrode (AUX3) and a fourth auxiliary electrode (AUX4) disposed on the second active layer 731.

The third and fourth auxiliary electrodes AUX3 and AXU4 are disposed on the same layer as the first and second auxiliary electrodes AUX1 and AUX2 and may include the same material.

Referring to FIGS. 7A to 7C , a display device according to embodiments of the present disclosure may have a region including different storage capacitor electrodes of the storage capacitor Cst within one subpixel.

For example, referring to FIGS. 7A to 7C and FIG. 8 , in the display device according to embodiments of the present disclosure, at least one subpixel includes a first storage capacitor (Cst1) and a second storage capacitor (Cst2). can do.

7A to 7C and 8, the first storage capacitor (Cst1) includes a light shield 510 that is the first lower storage capacitor electrode, a third auxiliary electrode (AUX3) that is the first middle storage capacitor electrode, and the first It may include a gate metal layer 570 and a pixel electrode 570, which are upper storage capacitor electrodes.

Specifically, a buffer layer 501 may be disposed on the light shield 510, which is the first lower storage capacitor electrode, and a second active layer 530 may be disposed on the buffer layer 501. A third auxiliary electrode (AUX3), which is a second intermediate storage capacitor electrode, may be disposed on the top. A gate insulating layer 602 may be disposed on the third auxiliary electrode AUX3, and a gate metal layer 751, which is a first upper storage capacitor electrode, and a pixel electrode 570 may be disposed on the gate insulating layer 602.

The pixel electrode 570 may be disposed on the gate metal layer 751, and the gate metal layer 751 may be disposed on the same layer as the first and second electrodes 551 and 552 of the transistor TR.

7A to 7C and 8, the second storage capacitor Cst2 includes a light shield 510 that is the second lower storage capacitor electrode, a fourth auxiliary electrode (AUX4) that is a second middle storage capacitor electrode, and a second electrode. It may include a pixel electrode 570, which is an upper storage capacitor electrode.

Specifically, a buffer layer 601 is disposed on the light shield 510, which is the second lower storage capacitor electrode, a second active layer 530 is disposed on the buffer layer 601, and a second active layer 530 is disposed on the second lower storage capacitor electrode. A fourth auxiliary electrode (AUX4), which is an intermediate storage capacitor electrode, may be disposed. A first insulating film 603 may be disposed on the fourth auxiliary electrode AUX4, and a pixel electrode 570, which is a second upper storage capacitor electrode, may be disposed on the first insulating film 603.

The first storage capacitor Cst1 and the second storage capacitor Cst2 may be connected in parallel, and through this, the capacity of the storage capacitor Cst may be increased.

Accordingly, in order to increase the capacity of the storage capacitor Cst, there may be no need to expand the area of the storage capacitor Cst and reduce the position of the opening (eg, light emitting area). In other words, the capacity of the storage capacitor (Cst) can be increased while maintaining the area of the opening.

9A and 9B are diagrams showing a cross-sectional structure of a display device according to embodiments of the present disclosure.

In the description below, content (configuration, effects, etc.) that overlaps with the previously described embodiments may be omitted. Additionally, in the description described later, the same drawing number may be used for the drawing number of a configuration overlapping with the previously described embodiments.

9A and 9B, the third electrode 563 of the display panel according to embodiments of the present disclosure includes a first gate electrode layer 963a, a second gate electrode layer 963b, and a third gate electrode layer 963c. may include.

Specifically, referring to FIGS. 9A and 9B , a first electrode 551, a second electrode 552, and a first gate electrode layer 963a may be disposed on the gate insulating film 602. The first gate electrode layer 963a is disposed on the same layer as the first electrode 551 and the second electrode 552 and may include the same material.

As shown in FIGS. 9A and 9B, the first electrode 551 is disposed on the first gate insulating layer portion 602a, the second electrode 5520 is disposed on the second gate insulating layer portion 602b, and the third electrode 5520 is disposed on the first gate insulating layer portion 602a. A first gate electrode layer 963a may be disposed on the gate insulating layer portion 602c.The first gate electrode layer 963a may be disposed to contact the upper surface of the third gate insulating layer portion 602c.

The width of the first gate electrode layer 963a may correspond to the width of the channel region 523 of the first active layer 520, but the width of the channel region 523 according to embodiments of the present disclosure is not limited to this. no. Here, the width of the first gate electrode layer 963a and the width of the channel region 523 are determined based on the direction perpendicular to the direction in which the buffer layer 601 is stacked on the substrate 600. This may refer to the minimum length of each area 523.

Referring to FIGS. 9A and 9B, the first active layer 520 is at least partially conductive or entirely conductive, like the first active layer 520 shown in FIGS. 6A to 6E. It may have a structure that includes second areas 521 and 522, and a channel area 523 is disposed between the first area 521 and the second area 522.

In FIG. 9A, a structure in which the entire first region 521 and the second region 522 of the first active layer 520 are conductive is shown as an example, but the structure is not limited thereto, and as shown in FIG. 6C, A structure in which only a portion of the first region 521 and the second region 522 of the first active layer 520 are conductive may be applied. On the contrary, in FIG. 9B, a structure in which a portion of each of the first region 521 and the second region 522 of the first active layer 520 is conductive is shown as an example, but the structure is not limited thereto, and the structure in FIGS. 6A and 6A and FIG. As shown in 6b, a structure in which the entire first region 521 and the second region 522 of the first active layer 520 are conductive may be applied.

A first insulating film 603 including a first hole CH1 may be disposed on the substrate 600 on which the first electrode 551, the second electrode 552, and the first gate electrode layer 963a are disposed.

Referring to FIGS. 9A and 9B , the first insulating film 603 may be disposed to expose a portion of the top surface of the first gate electrode layer 963a. A portion of the top surface of the first gate electrode layer 963a may be exposed through the first hole CH1 of the first insulating film 603.

A second insulating layer 604 including a second hole (CH2) overlapping the first hole (CH1) may be disposed on the first insulating layer (603).

The top surface of the first gate electrode layer 963a exposed through the first hole CH1 may also be exposed through the second hole CH2 of the second insulating film 604.

A second gate electrode layer 963b may be disposed inside the first hole CH1 and the second hole CH2 and on the top surface of the second insulating film 602.

Specifically, referring to FIGS. 9A and 9B, the second gate electrode layer 963b is disposed on the upper surface of the first gate electrode layer 963a exposed through the first and second holes CH1 and CH2, and the first and a portion of the upper surface of the second insulating film 604 disposed on the side surfaces of the first and second insulating films 603 and 604 within the second holes CH1 and CH2 and surrounding the second hole CH2. It can also be placed in .

That is, a portion of the second gate electrode layer 963b may be in contact with a portion of the upper surface of the first gate electrode layer 963a.

Referring to FIGS. 9A and 9B , the second gate electrode layer 963b may be disposed on the same layer as the pixel electrode 570 and may include the same material. For example, the material of the second gate electrode layer 963b may include a transparent conductive material.

A third gate electrode layer 963c may be disposed on the second gate electrode layer 963b.

The third gate electrode layer 963c may include a metal material. For example, it may include copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or molybdenum/titanium (MoTi).

The second and third gate electrode layers 963b and 963c are formed by forming the material of the second gate electrode layer 963b on the substrate 600 on which the second insulating film 604 is disposed. The material of the third gate electrode layer 963c may be formed thereon.

Afterwards, the third gate electrode layer 963c is formed by patterning the material of the third gate electrode layer 963c through a photolithography process using a halftone mask, and then the material of the second gate electrode layer 963b is patterned. A second gate electrode layer 963b can be formed.

Therefore, by forming the first gate electrode layer 963a, the second gate electrode layer 963b, and the third gate electrode layer 963c without increasing the number of masks, the first to third gate electrode layers 963a and 963b can be formed through a simple process. , 963c) can be formed.

In this way, the third gate electrode layer 963c containing a metal material is disposed inside the first and second holes CH1 and CH2 and overlaps the first active layer 520, and the first and second insulating films 603 , 604), it is possible to prevent light from passing through the first and second insulating films 603 and 604 and entering the first active layer 520. Accordingly, it is possible to prevent the characteristics of the transistor TR from being deteriorated due to internal light.

Additionally, referring to FIG. 9B, the third electrode 563 may further include a fourth gate electrode layer 963d disposed on the third gate electrode layer 963c.

The fourth gate electrode layer 963d may include a transparent conductive material.

Referring to FIG. 9B, a portion of the third electrode 563, which serves as the gate electrode of the transistor TR, may be formed through the same process as the pixel electrode 570.

Referring to Figure 9b, the pixel electrode 570 is disposed on the first pixel electrode layer 971a, the second pixel electrode layer 971b disposed on the first pixel electrode layer 971a, and the second pixel electrode layer 971b. It may include a third pixel electrode layer 971c.

Referring to FIG. 9B, the second to fourth gate electrode layers 963b, 963c, and 963d of the third electrode 563 are disposed on the same layer as the first to third pixel electrode layers 971a, 971b, and 971c and are performed in the same process. can be formed.

Accordingly, each of the first pixel electrode layer 971a and the third pixel electrode layer 971c may include a transparent conductive material, and the second pixel electrode layer 971b may include a metal material.

By forming the second to fourth gate electrode layers 963b, 963c, and 963d of the third electrode 563 and the first to third pixel electrode layers 971a, 971b, and 971c through the same process, the process can be simplified. It works.

Additionally, referring to FIG. 9B, the storage capacitor Cst includes a light shield 510 that is the first storage capacitor electrode, a conductive second active layer 530 that is the second storage capacitor electrode, and a pixel that is the third storage capacitor electrode. It may include an electrode 570.

By using the third storage capacitor electrode included in the storage capacitor Cst of the display device according to embodiments of the present disclosure as the pixel electrode 570 including the first to third pixel electrode layers 971a, 971b, and 971c. , since the process of forming the third storage capacitor electrode is not added, the process can be simplified. Additionally, since the light shield 510 functions as a first storage capacitor electrode and blocks light incident from the back of the substrate 600, a separate configuration and process for light blocking functions may not be added.

Next, the structure of the display device according to embodiments of the present disclosure is further reviewed with reference to FIGS. 10A to 10D as follows.

In the description below, content (configuration, effects, etc.) that overlaps with the previously described embodiments may be omitted. Additionally, in the description described later, the same drawing number may be used for the drawing number of a configuration overlapping with the previously described embodiments.

10A to 10D are diagrams illustrating the structure of a display device according to embodiments of the present disclosure.

First, referring to FIG. 10A, the first electrode, second electrode, and third electrode disposed in the subpixel of the display device according to embodiments of the present disclosure may be disposed on the same layer and may include the same material.

Specifically, referring to FIG. 10A, a gate insulating layer 602 including a plurality of gate insulating layer portions may be disposed on the first active layer 520.

Meanwhile, in FIG. 10A, the gate insulating film 602 shows a structure including a plurality of gate insulating film portions, but embodiments of the present disclosure are not limited thereto, and the channel region 523 of the first active layer 620 and It may also be composed of only the overlapping third gate insulating layer portion 602c.

As shown in FIG. 10A, when the gate insulating film 602 includes first to third gate insulating film portions 602a, 602b, and 602c, the first region 521 and the first region 521 of the first active layer 520 Each of the two regions 522 may include a conductive region and a non-conductive region. For example, the area where the first region 521 and the second region 522 do not overlap with the gate insulating film 602 is a conducting area, and the area overlapping with the gate insulating film 602 is a non-conducting area. It can be included.

On the other hand, when the gate insulating layer 602 includes only the second gate insulating layer portion 602c disposed on the channel region 523 of the first active layer 520, the first and second gate insulating layers 602c of the first active layer 520 Each of the two regions 521 and 522 may be a conductive region.

A first insulating film 603 having a first hole CH1 will be disposed on the gate insulating film 602, and a second insulating film 604 having a second hole CH2 will be disposed on the first insulating film 603. You can.

Referring to FIG. 10A , the first hole CH1 may overlap the third gate insulating layer portion 602c that overlaps the channel region 523 of the first active layer 520. That is, the first insulating film 603 may be disposed to expose at least a portion of the top surface of the third gate insulating film portion 602c.

Referring to FIG. 10A , the first insulating layer 603 may have at least one step within the first hole CH1. Accordingly, the width of the first hole CH1 may include regions having at least two different widths W1, W2, and W3.

A first electrode 551, a second electrode 552, and a third electrode 563 may be disposed on the first insulating film 603.

Referring to FIG. 10A, the first electrode 551 is connected to the first region 521 of the first active layer 520 through a contact hole provided in the first insulating film 551 and the first gate insulating film portion 602a. can be contacted. Additionally, the first electrode 551 may be in contact with the light shield 510 through a contact hole provided in the first insulating film 551, the first gate insulating film portion 602a, and the buffer layer 601.

The second electrode 552 may be in contact with the second region 522 of the first active layer 520 through a contact hole provided in the first insulating layer 551 and the second gate insulating layer portion 602b.

The third electrode 563 may be disposed in the first hole CH1 of the first insulating film 603. Within the first hole CH1, the third electrode 563 may contact a portion of the upper surface of the third gate insulating layer portion 602c.

This third electrode 563 may serve as a gate electrode of the transistor TR and at the same time prevent internal light from being incident on the first active layer 520.

Referring to FIG. 10A , the second insulating film 604 may be disposed on a portion of the upper surface of the first insulating film 603 where the first to third electrodes 551, 552, and 563 are disposed.

The second insulating film 604 may be disposed to expose at least a portion of the upper surface of each of the first to third electrodes 551, 552, and 563.

The second insulating film 604 includes a second hole (CH2) overlapping the first hole (CH1), and the second insulating film 604 is connected to the upper surface of the third electrode 563 through the second hole (CH2). At least part of it can be exposed.

Referring to FIG. 10A , the second insulating film 604 may include a contact hole exposing a portion of the top surface of the second electrode 552.

The pixel electrode 570 may be in contact with a portion of the upper surface of the second electrode 552 disposed on the first insulating film 603 through a contact hole in the second insulating film 604.

A bank 670 may be disposed on the first electrode 551, the second electrode 552, the third electrode 563, the pixel electrode 570, and the second insulating film 604.

The display device shown in FIGS. 10B to 10D is different from that of FIG. 10A only in the structure of the gate insulating film 602, the first electrode 551, the second electrode, the third electrode 563, and the pixel electrode 570. , the structure of the remaining configuration may be the same.

Specifically, in Figure 10a, the first electrode 551, the second electrode 552, the third electrode 563, and the pixel electrode 570 are shown as a single layer structure, but in Figures 10b to 10d, the first electrode (551), the third electrode 563 and the pixel electrode 570 have a multi-layer structure, and the pixel electrode 570 and the second electrode are shown as one body. In addition, in Figure 10a, the gate insulating film 602 shows a structure including the first to third gate insulating film portions 602, but in Figures 10b to 10d, the channel region 523 of the first active layer 520 and A structure including only the overlapping gate insulating layer 602 is shown.

The following description will focus on the structures of the first electrode 551, the third electrode 553, and the pixel electrode 570 shown in FIGS. 10B to 10D.

Referring to FIG. 10B, the first electrode 551, the third electrode 553, and the pixel electrode 570 may have a double-layer structure. For example, the first electrode 551 includes a first electrode layer 551a and a second electrode 551b, and the third electrode 553 includes first and second gate electrode layers 1063a and 1063b. , the pixel electrode 570 may include first and second pixel electrode layers 1071a and 1071b.

Specifically, referring to FIG. 10B , a first insulating layer 603 may be disposed on the substrate 600 on which the gate insulating layer 602 is disposed.

The first insulating layer 603 may be disposed to expose a portion of the upper surface of the gate insulating layer 602 disposed on the channel region 523 of the first active layer 520.

Referring to FIG. 10B, a first electrode 551, a third electrode 553, a pixel electrode 570, and a second insulating film 604 may be disposed on the first insulating film 603.

Referring to FIG. 10b, the first electrode 551 of the transistor (TR) includes a first electrode layer 551a disposed on the first insulating film 603, and a second electrode layer 551b disposed on the first electrode layer 551a. ) and a third electrode layer 551c disposed on the second electrode layer 551b.

Here, each of the first electrode layer 551a and the third electrode layer 551c may include a transparent conductive material. The second electrode layer 551b may include a metal material.

The third electrode 553 includes a gate insulating film 602, a first gate electrode layer 1063a disposed on the first insulating film 603, and a second gate electrode layer 1063b disposed on the first gate electrode layer 1063a. It can be included.

Here, the first gate electrode layer 1063a may include a transparent conductive material, and the second gate electrode layer 1063b may include a metal material.

The pixel electrode 570 includes a first pixel electrode layer 1071a disposed on the first insulating film 603 and the second insulating film 604, and a second pixel electrode layer 1071b disposed on the first pixel electrode layer 1071a. It can be included.

Here, the first pixel electrode layer 1071a may include a transparent conductive material, and the second pixel electrode layer 1071b may include a metal material.

The first electrode layer 1051a of the first electrode 551, the first gate electrode layer 1063a of the third electrode 563, and the first pixel electrode layer 1071a of the pixel electrode 570 include the same material and are the same. Can be placed on a layer.

In addition, the second electrode layer 1051b of the first electrode 551, the second gate electrode layer 1063b of the third electrode 563, and the second pixel electrode layer 1071b of the pixel electrode 570 include the same material. , can be placed on the same floor.

Accordingly, since the first electrode 551, the third electrode 563, and the pixel electrode 570 can be formed through the same process, the process can be simplified.

Additionally, referring to FIG. 10B, the first electrode 551 may be in contact with the conductive first region 521 of the first active layer 520 through a contact hole formed in the first insulating film 603.

The pixel electrode 570 is disposed in the entire emissive area (EA) and a portion of the non-emissive area (NEA), overlaps at least a portion of the second area 522 of the first active layer 520, and acts as a light shield ( 510) may also overlap with at least part of. This pixel electrode 570 is in contact with the second region 522 of the first active layer 520 through the contact hole of the first insulating film 603, and the contact hole of the first insulating film 603 and the buffer layer 601. By being in contact with the light shield 510 through , it can simultaneously serve as the second electrode of the transistor.

In addition, among the pixel electrodes 570, the first pixel electrode layer 1071a is disposed in the entire emitting area EA and part of the non-emitting area NEA, but the second pixel electrode layer 1071b is not disposed in the emitting area EA. and may be disposed only in a portion of the non-emission area (NEA). For example, referring to FIG. 10B, the second pixel electrode layer 1071b may be disposed only in an area that overlaps the second area 522 of the first active layer 520 and the light shield 510.

Next, referring to FIG. 10C, in the structure of FIG. 10B, the third electrode 563 may have a structure that further includes an additional gate electrode layer 1063d.

Specifically, referring to FIG. 10C, the first electrode 551 may have a double-layer structure, the third electrode 563 may have a triple-layer structure, and the pixel electrode 570 may have a double-layer structure.

The structure of the first electrode 551 and the pixel electrode 570 shown in FIG. 10C is the same as that of the first electrode 551 and the pixel electrode 570 shown in FIG. 10B, but the structure of the third electrode 563 is different from that of the third electrode 563. The structures may be different from each other.

Referring to FIG. 10C, the third electrode 563 includes an additional gate electrode layer 1063d, a first gate electrode layer 1063a disposed on the additional gate electrode layer 1063d, and a first gate electrode layer 1063a disposed on the first gate electrode layer 1063a. It may include 2 gate electrode layers 1063b.

Each of the additional gate electrode layer 1063d and the second gate electrode layer 1063b may include a metal material, and the first gate electrode layer 1063a may include a transparent conductive material.

The additional gate electrode layer 1063d of the third electrode 563 may be disposed on the gate insulating film 602 disposed on the channel region 523 of the first active layer 520.

A first insulating film 603 may be disposed on the additional gate electrode layer 1063d.

The first gate electrode layer 1063a and the second gate electrode layer 1063b of the third electrode 563 may be disposed on the first insulating film 603. As shown in FIG. 10C, the first and second gate electrode layers 1063a and 1063b may be disposed within the first hole CH1 of the first insulating film 603. Within the first hole CH1, the first gate electrode layer 1063a may be in contact with the top surface of the additional gate electrode layer 1063d.

Next, referring to FIG. 10D, a first electrode 551, a pixel electrode 570, and an overcoat layer 604 may be disposed on the first insulating film 603.

Referring to FIG. 10D, the first electrode 551 may have a triple-layer structure, the third electrode 553 may have a quadruple-layer structure, and the pixel electrode 570 may have a triple-layer structure. For example, the first electrode 551 includes first to third electrode layers 551a, 551b, and 551c, and the third electrode 553 includes first to fourth gate electrode layers 1063a, 1063b, 1063c, and 1063d. ), and the pixel electrode 570 may include first to third pixel electrode layers 1071a, 1071b, and 1071c.

Specifically, referring to FIG. 10D , the first gate electrode layer 1063a may be disposed on the gate insulating film 602. The first gate electrode layer 1063a may include a metal material.

A first insulating film 603 may be disposed on the substrate 600 on which the first gate electrode layer 1063a is disposed.

The first insulating film 603 may be disposed to expose a portion of the top surface of the first gate electrode layer 1063a. Referring to FIG. 10D, the first hole CH1 of the first insulating film 603 may overlap a portion of the upper surface of the first gate electrode layer 1063a.

Looking at FIG. 10D, a first electrode 551, a third electrode 553, a pixel electrode 570, and a second insulating film 604 may be disposed on the first insulating film 603.

Referring to FIG. 10D, the first electrode 551 of the transistor (TR) includes a first electrode layer 551a disposed on the first insulating film 603, and a second electrode layer 551b disposed on the first electrode layer 551a. ) and a third electrode layer 551c disposed on the second electrode layer 551b.

Here, each of the first electrode layer 551a and the third electrode layer 551c may include a transparent conductive material. The second electrode layer 551b may include a metal material.

The third electrode 553 includes an additional gate electrode layer 1063d, a first gate electrode layer 1063a disposed on the additional gate electrode layer 1063d, and a second gate electrode layer 1063b disposed on the first gate electrode layer 1063a. and a third gate electrode layer 1063c disposed on the second gate electrode layer 1063b.

Here, each of the additional gate electrode layer 1063d and the second gate electrode layer 1063b may include a metal material, and each of the first gate electrode layer 1063a and the third gate electrode layer 1063c may include a transparent conductive material.

The pixel electrode 570 includes a first pixel electrode layer 1071a disposed on the first insulating film 603 and the second insulating film 604, a second pixel electrode layer 1071b disposed on the first pixel electrode layer 1071a, and It may include a third pixel electrode layer 1071c disposed on the second pixel electrode layer 1071b.

Referring to FIG. 10D , each of the first to third pixel electrode layers 1071a, 1071b, and 1071c may be disposed throughout the entire emission area EA and may be disposed in a portion of the non-emission area NEA. Each of the first to third pixel electrode layers 1071a, 1071b, and 1071c may overlap a portion of the second region 521 of the first active layer 520 and may also overlap a portion of the light shield 510.

Each of the first pixel electrode layer 1071a and the third pixel electrode layer 1071c may include a transparent conductive material, and the second pixel electrode layer 1071b may include a metal layer.

The first electrode layer 1051a of the first electrode 551, the first gate electrode layer 1063a of the third electrode 563, and the first pixel electrode layer 1071a of the pixel electrode 570 include the same material and are the same. Can be placed on a layer.

The second electrode layer 1051b of the first electrode 551, the second gate electrode layer 1063b of the third electrode 563, and the second pixel electrode layer 1071b of the pixel electrode 570 include the same material and are the same. Can be placed on a layer. Each of the second electrode layer 1051b, the second gate electrode layer 1063b, and the second pixel electrode layer 1071b may include a metal material having low resistance and high reflectivity. For example, it may include any one of silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), and titanium (Ti), or at least one alloy thereof.

In addition, the third electrode layer 1051c of the first electrode 551, the third gate electrode layer 1063c of the third electrode 563, and the third pixel electrode layer 1071c of the pixel electrode 570 include the same material. , can be placed on the same floor.

Accordingly, the process of forming the first electrode 551, the third electrode 563, and the pixel electrode 570 can be simplified.

Referring to FIG. 10D, the pixel electrode 570 is disposed to overlap the light emitting area EA, and is connected to the first active layer 602 of the transistor TR through a contact hole provided in the first insulating layer 603. 2 may be contacted with area 522. Additionally, the pixel electrode 570 may be in contact with the light shield 510 through a contact hole provided in the buffer layer 601 and the first insulating layer 603.

That is, since the pixel electrode 570 contacts the first active layer 602 of the transistor and there is no need to form a separate second electrode that also contacts the pixel electrode 570, the structure of the transistor can be simplified, and the process can also be simplified. There is an effect that can be simplified.

Next, the manufacturing process of the display device according to embodiments of the present disclosure will be reviewed as follows.

FIGS. 11 to 21 are diagrams schematically showing the manufacturing process of the display device shown in FIG. 6C.

First, referring to FIG. 11 , a light shield 510 may be disposed on the substrate 600.

Afterwards, as shown in FIG. 12, the first buffer layer 601a is disposed on the substrate 600 on which the light shield 510 is disposed, and the second buffer layer 601b is disposed on the first buffer layer 601a. can be placed.

Referring to FIG. 12 , a first active layer pattern 1220 and a second active layer pattern 1221 may be disposed on the buffer layer 601 including the first and second buffer layers 601a and 601b. The first and second active layer patterns 1220 and 1221 may be formed by forming an active layer material on the buffer layer 601 and patterning it.

Next, referring to FIG. 13 , a gate insulating layer 602 may be disposed on the substrate on which the first and second active layer patterns 1220 and 1221 are disposed.

Multiple contact holes may be formed in the gate insulating film 602. Specifically, the gate insulating layer 602 may be formed with contact holes exposing a portion of the upper surface of the first active layer patterns 1220 and 1221 and a contact hole exposing a portion of the upper surface of the light shield 510. In the process of forming a contact hole through which the gate insulating layer 602 exposes a portion of the upper surface of the light shield 510, a contact hole may also be formed in the buffer layer 601 disposed below the gate insulating layer 602.

Additionally, the gate insulating layer 602 may be formed to expose the entire second active layer pattern 1221.

Thereafter, referring to FIG. 14 , a first electrode 551, a second electrode 552, and an electrode pattern 1463 may be formed on the gate insulating film 602 and the first active layer pattern 1220.

Specifically, an electrode material may be formed on the substrate 600 on which the gate insulating film 602 is disposed. The electrode material may include a metallic material.

A photoresist material may be formed on the electrode material. This photoresist material may be patterned to form a first photoresist pattern 1451, a second photoresist pattern 1452, and a third photoresist pattern 1453.

The photoresist material may be patterned through a halftone mask, and the height of the first and second photoresist patterns 1451 and 1452 formed after patterning may be higher than the height of the third photoresist pattern 1453.

Afterwards, the electrode material can be patterned using the first to third photoresist patterns 1451, 1452, and 1453 as masks. By patterning the electrode material, a first electrode 551 is formed under the first photoresist pattern 1451, a second electrode 552 is formed under the second photoresist pattern 1452, and a third photoresist is formed. An electrode pattern 1463 may be formed below the pattern 1453.

Thereafter, referring to FIG. 15 , the third photoresist pattern 1453 disposed on the electrode pattern 1463 may be removed.

The third photoresist pattern 1453 disposed on the electrode pattern 1463 can be removed through a dry etching process, and the first and second photoresist patterns have a height higher than the height of the third photoresist pattern 1453. (1451, 1452) Each is not removed.

However, in the process of removing the third photoresist pattern 1453, a portion of each of the first and second photoresist patterns 1451 and 1452 may also be removed, thereby lowering the height. Specifically, the height of the first and second photoresist patterns 1451 and 1452 of FIG. 15 may be lower than the height of the first and second photoresist patterns 1451 and 1452 of FIG. 14 .

Thereafter, referring to FIG. 16, the first active layer pattern 1220 and the second active layer pattern 1221 can be made into conductors through a dry etching process. At this time, the first active layer is etched through a dry etching process using carbon tetrafluoromethane (CF4), nitrogen trifutoride (NF3), sulfur hexafluoride (SF6), and helium (He) gas. At least a portion of each pattern and the second active layer pattern may be made into conductors to form the first active layer 520 and the second active layer 530.

Specifically, only a portion of the first active layer 520 may be conductive, and the entire second active layer 530 may be conductive.

Referring to FIG. 16, the area of the first active layer 520 that does not overlap with at least one of the gate insulating film 602, the first electrode 551, the second electrode 552, and the electrode pattern 1463 is made into a conductor. It may be an area where Accordingly, the first active layer 520 includes a conductive second auxiliary region 521b disposed between the first auxiliary region 521a and the channel region 523, and the third auxiliary region 522a and the channel It may be formed in a structure including a conductive fourth auxiliary region 522b disposed between the regions 523.

In other words, each of the first auxiliary region 521a, the third auxiliary region 522a, and the channel region 523 of the first active layer 520 includes a gate insulating film 602, a first electrode 551, and a second electrode. Since the electrode pattern 552 and the electrode pattern 1463 serve to shield the plasma, they may not be conductors, but the second auxiliary region 521b and the fourth auxiliary region 522b of the remaining region of the first active layer 520 ) and the second active layer 530 do not have a plasma element, so they can be made into conductors in a dry etching process.

Meanwhile, by using a dry etching process to conduct a portion of the first active layer 520 and the second active layer 530, the first photoresist pattern 1451 disposed on the first electrode 521 and Each of the second photoresist patterns 1452 disposed on the second electrode 522 may also be partially etched to reduce its height.

Accordingly, the height of each of the first and second photoresist patterns 1451 and 1452 shown in FIG. 16 may be lower than the height of each of the first and second photoresist patterns 1451 and 1452 shown in FIG. 15 .

Thereafter, as shown in FIG. 17 , the channel region 523 of the first active layer 520 and the electrode pattern 1463 disposed on the gate insulating layer 602 may be removed.

The electrode pattern 1463 may be removed through a wet etching process. In this process, the first electrode 551 and the second electrode 552, which include the same material as the electrode pattern 1463, are surrounded by the first photoresist pattern 1451 and the second photoresist pattern 1452. , the etching solution may not penetrate into the first and second electrodes 551 and 552. Accordingly, the first and second electrodes 551 and 552 remain without being removed, and since the photoresist pattern is controlled on the electrode pattern 1463, the electrode pattern 1463 can be removed in a wet etching process.

Thereafter, as shown in FIG. 18, the first and second photoresist patterns 1451 and 1452 disposed on the first and second electrodes 551 and 552 may be removed through a strip process. .

Next, referring to FIG. 19 , a first insulating film 603 and a second insulating film 604 may be disposed on the substrate 600 on which the first and second electrodes 551 and 552 are disposed.

Specifically, a first insulating film 603 material is formed on the substrate 600. Afterwards, the second insulating film 604 material is formed on the first insulating film 603 material.

Then, the material of the second insulating layer 604 is patterned to form a second insulating layer 604 that includes the second hole CH2 and does not overlap the second active layer 530 .

Afterwards, the first insulating film 603 including the first hole CH1 formed in the area overlapping the second hole CH2 is formed through a dry etching process. The thickness of the first insulating film 603 disposed on the second active layer 530 may be formed to be thinner than the thickness of the first insulating film 603 disposed on the first active layer 520.

However, the manufacturing process of the display device according to the embodiments of the present disclosure is not limited to this, and the first insulating film 603 is not disposed in the light emitting area to be formed later, including the second active layer 530, but the gate insulating film 602 is disposed on the second active layer 530 and may be disposed to extend to the light emitting area to be formed later.

Additionally, in the process of forming the first and second contact holes CH1 and CH2, a contact hole exposing a portion of the upper surface of the second electrode 552 is formed in the first insulating film 603 and the second insulating film 604. can be formed.

Thereafter, referring to FIG. 20 , a third electrode 563 material may be formed on the substrate 600 on which the second insulating film 604 is formed. The third electrode 563 material may be patterned through an etching process to form the third electrode 563 disposed on the second insulating film 604.

This third electrode 563 may be disposed on a portion of the upper surface of the second insulating film 604 and within the first hole CH1 and the second hole CH2. The third electrode 563 may contact the top surface of the gate insulating film 602 disposed on the channel region 523 within the first and second holes CH1 and CH2.

Thereafter, referring to FIG. 21 , a pixel electrode 570 material for forming the pixel electrode 570 may be formed on the substrate 600 on which the third electrode 563 is disposed.

The material of the pixel electrode 570 may be patterned through a patterning process, thereby forming the pixel electrode 570. The pixel electrode 570 may be in contact with the second electrode 552 through a contact hole in the first and second insulating films 603 and 604 that expose the second electrode 552 . This pixel electrode 570 is also disposed on the second active layer 530, and may be disposed to extend to the light emitting area to be formed later.

Referring to FIG. 21, a bank 670 material to form a bank 670 may be disposed on the substrate 600 on which the pixel electrode 570 is disposed.

The bank 670 material may be patterned and disposed only in the non-emissive area (NEA) and not in the emissive area (EA).

In summary, in the step of forming the gate insulating layer, the gate insulating layer material is formed of first to third gate insulating layer portions that at least partially overlap the top surface of the first active layer pattern, and can be removed on the second active layer pattern. there is. In addition, forming the first and second electrodes includes a first photoresist pattern, a second gate insulating film portion, and Forming a second photoresist pattern overlapping with a portion of each of the first active layer patterns and a third photoresist pattern overlapping with each portion of the third insulating film portion and the first active layer pattern, first to third photoresists Forming a first electrode, a second electrode, and an electrode pattern by patterning an electrode material using the pattern as a mask; converting a portion of the first active layer pattern and the second active layer pattern into conductors through a dry etching process to form a first electrode and forming a second active layer, and removing the first and second photoresist patterns disposed on the first and second electrodes, wherein the conductive area of the first active layer is It includes a region between the first and third gate insulating film portions and a region between the second and third gate insulating film portions, and the entire second active layer may be a conductor.

Meanwhile, although the manufacturing method of forming the third electrode 563 and the pixel electrode 570 through different processes has been described through FIGS. 20 and 21, the manufacturing method of the display device according to the embodiments of the present disclosure is described as follows. It is not limited.

FIGS. 22 and 23 are diagrams schematically showing process steps for forming the third electrode, pixel electrode, and bank of the display device shown in FIG. 6D, and FIGS. 24 and 25 are diagrams schematically showing the process steps of forming the third electrode, pixel electrode, and bank of the display device shown in FIG. 6E. This is a diagram schematically showing the process of forming three electrodes, pixel electrodes, and banks.

Meanwhile, the process steps before forming the third electrode 563 and the pixel electrode 570 in FIGS. 22 to 25 may be the same as the process steps described with reference to FIGS. 11 to 19 .

First, referring to FIG. 22, a third electrode 563 and a pixel electrode 570 may be formed on the first insulating film 603 and the second insulating film 604.

Specifically, a transparent conductive material layer may be formed on the substrate 600 on which the first and second insulating films 603 and 604 are disposed. Additionally, a metal material layer may be formed on the transparent conductive material layer.

Afterwards, the metal material layer can be patterned using a halftone mask. The patterned metal material layer may remain in a portion of the upper surface of the second insulating film 604 and in an area overlapping the first and second holes CH1 and CH2. In addition, the metal material layer is inside the contact hole of the first and second insulating films 603 and 604, which exposes a portion of the upper surface of the second electrode 552, and corresponds to the light emitting area (EA, the opening of the bank to be formed later). It may also remain in the area.

Afterwards, the transparent conductive material layer disposed below the metal material layer can be patterned. The patterned transparent conductive material layer may remain only in the area overlapping the metal material layer.

Afterwards, it is disposed inside the contact hole of the first and second insulating films 603 and 604 exposing a portion of the upper surface of the second electrode 552 and in the area corresponding to the light emitting area (EA, the opening of the bank to be formed later). The metal material layer is removed, leaving only the transparent conductive material layer corresponding to the pixel electrode 570.

Thereafter, the photoresist pattern disposed on a portion of the upper surface of the second insulating film 604 and the area overlapping the first and second holes CH1 and CH2 is finally removed to form the first gate electrode layer 563a and the second gate electrode layer 563a. A third electrode 563 made of the gate electrode layer 563b is formed.

Thereafter, as shown in FIG. 23, a bank 670 having an opening exposing a portion of the upper surface of the pixel electrode 570 may be formed.

Next, the process steps for forming the display device of FIG. 6E will be briefly reviewed with reference to FIGS. 24 and 25 as follows.

Referring to FIG. 24, a third electrode including a first gate electrode layer 563a, a second gate electrode layer 563b, and a third gate electrode layer 563c on the first insulating film 603 and the second insulating film 604. A pixel electrode 570 including 563 and first to third layers 570a, 570b, and 570c may be formed. The third electrode 563 and the pixel electrode 570 may be formed through the same process, and a halftone mask may be used during the process.

Specifically, a first transparent conductive material layer is formed on the substrate 600 on which the first and second insulating films 603 and 604 are disposed, a metal material layer is formed on the first transparent conductive material layer, and a metal material layer is formed on the metal material layer. A second transparent conductive material layer may be formed.

Afterwards, the second transparent conductive material layer can be patterned. The second transparent conductive material layer may remain in a portion of the upper surface of the second insulating film 604 and an area overlapping the first and second holes CH1 and CH2. In addition, the second transparent conductive material layer is inside the contact hole of the first and second insulating films 603 and 604, which exposes a portion of the upper surface of the second electrode 552, and the light emitting area (EA, the opening of the bank to be formed later). It may also remain in the corresponding area. The patterned second transparent conductive material layer may become the third gate electrode layer 563c of the third electrode 563 and the third layer 570c of the pixel electrode 570.

Thereafter, the metal material layer disposed below the second transparent conductive material layer may be patterned. The metal material layer may remain only in the area where the second transparent conductive material layer is disposed and may be removed from the remaining areas. Among the metal material layers patterned in this way, the metal material layer disposed below the third gate electrode layer 563c may be the second gate electrode layer 563b of the third electrode 563, and the third layer of the pixel electrode 570. The metal material layer disposed below (570c) may be the second layer 570b of the pixel electrode 570.

Thereafter, the first transparent conductive material layer disposed below the metal material layer may be patterned. The first transparent conductive material may remain only in the area where the metal material layer is disposed and may be removed from the remaining areas. Among the first transparent conductive material layers patterned in this way, the first transparent conductive material layer disposed below the second gate electrode layer 563b of the third electrode 563 is the first gate electrode layer 563a of the third electrode 563. may be, and the metal material layer disposed below the second layer 570b of the pixel electrode 570 may be the first layer 570a of the pixel electrode 570.

Through this process, the triple-layer third electrode 563 and the triple-layer pixel electrode 570 are formed in the same process, thereby simplifying the process.

Thereafter, as shown in FIG. 25 , a bank 670 having an opening exposing a portion of the upper surface of the third layer 570c of the pixel electrode 570 may be formed.

Next, with reference to FIGS. 26 to 36, the manufacturing method of the display device shown in FIG. 7A will be reviewed as follows.

FIGS. 26 to 36 are diagrams schematically showing the manufacturing process of the display device shown in FIG. 7A.

First, referring to FIG. 26, a light shield 510 may be formed on the substrate 600.

Afterwards, a buffer layer 601 may be formed on the light shield 510.

An active material may be formed on the buffer layer 601, and the active material may be patterned to form a first active layer pattern 2620 and a second active layer pattern.

An auxiliary electrode material is formed on the substrate on which the first active layer pattern 2620 and the second active layer pattern are formed, and the auxiliary electrode material is patterned to form a portion of the upper surface of the first active layer pattern and the upper surface of the second active layer pattern, respectively. Auxiliary electrodes (AUX1, AUX2, AUX3, AUX4) can be formed.

Specifically, referring to FIG. 26 , first and second auxiliary electrodes AUX1 and AUX2 may be disposed on a portion of the upper surface of the first active layer pattern 2620 to be spaced apart from each other.

In addition, referring to FIG. 26, a plurality of second active layer patterns may be formed in cross-section, and a third auxiliary electrode (AUX3) is disposed on one second active layer pattern and on the other second active layer pattern. A fourth auxiliary electrode (AUX4) may be disposed.

Areas where each of the first active layer pattern 2620 and the plurality of second active layer patterns are in contact with the auxiliary electrodes may be made into conductors by the auxiliary electrodes. Here, each of the first to fourth auxiliary electrodes (AUX1, AUX2, AUX3, and AUX4) may include a metal material or a conductive oxide.

For example, the first to fourth auxiliary electrodes (AUX1, AUX2, AUX3, AUX4) may include at least one of copper, aluminum, molybdenum (Mo), titanium (Ti), or molybdenum/titanium (MoTi). there is.

As another example, the first to fourth auxiliary electrodes (AUX1, AUX2, AUX3, and AUX4) may include at least one of transparent conductive oxide (TCO), nitrous oxide, and organic material. For example, transparent conductive oxides (TCOs) include Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO), Aluminum-doped Zinc Oxide (AZO), It may include one or more of Gallium-doped Zinc Oxide (GZO), Antimony Tin Oxide (ATO), and Flourine-doped Transparent Oxides (FTO). Nitric oxides may include ZnON (Zinc Oxynitride).

The active layer patterns in contact with the first to fourth auxiliary electrodes (AUX1, AUX2, AUX3, and AUX4) may be conductive. Accordingly, the channel region 523 of the first active layer pattern 2620 is not conductive, and the first and second auxiliary electrodes AUX1 and AUX2 in the first region 2621 and the second region 2622, respectively. The contacted area may be a conductive area. In other words, each of the first area 2621 and the second area 2622 may include a conductive area and a non-conductive area.

Thereafter, as shown in FIG. 27, a gate insulating layer material may be formed on the substrate 600 on which the first to fourth auxiliary electrodes AUX1, AUX2, AUX3, and AUX4 are disposed.

The gate insulating layer material may be patterned through a dry etching process to form a gate insulating layer 602 including first to third gate insulating layer portions 602a, 602b, and 602c. The gate insulating film 602 exposes the top surfaces of the first auxiliary electrode (AUX1) and the second auxiliary electrode (AUX2), is disposed to surround the top surface and side surfaces of the third auxiliary electrode (AUX3), and forms the fourth auxiliary electrode (AUX4). It may be formed to expose the top and sides of.

In addition, as shown in FIG. 27, in the dry etching process of the gate insulating film material, part of the gate insulating film material and part of the buffer layer 601 are etched to form a contact hole exposing part of the upper surface of the light shield 510. You can. At this time, the gate insulating film material and the buffer layer 601 are formed using carbon tetrafluoromethane (CF4), nitrogen trifutoride (NF3), sulfur hexafluoride (SF6), and oxygen (O2) gas. This can be dry etched.

Thereafter, referring to FIG. 28, an electrode material may be formed on the substrate 600. The electrode material may include a metallic material.

A photoresist material may be formed on the electrode material. This photoresist material may be patterned to form a first photoresist pattern 1451, a second photoresist pattern 1452, a third photoresist pattern 1453, and a fourth photoresist pattern 2854.

The photoresist material may be patterned through a halftone mask, and the height of the first, second, and fourth photoresist patterns 1451, 1452, and 2854 formed after patterning may be higher than the height of the third photoresist pattern 1453. there is.

Afterwards, the electrode material can be patterned using the first to fourth photoresist patterns 1451, 1452, 1453, and 2854 as masks. By patterning the electrode material, a first electrode 551 is formed under the first photoresist pattern 1451, a second electrode 552 is formed under the second photoresist pattern 1452, and a third photoresist is formed. An electrode pattern 1463 may be formed below the pattern 1453, and a gate metal layer 751 may be formed below the fourth photoresist pattern 2854.

As shown in FIG. 28 , the second electrode 552 may be formed to contact the upper surface of the light shield 510 through a contact hole formed in the buffer layer 601 and the gate insulating film 602.

Thereafter, referring to FIG. 29, the third photoresist pattern 1453 disposed on the electrode pattern 1463 may be removed.

The third photoresist pattern 1453 disposed on the electrode pattern 1463 can be removed through a dry etching process, and the first, second, and fourth photoresist patterns 1453 have a height higher than the height of the third photoresist pattern 1453. Each of photoresist patterns 1451, 1452, and 2854 is not removed.

However, in the process of removing the third photoresist pattern 1453, portions of each of the first, second, and fourth photoresist patterns 1451, 1452, and 2854 may be removed, thereby lowering the height. Specifically, the height of the first, second, and fourth photoresist patterns 1451, 1452, and 2854 of FIG. 29 is higher than the height of the first, second, and fourth photoresist patterns 1451, 1452, and 2854 of FIG. 28. It could be lower.

Next, referring to FIG. 30, the first active layer pattern 1220 and the second active layer pattern 1221 can be made into conductors through a dry etching process. At this time, the first active layer is etched through a dry etching process using carbon tetrafluoromethane (CF4), nitrogen trifutoride (NF3), sulfur hexafluoride (SF6), and helium (He) gas. Some areas of the pattern may be additionally conductive.

Specifically, referring to FIG. 30, in the dry etching process, a portion of the third gate insulating layer portion 602c of the gate insulating layer 602 may be additionally removed, exposing a portion of the upper surface of the first active layer pattern. . And, the exposed first active layer pattern can be made into a conductor through a dry etching process.

In other words, the first active layer pattern is formed not only in the area overlapping with the first and second auxiliary electrodes (AUX1 and AUX2), but also between the first auxiliary electrode (AUX1) and the third gate insulating film portion 602c and the second auxiliary electrode. The first active layer pattern is also made into a conductor in the regions corresponding to each region between (AUX2) and the third gate insulating layer portion 602c, thereby finally including the second auxiliary region 521b and the fourth auxiliary region 521d. A first active layer 520 may be formed.

That is, each of the second auxiliary region 521b and the fourth auxiliary region 521d of the first active layer 520 is partially conductive by the first and second auxiliary electrodes AUX1 and AUX2, and the other portion is conductive by the first and second auxiliary electrodes AUX1 and AUX2. The gate insulating film 602 may be formed as a conductor during a dry etching process.

Thereafter, referring to FIG. 31 , the electrode pattern 1463 disposed on the channel region 523 of the first active layer 520 and the gate insulating layer 602 may be removed. The electrode pattern 1463 may be removed through a wet etching process.

Thereafter, referring to FIG. 32, first, second, and fourth photoresist patterns 1451, 1452, and 2854 disposed on the first and second electrodes 551 and 552 and the third gate metal layer 751. This can be removed through a strip process.

Thereafter, referring to FIG. 33, a first insulating film 603 and a second insulating film 604 are formed on the substrate 600 on which the first electrode 551, the second electrode 552, and the gate metal layer 751 are disposed. can be placed.

Specifically, a first insulating film 603 material is formed on the substrate 600. Afterwards, the second insulating film 604 material is formed on the first insulating film 603 material.

Thereafter, the material of the second insulating layer 604 is patterned to form a second insulating layer 604 that includes the second hole CH2 and does not overlap the second active layer 530 .

Thereafter, the first insulating film 603 including the first hole CH1 formed in the area overlapping the second hole CH2 is formed through a dry etching process. The thickness of the first insulating film 603 disposed on the second active layer 530 may be formed to be thinner than the thickness of the first insulating film 603 disposed on the first active layer 520.

Additionally, in the process of forming the first and second contact holes CH1 and CH2, a contact hole exposing a portion of the upper surface of the second electrode 552 is formed in the first insulating film 603 and the second insulating film 604. can be formed. The contact hole exposing a portion of the upper surface of the second electrode 552 will be formed through a process of patterning the second insulating film 604 material and then additionally patterning the first insulating film 603 material through a dry etching process. You can.

Thereafter, referring to FIG. 34 , a third electrode 563 material may be formed on the substrate 600 on which the second insulating film 604 is formed. The third electrode 563 material may be patterned through an etching process (eg, wet etching) to form the third electrode 563 disposed on the second insulating film 604.

This third electrode 563 may be disposed on a portion of the upper surface of the second insulating film 604 and within the first hole CH1 and the second hole CH2. The third electrode 563 may contact the top surface of the gate insulating film 602 disposed on the channel region 523 within the first and second holes CH1 and CH2.

Thereafter, referring to FIG. 35 , a pixel electrode 570 material for forming the pixel electrode 570 may be formed on the substrate 600 on which the third electrode 563 is disposed.

The material of the pixel electrode 570 may be patterned through a patterning process, thereby forming the pixel electrode 570. The pixel electrode 570 may be in contact with the second electrode 552 through a contact hole in the first and second insulating films 603 and 604 that expose the second electrode 552 . This pixel electrode 570 is also disposed on the second active layer 530, and may be disposed to extend to the light emitting area to be formed later.

Additionally, the pixel electrode 570 may be formed to overlap a plurality of second active layers 530 and the gate metal layer 751.

Thereafter, as shown in FIG. 36 , bank 670 material to form the bank 670 may be disposed on the substrate 600 on which the pixel electrode 570 is disposed.

In summary, forming an auxiliary electrode material on a portion of the upper surface of the first active layer pattern and the entire upper surface of the second active layer pattern and patterning the auxiliary electrode material to form first and second electrodes spaced apart from each other on the first active layer pattern. Forming an auxiliary electrode and forming third and fourth auxiliary electrodes on each of the upper surfaces of the two active layer patterns, wherein each of the first and second active layer patterns is in contact with the first to fourth auxiliary electrodes. It can be conductive in the area. Here, a first auxiliary electrode may be disposed in the area between the first gate insulating layer portion and the third gate insulating layer portion, and the second auxiliary electrode may be disposed in the area between the second gate insulating layer portion and the third gate insulating layer portion. there is. Additionally, the gate insulating layer may include a portion surrounding one second active layer.

The step of patterning the electrode material disposed on the gate insulating film includes a first photoresist pattern, a second gate insulating film portion, and A portion of the second photoresist pattern and third insulating film overlapping a portion of each of the first active layer patterns, a third photoresist pattern overlapping with a portion of each of the first active layer patterns, and a gate insulating film disposed on the third auxiliary electrode; Forming an overlapping fourth photoresist pattern, patterning an electrode material using the first to fourth photoresist patterns as a mask to form a first electrode, a second electrode, an electrode pattern, and a gate metal layer, a dry etching process Through this, a part of the third gate insulating film is removed, a part of the first active layer pattern is made into a conductor to form a first active layer, and the third photoresist pattern disposed on the electrode pattern is removed, and a first It may include removing the first, second, and fourth photoresist patterns.

In the dry etching process after forming the first electrode, second electrode, electrode pattern, and gate metal layer, the first active layer is formed in the area between the first auxiliary electrode and the third gate insulating film portion and the second auxiliary electrode and the third gate. The region between the insulating film portions may additionally be made conductive.

Although a manufacturing method of forming the third electrode 563 and the pixel electrode 570 using different processes has been described with reference to FIG. 35, the manufacturing method of the display device according to embodiments of the present disclosure is not limited thereto.

FIGS. 37 and 38 are diagrams schematically showing process steps for forming the third electrode, pixel electrode, and bank of the display device shown in FIG. 7B, and FIGS. 39 and 40 are diagrams schematically showing the process steps of forming the third electrode, pixel electrode, and bank of the display device shown in FIG. 7C. This is a diagram schematically showing the process of forming three electrodes, pixel electrodes, and banks.

The process steps before forming the third electrode 563 and the pixel electrode 570 in FIGS. 37 to 40 may be the same as the process steps described with reference to FIGS. 26 to 33 .

First, referring to FIG. 37, a transparent conductive material layer may be formed on the substrate 600 on which the first and second insulating films 603 and 604 are disposed. Additionally, a metal material layer may be formed on the transparent conductive material layer.

Afterwards, the metal material layer can be patterned using a halftone mask. The patterned metal material layer may remain in a portion of the upper surface of the second insulating film 604 and in an area overlapping the first and second holes CH1 and CH2. In addition, the metal material layer is inside the contact hole of the first and second insulating films 603 and 604, which exposes a portion of the upper surface of the second electrode 552, and corresponds to the light emitting area (EA, the opening of the bank to be formed later). It may also remain in the area.

Afterwards, the transparent conductive material layer disposed below the metal material layer can be patterned. The patterned transparent conductive material layer may remain only in the area overlapping the metal material layer.

Afterwards, it is disposed inside the contact hole of the first and second insulating films 603 and 604 exposing a portion of the upper surface of the second electrode 552 and in the area corresponding to the light emitting area (EA, the opening of the bank to be formed later). The metal material layer is removed, leaving only the transparent conductive material layer corresponding to the pixel electrode 570.

Finally, the photoresist pattern disposed on a portion of the upper surface of the second insulating film 604 and the area overlapping the first and second holes CH1 and CH2 is removed to form the first gate electrode layer 563a and the second gate electrode layer. A third electrode 563 made of (563b) is formed.

Thereafter, as shown in FIG. 38, a bank 670 having an opening exposing a portion of the upper surface of the pixel electrode 570 may be formed.

Next, the process steps for forming the display device of FIG. 7C will be briefly reviewed with reference to FIGS. 39 and 40 as follows.

First, referring to FIG. 39, a first transparent conductive material layer is formed on the substrate 600 on which the first and second insulating films 603 and 604 are disposed, and a metal material layer is formed on the first transparent conductive material layer. , a second transparent conductive material layer may be formed on the metal material layer.

Afterwards, the second transparent conductive material layer can be patterned. The second transparent conductive material layer may remain in a portion of the upper surface of the second insulating film 604 and an area overlapping the first and second holes CH1 and CH2. In addition, the second transparent conductive material layer is inside the contact hole of the first and second insulating films 603 and 604, which exposes a portion of the upper surface of the second electrode 552, and the light emitting area (EA, the opening of the bank to be formed later). It may also remain in the corresponding area. The patterned second transparent conductive material layer may become the third gate electrode layer 563c of the third electrode 563 and the third layer 570c of the pixel electrode 570.

Thereafter, the metal material layer disposed below the second transparent conductive material layer may be patterned. The metal material layer may remain only in the area where the second transparent conductive material layer is disposed and may be removed from the remaining areas. Among the metal material layers patterned in this way, the metal material layer disposed below the third gate electrode layer 563c may be the second gate electrode layer 563b of the third electrode 563, and the third layer of the pixel electrode 570. The metal material layer disposed below (570c) may become the second layer 570b of the pixel electrode 570.

Then, the first transparent conductive material layer disposed below the metal material layer can be patterned. The first transparent conductive material may remain only in the area where the metal material layer is disposed and may be removed from the remaining areas. Among the first transparent conductive material layers patterned in this way, the first transparent conductive material layer disposed below the second gate electrode layer 563b of the third electrode 563 is the first gate electrode layer 563a of the third electrode 563. may be, and the metal material layer disposed below the second layer 570b of the pixel electrode 570 may be the first layer 570a of the pixel electrode 570.

Through this process, the triple-layer third electrode 563 and the triple-layer pixel electrode 570 are formed in the same process, thereby simplifying the process.

Thereafter, as shown in FIG. 40 , a bank 670 having an opening exposing a portion of the upper surface of the third layer 570c of the pixel electrode 570 may be formed.

The bank 670 may overlap with the transistor and the storage capacitor (Cst), but this is only an example, and the bank 670 may not overlap with at least one of the transistor and the storage capacitor (Cst).

Next, the manufacturing method of the display device shown in FIG. 10A will be reviewed with reference to FIGS. 41 to 44 as follows.

FIGS. 41 to 44 are diagrams schematically showing the manufacturing process of the display device shown in FIG. 10A.

In FIG. 10A, the gate insulating film 602 shows a structure including first to third gate insulating film portions 602a, 602b, and 602c. However, for convenience of explanation, the gate insulating film 602 is shown in FIGS. 41 to 44. The description will focus on the structure consisting only of the third gate insulating film portion 602c of 10a.

First, referring to FIG. 42, a light shield 510 and a buffer layer 601 may be formed on the substrate 600.

Thereafter, an active material may be formed on the buffer layer 601, and the active material may be patterned to form a first active layer pattern 4120 and a second active layer pattern 4221.

Next, referring to FIG. 42, after forming the gate insulating material on the substrate 600 on which the first and second active layer patterns 4120 and 4221 are disposed, the gate insulating material is patterned through a dry etching process to form the gate. An insulating film 602 can be formed.

Specifically, as shown in FIG. 42, the gate insulating film material is removed and a photoresist pattern 4201 is formed only at the remaining location. Thereafter, through a dry etching process, only the gate insulating layer material located below the photoresist pattern 4201 is left, and the remaining gate insulating layer material is removed to form the gate insulating layer 602.

In the dry etching process to form the gate insulating film 602, carbon tetrafluoromethane (CF4), nitrogen trifutoride (NF3), sulfur hexafluoride (SF6), and helium (He) gas will be used. In this process, a portion of the first active layer pattern and the entire second active layer pattern may become conductive.

Specifically, the first active layer pattern may be conductive in the area where the gate insulating film material is removed through a dry etching process, and through this, the first and second regions 521 and 522, which are conductive areas, may be formed. A first active layer 520 may be formed.

The second active layer pattern may be converted into a conductor to become the second active layer 521.

Meanwhile, in FIG. 42, a structure in which the width of the channel region 523 of the first active layer 520 is narrower than the width of the gate insulating layer 602 is shown. However, the first active layer of the display device according to embodiments of the present disclosure is shown. The width of the channel region 523 of 520 may vary depending on process conditions for forming the gate insulating film 602. For example, the width of the channel region 523 of the first active layer 520 and the width of the gate insulating film 602 are the same, or the width of the channel region 523 of the first active layer 520 is the gate insulating film ( It may be larger than the width of 602).

Here, the width of the channel region 523 of the first active layer 520 and the width of the gate insulating layer 602 are the minimum in the direction perpendicular to the direction in which the buffer layer 601 is stacked on the substrate 600 in cross-section. It can mean length.

After forming the gate insulating film 602, the photoresist pattern 4201 disposed on the gate insulating film 602 can be removed.

Thereafter, referring to FIG. 43 , a first insulating film 603 and a second insulating film 604 may be formed on the substrate 600 on which the gate insulating film 602 is formed.

Thereafter, referring to FIG. 44, an electrode material may be formed on the substrate 600 and the electrode material may be patterned to form the first electrode 551, the second electrode 552, and the third electrode 563. there is.

A pixel electrode material is formed on the substrate on which the first to third electrodes 551, 552, and 563 are formed, and the pixel electrode material is patterned to form a pixel electrode 570 on the first and second insulating films 603 and 604. can be formed.

Thereafter, as shown in FIG. 44, a bank 670 may be formed on a portion of the pixel electrode 570 of the first to third electrodes 551, 552, and 563.

41 to 44, the first electrode 551, the second electrode 552, and the third electrode 563 are formed through the same process, and the pixel electrode 570 is formed using the first to third electrodes 551, 552, and 563. 563) has been described, but the manufacturing process of the display device according to the embodiments of the present disclosure is not limited thereto.

FIG. 45 is a diagram schematically showing the steps of forming the first electrode 551, the third electrode 563, and the pixel electrode 570 in the display device of FIG. 10B, and FIGS. 46 and 47 are representations of FIG. 10D. This diagram schematically illustrates the steps of forming the first electrode 551, the third electrode 563, and the pixel electrode 570 in the device.

Meanwhile, the process steps before forming the first electrode 551, the third electrode 563, and the pixel electrode 570 in FIG. 45 may be the same as the process steps described with reference to FIGS. 41 to 43.

Referring to FIG. 45 , a transparent conductive material layer may be formed on the substrate 600 on which the first and second insulating films 603 and 604 are formed, and a metal material layer may be formed on the transparent conductive material layer.

Afterwards, the metal material layer can be patterned using a halftone mask. A portion of the patterned metal material layer is disposed on a portion of the upper surface of the first insulating film 603, and the first insulating film 603 exposes a portion of the upper surface of the first region 521 of the first active layer 520. It is disposed in an area corresponding to the hole and can ultimately become the second electrode layer 1051b of the first electrode 551.

In addition, another part of the patterned metal material layer is disposed on a portion of the upper surface of the first insulating film 603 and in an area corresponding to the first hole CH1 of the first insulating film 603, ultimately forming a third electrode ( 563) may be the second gate electrode layer 1063b.

In addition, another part of the patterned metal material layer is disposed on a portion of the upper edge of the first insulating layer 603, and the first insulating layer 603 is located on a portion of the upper surface of the second region 522 of the first active layer 520. The contact hole exposing the first insulating film 603 and the buffer layer 601 are disposed in an area corresponding to the contact hole exposing a portion of the upper surface of the light shield 510, ultimately forming the second layer of the pixel electrode 570. It could be (1071b).

Thereafter, the transparent conductive material layer disposed below the metal material layer can be patterned using the patterned metal material layer and the photoresist pattern as a mask. After patterning the transparent conductive material, it may remain under the metal material layer (second electrode layer 1051b, second gate electrode layer 1063b, and second layer 1071b) that remains patterned in the previous step.

Specifically, a portion of the patterned transparent conductive material layer may become the first electrode layer 1051a of the first electrode 551 disposed below the second electrode layer 1051b of the first electrode 551.

Additionally, another part of the patterned transparent conductive material layer may be the first gate electrode layer 1063a disposed below the second gate electrode layer 1063b of the third electrode 563.

Additionally, another part of the patterned transparent conductive material layer may be the first layer 1071a disposed below the second layer 1071b of the pixel electrode 570. Referring to FIG. 45, the first layer 1071a of the pixel electrode 570 includes an area overlapping with the second layer 1071b, and may be formed to extend to the second active layer 530 and the light emitting area. .

Next, with reference to FIGS. 46 and 47 , the steps of forming the first electrode 551, the third electrode 563, and the pixel electrode 570 of the display device of FIG. 10D are reviewed as follows.

The process steps before forming the first electrode 551, the third electrode 563, and the pixel electrode 570 in FIGS. 46 and 47 may be the same as the process steps described with reference to FIGS. 41 and 42 .

First, referring to FIG. 46 , a first metal material layer for forming an additional gate insulating layer 1063d may be formed on the substrate 600 on which the gate insulating film 602 is formed.

The first metal material layer may be patterned through a process such as wet etching and remain only on the gate insulating layer 602 disposed on the channel region 523 of the first active layer 520.

In this way, after forming the additional gate insulating layer 1063d, the first and second insulating films 603 and 604 can be formed. Specifically, a first insulating layer material and a second insulating layer material may be sequentially formed on the substrate 600, and then the second insulating layer material may be patterned, and then the first insulating layer material may be patterned. A dry etching process may be used to pattern the first insulating layer material.

Thereafter, as shown in FIG. 47, the first electrode 551, the first to third gate insulating layers 1063a, 1063b, and 1063c of the third electrode 563, and the pixel electrode 570 can be formed. .

Specifically, a first transparent conductive material layer, a second metal material layer, and a second transparent conductive material layer may be sequentially formed on the substrate 600 on which the first and second insulating films 603 and 604 are formed.

Thereafter, the second transparent conductive material layer, the second metal material layer, and the first transparent conductive material layer are sequentially patterned to form the first to third gate insulating layers 1063a of the first electrode 551 and the third electrode 563. , 1063b, 1063c) and the pixel electrode 570 can be formed in the same process.

Meanwhile, Figures 46 and 47 illustrate the process of forming the first electrode 551, the third electrode 563, and the pixel electrode 570 shown in Figure 10d, but in Figure 47, the process of forming the second transparent conductive material layer is shown. If the patterning process is deleted, the first electrode 551, third electrode 563, and pixel electrode 570 shown in FIG. 10C can be formed.

The embodiments of the present disclosure described above are briefly described as follows.

Embodiments of the present disclosure are disposed on a substrate and include a channel region 523, a first region 521 located on a first side of the channel region 523, and a second side of the channel region 523. A first active layer 520 including a second region 522, a gate insulating layer 602 disposed on the first active layer 520, and a first region 521 disposed on the gate insulating layer 602. A first electrode 551 electrically connected to the gate insulating layer 602, and a second electrode 552 electrically connected to the second region 522, disposed on the gate insulating layer 602, and a channel region a first insulating film 603 having a first hole CH1 overlapping at least a portion of the first insulating film 603, and a second hole CH2 disposed on the first insulating film 603 and overlapping at least a portion of the first hole CH1. ), a display panel including a second insulating film 604 disposed in the first hole CH1 and a third electrode 563 disposed to overlap the channel region 523 in the first hole CH1. and a display device may be provided.

According to embodiments of the present disclosure, the electrode disposed on the active layer overlaps the entire channel region of the active layer and also overlaps a portion of each of the first region and the second region disposed on both sides of the channel region of the active layer. By being disposed, it is possible to provide a display panel and a display device that can prevent internal light from entering the active layer and deteriorating the characteristics of the transistor.

According to embodiments of the present disclosure, the thickness of the insulating film is designed to increase the distance between the electrodes of the transistor, thereby providing a display panel and a display device that can prevent driving characteristics from being deteriorated due to an increase in parasitic capacitance. can be provided.

According to embodiments of the present disclosure, a display panel and a display device including a high-capacity storage capacitor can be provided by including a plurality of storage capacitor electrodes and a plurality of storage capacitors connected in parallel.

The above description is merely an illustrative explanation of the technical idea of the present disclosure, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but rather are for explanation, and therefore the scope of the technical idea of the present disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this disclosure.

Claims (40)

Board;
a first active layer disposed on the substrate and including a channel region, a first region located on a first side of the channel region, and a second region located on a second side of the channel region;
a gate insulating layer disposed on the first active layer;
a first electrode disposed on the gate insulating layer and electrically connected to the first region;
a second electrode disposed on the gate insulating layer and electrically connected to the second region;
a first insulating layer disposed on the gate insulating layer and including a first hole overlapping at least a portion of the channel region; and
A display panel including a third electrode disposed within the first hole and overlapped with the channel region within the first hole.
According to claim 1,
A display panel in which an area of the first active layer that does not overlap the gate insulating layer is a conductive area.
According to clause 2,
The display panel wherein the first area and the second area include a conductive area.
According to clause 3,
The first area includes a first auxiliary area that is a non-conducting area, and a second auxiliary area that extends from the first auxiliary area but is a conductive area,
The second region includes a third auxiliary region that is a non-conducting region, and a fourth auxiliary region that extends from the third auxiliary region but is a conductive region,
The display panel wherein the second and fourth auxiliary regions include areas that do not overlap the first electrode, the second electrode, and the gate insulating layer.
According to clause 4,
The second auxiliary area is disposed between the first auxiliary area and the channel area,
The fourth auxiliary area is a display panel disposed between the second auxiliary area and the channel area.
According to claim 1,
The gate insulating film is,
A display panel including a first gate insulating layer portion overlapping a portion of the first region, a second gate insulating layer portion overlapping a portion of the second region, and a third gate insulating layer portion overlapping the entire channel region.
According to clause 6,
At least a portion of the second auxiliary region, which is a conductive region disposed on one side of the channel region of the first active layer, overlaps an area between the first gate insulating film portion and the third gate insulating film portion,
A display panel wherein at least a portion of the fourth auxiliary area, which is a conductive area and disposed on the other side of the channel area of the first active layer, overlaps an area between the second gate insulating layer portion and the third gate insulating layer portion.
According to clause 6,
At least a portion of the upper surface of the third gate insulating layer portion overlaps the first hole in the first insulating layer.
According to claim 1,
A display panel in which the first insulating layer has at least one step within the first hole.
According to claim 1,
The display panel wherein the third electrode overlaps at least a portion of each of the first area and the second area.
According to claim 1,
The first electrode and the second electrode are each one of a source electrode and a drain electrode,
A display panel wherein the third electrode is a gate electrode.
According to claim 1,
a second insulating film disposed on the first insulating film and having a second hole overlapping at least a portion of the first hole;
The third electrode is disposed inside the first hole and the second hole, and is disposed on a portion of the upper surface of the second insulating layer.
According to claim 12,
The third electrode includes a first gate electrode layer and a second gate electrode layer,
The first gate electrode layer is disposed on the gate insulating film overlapping the channel region,
The display panel wherein the second gate electrode layer is disposed on the first gate electrode layer, is disposed within the first hole and the second hole, and is disposed on a portion of the upper surface of the second insulating layer.
According to claim 13,
The third electrode further includes an additional gate electrode layer,
The display panel wherein the additional gate electrode layer is disposed between the gate insulating layer disposed on the channel region and the first insulating layer, and overlaps the first hole of the first insulating layer.
According to claim 13,
The third electrode further includes a third gate electrode layer,
A display panel wherein the third gate electrode layer is disposed on the second gate electrode layer.
According to claim 15,
The first and third gate electrode layers are made of a transparent conductive material,
A display panel wherein the second gate electrode layer is made of a metal material.
According to claim 12,
Further comprising a pixel electrode disposed on the second insulating film,
The pixel electrode includes a first pixel electrode layer,
A display panel wherein the first pixel electrode layer includes a transparent conductive material.
According to claim 17,
The pixel electrode includes a second pixel electrode layer disposed on the first pixel electrode layer and a third pixel electrode layer disposed on the second pixel electrode layer,
The first pixel electrode layer is disposed on the same layer as the first gate electrode layer of the third electrode,
The second pixel electrode layer is disposed on the same layer as the second gate electrode layer of the third electrode,
A display panel wherein the third pixel electrode layer is disposed on the same layer as a third gate electrode layer of the third electrode.
According to claim 1,
Further comprising a light shield disposed below the first active layer,
The light shield overlaps a conductive area of the second active layer spaced apart from the first active layer,
comprising a pixel electrode overlapping the light shield and the conductive area of the second active layer,
The light shield, the conductive area of the second active layer, and the pixel electrode each overlap with each other to form a storage capacitor.
According to clause 19,
The pixel electrode extends to the light emitting area,
In the light emitting area, the display panel further includes an organic layer including a light emitting layer on the pixel electrode and a common electrode disposed on the organic layer.
According to claim 1,
The first electrode, the second electrode, and the third electrode are disposed on the first insulating film,
The second insulating film includes a contact hole exposing a portion of the upper surface of the second electrode,
A display panel wherein the second electrode is electrically connected to a pixel electrode through the contact hole.
According to claim 1,
Comprising a first auxiliary electrode and a second auxiliary electrode disposed on the first active layer,
The first auxiliary electrode is disposed on the first area,
The second auxiliary electrode is disposed on the second area,
A display panel wherein the first and second auxiliary electrodes include a metal material.
According to clause 22,
The first and second auxiliary electrodes further include a transparent conductive material layer, a transparent conductive oxide layer, a nitrous oxide layer, or an organic material layer disposed between the first active layer and the layer made of the metal material.
According to clause 22,
The first auxiliary electrode overlaps a portion of the conductive area of the first region of the first active layer,
The display panel wherein the second auxiliary electrode overlaps a portion of the conductive area of the second region of the first active layer.
According to clause 22,
A second active layer disposed on the same layer as the first active layer, a third auxiliary electrode disposed on a portion of the upper surface of the second active layer, a metal layer disposed on the third auxiliary electrode, and disposed on the metal layer. Comprising a pixel electrode and a light shield disposed below the second active layer,
The light shield, the third auxiliary electrode, and the metal layer constitute a first storage capacitor.
According to clause 25,
A fourth auxiliary electrode disposed on the second active layer and spaced apart from the third auxiliary electrode and a pixel electrode disposed on the fourth auxiliary electrode,
The light shield, the fourth auxiliary electrode, and the pixel electrode constitute a second storage capacitor.
According to clause 26,
A display panel wherein the first storage capacitor and the second storage capacitor are connected in parallel.
Board;
a first active layer disposed on the substrate and including a channel region, a first region located on a first side of the channel region, and a second region located on a second side of the channel region;
a gate insulating layer disposed on the first active layer;
a first electrode disposed on the gate insulating layer and electrically connected to the first region;
a second electrode disposed on the gate insulating layer and electrically connected to the second region;
a first insulating layer disposed on the gate insulating layer and including a first hole overlapping at least a portion of the channel region;
A display device including a third electrode disposed within the first hole and overlapped with the channel region within the first hole.
forming a light shield on the substrate;
forming a buffer layer on the substrate on which the light shield is disposed;
forming an active material on the buffer layer and patterning the active material to form a first active pattern and at least one second active pattern;
forming a gate insulating layer on the first and second active patterns and forming a plurality of contact holes in the gate insulating layer and the buffer layer through a first dry etching process;
forming an electrode material on the gate insulating film and patterning the electrode material to form first and second electrodes;
forming a first insulating layer material on the substrate on which the first and second electrodes are formed, and patterning the first insulating layer material to form holes and contact holes;
A display panel manufacturing method comprising forming a third electrode by forming and patterning a second electrode material on the first insulating film.
According to clause 29,
In forming the gate insulating film,
The gate insulating layer material is formed of first to third gate insulating layer portions that at least partially overlap a top surface of the first active layer pattern, and is removed on the second active layer pattern.
According to claim 30,
Forming the first and second electrodes includes:
A first photoresist pattern disposed on the electrode material and overlapping a portion of each of the first gate insulating layer portion and the first active layer pattern, and a first photoresist pattern overlapping a portion of each of the second gate insulating layer portion and the first active layer pattern. forming a third photoresist pattern overlapping a second photoresist pattern and a portion of each of the third insulating film portion and the first active layer pattern;
patterning the electrode material using the first to third photoresist patterns as a mask to form a first electrode, a second electrode, and an electrode pattern;
forming first and second active layers by converting a portion of the first active layer pattern and the second active layer pattern into conductors through a second dry etching process; and
A display panel manufacturing method comprising removing the first and second photoresist patterns disposed on the first and second electrodes.
According to claim 31,
The conductive region of the first active layer includes a region between the first and third gate insulating film portions and a region between the second and third gate insulating film portions,
A method of manufacturing a display panel in which the second active layer is entirely conductive.
According to claim 30,
Before forming the gate insulating film material to form the gate insulating film,
forming an auxiliary electrode material on a portion of the upper surface of the first active layer pattern and the entire upper surface of the second active layer pattern; and
patterning the auxiliary electrode material to form first and second auxiliary electrodes spaced apart from each other on the first active layer pattern, and forming third and fourth auxiliary electrodes on each of the upper surfaces of the two active layer patterns. Contains,
Each of the first and second active layer patterns is conductive in a region in contact with the first to fourth auxiliary electrodes.
According to clause 33,
The first auxiliary electrode is disposed in a region between the first gate insulating layer portion and the third gate insulating layer portion,
A display panel manufacturing method wherein the second auxiliary electrode is disposed in a region between the second gate insulating layer portion and the third gate insulating layer portion.
According to clause 33,
The method of manufacturing a display panel, wherein the gate insulating layer includes a portion surrounding one of the second active layers.
According to clause 35,
The step of patterning the electrode material disposed on the gate insulating film,
A first photoresist pattern disposed on the electrode material and overlapping with a portion of each of the first gate insulating layer portion and the first active layer pattern, and a first photoresist pattern overlapping with a portion of each of the second gate insulating layer portion and the first active layer pattern. Forming a third photoresist pattern overlapping with a portion of each of the second photoresist pattern, the third insulating layer portion, and the first active layer pattern, and a fourth photoresist pattern overlapping with the gate insulating layer disposed on the third auxiliary electrode. steps;
patterning the electrode material using the first to fourth photoresist patterns as a mask to form a first electrode, a second electrode, an electrode pattern, and a gate metal layer;
Through a second dry etching process, a portion of the third gate insulating layer is removed, a portion of the first active layer pattern is converted into a conductor to form a first active layer, and a third photo disposed on the electrode pattern is formed. The resist pattern is removed; and
A display panel manufacturing method comprising removing the first, second, and fourth photoresist patterns.
According to clause 36,
In the second dry etching process,
The method of manufacturing a display panel in which the first active layer further conducts a region between the first auxiliary electrode and the third gate insulating layer portion and a region between the second auxiliary electrode and the third gate insulating layer portion.
According to clause 36,
Further comprising forming a second insulating film on the first insulating film,
The third electrode is disposed in a hole provided in the first insulating layer and the second insulating layer and is formed to overlap a gate insulating layer disposed on a channel region of the first active layer.
According to clause 38,
Further comprising forming a pixel electrode on the first and second insulating films,
The third electrode and the pixel electrode are made of a single layer and include different materials.
According to clause 29,
A display panel manufacturing method that simultaneously forms a pixel electrode in the process step of forming the third electrode.

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