KR20240069304A - Display device - Google Patents

Abstract

Embodiments include a substrate including a display area; a plurality of wires electrically connected to the display area; and a sacrificial electrode disposed between the plurality of wires, wherein a voltage lower than that applied to the plurality of wires is applied to the sacrificial electrode.

Description

Display device {DISPLAY DEVICE}

The embodiment relates to a display device.

In the recent information society, the importance of display devices as a visual information transmission medium is increasingly emphasized, and in order to occupy a major position in the future, they must meet requirements such as low power consumption, thinness, weight, and high image quality.

Display devices include Cathode Ray Tube (CRT), Electro Luminescence (EL), Light Emitting Diode (LED), Vacuum Fluorescent Display (VFD), and electric field devices that emit light. It can be divided into luminous types such as Field Emission Display (FED) and Plasma Display Panel (PDP) and non-emissive types that do not emit light themselves, such as Liquid Crystal Display (LCD). .

A display device can improve visibility from various angles or reduce the area of a non-display area by bending at least some areas.

However, the display device is subjected to stress due to bending, and the stress is concentrated in the bending area. Accordingly, there is a problem in that cracks occur in wiring disposed in a bending area where stress is concentrated, thereby reducing reliability.

An embodiment provides a display device that can prevent cracks formed in wiring from propagating.

The problems to be solved by the embodiment are not limited to the problems mentioned above, and other problems not mentioned here will be clearly understood by those skilled in the art from the description below.

A display device according to one aspect of the present invention includes a substrate including a display area; a plurality of wires electrically connected to the display area; and a sacrificial electrode disposed between the plurality of wires, wherein a voltage lower than that applied to the plurality of wires is applied to the sacrificial electrode.

The substrate may include a bending area where the plurality of wires are bent, and the sacrificial electrode may be disposed between the plurality of wires in the bending area.

The negative voltage applied to the sacrificial electrode may be lower than the lowest negative voltage among the negative voltages applied among the plurality of wires.

The sacrificial electrode may be disposed closest to the wire to which the lowest voltage is applied among the plurality of wires.

The negative voltage applied to the sacrificial electrode may be smaller than an average value of voltages applied to the plurality of wires.

The width of the sacrificial electrode may be larger than the plurality of wires.

It includes a drive IC that applies voltage to the plurality of wires, and the drive IC can apply the lowest negative voltage to the sacrificial electrode.

The bending area includes a first planarization layer disposed on the substrate and a second planarization layer disposed on the first planarization layer, and the plurality of wires and the plurality of sacrificial electrodes are disposed on the first planarization layer. You can.

The plurality of sacrificial electrodes include a through electrode that penetrates the first planarization layer and is connected to a connection electrode disposed on the substrate, and the plurality of sacrificial electrodes may be electrically connected by the connection electrode.

The bending area includes a first planarization layer disposed on the substrate and a second planarization layer disposed on the first planarization layer, and the plurality of wires are disposed between the first planarization layer and the second planarization layer. The sacrificial electrode may be disposed between the substrate and the first planarization layer.

The sacrificial electrode may be disposed below a wire to which a negative voltage is applied among the plurality of wires.

The voltage applied to the sacrificial electrode may be different when the panel is driven and when the panel is not driven.

A display device according to another feature of the present invention includes a display panel including a display area; a plurality of wires electrically connected to the display area; and a sacrificial electrode disposed between the plurality of wires, wherein a negative voltage is applied to the sacrificial electrode even when the display panel is not driven.

The voltage applied to the sacrificial electrode may be different when the display panel is driven and when the display panel is not driven.

The sacrificial electrode is disposed closest to the wire to which the lowest voltage is applied among the plurality of wires, and the voltage applied to the sacrificial electrode may be lower than the voltage applied to the wire to which the lowest voltage is applied.

According to the embodiment, it is possible to prevent cracks formed in wiring from propagating.

Additionally, it is possible to prevent wiring from reacting with impurities and corroding.

Accordingly, reliability defects in wiring can be improved, the lifespan of the panel can be increased, and a low-power configuration can be achieved.

The various and beneficial advantages and effects of the embodiments are not limited to the above-described content, and may be more easily understood through description of specific embodiments of the embodiments.

1 is a conceptual diagram of a display device according to an embodiment of the present invention.
Figure 2 is a cross-sectional view showing the cross-sectional structure of the display area.
Figure 3 is a diagram showing a bent state of a display device according to an embodiment of the present invention.
Figure 4 is a diagram showing the process of forming an oxide film on a crack formed in a wiring.
Figure 5 is a diagram showing the process in which corrosion occurs due to cracks formed in wiring.
FIG. 6 is a diagram showing wiring formed in a bending area of a display device.
Figure 7 is a graph measuring cracks in wiring.
Figure 8 is a graph measuring cracks formed in another wiring structure.
Figure 9 is a diagram showing a partial area of the bending area.
Figure 10 is a cross-sectional view taken along line AA' of Figure 9.
Figure 11a is a photograph showing the voltage applied to a plurality of wires.
Figure 11b is a photograph showing a damaged state in which a wiring to which a negative voltage is applied is damaged.
Figure 12 is a block diagram schematically showing the drive IC configuration.
Figure 13 is a diagram showing a modified example of a sacrificial electrode.
FIG. 14 is a cross-sectional view taken along BB' of FIG. 13.
Figure 15 is a diagram showing another modified example of a sacrificial electrode.
Figure 16 is a plan view of Figure 15.
Figure 17 is a conceptual diagram showing a display device according to another embodiment of the present invention.
Figure 18 is a diagram showing the gate driver in a folded state.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the description of the embodiment, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

Features of various embodiments can be partially or entirely combined or combined with each other, various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

The pixel circuit and the gate driver formed on the display panel of the present invention may include a plurality of transistors. Transistors can be implemented as Oxide TFT (Thin Film Transistor) including oxide semiconductor, LTPS including Low Temperature Poly Silicon (LTPS), TFT, etc. And, each of the transistors may be implemented as a p-channel TFT or n-channel TFT.

A transistor is a three-electrode device including a gate, source, and drain. Here, the source is an electrode that supplies carriers to the transistor. Then, within the transistor, carriers begin to flow from the source. Additionally, the drain is the electrode through which carriers go out of the transistor. And, in a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. At this time, the direction of current in the n-channel transistor flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. And, since holes flow from the source to the drain in a p-channel transistor, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between Gate On Voltage and Gate Off Voltage. Here, the gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (VGH/VEH), and the gate-off voltage may be the gate low voltage (VGL/VEL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL/VEL), and the gate-off voltage may be the gate high voltage (VGH/VEL).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a conceptual diagram of a display device according to an embodiment of the present invention. Figure 2 is a cross-sectional view showing the cross-sectional structure of the display area.

Referring to FIG. 1 , a display device according to an embodiment of the present invention may include a display panel 100 including a display area DA and a plurality of wires 200 formed on the display panel 100 .

The display area DA of the display panel 100 includes data lines DL, gate lines GL that intersect the data lines DL, and the data lines DL and the gate lines GL. Pixels P arranged in a matrix form defined by may be arranged. Additionally, the display panel 100 may include a bezel area that is a non-display area (NA) outside the display area (DA).

Each of the pixels P includes subpixels of different colors for color implementation. Subpixels include red (hereinafter referred to as “R subpixel”), green (hereinafter referred to as “G subpixel”), and blue (hereinafter referred to as “B subpixel”). Although not shown, each of the pixels P may further include a white subpixel. Hereinafter, a pixel may be interpreted as a sub-pixel unless otherwise defined. Additionally, each subpixel may include a pixel circuit.

The pixel circuit includes a light-emitting element, a driving element that supplies current to the light-emitting element, one or more switch elements that switch the current paths of the driving element and the light-emitting element, and a voltage (Vgs) between the gate and source of the driving element. It may include a capacitor, etc.

The light emitting device can be implemented as OLED. OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included, but is not limited thereto. When voltage is applied to the anode and cathode electrodes of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, producing visible light in the emitting layer (EML). This is emitted.

The display panel driver writes pixel data of the input image into pixels (P). The display panel driver includes a data driver that supplies a data voltage of pixel data to the data lines DL, and a gate driver (GIP) that sequentially supplies gate pulses to the gate lines GL. The data driver part is integrated into the drive IC (DIC). A drive IC (DIC) may be attached to the display panel 100 .

The drive IC (DIC) is connected to the data lines (DL) through data output channels and supplies the voltage of the data signal to the data lines. The drive IC (DIC) includes a timing controller. The timing controller transmits pixel data of the input image received from the host system to the data driver and controls the operation timing of the data driver and the gate driver (GIP).

The data driver part of the drive IC (DIC) converts pixel data into a gamma compensation voltage through a digital to analog converter (DAC) and outputs the data voltage. The drive IC (DIC) may apply a negative voltage to the sacrificial electrode 210 disposed between the wires.

The gate driver (GIP) may include a pixel array and a shift register formed in the circuit layer of the display panel 100. The shift register of the gate driver (GIP) sequentially supplies gate signals to the gate lines (GL) under the control of the timing controller. The gate signal may include a scan pulse and an emission control pulse.

The display panel may be implemented as a flexible panel applicable to a flexible display. Flexible displays can change the size of the screen by winding, folding, or bending the flexible panel, and can be easily produced in various designs.

Flexible displays can be implemented as rollable displays, foldable displays, bendable displays, slideable displays, etc.

Flexible panels can be made of so-called “plastic OLED panels.” A plastic OLED panel may include a back plate and a pixel array on an organic thin film glued on the back plate. A touch sensor array may be formed on the pixel array.

The back plate may be a PET (Polyethylene terephthalate) substrate. A pixel array and a touch sensor array can be formed on an organic thin film. The back plate can block moisture permeation toward the organic thin film to prevent the pixel array from being exposed to humidity.

The organic thin film may be a polyimide (PI) substrate. A multi-layer buffer film may be formed on the organic thin film using an insulating material not shown.

The driving element of the pixel circuit may be implemented as a transistor. The driving element must have uniform electrical characteristics among all pixels, but there may be differences between pixels due to process deviation and variation in device characteristics and may change over display driving time.

To compensate for variations in the electrical characteristics of the driving elements, the display device may include an internal compensation circuit and an external compensation circuit. The internal compensation circuit is added to the pixel circuit in each of the subpixels to sample the threshold voltage (Vth) and/or mobility (μ) of the driving element that change depending on the electrical characteristics of the driving element and compensate for the changes in real time.

The external compensation circuit may transmit the sensed threshold voltage and/or mobility of the driving element to an external compensation unit through a sensing line connected to each subpixel. The compensation unit of the external compensation circuit can compensate for changes in the electrical characteristics of the driving element by modulating the pixel data of the input image by reflecting the sensing results.

By sensing the voltage of a pixel that changes according to the electrical characteristics of the external compensation driving element and modulating the data of the input image in an external circuit based on the sensed voltage, the deviation in the electrical characteristics of the driving element between pixels can be compensated.

Referring to FIG. 2, circuit layers, device layers, etc. may be stacked on the substrates PI1 and PI2 in the pixel area. The substrates PI1 and PI2 may include a first PI substrate (PI1) and a second PI substrate (PI2). An inorganic layer (IPD) may be formed between the first PI substrate (PI1) and the second PI substrate (PI2). Inorganic membrane (IPD) can block moisture penetration.

The first buffer layer (BUF1) may be formed on the second PI substrate (PI2). A first metal layer may be formed on the first buffer layer (BUF1), and a second buffer layer (BUF2) may be formed on the first metal layer.

The first metal layer may be patterned in a photolithography process. The first metal layer may include a light shield pattern (BSM). The optical shield pattern (BSM) can prevent photo current of the TFT formed in the pixel area by blocking external light so that light is not irradiated to the active layer of the TFT.

When the optical shield pattern (BSM) is formed of a metal with a lower absorption coefficient of the laser wavelength used in the laser ablation process compared to the metal layer (e.g., cathode electrode) to be removed from the second display area (CA), the optical shield pattern (BSM) is formed. BSM) can also serve as an optical shield layer (LS) that blocks the laser beam (LB) in the laser ablation process.

Each of the first and second buffer layers BUF1 and BUF2 is made of an inorganic insulating material and may be composed of one or more insulating layers.

The active layer (ACT) may be formed of a semiconductor material deposited on the second buffer layer (BUF2) and patterned through a photo-lithography process. The active layer (ACT) may include active patterns for each of the TFTs of the pixel circuit and the TFT of the gate driver. The active layer (ACT) may be partially metalized by ion doping. The metalized portion can be used as a jumper pattern to connect metal layers at some nodes of the pixel circuit to connect the components of the pixel circuit.

The gate insulating layer GI may be formed on the second buffer layer BUF2 to cover the active layer ACT. The gate insulating layer (GI) may be made of an inorganic insulating material.

The second metal layer may be formed on the second gate insulating layer (GI). The second metal layer may be patterned by a photo-lithography process. The second metal layer may include a gate line and gate electrode pattern (GATE), a lower electrode of the storage capacitor (Cst1), and a jumper pattern connecting the patterns of the first metal layer and the third metal layer.

The first interlayer insulating layer (ILD1) may be formed on the gate insulating layer (GI) to cover the second metal layer. A third metal layer may be formed on the first interlayer insulating layer (ILD2), and the second interlayer insulating layer (ILD2) may cover the third metal layer. The third metal layer may be patterned by a photo-lithography process. The third metal layer may include metal patterns TM such as the upper electrode of the storage capacitor Cst1. The first and second interlayer insulating layers ILD1 and ILD2 may include an inorganic insulating material.

A fourth metal layer may be formed on the second interlayer insulating layer (ILD2), and an inorganic insulating layer (PAS1) and a first planarization layer (PLN1) may be laminated thereon. A fifth metal layer may be formed on the first planarization layer (PLN1).

Some patterns of the fourth metal layer may be connected to the third metal layer through contact holes penetrating the first planarization layer (PLN1) and the inorganic insulating layer (PAS1). The first and second planarization layers (PLN1 and PLN2) may be made of an organic insulating material that flattens the surface.

The fourth metal layer may include first and second electrodes of the TFT connected to the active pattern of the TFT through a contact hole penetrating the second interlayer insulating layer (ILD2). The data line DL and the power wiring may be implemented as the fourth metal layer pattern SD1 or the fifth metal layer pattern SD2.

The anode electrode (AND), which is the first electrode layer of the light emitting device (OLED), may be formed on the second planarization layer (PLN2). The anode electrode (AND) may be connected to the electrode of the TFT used as a switch element or driving element through a contact hole penetrating the second planarization layer (PLN2). The anode electrode (AND) may be made of a transparent or translucent electrode material.

The pixel defining layer (BNK) may cover the anode electrode (AND) of the light emitting device (OLED). The pixel defining layer (BNK) may be formed in a pattern that defines a light emitting area (or opening area) through which light passes outward from each pixel. A spacer (SPC) may be formed on the pixel defining layer (BNK). The pixel defining layer (BNK) and spacer (SPC) may be integrated with the same organic insulating material. The spacer (SPC) can secure a gap between the FMM and the anode electrode (AND) to prevent the FMM (Fine Metal Mask) from contacting the anode electrode (AND) during the deposition process of the organic compound (EL).

An organic compound (EL) may be formed in the emission area of each pixel defined by the pixel defining layer (BNK). The cathode electrode (CAT), which is the second electrode layer of the light emitting device (OLED), may be formed on the front surface of the display panel 100 to cover the pixel defining layer (BNK), the spacer (SPC), and the organic compound (EL). The cathode electrode (CAT) may be connected to a VSS line formed from any of the underlying metal layers. The capping layer (CPL) may cover the cathode electrode (CAT). The capping layer (CPL) is formed of an inorganic insulating material and can protect the cathode electrode (CAT) by blocking the penetration of air and out gassing of the organic insulating material applied on the capping layer (CPL). there is. The inorganic insulating layer (PAS2) may cover the capping layer (CPL), and a planarization layer (PCL) may be formed on the inorganic insulating layer (PAS2). The planarization layer (PCL) may include an organic insulating material. The inorganic insulating layer (PAS3) of the encapsulation layer may be formed on the planarization layer (PCL).

Figure 3 is a diagram showing a bent state of a display device according to an embodiment of the present invention. Figure 4 is a diagram showing the process of forming an oxide film on a crack formed in a wiring. Figure 5 is a diagram showing the process in which corrosion occurs due to cracks formed in wiring.

Referring to FIG. 3, a portion of the display panel 100 including the drive IC may be bent backward. During this process, a crack 200a may occur in a portion of the wiring 200 disposed in the bending area BA.

Referring to FIG. 4, the wiring 200 may generally be composed of a Ti layer 203, an aluminum layer 202, and a Ti layer 201. Aluminum, titanium, stainless steel, etc. naturally form an oxide film (TiO ₂ , Al ₂ O ₃ ) of several nanometers in the air, which can prevent the metal from corroding.

Therefore, even if a crack 200a occurs in the wiring 200 in the bending area, the oxide film 204 is formed on the surface during the TFT process, as shown in (C) of FIG. 4, and the crack can be prevented from propagating. Additionally, the oxide film 204 due to O ₂ may be formed relatively well on the wiring 200 to which a positive voltage is applied during operation due to an anodizing effect.

However, as shown in FIG. 5, the formation of an oxide film may be hindered due to the high concentration of impurities around the wiring 200 to which a negative voltage is applied. Therefore, Al and Ti may react with surrounding ionic impurities (F ^- , Cl ^- ) rather than with O ₂ and corrosion 205 may occur.

FIG. 6 is a diagram showing wiring formed in a bending area of a display device. Figure 7 is a graph measuring cracks in wiring. Figure 8 is a graph measuring cracks formed in another wiring structure.

Referring to FIG. 6, there are a large number of wires 200 in the bending area BA, and among them, a number of wires to which negative voltages are applied are arranged. For example, in the case of the gate low voltage line (VGL), a negative voltage may be applied. Therefore, if a crack 200a occurs in the gate low voltage line (VGL) during bending, corrosion may occur as voltage is applied thereafter, resulting in a signal defect.

Referring to Figures 7 and 8, it can be seen that many cracks occur in the gate low voltage line (VGL), start signal line (VST), and scan line to which a negative voltage is applied, resulting in a high defect rate. Here, the Y-axis is the number of defects that occurred as a result of the experiment. The G1OUT wiring is connected to the last output of the gate driver and is for monitoring when a defect occurs. The voltage of the last stage of the gate driver is output to the G1OUT wiring.

In contrast, it can be confirmed that no defects were detected in the gate high voltage wiring (VGH), etc., where a positive voltage is applied. Therefore, it is important to create an environment in which an oxide film is well formed on wiring to which such negative voltage is applied.

Referring to FIGS. 9 and 10 , the sacrificial electrode 210 may be disposed closer to the wiring 202 to which a negative voltage is applied than to the wiring 201 to which a positive voltage is applied. The sacrificial electrode 210 may be placed around wiring to which more than 50% of the negative voltage is applied during the signal cycle. That is, the sacrificial electrode 210 may be disposed on a wiring to which positive and negative voltages are alternately applied during one cycle when more negative voltage is applied.

At this time, the width W2 of the sacrificial electrode 210 may be the same as the width W1 of the wiring 200, but is not necessarily limited thereto. For example, the width W2 of the sacrificial electrode 210 may be larger or smaller than the width W1 of the wiring 200. Additionally, the width W2 of the sacrificial electrode 210 may have different widths depending on the space where it is to be placed.

According to an embodiment, after bending the bending area BA when manufacturing a panel, voltage may be applied to the plurality of wires 200 and the sacrificial electrode 210 for a predetermined time. A film can be formed on the plurality of wirings 200 by applying a positive voltage to the plurality of wirings 200 and applying a negative voltage to the sacrificial electrode 210 in an O ₂ atmosphere to perform an anodizing process. . Therefore, an oxide film is formed on the crack formed during the bending process, thereby preventing the crack from propagating. Anodizing may refer to an electrochemical process that forms a film using an anodic oxidation action.

For effective anodizing, it may be advantageous to adjust the voltage difference between the sacrificial electrode 210 and the wiring 200 to 17 V or more. As an example, a voltage of 8.5V may be applied to all wiring and a voltage of -8.5V may be applied to the sacrificial electrode, but this is not necessarily limited. The negative voltage applied to the sacrificial electrode 210 may be set to be smaller than the average value of the voltage applied to the plurality of wires. Even in this case, a film may be formed on the wiring to which a higher voltage is applied than the sacrificial electrode.

After panel manufacturing is completed and the panel is driven, a voltage lower than the lowest voltage among the voltages applied to the plurality of wires 200 may be applied to the sacrificial electrode 210 . For example, if -11V is applied to the gate low voltage line (VGL), a lower voltage of about -17V may be applied to the sacrificial electrode 210. Accordingly, a voltage difference occurs between the gate low voltage line and the sacrificial electrode 210, and the sacrificial electrode 210 to which a relatively high voltage is applied may be corroded and a film may be formed on the gate low voltage line VGL.

According to an embodiment, a film is initially formed on all wiring during the panel manufacturing process, and a film can be continuously formed on the wiring by applying a negative voltage to the sacrificial electrode during driving. As a result, even if a crack occurs in the wiring 200 due to the bending process, an oxide film is formed around the crack to prevent the crack from propagating. Accordingly, reliability defects in wiring can be improved.

Referring to (a) of FIG. 11, the gate high voltage line (VGH) and the gate low voltage line (VGL) may be disposed adjacent to each other. At this time, if the voltage applied to the gate high voltage wiring (VGH) is -11.5V and the voltage applied to the gate low voltage wiring (VGL) is 6.2V, corrosion failure may occur. That is, at a voltage difference of 17.7V, the positive wiring may be anodized and the negative wiring may be corroded. Therefore, a portion of the gate low voltage wiring (VGL) may be damaged, as shown in FIG. 11(b).

To prevent this phenomenon, the embodiment may place the sacrificial electrode 210 adjacent to the gate low voltage line (VGL). Accordingly, the voltage applied to the gate low voltage line (VGL) is lower than that of the gate high voltage line (VGH), but the voltage applied to the gate low voltage line (VGL) is relatively high compared to the sacrificial electrode 210, so corrosion can be prevented. By placing the sacrificial electrode 210 between the gate high voltage line (VGH) and the gate low voltage line (VGL), corrosion of the gate low voltage line (VGL) can be more effectively prevented.

Table 1 and Table 2 below are tables showing the voltage of each wiring and sacrificial electrode.

Wiring type Voltage VGH1, VGL1 6.2V, -11.5V VGH2, VGL2 6.2V, -11.5V VINI_H/VOBS 6.0V VINI_L / VINI -5.0V VAR -5.6V ELVDD 2.8V ELVSS -5.6V sacrificial electrode -15V

Wiring type Voltage VGH1, VGL1 12.2V, 0.5V VGH2, VGL2 18.2V, 0.5V VINI_H/VOBS 18.0V VINI_L / VINI 7.0V VAR 6.4V ELVDD 14.8V ELVSS 6.4V sacrificial electrode -3V

As shown in Table 1, negative voltage is applied to the gate low voltage wiring (VGL1, VGL2), initialization voltage wiring (VINI_L), and reset voltage wiring (VAR), and the voltage of the sacrificial electrode is higher than the lowest voltage applied to the wiring. It can be set to a low negative voltage (-15V). Additionally, as shown in Table 2, all voltages of the wiring may be set to positive voltages, and only the voltage of the sacrificial electrode may be set to a negative voltage (-3V).

In another embodiment, the voltage applied to the wiring may be applied differently when the display device is driven and when the display device is not driven. Table 3 below shows the voltage applied to each wire when driving, and Table 4 shows the voltage applied to each wire and sacrificial electrode when not driven.

Wiring type Voltage VGH1, VGL1 6.2V, -11.5V VGH2, VGL2 6.2V, -11.5V VINI_H/VOBS 6.0V VINI_L / VINI -5.0V VAR -5.6V ELVDD 2.8V ELVSS -5.6V sacrificial electrode -15V

Wiring type Voltage VGH1, VGL1 GND VGH2, VGL2 GND VINI_H/VOBS GND VINI_L / VINI GND VAR GND ELVDD GND ELVSS GND sacrificial electrode -3.5V

Wiring type Voltage VGH1, VGL1 3.5V VGH2, VGL2 3.5V VINI_H/VOBS 3.5V VINI_L / VINI 3.5V VAR 3.5V ELVDD 3.5V ELVSS 3.5V sacrificial electrode -3.5V

Referring to Table 3, the voltage of the sacrificial electrode may be applied at a lower voltage than the wiring to which a negative voltage is applied during driving. The voltage can be applied so that the lowest negative voltage is 3.5V lower than the applied wiring (VGL). For example, -11.5V may be applied to the wiring to which the lowest negative voltage is applied, and -15V may be applied to the sacrificial electrode.

However, as shown in Table 4, when not driving, no voltage is applied to the wiring, so a voltage of -3.5V, which is lower than the ground (0V), can be applied. That is, the voltage applied to the sacrificial electrode may be set differently when the panel is driven and when the panel is not driven. Additionally, as shown in Table 5, when the screen is not driven, the potential difference can be increased by uniformly applying 3.5V voltage to each wire.

Figure 12 is a block diagram schematically showing the drive IC configuration.

Referring to FIG. 12 , a drive IC (DIC) may be connected to the host system 200, the first memory 301, and the display panel 100. The drive IC (DIC) may include a data reception and calculation unit 308, a timing controller 303, a data driver 306, a gamma compensation voltage generator 305, a power supply unit 304, and a second memory 302. You can.

The data reception and calculation unit 308 may include a reception unit that receives pixel data input as a digital signal from the host system 200, and a data calculation unit that improves image quality by processing the pixel data input through the reception unit.

The data operation unit may include a data restoration unit that decodes and restores compressed pixel data, and an optical compensation unit that adds a preset optical compensation value to the pixel data. The optical compensation value may be set as a value for correcting the luminance of each pixel data based on the luminance of the screen measured based on camera images captured during the manufacturing process.

The timing controller 303 may provide pixel data of an input image received from the host system 200 to the data driver 306. The timing controller 303 generates a gate timing signal for controlling the gate driver (GIP) and a source timing signal for controlling the data driver 306 to control the operation timing of the gate driver (GIP) and the data driver 306. You can control it.

The data driver 306 may convert digital data including pixel data received from the timing controller 303 through a digital to analog converter (DAC) into a gamma compensation voltage and output the data voltage. The data voltage output from the data driver 306 may be supplied to the data lines DL of the pixel array through an output buffer connected to the data channel of the drive IC (DIC).

The gamma compensation voltage generator 305 may generate a gamma compensation voltage for each gray level by dividing the gamma reference voltage from the power supply unit 304 through a voltage dividing circuit. The gamma compensation voltage is an analog voltage whose voltage is set for each gray level of pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 may be provided to the data driver 306.

The power supply unit 304 may use a DC-DC converter to generate power required to drive the pixel array, gate driver (GIP), and drive IC (DIC) of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

The power supply unit 304 adjusts the direct current input voltage from the host system 200 to a gamma reference voltage and a gate-off voltage (VGL). Direct current power such as gate-on voltage (VGH), pixel driving voltage (VDD), low-potential power supply voltage (VSS), and initialization voltage (Vini) can be generated. At this time, the power supply unit 304 may also generate a negative voltage applied to the sacrificial electrode 210.

The gamma reference voltage may be supplied to the gamma compensation voltage generator 305. The gate-off voltage (VGL) and gate-on voltage (VGH) may be supplied to the level shifter 307 and the gate driver (GIP). Pixel power, such as the pixel driving voltage (VDD), low-potential power supply voltage (VSS), and initialization voltage (Vini), may be commonly supplied to the pixels (P). Additionally, the lowest negative voltage can be applied to the sacrificial electrode.

The initialization voltage (Vini) is set to a direct current voltage lower than the pixel driving voltage (VDD) and lower than the threshold voltage of the light-emitting device (OLED) to initialize the main nodes of the pixel circuits and suppress the light emission of the light-emitting device (OLED). .

The second memory 302 may store compensation values, register setting data, etc. received from the first memory 301 when power is input to the drive IC (DIC).

Compensation values can be applied to various algorithms that improve image quality. The compensation value may include an optical compensation value. Register setting data can define the operations of the data driver 306, timing controller 303, and gamma compensation voltage generator 305. The first memory 301 may include flash memory. The second memory 302 may include static RAM (SRAM).

Figure 13 is a diagram showing a modified example of a sacrificial electrode. FIG. 14 is a cross-sectional view taken along line B-B' of FIG. 13. Figure 15 is a diagram showing another modified example of a sacrificial electrode. Figure 16 is a plan view of Figure 15.

13 and 14, in the bending area, the sacrificial electrode 210 is disposed between the first planarization layer (PLN1) and the second planarization layer (PLN2) and is a penetrating electrode ( 211) and a connection electrode 212 disposed between the first planarization layer (PLN1) and the substrate (PI). According to this configuration, since a plurality of sacrificial electrodes 210 are connected to each other, the number of pads connecting the sacrificial electrode 210 and the drive IC can be reduced. That is, if a negative voltage is applied to only one of the plurality of sacrificial electrodes 210, a negative voltage can be applied to all of the connected sacrificial electrodes 210.

Referring to FIGS. 15 and 16 , the sacrificial electrode 210 may be disposed below the plurality of wires 200 . Since the plurality of wires 200 are densely arranged in the bending area, it may be difficult to secure a place to form the sacrificial electrode 210. In this case, by disposing the sacrificial electrode 210 below the first planarization layer (PLN1), a film can be formed while ensuring the arrangement of the plurality of wires 200 as is. This configuration can maximize the area of the bending area and thus improve the degree of freedom in designing the wiring 200.

The width of the sacrificial electrode 210 may be larger than the width of the wiring 200 . Accordingly, one sacrificial electrode 210 can serve as a sacrificial electrode for a plurality of wires. Additionally, when a plurality of wires 200 to which a negative voltage is applied are arranged adjacent to each other, a sacrificial electrode 210 having a width that overlaps the plurality of wires 200 may be disposed below.

According to this configuration, the sacrificial electrode 210 can be formed under the wiring 200 to which a negative voltage is applied, which has the advantage of being easy to design.

Figure 17 is a conceptual diagram showing a display device according to another embodiment of the present invention. Figure 18 is a diagram showing the gate driver in a folded state.

Referring to FIGS. 17 and 18 , the display device according to the embodiment includes a gate driver (GIP) connected to the display area DA, and a sacrificial electrode 210 between the wires 200 of the gate driver (GIP). This can be placed.

A portion of the display panel 100 including the drive IC (DIC) may be bent backward. Accordingly, a bending area BA may be formed in the display panel 100, and a sacrificial electrode 210 may be disposed in the bending area BA.

Additionally, the display panel 100 can be folded in both bezel areas where the gate driver (GIP) is mounted. Accordingly, bending areas BA may be formed in bezel areas on both sides of the display panel 100 based on the X direction, and sacrificial electrodes 210 may be disposed in the bending areas BA. Therefore, reliability can be secured even if a crack occurs in the wiring in the bending area of the gate driver (GIP).

Since the contents of the specification described in the problem to be solved, the means to solve the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display panel
200: Wiring
210: sacrificial electrode
BNK: bank
PAS: Inorganic insulating layer
PLN1: first planarization layer
PLN2: second planarization layer
SPC: Spacer

Claims (15)

A substrate including a display area;
a plurality of wires electrically connected to the display area; and
Includes a sacrificial electrode disposed between the plurality of wires,
A display device in which a voltage lower than that applied to the plurality of wires is applied to the sacrificial electrode. According to paragraph 1,
The substrate includes a bending area where the plurality of wires are bent,
The sacrificial electrode is disposed between the plurality of wires in the bending area. According to paragraph 1,
The display device wherein the negative voltage applied to the sacrificial electrode is lower than the lowest negative voltage among the negative voltages applied among the plurality of wires. According to paragraph 1,
A display device in which the sacrificial electrode is disposed closest to a wire to which the lowest voltage is applied among a plurality of wires. According to paragraph 1,
A display device wherein the negative voltage applied to the sacrificial electrode is smaller than an average value of voltages applied to the plurality of wires. According to paragraph 1,
A display device in which the width of the sacrificial electrode is greater than the width of each of the plurality of wires. According to paragraph 1,
Includes a drive IC that applies voltage to the plurality of wires,
A display device in which the drive IC applies the lowest negative voltage to the sacrificial electrode. According to paragraph 2,
The bending area includes a first planarization layer disposed on the substrate and a second planarization layer disposed on the first planarization layer,
A display device wherein the plurality of wires and the plurality of sacrificial electrodes are disposed on a first planarization layer. According to clause 8,
The plurality of sacrificial electrodes include a through electrode that penetrates the first planarization layer and is connected to a connection electrode disposed on the substrate,
A display device in which the plurality of sacrificial electrodes are electrically connected by the connection electrode. According to paragraph 2,
The bending area includes a first planarization layer disposed on the substrate and a second planarization layer disposed on the first planarization layer,
The plurality of wires are disposed between the first planarization layer and the second planarization layer,
The sacrificial electrode is disposed between the substrate and the first planarization layer. According to clause 10,
The display device wherein the sacrificial electrode is disposed below a wire to which a negative voltage is applied among the plurality of wires. According to paragraph 1,
A display device in which the voltage applied to the sacrificial electrode is different when the panel is driven and when the panel is not driven. A display panel including a display area;
a plurality of wires electrically connected to the display area; and
Includes a sacrificial electrode disposed between the plurality of wires,
A display device in which a negative voltage is applied to the sacrificial electrode even when the display panel is not driven. According to clause 13,
A display device wherein the sacrificial electrode has a different voltage applied when the display panel is driven and when the display panel is not driven. According to clause 13,
The sacrificial electrode is disposed closest to the wire to which the lowest voltage is applied among the plurality of wires,
A display device in which the voltage applied to the sacrificial electrode is lower than the voltage applied to the wiring to which the lowest voltage is applied.

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