KR20240045701A - Nuclear PR, NEMP and non-nuclear NNEMP multi-protection devices with multi-signal processing circuitry - Google Patents

Abstract

The present invention relates to a nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device, which includes at least one of an EMP sensing unit including a PR sensor and an EMP sensor, a sensor circuit unit that outputs a sensing signal, and a final EMP signal based on the sensing signal. An error filtering unit that generates a detection signal, a multi-signal processor that receives the output of the sensor circuit unit and the error filtering unit and outputs a power-off command signal to control the power based on a preset sensitivity, and a multi-signal processing unit that receives the output of the sensor circuit unit and the error filtering unit and outputs a power-off command signal and a power control unit that cuts off power supplied to the electronic device, wherein the multi-signal processor outputs the power cut-off command signal when one of the outputs of the sensor circuit unit and the error filtering unit exceeds the preset sensitivity. Do it as

Description

Nuclear PR, NEMP and non-nuclear NNEMP multi-protection devices with multi-signal processing circuitry}

The present invention relates to a multiple protection device, and more specifically, to a nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device equipped with a multiple signal processing circuit.

When a prompt gamma-ray, a high-energy radiation (PR) in the form of a pulse, is incident on electronic equipment during a nuclear explosion, the electrons in the atom are separated due to the strong energy, creating a large amount of electron/hole pairs, and depending on the applied bias. This causes unwanted current flow in electronic devices. As a result, an error occurs due to an upset phenomenon in which the data value in the device changes, or a latch-up phenomenon occurs in which a parasitic thyristor in the electronic device operates, causing the device to be damaged. Additionally, the movement of electrons generated by the nuclear explosion causes NEMP (Nuclear Electromagnetic Pulse) to occur. NEMP refers to the electromagnetic wave rupture caused by a nuclear explosion, and the rapidly changing electric and magnetic fields resulting from this can be associated with electrical and electronic systems that cause harmful current and voltage surges. Therefore, the NEMP causes a lock-up phenomenon in a wide range of electronic equipment, resulting in paralysis of military power. In addition to the NEMP mentioned above, NNEMP (non-nuclear EMP, non-nuclear NEMP) also exists and causes damage to electronic equipment and communication networks in specific areas within several kilometers. As detailed above, the high-energy PR and nuclear NEMP and NNEMP generated during a nuclear explosion cause malfunction and paralysis of devices and electronic systems, acting as a serious risk factor for major national facilities and military weapons systems.

The technology to protect electronic equipment from nuclear bomb damage that is currently being developed and applied has the problem of being applied independently to pulse radiation and NEMP damage that initially occur simultaneously. This is because if only one side is protected, the equipment being protected will be damaged by the other side's energy. To overcome the above problems, for example, Patent Publication No. 10-2017-0103555 discloses a protection technology that combines TVS (Transient voltage suppression) for NEMP protection and NED (nuclear event detector) for PR blocking into one module. . This active power control technique can be simultaneously applied to NEMP protection using the signal from the NED sensor.

However, since the detection area of the NED sensor is relatively narrow compared to NEMP, there is a problem in that the active protection area of NEMP only corresponds to a portion of the entire NEMP damage area. Additionally, there is a problem that the NED and the power control circuit must be configured separately. In addition, non-nuclear NEMPs generated by EMP bombs mounted on missiles or aircraft bombs disable a wide range of enemy communication networks or command and control systems with a power approximately 100 times stronger than lightning, and portable EMP bombs can be used to target the enemy's rear, civilian areas, etc. Since it attacks areas where high-tech equipment is operated and stops the operation of the equipment, protective measures are necessary. In other words, the existing EMP protection technology (Shield Filter) has limitations in applicability to various fixed-mobile advanced electronic weapon systems, and in particular, the transient surge current induced inside electronic equipment due to external high-output electromagnetic wave energy cannot be applied to existing EMP protection technology. Because the blocking is incomplete, the effects of the fault signal generated when the power is turned on and off must be blocked.

Korean Patent Publication No. 10-2017-0103555 (“Nuclear protection module and control method thereof”. Announcement date 2017.09.13.)

The present invention was created to solve the problems described above, and the purpose of the nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to the present invention is to protect electronic equipment from PR, NEMP, and non-nuclear NNEMP caused by nuclear bombs. The goal is to provide an active, integrated protection device that is easy to apply to the target.

Nuclear PR, NEMP, and non-nuclear NNEMP multiple protection devices according to various embodiments of the present invention to solve the problems described above include at least one of an EMP sensing unit including a PR sensor and an EMP sensor to output a sensing signal. A sensor circuit unit, an error filtering unit that generates a final EMP detection signal based on the sensing signal, a multiplexer that receives the outputs of the sensor circuit unit and the error filtering unit and outputs a power cut command signal that controls the power based on a preset sensitivity. It includes a signal processing unit and a power control unit that cuts off power supplied to the electronic device based on the power cut command signal, wherein the multi-signal processing unit causes one of the sensor circuit unit and the error filtering unit output to exceed the preset sensitivity. When doing so, the power cut-off command signal is output.

In addition, the feedback inverter logic circuit is connected to the output of the multiple signal processor, and the output is connected to the input of the multiple signal processor, and adjusts the maintenance time of the power cut command signal output from the multiple signal processor to the power control unit. It is characterized in that it further includes a power cut-off time control unit.

In addition, the multiple signal processing unit is characterized by including a NOR logic circuit that receives the output of the sensor circuit unit.

In addition, the multi-signal processing unit, the feedback inverter logic circuit, or the power-off time control unit is characterized in that the circuit is composed only of a plurality of p-MOSFETs and passive elements.

In addition, the NOR logic circuit includes first and second p-MOSFETs and first and second n-MOSFETs whose gate terminals are connected to the first and second p-MOSFETs, respectively, where the source terminal of the first p-MOSFET is is connected to a predetermined voltage, the source terminal of the first p-MOSFET is connected to a predetermined voltage, the drain terminal of the first p-MOSFET is connected to the source terminal of the second p-MOSFET, and the first p -The gate terminal of the MOSFET is connected to the PR sensor, and the gate terminal of the second p-MOSFET is connected to the error filtering unit, and the first and second n-MOSFETs are connected to each other at their source terminals and drain terminals, and the second p-MOSFET is connected to the error filtering unit. The connection nodes of the source terminals of the 1st and 2nd n-MOSFETs are connected to the drain terminals of the second p-MOSFETs, and the connection nodes of the drain terminals of the first and 2nd n-MOSFETs are connected to the ground.

In addition, the NOR logic circuit includes first and second p-MOSFETs and a first resistor connected to the second p-MOSFET, wherein the source terminal of the first p-MOSFET is connected to a predetermined voltage, and the first p-MOSFET is connected to a predetermined voltage. -The drain terminal of the MOSFET is connected to the source terminal of the second p-MOSFET, the gate terminal of the first p-MOSFET is connected to the PR sensor, and the gate terminal of the second p-MOSFET is connected to the error filtering unit. It is characterized by being

In addition, the NOR logic circuit includes first to third p-MOSFETs and first to third n-MOSFETs whose gate terminals are connected to each of the first to third p-MOSFETs, wherein the source terminal of the first p-MOSFET is connected to a predetermined voltage, the drain terminal of the first p-MOSFET is connected to the source terminal of the second p-MOSFET, the gate terminal of the first p-MOSFET is connected to the PR sensor, and the second The gate terminal of the p-MOSFET is connected to the error filtering unit, the drain terminal of the second p-MOSFET is connected to the source terminal of the third p-MOSFET, and the first to third n-MOSFETs are connected to each other's source terminals. and drain terminals are connected to each other, so that the connection node of the source terminal of the first to third n-MOSFETs is connected to the drain terminal of the third p-MOSFET, and the connection node of the drain terminal of the first to third n-MOSFETs is connected to It is connected to the ground, and the feedback inverter logic circuit includes a p-MOSFET for feedback and an n-MOSFET for feedback connected between the p-MOSFET for feedback and a drain terminal, and the power cut-off time control unit is a p-MOSFET for adjusting the cut-off time. , a capacitor and a resistor for adjusting the blocking time, wherein the source terminal of the feedback p-MOSFET is connected to the predetermined voltage, the source terminal of the feedback n-MOSFET is connected to the ground, and the gate terminal of the feedback n-MOSFET is connected to the ground. is connected to the gate terminal of the feedback p-MOSFET, and the gate terminal of the third p-MOSFET is connected to the connection node of the drain terminal of the feedback p-MOSFET and the feedback n-MOSFET, and the capacitor is The drain terminal of the third p-MOSFET is connected to the resistor for controlling the blocking time, and the resistor for controlling the blocking time is connected to the source terminal of the first p-MOSFET and the gate terminal of the feedback p-MOSFET, and the blocking time is connected to the source terminal of the first p-MOSFET and the gate terminal of the feedback p-MOSFET. The drain terminal and source terminal of the time control p-MOSFET are connected to both ends of the capacitor, and the gate terminal of the blocking time control p-MOSFET is connected to the connection node of the feedback p-MOSFET and the feedback n-MOSFET. It is characterized by

In addition, the NOR logic circuit includes first to third p-MOSFETs and a first resistor connected to the third p-MOSFET, wherein the source terminal of the first p-MOSFET is connected to a predetermined voltage, and the first p-MOSFET is connected to a predetermined voltage. -The drain terminal of the MOSFET is connected to the source terminal of the second p-MOSFET, the drain terminal of the second p-MOSFET is connected to the source terminal of the third p-MOSFET, and the gate of the first p-MOSFET The terminal is connected to the PR sensor, the gate terminal of the second p-MOSFET is connected to the error filtering unit, and the feedback inverter logic circuit is connected to the feedback p-MOSFET and the drain terminal of the feedback p-MOSFET. 2 resistors, wherein the connection node of the feedback p-MOSFET and the second resistor is connected to the gate terminal of the third p-MOSFET, and the power cut-off time control unit includes a p-MOSFET for cut-off time adjustment, a capacitor, and a cut-off time control unit. It includes a resistor for time adjustment, wherein the source terminal of the feedback p-MOSFET is connected to the predetermined voltage, the second resistor is connected to ground, and the capacitor is connected to the drain terminal of the third p-MOSFET and the blocking time. It is connected to a resistor for adjustment, wherein the resistor for adjusting the blocking time is connected to the source terminal of the first p-MOSFET and the gate terminal of the p-MOSFET for feedback, and the drain terminal and the source terminal of the p-MOSFET for adjusting the blocking time are connected to the It is connected to both ends of the capacitor, and the gate terminal of the p-MOSFET for blocking time adjustment is connected to the connection node of the feedback p-MOSFET and the second resistor.

According to the nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to various embodiments of the present invention as described above, it is possible to detect not only PR and NEMP generated from a nuclear explosion but also non-nuclear EMP, and simultaneously process PR sensor and EMP sensor signals. There is a possible effect.

In addition, it has the effect of preventing secondary damage by embedding a power cut and return function within a time period during which the target weapon system can operate normally.

In addition, it has the effect of minimizing malfunction of the protection module through error signal discrimination technology for Absolute Need State operation.

Figure 1 is a block diagram showing the configuration of a nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention;
Figure 2 is a diagram illustrating Figure 1 in detail,
Figure 3 is a diagram showing an external EMP sensor unit according to an embodiment of the present invention;
Figure 4 is a diagram showing an internal EMP sensor unit according to an embodiment of the present invention;
Figure 5 is a circuit diagram showing an error filtering unit according to an embodiment of the present invention;
Figure 6 is a circuit diagram showing an error filtering unit according to another embodiment of the present invention;
Figure 7 is a circuit diagram showing a multiple signal processing unit according to an embodiment of the present invention;
Figure 8 is a circuit diagram showing a radiation-resistant multiple signal processing unit according to another embodiment of the present invention;
Figure 9 is a graph showing simulation results of the power-off time control unit according to an embodiment of the present invention;
Figure 10 is a circuit diagram showing a power control unit according to an embodiment of the present invention;
Figure 11 is a diagram showing a nuclear PR, NEMP and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention;
Figure 12 is a diagram showing the connection of nuclear PR, NEMP, and non-nuclear NNEMP multiple protection devices according to an embodiment of the present invention.

In order to explain the present invention, its operational advantages, and the purpose achieved by practicing the present invention, preferred embodiments of the present invention are illustrated and discussed with reference to them.

First, the terms used in this application are only used to describe specific embodiments and are not intended to limit the present invention, and singular expressions may include plural expressions unless the context clearly indicates otherwise. In addition, in the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other It should be understood that this does not exclude in advance the presence or addition of features, numbers, steps, operations, components, parts, or combinations thereof.

In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

Figure 1 is a block diagram showing the configuration of a nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention.

As shown in Figure 1, the nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention includes a sensor circuit unit 100, an error filtering unit 300, a multiple signal processing unit 200, and a power control unit ( 500),

The sensor circuit unit 100 includes at least one of a PR sensor 110 that generates a photocurrent in response to gamma rays and an EMP sensing unit 120 that detects EMP, and outputs a sensing signal.

The error filtering unit 300 generates a final EMP detection signal based on the sensing signal.

The multi-signal processing unit 200 uses the outputs of the sensor circuit unit 100 and the error filtering unit 300 as input and outputs a power cut command signal for controlling the power of the electronic device based on a preset sensitivity.

The power control unit 500 turns off the power of the electronic device based on the power-off command signal generated by the multi-signal processor 200.

At this time, the nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention may be provided between the power source and the electronic device.

In addition, a power-off time control unit 400 may be further included between the multiple signal processing unit 200 and the power control unit 500.

FIG. 2 is a diagram illustrating FIG. 1 in detail.

Through Figure 2, the nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention will be described in detail.

As shown in FIG. 2, the EMP sensing unit 120 of the sensor circuit unit 100 may include an external EMP sensor unit 121 and an internal EMP sensor unit 122.

Figure 3 is a diagram showing the external EMP sensor unit of the present invention.

As shown in FIG. 3, the external EMP sensor unit 121 may include an antenna sensor. The antenna sensor includes a filter function that detects only frequencies within a predetermined range of EMP, and may include an indicator that measures a plurality of voltages and at least one 90° magnetic field sensor. The 90° magnetic field sensor is provided on the x-axis, y-axis, and z-axis, which can expand the detection area and prevent shadow effects. The shadow effect refers to a phenomenon in which a range that cannot be sensed exists depending on the angle of electromagnetic waves. More specifically, the external EMP sensor unit 121 receives electromagnetic waves from the antenna sensor and operates as an AC power source, generating a magnetic field in the primary coil (L1), an induced current flows in the secondary coil (L2), and the inductor Depending on the values of (L1, L2) and capacitor (C1), a strong induced current flows only in electromagnetic waves of the same frequency as the resonance frequency.

Meanwhile, the internal EMP sensor unit 122 can sense the internal instantaneous current induced by EMP.

Figure 4 is a diagram showing the internal EMP sensor unit of the present invention.

As shown in FIG. 4, the internal EMP sensor unit 122 may include a current sensing circuit. At this time, the internal EMP sensor unit 122 may include a current sensing circuit for internal instantaneous current sensing, and has a Flat Freq. It may be configured to include characteristics and impedance characteristics similar to those of the target shield. Specifically, the current sensing circuit may include a shunt resistor (resistor for current detection). As a result, radiation resistance characteristics can be secured by implementing only radiation-resistant passive elements without radiation-sensitive active elements. Accordingly, the voltage generated by the internal EMP sensor unit 122 can be applied to the error filtering unit 300, and current changes can be monitored.

In addition, the PR sensor 110 and the internal EMP sensor unit 122 of the sensor circuit unit 100 are provided on one board and share a circuit for processing the sensing signal, so miniaturization is possible.

In addition, the error filtering unit 300 may generate a final EMP detection signal based on the sensing signal. Based on the sensing signals of the external EMP sensor unit 121 and the internal EMP sensor unit 122, cases of detection errors can be filtered out to determine whether the final EMP detection signal is activated. Specifically, the error filtering unit 300 may deactivate the final EMP detection signal when one of the plurality of EMP sensing signals is not EMP detected. On the other hand, when all of the plurality of EMP sensing signals are EMP detection, the final EMP detection signal can be activated. More specifically, the error filtering unit 300 may include an AND logic circuit connected to a plurality of EMP sensing signals. At this time, it is revealed that the plurality of EMP sensing signals is a term that collectively represents each of the sensing signals of the external EMP sensor unit 121 and the internal EMP sensor unit 122.

Figure 5 is a circuit diagram showing an error filtering unit according to another embodiment of the present invention.

As shown in FIG. 5, the error filtering unit 300 may include a NAND logic circuit and an inverting logic circuit.

The NAND logic circuit receives multiple sensing signals.

The inverting logic circuit receives the output of the NAND logic circuit and inverts it to provide a final EMP detection signal.

Specifically, the NAND logic circuit includes first and second p-MOSFETs (P1, P2) and first and second n-MOSFETs (N1, N2) connected to at least one of the first and second p-MOSFETs. ) may include.

Additionally, the inverting logic circuit may include a third p-MOSFET (P3) and a third n-MOSFET (N3) connected to the drain terminal of the third p-MOSFET (P3).

More specifically, looking at the connection relationship of each configuration, the source terminals of the first to third p-MOSFETs are all connected to voltages of the same predetermined magnitude, and the gate terminal of the first p-MOSFET (P1) is connected to the plurality of voltages. It may be connected to any one of the EMP sensing signals and the gate terminal of the first n-MOSFET (N1). At this time, the EMP sensing signal connected to the gate terminal of the first p-MOSFET (P1) may be a sensing signal output from the external EMP sensor unit 121.

Additionally, the gate terminal of the second p-MOSFET (P2) may be connected to the gate terminal of the second n-MOSFET (N2) and connected to another EMP sensing signal among the plurality of EMP sensing signals. In addition, the drain terminal of the second p-MOSFET (P2) may be connected to the drain terminal of the first n-MOSFET (N1), and the source terminal of the first n-MOSFET (N1) may be connected to the second n-MOSFET (N1). It can be connected to the drain terminal of the MOSFET (N2). Meanwhile, the gate terminal of the third p-MOSFET (P3) is connected to the gate terminal of the third n-MOSFET (N3), and the gate terminal of the first p-MOSFET (P1) is connected to the second p-MOSFET. It may be connected to a connection node between (P2) and the first n-MOSFET (N1) and to a connection node between the third p-MOSFET (P3) and the third n-MOSFET (N3). The above-described circuit is based on CMOS logic, which reduces the complexity of the circuit structure and operation and enables miniaturization. In addition, by finally applying the AND logic circuit, 1 is output when the sensing signal is detected simultaneously in the external EMP sensor unit 121 and the internal EMP sensor unit 122, thereby outputting the final EMP detection signal. You can.

Meanwhile, the error filtering unit 300 may be composed only of a plurality of p-MOSFETs and passive elements excluding the n-MOSFET, which is vulnerable to radiation. Specifically, the n-MOSFET of FIG. 5 may be replaced with a passive element, and more specifically, the passive element may be a resistor.

Figure 6 is a circuit diagram showing an error filtering unit according to another embodiment of the present invention.

As shown in FIG. 6, the AND logic circuit may include first to n p-MOSFETs and first to m passive elements.

The first to n p-MOSFETs may be the first to third p-MOSFETs (P1, P2, P3).

The first to m passive elements may be the first and second passive elements R1 and R2, and may be connected to the second p-MOSFET (P2) and ground, and the third p-MOSFET (P3) and ground, respectively.

Specifically, looking at the connection relationship of each configuration, the source terminal of the first to third p-MOSFETs is connected to a voltage of a predetermined magnitude, and the gate terminal of the first p-MOSFET (P1) is connected to the plurality of EMP sensing signals. It can be connected to any one of the EMP sensing signals. Additionally, the gate terminal of the second p-MOSFET (P2) may be connected to another EMP sensing signal among the plurality of EMP sensing signals. More specifically, the gate terminal of the first p-MOSFET (P1) may be connected to the external EMP sensor unit 121, and the gate terminal of the second p-MOSFET (P2) may be connected to the internal EMP sensor unit 122. ) can be connected to. Additionally, drain terminals of the first and second p-MOSFETs (P1, P2) may be connected to the gate terminal of the third p-MOSFET (P3). Accordingly, the n-MOSFET, which is vulnerable to radiation, can be replaced with a resistor, thereby ensuring radiation resistance characteristics of the error filtering unit 300.

The multiple signal processing unit 200 may output the power cut-off command signal when a signal input from at least one of the sensor circuit unit 100 and the error filtering unit 300 is higher than the preset sensitivity.

Specifically, it may include a CMOS-based NOR logic circuit for multiple signal processing.

The NOR logic circuit receives the output of the sensor circuit unit 100.

Figure 7 is a circuit diagram showing a multiple signal processing unit according to an embodiment of the present invention.

As shown in FIG. 7, the NOR logic circuit included in the multiple signal processing unit 200 includes first and second p-MOSFETs (P1 and P2) and first and second n-MOSFETs (N1 and N2). can do. At this time, the gate terminals of the first and second n-MOSFETs (N1, N2) and the first and second p-MOSFETs (P1, P2) may be connected to each other.

The source terminal of the first p-MOSFET (P1) may be connected to a voltage of a predetermined level, and the drain terminal of the first p-MOSFET (P1) may be connected to the source terminal of the second p-MOSFET (P2). . Additionally, the gate terminal of the first p-MOSFET (P1) may be connected to the PR sensor 110, and the gate terminal of the second p-MOSFET (P2) may be connected to the error filtering unit 300. Although the error filtering unit 300 is not shown in FIG. 7, the output of the EMP sensing unit 120 may be input to the error filtering unit 300 and then input to the NOR logic circuit. In addition, the source terminal and drain terminal of the first and second n-MOSFETs (N1, N2) are connected to each other, and the connection node of the source terminal of the first and second n-MOSFETs (N1, N2) is connected to the second p. It may be connected to the drain terminal of the -MOSFET (P2), and the connection node of the drain terminal of the first and second n-MOSFETs (N1, N2) may be connected to the ground.

Figure 8 is a circuit diagram showing a radiation-resistant multiple signal processing unit according to another embodiment of the present invention.

As shown in FIG. 8, the NOR logic circuit included in the multiple signal processing unit 200 may include only a plurality of p-MOSFETs and passive elements. Specifically, it may include first and second p-MOSFETs (P1, P2) and a first resistor (R1) connected to the second p-MOSFET (P2). Specifically, the source terminal of the first p-MOSFET (P1) is connected to a voltage of a predetermined magnitude, and the drain terminal of the first p-MOSFET (P1) is connected to the source terminal of the second p-MOSFET (P2). can be connected Additionally, the gate terminal of the first p-MOSFET (P1) may be connected to the PR sensor 110, and the gate terminal of the second p-MOSFET (P2) may be connected to the error filtering unit 300. . Like FIG. 7 , the error filtering unit 300 is not shown in FIG. 8 , but when the error filtering unit 300 is included, the output of the EMP sensing unit 120 is transmitted to the error filtering unit 300. It can be input to the NOR logic circuit, and when the error filtering unit 300 is not included, the output of the EMP sensing unit 120 is directly input to the NOR logic circuit as shown in FIGS. 7 and 8. It can be.

Meanwhile, as shown in FIGS. 7 and 8, a feedback inverter logic circuit 600 and a power cut-off time adjusting unit 400 may be further included.

The feedback inverter logic circuit 600 may be connected to the output of the multiple signal processor 200, and the output may be connected to the multiple signal processor 200.

The power-off time adjusting unit 400 may adjust the maintenance time of the power-off command signal output from the multi-signal processor 200 and provide the power-off command signal to the power control unit 500.

As shown in FIG. 7, the feedback inverter logic circuit 600 includes a feedback p-MOSFET (P4) and a feedback n-MOSFET (N4) connected between the feedback p-MOSFET (P4) and the drain terminal. It can be included.

), 커패시터(

) 및 차단시간 조절용 저항(

)을 포함할 수 있다. In addition, the power cut-off time control unit 400 is a p-MOSFET (

), capacitor (

) and resistance for controlling the blocking time (

) may include.

Accordingly, the NOR logic circuit may include first to third p-MOSFETs (P1, P2, and P3) and first to third n-MOSFETs (N1, N2, and N3). Gate terminals of the first to third n-MOSFETs may be connected to gate terminals of the first to third p-MOSFETs, respectively. Specifically, looking at the connection relationship between the components, the source terminal of the first p-MOSFET (P1) is connected to a voltage of a predetermined level, and the drain terminal of the first p-MOSFET (P1) is connected to the second p-MOSFET (P1). It is connected to the source terminal of the -MOSFET (P2), and the gate terminal of the first p-MOSFET (P1) may be connected to the PR sensor 110.

The gate terminal of the second p-MOSFET (P2) is connected to the error filtering unit 300, and the drain terminal of the second p-MOSFET (P2) is connected to the source terminal of the third p-MOSFET (P3). can be connected

The first to third n-MOSFETs (N1, N2, N3) have source terminals and drain terminals connected to each other, and the source terminal connection node of the first to third n-MOSFETs (N1, N2, N3) is connected to the first to third n-MOSFETs (N1, N2, N3). It may be connected to the drain terminal of the 3 p-MOSFETs (P3), and the drain terminal connection node of the first to 3 n-MOSFETs (N1, N2, N3) may be connected to the ground.

Additionally, the source terminal of the feedback p-MOSFET (P4) may be connected to the predetermined voltage, and the source terminal of the feedback n-MOSFET (N4) may be connected to the ground. Additionally, the gate terminal of the feedback n-MOSFET (N4) may be connected to the gate terminal of the feedback p-MOSFET (P4). At this time, the gate terminal of the third p-MOSFET (P3) is connected to the connection node of the drain terminal of the feedback p-MOSFET (P4) and the feedback n-MOSFET (N4), thereby providing feedback.

)는 상기 제 3 p-MOSFET(P3)의 드레인 단자와 상기 차단시간 조절용 저항(

)과 연결되어, 상기 차단시간 조절용 저항(

)은 상기 제 1 p-MOSFET(P1)의 소스 단자 및 상기 피드백용 p-MOSFET(P4)의 게이트 단자와 연결될 수 있다. 또한, 상기 차단시간 조절용 p-MOSFET(

)의 드레인 단자 및 소스 단자가 상기 커패시터(

)의 양단에 연결되어, 상기 차단시간 조절용 p-MOSFET(

)의 게이트 단자는 상기 피드백용 p-MOSFET(P4)과 상기 피드백용 n-MOSFET(N4)의 연결 노드에 연결될 수 있다. In addition, the capacitor (

) is the drain terminal of the third p-MOSFET (P3) and the resistance for controlling the blocking time (

) is connected to the resistance for controlling the blocking time (

) may be connected to the source terminal of the first p-MOSFET (P1) and the gate terminal of the feedback p-MOSFET (P4). In addition, the p-MOSFET for controlling the blocking time (

)'s drain terminal and source terminal are connected to the capacitor (

) is connected to both ends of the p-MOSFET (

) can be connected to a connection node of the feedback p-MOSFET (P4) and the feedback n-MOSFET (N4).

Meanwhile, as shown in FIG. 8, the feedback inverter logic circuit 600 and the power-off time control unit 400 can also replace the n-MOSFET, which is vulnerable to radiation, with a resistor, thereby ensuring radiation resistance characteristics. .

Specifically, the NOR logic circuit may include first to third p-MOSFETs (P1, P2, and P3) and a first resistor (R1). At this time, the source terminal of the first p-MOSFET (P1) is connected to a voltage of a predetermined level, and the drain terminal of the first p-MOSFET (P1) is connected to the source terminal of the second p-MOSFET (P2). You can.

Additionally, the drain terminal of the second p-MOSFET (P2) may be connected to the source terminal of the third p-MOSFET (P3).

In addition, the gate terminal of the first p-MOSFET (P1) may be connected to the PR sensor 110, and the gate terminal of the second p-MOSFET (P2) may be connected to the error filtering unit 300.

The feedback inverter logic circuit 600 may include a p-MOSFET (P4) and a second resistor (R2) for feedback. At this time, the second resistor (R2) may be connected to the drain terminal and ground of the feedback p-MOSFET (P4). Additionally, the connection node of the feedback p-MOSFET (P4) and the second resistor (R2) can be fed back by being connected to the gate terminal of the third p-MOSFET (P3).

), 커패시터(

), 및 차단시간 조절용 저항(

)을 포함할 수 있다. The power cut-off time control unit 400 is a p-MOSFET (p-MOSFET) for shut-off time control.

), capacitor (

), and resistance for adjusting the blocking time (

) may include.

)는 상기 제 3 p-MOSFET(P3)의 드레인 단자와 상기 차단시간 조절용 저항(

)에 연결되되, 상기 차단시간 조절용 저항(

)은 상기 제 1 p-MOSFET(P1)의 소스 단자 및 상기 피드백용 p-MOSFET(

)의 게이트 단자와 연결될 수 있다. 더불어, 상기 차단시간 조절용 p-MOSFET(

)의 드레인 단자 및 소스 단자가 상기 커패시터(

)의 양단에 연결되며, 상기 차단시간 조절용 p-MOSFET(

)의 게이트 단자는 상기 피드백용 p-MOSFET(P4)과 상기 제 2 저항(R2)의 연결 노드에 연결될 수 있다. More specifically, the source terminal of the feedback p-MOSFET (P4) may be connected to the voltage of the predetermined level. Additionally, the capacitor (

) is the drain terminal of the third p-MOSFET (P3) and the resistance for controlling the blocking time (

), and the resistance for controlling the blocking time (

) is the source terminal of the first p-MOSFET (P1) and the feedback p-MOSFET (

) can be connected to the gate terminal. In addition, the p-MOSFET for controlling the blocking time (

) The drain terminal and source terminal of the capacitor (

) is connected to both ends of the p-MOSFET (

) may be connected to a connection node of the feedback p-MOSFET (P4) and the second resistor (R2).

) 및 상기 차단시간조절용 저항(

)에 의해 결정되는 시정수로 상기 전원 차단 지령 신호의 유지 시간을 설정할 수 있는 것이다. Therefore, the capacitor (

) and the resistance for controlling the blocking time (

) The maintenance time of the power cut command signal can be set with a time constant determined by .

Figure 9 is a graph showing simulation results of the power-off time control unit according to another embodiment of the present invention.

)을 적용하기 전에는 노드의 전압이 기존 전압 레벨(high state)로 안정화되는 시간이 필요하기 때문에 같은 조건(동일

,

) 에서도 제어신호의 폭이 변화되는 오류가 발생할 수 있다. 그러나, 상기 차단시간 조절용 p-MOSFET(

)을 제어신호와 정상상태의 high state 전압 사이에 연결하여 일정한 폭을 갖는 제어신호를 출력한 뒤 바로 상기 차단시간 조절용 p-MOSFET이 온(on)되어 전압레벨을 맞추고 2차 Event가 발생하기 때문에 두 번째 제어신호는 첫 번째 제어신호와 동일한 폭으로 출력할 수 있다. As shown in Figure 9, when a primary event occurs and a control signal with a certain width is output and a secondary event occurs, the blocking time adjustment p-MOSFET (

), because it takes time for the voltage of the node to stabilize to the existing voltage level (high state) before applying

,

), errors in which the width of the control signal changes may also occur. However, the p-MOSFET for controlling the blocking time (

) is connected between the control signal and the high state voltage in the normal state to output a control signal with a certain width, and then the p-MOSFET for controlling the blocking time is turned on to adjust the voltage level and a secondary event occurs. The second control signal can be output with the same width as the first control signal.

)을 포함함으로써 한 번 상기 전원 차단 지령 신호를 출력하고 복구한 후, 상기 전원 차단 지령 신호의 전압을 상기 소정 크기의 전압 레벨과 동일하게 유지시킴으로써 복구 후 바로 다른 손상이 추가적으로 발생할 경우 상기 전원 차단 지령 신호의 펄스 폭 변화를 방지할 수 있어, 상기 전원 차단 지령 신호가 일정한 펄스 폭을 유지할 수 있는 것이다. In other words, the p-MOSFET for controlling the power-off time (

) by including once the power cut-off command signal is output and restored, and the voltage of the power-off command signal is maintained equal to the voltage level of the predetermined magnitude, so that if other damage additionally occurs immediately after recovery, the power cut command Changes in the pulse width of the signal can be prevented, so the power cut-off command signal can maintain a constant pulse width.

In addition, the feedback inverter logic circuit 600 can receive the output of the power-off time control unit 400 and input a signal to restore the power-off command signal after a predetermined time to the multiple signal processor 200. . Accordingly, power to the electronic device may be applied again.

In conclusion, if any of the sensing signals output from the PR sensor 110 and the EMP sensing unit 120 exceed the preset sensitivity standard, the power cut command signal can be output, and the PR sensor ( 110) and the EMP sensing unit 120 outputs the power cut-off command signal in response to the sensing signal generated first even if the sensing signals are generated simultaneously, so that the electrons are removed from the energy that arrives later when the power is turned off. It has the effect of protecting the device.

Figure 10 is a circuit diagram showing a power control unit according to an embodiment of the present invention.

As shown in FIG. 10, the power control unit 500 may include a crowbar circuit (clover circuit).

Specifically, the clover circuit may be composed of only a BJT (Bipolar Junction Transistor) and passive elements. Since the BJT is resistant to radiation, malfunction can be prevented when PR or EMP occurs.

More specifically, the configuration of the clover circuit and the connection relationship between each configuration will be described. The clover circuit may include a first control means and a second control means.

A first regulating means is provided between the power source and the electronic device.

The second control means is provided between the first control means and the ground and the node to which the electronic device is connected.

At this time, when the power cut command signal is activated, the first control means may be open and the second control means may be closed.

First, the first regulating means includes first to fifth pnp transistors, first to third npn transistors, and first to fifth resistors.

The first pnp transistor Q2 may be provided between the power source and the electronic device, and its emitter terminal and collector terminal may be connected, respectively.

The first npn transistor (Q1) may be provided between the ground and the node where the power source and the first pnp transistor (Q2) are connected.

The first resistor (R1) may be connected to the multi-signal processing unit 200 and the base terminal of the first npn transistor (Q1).

The second resistor R2 may be connected to a node where the power source and the first pnp transistor Q2 are connected and a collector terminal of the first npn transistor Q1.

The second pnp transistor (Q3) may be provided between the ground and the node where the power source and the first pnp transistor (Q2) are connected.

The second npn transistor Q4 may be connected to the second pnp transistor Q3 and its collector terminal, and may be connected to its base terminal.

The third pnp transistor (Q5) may be connected to the emitter terminal of the second pnp transistor (Q3).

The third npn transistor (Q6) may be connected to the third pnp transistor (Q5) with its collector terminal and its base terminal.

One end of the third resistor (R3) is connected to the base terminal connection node of the second pnp transistor (Q3) and the second npn transistor (Q4), and the other end is connected to the second resistor (R2) and the first npn transistor. It can be connected to the connection node between (Q1).

One end of the fourth resistor R4 may be connected to the base terminal of the first pnp transistor Q2, and the other end may be connected to a connection node of the other end of the third resistor R3.

One end of the fifth resistor R5 is connected to the connection node of the third resistor R3 and the fourth resistor R4, and the other end is connected to the third pnp transistor Q5 and the third npn transistor Q6. It can be connected to the base terminal connection node.

In addition, the first control means may include an inductor (L1) between the power supply and a node to which the power source and the second resistor (R2) are connected, and the inductor (L1), the power source, and the second resistor (R2) may include a capacitor (C1) connected to the ground between the connected nodes.

Meanwhile, the second control means includes fourth and fifth pnp transistors.

The fourth pnp transistor M1 may have an emitter terminal and a collector terminal connected between the ground and a node to which the first pnp transistor Q2 and the electronic device are connected.

The emitter terminal of the fifth pnp transistor (M2) is connected to the emitter terminal of the fourth pnp transistor (M1), and the collector terminal of the fifth pnp transistor (M2) is connected to the collector of the fourth pnp transistor (M1). Can be connected to the terminal.

At this time, the base terminal of the fourth pnp transistor (M1) may be connected to the collector terminal connection node of the second pnp transistor (Q3) and the second npn transistor (Q4), and the base terminal of the fifth pnp transistor (M2) may be connected to the collector terminal connection node of the second pnp transistor (Q3) and the second npn transistor (Q4). The base terminal may be connected to collector terminal connection nodes of the third pnp transistor (Q5) and the third npn transistor (Q6).

Looking at the operation of the above-described configurations, the clover circuit receives the power-off command signal, which is the output of the multiple signal processor 200, and when the power-off command signal, which was maintained high, falls to low due to PR or EMP. The first pnp transistor (Q2) is turned off, disconnecting the power supply line, and the fourth pnp transistor (M1) and the fifth pnp transistor (M2) are turned on, thereby supplying the remaining power to the electronic device. It can be discharged. Thereafter, when the power cut command signal returns to high again after a predetermined time, the first pnp transistor (Q1), the fourth pnp transistor (M1), and the fifth pnp transistor (M2) operate in reverse to turn the electronics back on. Can supply power to the device.

In other words, the clover circuit is provided between the power source of the electronic device to be protected and the electronic device, and can cut off the power supplied to the electronic device based on the power cut command signal. In addition, the power cut time can be maintained during the time exposed to PR and EMP, and the power can be restored afterwards.

Figure 11 is a diagram showing a nuclear PR, NEMP and non-nuclear NNEMP multiple protection device according to an embodiment of the present invention;

Figure 12 is a diagram showing the connection of nuclear PR, NEMP, and non-nuclear NNEMP multiple protection devices according to an embodiment of the present invention.

As shown in Figure 11 or Figure 12, the PR sensor 110 and the internal EMP sensor unit 122 may share a signal processing circuit that processes the sensing signal, so the protection device 1000 of the present invention can be miniaturized. In addition, the external EMP sensor unit 121 can be equipped with magnetic field sensors in the x-axis, y-axis, and z-axis to increase sensing sensitivity and range. Additionally, the external EMP sensor unit 121 may include a protective cap to protect the magnetic field sensor.

In addition, the internal EMP sensor unit 122 includes a board including the signal processing circuit, and at least one current probe may be provided at the edge of the board, thereby monitoring the current throughout the interior. It works.

In addition, the multiple signal processing unit 200, the power cut-off time control unit 400, the feedback inverter logic circuit 600, the power control unit 500, and the error filtering unit 300 are provided on one substrate. By doing so, there is an effect of being able to protect not only the nuclear PR and NEMP but also the non-nuclear NNEMP of the electronic device to be protected with a single protection device. In addition, it has the effect of reducing time and costs incurred when applying it at the design stage of an electronic device.

In addition, the nuclear PR, NEMP, and non-nuclear NNEMP multiple protection device 1000 having the above-described features may include a connection port that is connected to or disconnected from the electronic device. Specifically, the connection port may be in a USB format. Therefore, it can be provided between an electronic device and a power source of the electronic device, so it can be easily applied to protection.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to the specific embodiments described above. In other words, a person skilled in the art to which the present invention pertains can make numerous changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications can be made. Equivalents should be considered as falling within the scope of the present invention.

10: Motherboard power terminal
20:GND
30: Battery output terminal
1000: Nuclear PR, NEMP and non-nuclear NNEMP multiple protection devices
100: sensor circuit part
110: PR sensor
120: EMP sensing unit
121: External EMP sensor unit
122: Internal EMP sensor unit
200: Multiple signal processing unit
300: error filtering unit
400: Power cut-off time control unit
500: Power control unit
600: Feedback inverter logic circuit

Claims (8)

A sensor circuit unit including at least one of an EMP sensing unit including a PR sensor and an EMP sensor to output a sensing signal;
An error filtering unit that generates a final EMP detection signal based on the sensing signal;
a multi-signal processing unit that receives the outputs of the sensor circuit unit and the error filtering unit and outputs a power-off command signal for controlling power based on a preset sensitivity; and
It includes a power control unit that cuts off power supplied to the electronic device based on the power cut command signal,
The multiple signal processing unit,
Outputting the power cut-off command signal when any one of the output of the sensor circuit unit and the error filtering unit exceeds the preset sensitivity.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 1,
a feedback inverter logic circuit connected to the output of the multiple signal processing unit, the output of which is connected to the input of the multiple signal processing unit; and
It further includes a power-off time control unit that adjusts the maintenance time of the power-off command signal output from the multi-signal processor and provides it to the power control unit.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 2,
The multiple signal processing unit,
Including a NOR logic circuit that receives the output of the sensor circuit unit.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 3,
The multi-signal processing unit, the feedback inverter logic circuit, or the power-off time control unit,
A circuit composed only of multiple p-MOSFETs and passive elements
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 3,
The NOR logic circuit is,
1st and 2nd p-MOSFET; and
A first and second n-MOSFET connected to gate terminals of the first and second p-MOSFET, respectively,
The source terminal of the first p-MOSFET is connected to a predetermined voltage,
The source terminal of the first p-MOSFET is connected to a predetermined voltage, the drain terminal of the first p-MOSFET is connected to the source terminal of the second p-MOSFET,
The gate terminal of the first p-MOSFET is connected to the PR sensor, and the gate terminal of the second p-MOSFET is connected to the error filtering unit,
The first and second n-MOSFETs are connected to each other through source terminals and drain terminals, the connection node of the source terminal of the first and second n-MOSFETs is connected to the drain terminal of the second p-MOSFET, and the first And the connection node of the drain terminal of the 2 n-MOSFET is connected to the ground.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 4,
The NOR logic circuit is,
1st and 2nd p-MOSFET; and
Includes a first resistor connected to the second p-MOSFET,
The source terminal of the first p-MOSFET is connected to a predetermined voltage,
The drain terminal of the first p-MOSFET is connected to the source terminal of the second p-MOSFET,
The gate terminal of the first p-MOSFET is connected to the PR sensor, and the gate terminal of the second p-MOSFET is connected to the error filtering unit.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 3,
The NOR logic circuit is,
1st to 3rd p-MOSFET; and
Including the first to third n-MOSFETs whose gate terminals are connected to the first to third p-MOSFETs, respectively,
The source terminal of the first p-MOSFET is connected to a predetermined voltage, the drain terminal of the first p-MOSFET is connected to the source terminal of the second p-MOSFET, and the gate terminal of the first p-MOSFET is connected to the voltage. Connected to PR sensor,
The gate terminal of the second p-MOSFET is connected to the error filtering unit, the drain terminal of the second p-MOSFET is connected to the source terminal of the third p-MOSFET,
The first to third n-MOSFETs have their source terminals and drain terminals connected to each other, the connection node of the source terminal of the first to third n-MOSFETs is connected to the drain terminal of the third p-MOSFET, and the first The connection node of the drain terminal of the to 3 n-MOSFET is connected to the ground,
The feedback inverter logic circuit is,
p-MOSFET for feedback; and
It includes a feedback n-MOSFET connected between the feedback p-MOSFET and the drain terminal,
The power-off time control unit,
p-MOSFET for blocking time adjustment;
capacitor; and
Includes a resistor for controlling the blocking time,
The source terminal of the feedback p-MOSFET is connected to the predetermined voltage, the source terminal of the feedback n-MOSFET is connected to the ground, and the gate terminal of the feedback n-MOSFET is connected to the gate terminal of the feedback p-MOSFET. Connected,
The gate terminal of the third p-MOSFET is connected to the connection node of the drain terminal of the feedback p-MOSFET and the feedback n-MOSFET,
The capacitor is,
Connected to the drain terminal of the third p-MOSFET and the resistor for controlling the blocking time,
The resistor for controlling the blocking time is connected to the source terminal of the first p-MOSFET and the gate terminal of the feedback p-MOSFET,
The drain terminal and source terminal of the p-MOSFET for controlling the blocking time are connected to both ends of the capacitor,
The gate terminal of the blocking time adjustment p-MOSFET is connected to the connection node of the feedback p-MOSFET and the feedback n-MOSFET.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.
According to paragraph 4,
The NOR logic circuit is,
1st to 3rd p-MOSFET; and
A first resistor connected to the third p-MOSFET,
The source terminal of the first p-MOSFET is connected to a predetermined voltage,
The drain terminal of the first p-MOSFET is connected to the source terminal of the second p-MOSFET,
The drain terminal of the second p-MOSFET is connected to the source terminal of the third p-MOSFET,
The gate terminal of the first p-MOSFET is connected to the PR sensor, and the gate terminal of the second p-MOSFET is connected to the error filtering unit,
The feedback inverter logic circuit is,
p-MOSFET for feedback; and
A second resistor connected to the drain terminal of the feedback p-MOSFET,
The connection node of the feedback p-MOSFET and the second resistor is connected to the gate terminal of the third p-MOSFET,
The power-off time control unit,
p-MOSFET for blocking time adjustment;
capacitor; and
Includes a resistor for controlling the blocking time,
The source terminal of the feedback p-MOSFET is connected to the predetermined voltage, and the second resistor is connected to ground,
The capacitor is,
Connected to the drain terminal of the third p-MOSFET and the resistor for controlling the blocking time,
The resistor for adjusting the blocking time is connected to the source terminal of the first p-MOSFET and the gate terminal of the feedback p-MOSFET,
The drain terminal and source terminal of the p-MOSFET for controlling the blocking time are connected to both ends of the capacitor,
The gate terminal of the blocking time adjustment p-MOSFET is connected to the connection node of the feedback p-MOSFET and the second resistor.
PR, NEMP and non-nuclear NNEMP multiple protection devices featuring.

Images