KR101997476B1 - Radiation tolerant nuclear event detector - Google Patents

Abstract

The present invention relates to a radiation-resistant nuclear explosion detector, and a radiation-resistant nuclear explosion detector according to an embodiment of the present invention includes: a sensor circuit unit for outputting a photocurrent generated according to the incidence of pulse radiation as a voltage signal; A latch circuit for holding a detection signal for a predetermined time through a latch circuit using a plurality of PMOS elements as the voltage signal is transmitted and returning the detection signal to an initial state; And a buffer circuit unit for outputting the detection signal as an inverted signal.

Description

[0001] RADIATION TOLERANT NUCLEAR EVENT DETECTOR [0002]

The present invention relates to a radiation vulnerable nuclear explosion detector, and more particularly, to a radiation detector using a PMOS device and a CMOS inverter buffer circuit based on a DGA n-MOSFET layout, to protect against a direct gamma ray , And a nuclear explosion detector that is robust to radiation.

Silicon-based semiconductor devices, when exposed to pulsed radiation, split electrons in the atom due to strong energy and generate a large number of electron / hole pairs in the depletion region of the PN junction, An undesirable transient current flows internally due to the applied potential difference.

This transient current causes an upset phenomenon that changes the voltage stored in the circuit or a latch-up phenomenon that completely destroys the device.

In order to prevent this phenomenon, it is necessary to shut off the power supply before the upset or latch-up phenomenon occurs. For this purpose, a 'Nuclear Event Detector (NED)' is required.

In other words, a nuclear explosion detector detects pulse radiation occurring at the beginning of a nuclear explosion and outputs an output signal at a high speed, thereby shutting off power of other electronic components in the system, and restoring it after a predetermined time.

A conventional nuclear explosion detector converts an electric current generated in a sensor unit by a pulse radiation into a voltage, amplifies the signal through an amplification unit, and then generates an output signal through a pulse timer capable of adjusting a pulse width.

Such a conventional nuclear explosion detector is composed of a sensor unit, an amplifier unit, a timer unit, and an output unit, and operates at a 5 V power supply voltage. When pulse radiation is applied to the detection sensor of the sensor part, a photocurrent is generated. The generated photocurrent is converted into a voltage. When the converted voltage is equal to or higher than the reference voltage, a detection signal is output. The timer unit initializes the detection signal with the generated signal.

Conventional nuclear explosion detectors are vulnerable to transient radiation effects and total ionizing dose effects when they are fabricated as integrated circuits with a positive feedback structure for fast response speeds, It may occur that the mobile terminal becomes disabled.

As such, the nuclear explosion detector must be in a state of power supply unlike the protection circuits even in the case of nuclear explosion. Therefore, if the circuit malfunctions or becomes inoperable due to radiation, it can not be stably protected.

Therefore, when a nuclear explosion detector is fabricated as an integrated circuit with a positive feedback structure for a fast response speed, it is required to have a strong characteristic for the effect of transient radiation and cumulative radiation.

U.S. Patent No. 4,687,622 (registered on Aug. 18, 1987) U.S. Patent No. 5,672,918 (registered on September 30, 1997)

 'Development and Verification of Nuclear Bomb Detector for Transient Radiation Detection', Sung Hoon Hoon, The Institute of Electrical Engineers, 26 (5) 639-642, 2013

It is an object of the present invention to provide a radiation-resistant nuclear explosion detector for protecting against instantaneous gamma rays occurring at the beginning of a nuclear explosion by designing a latch circuit using a PMOS device and a CMOS inverter buffer circuit based on a DGA n-MOSFET layout.

A radiation-resistant nuclear explosion detector according to an embodiment of the present invention includes a sensor circuit unit for outputting a photocurrent generated according to the incidence of pulse radiation as a voltage signal; A latch circuit for holding a detection signal for a predetermined time through a latch circuit using a plurality of PMOS elements as the voltage signal is transmitted and returning the detection signal to an initial state; And a buffer circuit unit for outputting the detection signal as an inverted signal, wherein the PMOS devices include a first PMOS, a second PMOS, a third PMOS, and a fourth PMOS to generate a cascade- To form a multi-stage amplifier.

The sensor circuit portion may include a capacitor and a resistor for adjusting a threshold voltage level.

The sensor circuit unit may include a photodiode that generates a photocurrent according to the incident pulse radiation.

The sensor circuit unit may convert the photocurrent into a voltage through a resistor and output a voltage signal through a differential circuit composed of a capacitor and a resistor.

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Wherein the gate of the first PMOS is applied with the voltage signal, the drain of the first PMOS and the gate of the second PMOS are connected to each other, and the drain of the second PMOS and the gate of the fourth PMOS are connected to a timing capacitor A drain of the fourth PMOS may be connected to a gate of the third PMOS and a drain of the third PMOS may be connected to a drain of the second PMOS and an upper electrode of the timing capacitor.

The lower electrode side of the timing capacitor and the gate of the fourth PMOS may be connected to the ground through a resistor.

The buffer circuit part forms a CMOS inverter by connecting the fifth PMOS and the first NMOS in a cascode structure, and the drain voltage of the third PMOS can be input to the gates of the fifth PMOS and the first NMOS .

The first NMOS may be a dummy gate-assisted (DGA) n-MOSFET layout.

The size of the first NMOS may be designed to be larger than the size of the fifth PMOS.

By designing a latch circuit using a PMOS device and a CMOS inverter buffer circuit based on a DGA n-MOSFET layout, the present invention can protect against a direct gamma ray occurring at the beginning of a nuclear explosion.

In addition, the present invention can prevent malfunction due to transient radiation and deterioration due to cumulative radiation effects caused by integrating a nuclear explosion detector that protects core weapons systems from the immediate gamma ray from the initial nuclear explosion.

In addition, the present invention can contribute to miniaturization and low power consumption of a military weapon system by applying a CMOS inverter buffer circuit in which a PMOS device, a resistor circuit composed of a resistor and a DGA n-MOSFET layout are applied.

Figures 1 and 2 are circuit diagrams of a radiation resistant nuclear explosion detector according to an embodiment of the present invention;
3 is a view showing a result of a TCAD simulation on the transient radiation effects of the PMOS device and the NMOS device,
4 is a waveform diagram of input / output signals of a nuclear explosion detector according to an embodiment of the present invention,
5 is an enlarged view of a falling edge response characteristic of the output signal of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the accompanying drawings, detailed description of well-known functions or constructions that may obscure the subject matter of the present invention will be omitted. It should be noted that the same constituent elements are denoted by the same reference numerals as possible throughout the drawings.

The terms and words used in the present specification and claims should not be construed in an ordinary or dictionary sense, and the inventor shall properly define the terms of his invention in the best way possible It should be construed as meaning and concept consistent with the technical idea of the present invention.

Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention, and not all of the technical ideas of the present invention are described. Therefore, It is to be understood that equivalents and modifications are possible.

In the accompanying drawings, some of the elements are exaggerated, omitted or schematically shown, and the size of each element does not entirely reflect the actual size. The invention is not limited by the relative size or spacing depicted in the accompanying drawings.

When an element is referred to as "including" an element throughout the specification, it is to be understood that the element may include other elements as well, without departing from the spirit or scope of the present invention. Also, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between.

The singular expressions include plural expressions unless the context clearly dictates otherwise. It will be understood that terms such as "comprise" or "comprise ", when used in this specification, specify the presence of stated features, integers, , But do not preclude the presence or addition of one or more other features, elements, components, components, or combinations thereof.

Also, as used herein, the term "part " refers to a hardware component such as software, FPGA or ASIC, and" part " However, "part" is not meant to be limited to software or hardware. "Part" may be configured to reside on an addressable storage medium and may be configured to play back one or more processors. Thus, by way of example, and not limitation, "part (s) " refers to components such as software components, object oriented software components, class components and task components, and processes, Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays and variables. The functions provided in the components and "parts " may be combined into a smaller number of components and" parts " or further separated into additional components and "parts ".

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 and 2 are circuit diagrams of a radiation resistant nuclear explosion detector in accordance with an embodiment of the present invention.

FIGS. 1 and 2 illustrate a radiation-resistant nuclear explosion detector (hereinafter referred to as a "nuclear explosion detector") according to an embodiment of the present invention protects a core military weapon system from a prompt gamma-ray at the beginning of a nuclear explosion As a device, a latch circuit composed of a PMOS (p-MOSFET) element and a resistor is applied to prevent a malfunction due to the transient radiation effect caused by the design of an integrated circuit, A CMOS inverter buffer circuit based on a DGA NMOS (n-MOSFET) layout (dummy gate-assisted n-MOSFET layout) is applied.

To this end, the nuclear explosion detector includes a sensor circuit unit 110, a latch circuit unit 120, and a buffer circuit unit 130.

The sensor circuit unit 110 transmits the voltage signal LATCH_TRIG obtained by converting the photocurrent to the voltage according to the incident pulse radiation (immediate gamma ray) to the latch circuit unit 120.

The sensor circuit unit 110 includes a photodiode D1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, A second capacitor C2, and a third capacitor C3, and a bias voltage VB is applied.

When the pulse radiation is incident on the photodiode D1, the sensor circuit unit 110 generates a photocurrent, converts the generated photocurrent into a voltage through a resistor, passes through a differential circuit composed of a capacitor and a resistor, Signal (LATCH_TRIG).

First, the photodiode D1 is a PIN diode. The cathode of the photodiode D1 is connected to the bias voltage VB through a first resistor R1 and to ground (ground) through a first capacitor C1 which is a filter. Here, a reverse bias is applied to the photodiode D1. The anode of the photodiode D1 is connected to ground through a voltage divider in which the second and third resistors R2 and R3 are configured in series combination. Here, the photocurrent generated when the pulse radiation is applied is converted into a voltage by using the second and third resistors R2 and R3 in the photodiode D1.

The first capacitor C1 functions as a bypass capacitor for removing noise.

The common connection of the second and third resistors R2 and R3 connected in series includes an electric component for adjusting the threshold voltage level of the sensor circuit portion 110 and includes a threshold voltage capacitor CTH and a threshold voltage resistance RTH) are connected in parallel.

That is, the sensor circuit unit 110 can adjust the threshold voltage level according to the threshold voltage capacitor CTH and the threshold voltage resistance RTH. For example, if the threshold voltage capacitor CTH is made smaller, the sensitivity of the sensor circuit 110 can be increased. If the threshold voltage resistance RTH is made smaller, the sensitivity of the input signal TH_ADJ can be increased. The threshold dose rate can be reduced.

The threshold voltage capacitor CTH and the threshold voltage resistor RTH are connected at one end to the common connection of the second and third resistors R2 and R3 and at the other end to the ground.

The third resistor R3 is shunted by the threshold voltage capacitor CTH, the threshold voltage resistor RTH, and the third capacitor C3. That is, the voltage signal of the sensor circuit unit 110 is coupled to the latch circuit unit 120 through the second capacitor C2, which is a coupling capacitor. As described above, the voltage signal of the sensor circuit unit 110 transfers only the AC signal to the latch circuit unit 120.

The third resistor R3 and the third capacitor C3 determine a predetermined threshold voltage level and the third resistor R3 can be trimmed to the desired threshold voltage level. That is, even if the same photocurrent is generated by the sensor circuit unit 110 by the pulse radiation, the AC signal transmitted to the latch circuit unit 120 can be reduced by using the threshold voltage capacitor CTH and the threshold voltage resistance RTH . Thus, the threshold voltage resistor RTH and the threshold voltage capacitor RTH are used to adjust the detectable voltage level.

When the voltage signal LATCH_TRIG is transmitted from the sensor circuit unit 110, the latch circuit unit 120 is triggered at a high speed to maintain the detection signal NED_B as an inverted signal for a predetermined time, and then returns to the initial state.

Here, since the latch circuit section 120 is designed by using the PMOS element and the resistor, it is possible to prevent a malfunction phenomenon of the pulse type radiation.

As can be seen from the TCAD simulation of FIG. 3, the PMOS device is more resistant to transient radiation than the NMOS device. 3 is a view showing a result of a TCAD simulation on the effect of transient radiation of a PMOS device and an NMOS device.

Therefore, the latch circuit unit 120 is robust against transient radiation because it constitutes a circuit using only PMOS devices without NMOS devices.

The latch circuit unit 120 includes a first resistor R5 and a sixth resistor R5 which are connected in series to the first PMOS PM1, the second PMOS PM2, the third PMOS PM3, the fourth PMOS PM4, the timer capacitor CT, (R6), a seventh resistor (R7) and an eighth resistor (R8), and a voltage (VH) for the hybrid microcircuit is applied.

The first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 form a cascade PMOS common source multi-stage amplifier structure.

The first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 are connected in common to the source voltage VH.

First, the gate of the first PMOS PM1 is applied with the voltage signal LATCH_TRIG transferred from the sensor circuit portion 110, and the drain thereof is connected to the ground through the fifth resistor R5. Accordingly, the drain voltage Va of the first PMOS PM1 appears at a point (point A) between the drain of the first PMOS PM1 and the fifth resistor R5.

Next, the gate of the second PMOS PM2 is connected between the drain of the first PMOS PM1 and the fifth resistor R5, the drain is connected to the ground via the sixth resistor R6, The drain of the PMOS transistor PM3, and the first electrode of the timer capacitor CT are also connected. Accordingly, the drain voltage Vb of the second PMOS PM2 or the third PMOS PM3 appears at a point (point B, point B ') between the drain of the second PMOS PM2 and the sixth resistor R6 .

Next, the gate of the fourth PMOS PM4 is connected to the second electrode side of the timer capacitor CT. That is, the drain of the second PMOS PM2 and the gate of the fourth PMOS PM4 are coupled through the timer capacitor CT. The gate of the fourth PMOS PM4 and the second electrode side of the timer capacitor CT are connected to the ground through a seventh resistor R7.

The gate of the fourth PMOS PM4 and the contact point C of the one end of the seventh resistor R7 of the timer capacitor CT are connected to the gate voltage Vc of the fourth PMOS PM4, .

Further, the drain of the fourth PMOS PM4 is connected to the ground through the eighth resistor R8, and the gate of the third PMOS PM3 is also connected. Thus, the drain voltage Vd of the fourth PMOS PM4 appears at a point (point D) between the drain of the fourth PMOS PM4 and the eighth resistor R8.

Hereinafter, the operation of the latch circuit unit 120 will be described.

First, the first PMOS PM1 is turned off for a moment by the voltage signal LATCH_TRIG transmitted from the sensor circuit 110 and the voltage Va at the point A, which is the drain voltage of the first PMOS PM1, Lt; / RTI > becomes logically low.

The second PMOS PM2 is turned on for a moment because the gate thereof is connected to the drain of the first PMOS PM1 and the voltage Vb at the point B which is the drain voltage is logically high, State. At this time, since the both sides of the timer capacitor CT are also in the high state, the voltage Vc at the point C, which is the gate voltage of the fourth PMOS PM4, becomes logically high.

Next, since the gate of the fourth PMOS PM4 is connected to the second electrode side of the timer capacitor CT, the PMOS PM4 is turned off for a moment, and the voltage Vd at the point D which is the drain voltage is logically low low state.

Next, since the third PMOS PM3 has its gate connected to the drain of the fourth PMOS PM4 for an instant, and the drain thereof is connected to the first electrode side of the timer capacitor CT And again charges the timer capacitor CT to a high state.

The drain of the fourth PMOS PM4 is connected to the gate of the third PMOS PM3 and the drain of the third PMOS PM3 is connected to the gate of the fourth PMOS PM4 through the timer capacitor CT Accordingly, the fourth PMOS PM4 and the third PMOS PM3 form a positive feedback (PF) loop.

The buffer circuit unit 130 receives the output signal of the latch circuit unit 120 and outputs a detection signal NED_B. At this time, the buffer circuit unit 130 receives the voltage Vb 'at the point B' in the latch circuit unit 120. Here, the voltage Vb 'at the point B' in the latch circuit portion 120 is equal to the voltage Vb at the point B.

The buffer circuit unit 130 is a CMOS inverter structure in which the fifth PMOS PM5 and the first NMOS NM1 are connected in a cascode structure.

The output signals of the latch circuit portion 120 are commonly applied to the gates of the fifth PMOS PM5 and the first NMOS NM1. The source of the fifth PMOS PM5 is connected to VH like the first to fourth PMOSs PM1 to PM4 and the drain thereof is connected to the drain of the first NMOS NM1. At this time, the source of the first NMOS NM1 is connected to the ground.

The first NMOS NM1 applies a DGA n-MOSFET layout for robust design from cumulative radiation effects.

Meanwhile, the buffer circuit unit 130 is designed such that the size of the first NMOS NM1 is larger than the size of the fifth PMOS PM5 for high-speed pulldown.

As described above, when the first electrode side voltage of the timer capacitor CT, that is, the voltages Vb and Vb 'at the point B or B' is input, the buffer circuit unit 130 detects the occurrence of a nuclear explosion event And outputs an inverted signal of the signal NED_B.

When the latch circuit part 120 is triggered by applying the voltage signal LATCH_TRIG from the sensor circuit part 110 to the timer capacitor CT, the stored charge does not flow through the seventh resistor R7 do.

At this time, when the latch circuit 120 is activated, the detection signal NED_B starts to decrease as the fourth PMOS PM4 is turned off for a moment. Then, the detection signal NED_B returns to the initial voltage state at the time when the fourth PMOS PM4 is turned on.

As described above, the time taken for the latch circuit unit 120 to be triggered and returned to the initial voltage state is determined by the discharge time of the timer capacitor CT. Here, since the discharge time of the timer capacitor CT is determined by the seventh resistor R7 and the time constant of the timer capacitor CT, these values are changed to control the pulse width of the detection signal NED_B can do.

Thus, the nuclear explosion detector according to an embodiment of the present invention can protect the military weapon system from the gamma ray by providing the pulse detection signal NED_B as a flag signal.

FIG. 4 is a waveform diagram of an input / output signal of a nuclear explosion detector according to an embodiment of the present invention. FIG. 5 is an enlarged view of a falling edge response characteristic of the output signal of FIG.

4 shows a detection signal NED_B as a pulse-shaped output signal by detecting an input signal TH_ADJ when a nuclear explosion detector enters an initial gamma ray coming from an early stage of a nuclear explosion.

The nuclear explosion detector outputs the detection signal NED_B at a high speed to the input signal TH_ADJ according to the incidence of the pulse type immediate gamma ray to cut off the power of other electronic parts and restore the same again after a predetermined time.

The detection signal NED_B represents a response characteristic in which the voltage falls to the inverted signal with respect to the input signal TH_ADJ, and is maintained at a pulse width for a predetermined time, and then restored to its original state. When the falling edge 201 of the detection signal NED_B is enlarged, the detection signal NED_B responds to the input signal TH_ADJ with a predetermined reaction time at which the voltage falls to the inverted signal.

Referring to FIGS. 4 and 5, the detection signal NED_B rises while the voltage falls to an inversion signal during a pulse width of 2.58 ms (timer capacitor CT = 1 rd), and the reaction time for the voltage to fall by the inversion signal is 23 ㎱ (parasitic capacitor CP = 15 ㎊).

Although the foregoing is directed to novel features of the present invention that are applicable to various embodiments, those skilled in the art will appreciate that the apparatus and method described above, without departing from the scope of the present invention, It will be understood that various deletions, substitutions, and alterations can be made in form and detail without departing from the spirit and scope of the invention. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description. All variations within the scope of the appended claims are embraced within the scope of the present invention.

110: sensor circuit part 120: latch circuit part
130: buffer circuit part D1: photodiode
C1 to C3: first to third capacitors R1 to R8: first to eighth resistors
RTH: Threshold Voltage Resistance CTH: Threshold Voltage Capacitor
PM1 to PM5: first PMOS to fifth PMOS NM1: first NMOS
CT: Timer capacitor TH_ADJ: Input signal
LATCH_TRIG: voltage signal NED_B: detection signal

Claims (10)

A sensor circuit part for outputting a photocurrent generated according to the incidence of pulse radiation as a voltage signal;
A latch circuit for holding a detection signal for a predetermined time through a latch circuit using a plurality of PMOS elements as the voltage signal is transmitted and returning the detection signal to an initial state; And
And a buffer circuit unit for outputting the detection signal as an inverted signal,
Wherein the PMOS devices comprise a first PMOS, a second PMOS, a third PMOS, and a fourth PMOS to form a cascade-structured PMOS common-source multi-stage amplifier.
The method according to claim 1,
The sensor circuit unit includes:
A radiation resistant nuclear explosion detector comprising a capacitor and a resistor for adjusting a threshold voltage level.
The method according to claim 1,
The sensor circuit unit includes:
And a photodiode for generating a photocurrent in response to the pulse radiation incident.
The method according to claim 1,
The sensor circuit unit includes:
A radiation resistant nuclear explosion detector that converts the photocurrent into a voltage through a resistor and outputs a voltage signal via a differential circuit comprised of a capacitor and a resistor.
delete The method according to claim 1,
The gate of the first PMOS is supplied with the voltage signal,
The drain of the first PMOS and the gate of the second PMOS are connected to each other,
A drain of the second PMOS and a gate of the fourth PMOS are coupled through a timing capacitor,
The drain of the fourth PMOS is connected to the gates of the third PMOS,
And a drain of the third PMOS is resistant to radiation coupled to a drain of the second PMOS and an upper electrode side of the timing capacitor.
The method according to claim 6,
Between the lower electrode side of the timing capacitor and the gate of the fourth PMOS,
Radiation-resistant nuclear explosion detector connected to ground through a resistor.
The method according to claim 6,
Wherein the buffer circuit section comprises:
The fifth PMOS and the first NMOS are connected in a cascode structure to form a CMOS inverter,
Wherein the gate of the fifth PMOS and the gate of the first NMOS are connected,
Wherein the drain voltage of the third PMOS is robust against the input radiation.
9. The method of claim 8,
The first NMOS includes:
A radiation-robust nuclear explosion detector that applies a Dummy Gate-Assisted (DGA) n-MOSFET layout.
9. The method of claim 8,
Wherein the size of the first NMOS is designed to be larger than the size of the fifth PMOS.

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