KR20240030242A - Display apparatus and operating method thereof - Google Patents

Abstract

A display device according to an embodiment of the present specification includes a display panel on which a pixel circuit including a light-emitting element and at least one transistor is disposed; A gate driver that generates a light emitting signal and provides it to the display panel; a data driver that generates data voltage and provides it to the display panel; and confirming the light emission duty cycle value and data voltage value corresponding to a predetermined dimming level value using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections, and obtaining the light emission duty cycle value. It includes a timing controller that provides information about the data voltage value to the gate driver and provides information about the data voltage value to the data driver, wherein the gate driver generates a light emission signal based on the light emission duty cycle value received from the timing controller, and the data voltage value is provided to the data driver. The driver may generate a data voltage based on the data voltage value received from the timing controller.

Description

Display device and operating method thereof {DISPLAY APPARATUS AND OPERATING METHOD THEREOF}

This specification relates to a display device and a method of operating the display device.

As the information society develops, various demands for display devices that display images are increasing, and various types of display devices such as liquid crystal displays, plasma displays, and organic light emitting displays are being utilized. Among these display devices, organic light emitting display devices including organic light emitting diodes (OLED) are widely used due to their advantages of fast response speed, luminous efficiency, luminance, and viewing angle.

An organic light emitting display device may include a display panel in which gate lines, data lines, and sub-pixels are arranged. An organic light emitting display device can control light emission of a sub-pixel based on applying a specific signal (or specific voltage) to a gate line and a data line.

Since the luminous efficiency and voltage charging time required for luminescence of sub-pixels may vary depending on the corresponding color, when controlling luminance to a specific value, the color coordinates are optimized to control the signal applied to the display panel to ensure effective luminescence. Needs to be.

The problem to be solved by the embodiments of the present specification is to provide a display device and a method of operating the same that control signals applied to the display panel so that light emission with optimized color coordinates is achieved.

However, the tasks of this specification are not limited to those mentioned above, and other technical tasks can be inferred from the following embodiments.

A display device according to an embodiment of the present specification includes a display panel on which a pixel circuit including a light-emitting element and at least one transistor is disposed; a gate driver that generates a light emitting signal and provides it to the display panel; a data driver that generates a data voltage and provides it to the display panel; and confirming the light emission duty cycle value and data voltage value corresponding to a predetermined dimming level value using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections, and obtaining the light emission duty cycle value. It includes a timing controller that provides information about the data voltage value to the gate driver and provides information about the data voltage value to the data driver, where the gate driver generates a light emitting signal based on the light emitting duty cycle value received from the timing controller, and the data driver Can generate a data voltage based on the data voltage value received from the timing controller.

A display device according to an embodiment of the present specification includes a display panel on which a pixel circuit including a light-emitting element and at least one transistor is disposed; and confirming the emission duty cycle value and data voltage value corresponding to a predetermined dimming level value using optical compensation data in which the emission duty cycle changes in at least one section among at least four dimming level sections, and based on the emission duty cycle value. It may include a control unit that generates a light emitting signal and generates a data voltage based on the data voltage value, and provides the light emitting signal and the data voltage to the display panel.

A method of operating a display device according to an embodiment of the present specification includes checking whether a preset condition is satisfied; Confirming a dimming level value corresponding to a preset condition; Confirming the light emission duty cycle value and data voltage value corresponding to the confirmed dimming level value using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections; generating a light emitting signal based on the confirmed light emission duty cycle and generating a data voltage based on the confirmed data voltage value; and driving the pixel circuit using the generated light emission signal and the generated data voltage.

Specific details of other embodiments are included in the detailed description and drawings.

The display device and operating method according to the present specification can optimize color coordinates when emitting light by controlling signals applied to the display panel.

Since the contents of the problem to be solved, the means for solving the problem, and the effects mentioned above do not specify the essential features of the claims, the scope of the claims is not limited by the matters described in the contents of the invention.

1 is a block diagram of a display device according to an embodiment of the present specification.
FIG. 2 is a diagram for explaining a pixel circuit of a display device according to an embodiment of the present specification.
Figure 3 shows an example of a pixel circuit of a display device according to an embodiment of the present specification.
FIG. 4 is a cross-sectional view of at least a portion of a display device according to an embodiment of the present specification.
Figure 5 is an example of optical compensation data used in a display device according to an embodiment of the present specification.
Figure 6 is another example of optical compensation data used in a display device according to an embodiment of the present specification.
FIG. 7 is a diagram illustrating the step-by-step flow of a method of operating a display device according to an embodiment of the present specification.
FIG. 8 is a diagram illustrating the step-by-step flow of a method of operating a timing controller included in a display device according to an embodiment of the present specification.
FIG. 9 is a diagram for explaining signals in the first section and the second section among the dimming level sections of the display device according to an embodiment of the present specification.
FIG. 10 is a diagram for explaining a signal in a third section among the dimming level sections of a display device according to an embodiment of the present specification.
FIG. 11 is a diagram for explaining a signal in a fourth section among the dimming level sections of a display device according to an embodiment of the present specification.
Figure 12 shows the results of an experiment on the amount of color coordinate variation of a display device according to an embodiment of the present specification.

The terms used in the embodiments are general terms that are currently widely used as much as possible while considering the functions in the present disclosure, but this may vary depending on the intention or precedent of a person working in the art, the emergence of new technology, etc. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the relevant description. Therefore, the terms used in this disclosure should be defined based on the meaning of the term and the overall content of this disclosure, rather than simply the name of the term.

When it is said that a part "includes" a certain element throughout the specification, this means that, unless specifically stated to the contrary, it does not exclude other elements but may further include other elements.

The expression “at least one of a, b, and c” used throughout the specification means ‘a alone’, ‘b alone’, ‘c alone’, ‘a and b’, ‘a and c’, ‘b and c ', or 'all of a, b, and c'. The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments in this specification are illustrative, and the embodiments in this specification are not limited to the matters shown. Additionally, in describing the embodiments, if it is determined that detailed descriptions of related known technologies may unnecessarily obscure the gist of the embodiments, the detailed descriptions will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added. When a component is expressed in the singular, the plural is included unless specifically stated otherwise. In addition, when interpreting components, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, when the positional relationship between two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., between the two parts One or more other parts may be located in . When an element or layer is referred to as “on” another element or layer, it includes instances where the other layer or other element is directly on top of or interposed between the other element and the other element.

Additionally, terms such as first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The area, length, or thickness of each component described in the specification is shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the depicted component.

The features of each of the various embodiments of the present specification can be partially or entirely combined or combined with each other, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. You may.

And the terms described later are defined in consideration of their function in the implementation of this specification, which may vary depending on the intention or custom of the user or operator. Therefore, the definition should be made based on the overall contents of this specification.

The transistor constituting the pixel circuit of the present specification includes at least one of oxide TFT (Oxide Thin Film Transistor; Oxide TFT), amorphous silicon TFT (a-Si TFT), and low temperature poly silicon (LTPS) TFT. can do.

The following embodiments will be described focusing on the organic light emitting display device. However, embodiments of the present invention are not limited to organic light emitting display devices and may be applied to inorganic light emitting display devices including inorganic light emitting materials. For example, embodiments of the present invention can also be applied to quantum dot display devices.

Expressions such as 'first', 'second', and 'third' are terms used to distinguish configurations for each embodiment, and the embodiments are not limited to these terms. Therefore, it should be noted that the same term may refer to different configurations depending on the embodiment.

Hereinafter, embodiments of the present specification will be described with reference to the drawings.

1 is a block diagram of a display device according to an embodiment of the present specification.

The display device 1 according to an embodiment of the present specification may be an electroluminescent display. The electroluminescent display device may include an Organic Light Emitting Diode (OLED) display device, a Quantum-dot Light Emitting Diode display device, or an Inorganic Light Emitting Diode display device. there is.

The display device 1 according to an embodiment includes a display panel 10 on which sub-pixels (PXL) for internal compensation are formed, and a data driver (or data driving circuit) that drives the data lines 14. data driving circuit) (12), a gate driver (or gate driving circuit) (13) that drives the gate lines (15), and a data driver (12) and gate driver (13) A timing controller (T-con) 11 that controls the driving timing of may be provided. For example, the gate driver 13 may be a first driving circuit, but the term is not limited. For example, the data driver 12 may be a second driving circuit, but the term is not limited thereto.

Depending on the embodiment, the display device 1 may include a display panel 10 and a control unit 20. The control unit 20 can control the display panel 10. The control unit 20 may include a timing controller 11, a data driver 12, and a gate driver 13. In this case, the operations of the timing controller 11, data driver 12, and/or gate driver 13, which will be described later, may be performed by the control unit 20.

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 intersect, and the intersection area of the data lines 14 and/or the gate lines 15 is used for internal compensation. Sub-pixels (PXL) are arranged. The sub-pixel PXL may be arranged in a matrix form as shown, but is not limited thereto. Sub-pixels (PXL) arranged in the same pixel row are connected to a plurality of gate lines 15, and the plurality of gate lines 15 may include at least one scan line and at least one emission control line.

For example, each sub-pixel (PXL) may be connected to one data line 14, at least one scan line, and one or more emission control lines. The sub-pixels (PXL) may commonly receive a high-potential voltage (Vdd), a low-potential voltage (Vss), and a reference voltage (Vref) from the power generator. To prevent unnecessary light emission of OLED (organic light emitting diode) in the initialization section and sampling section, the reference voltage (Vref) may be within a voltage range sufficiently lower than the operating voltage of the OLED, and may be equal to or lower than the low-potential voltage (Vss). It can be set lower than the voltage (Vss). For example, the low potential voltage (Vss) may include ground voltage (or 0V). For example, the high potential voltage (Vdd) may be the first voltage, but the term is not limited. For example, the low potential voltage (Vss) may be a second voltage, but the term is not limited. The sub-pixels (PXL) may further commonly receive an initialization voltage (Vini) and a reset voltage (VAR) from the power generator.

Thin film transistors (TFTs) constituting the sub-pixel (PXL) may be implemented as oxide transistors (or oxide TFTs) including an oxide semiconductor layer. Oxide TFT may be advantageous for increasing the area of the display panel 10 when considering both electron mobility and process deviation. However, the embodiments of the present specification are not limited to this, and the semiconductor layer of the TFT may be formed of amorphous silicon or polysilicon.

Each sub-pixel (PXL) may include a plurality of TFTs and a storage capacitor to compensate for a deviation in the threshold voltage (Vth) of the driving TFT. The specific configuration of each sub-pixel (PXL) will be described later.

In FIG. 1, the basic pixel may be composed of at least three sub-pixels among white (W), red (R), green (G), and blue (B) sub-pixels. For example, the basic pixels include sub-pixels of a combination of red (R), green (G), and blue (B), sub-pixels of a combination of white (W), red (R), and green (G), and blue (B). ), white (W), red (R) combination of sub-pixels, green (G), blue (B), white (W) combination, or white (W), red (R), It may be composed of sub-pixels of a combination of green (G) and blue (B), and the embodiments of the present specification are not limited thereto.

The timing controller 11 rearranges digital video data (RGB) input from the outside to match the resolution of the display panel 10 and supplies it to the data driver 12. In addition, the timing controller 11 controls the data driver 12 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the dot clock signal (DCLK), and the data enable signal (DE). A data control signal (DDC) for controlling the operation timing and a gate control signal (GDC) for controlling the operation timing of the gate driver 13 can be generated.

The data driver 12 may convert digital video data (RGB) input from the timing controller 11 into an analog data voltage based on the data control signal (DDC) and supply it to the plurality of data lines 14.

The gate driver 13 can generate scan signals (Scan1, Scan2) and a light emission signal (or light emission control signal) (EM) based on the gate control signal (GDC). The gate driver 13 may include a scan driver and a light emission signal driver. The scan driver may generate scan signals in a row sequential manner to drive at least one scan line connected to each pixel row and supply the scan signals to the scan lines. The light emitting signal driver may generate the light emitting signal EM in a row sequential manner to drive at least one light emitting signal line connected to each pixel row and supply the light emitting signal EM to the light emitting signal lines.

Depending on the embodiment, the gate driver 13 may be built into a non-display area of the display panel 10 according to a gate-driver in panel (GIP) method, but is not limited thereto. In some cases, the gate driver 13 may include a plurality and may be disposed on at least two sides of the display panel 10, but the embodiment of the present specification is not limited thereto.

FIG. 2 is a diagram for explaining a pixel circuit of a display device according to an embodiment of the present specification. FIG. 2 shows an example of a pixel circuit of the sub-pixel (PXL) of FIG. 1.

Referring to FIG. 2, each of the sub-pixels (PXL) disposed on the substrate (SUB) in the display area (AA) of the display panel 110 has a light-emitting element (OLED) and a light-emitting element (OLED) for driving the light-emitting element (OLED). a driving transistor (DRT) for transmitting the data voltage (Vdata) to the first node (N1) of the driving transistor (DRT), and a constant voltage for one frame. It may include a storage capacitor (Cst) to maintain .

The driving transistor (DRT) receives a high potential common voltage ( It may include a third node (N3) to which Vdd) is applied. In the driving transistor DRT, the first node N1 is a gate node, the second node N2 is a source node or a drain node, and the third node N3 is a drain node or a source node.

A light emitting device (OLED) may include an anode electrode (AE), a light emitting layer (EL), and a cathode electrode (CE). The anode electrode AE may be a pixel electrode disposed in each sub-pixel PXL, and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel PXL. The cathode electrode (CE) may be a common electrode commonly disposed in the plurality of sub-pixels (PXL), and a low-potential common voltage (Vss) may be applied.

For example, the anode electrode (AE) may be a pixel electrode, and the cathode electrode (CE) may be a common electrode. Conversely, the anode electrode (AE) may be a common electrode, and the cathode electrode (CE) may be a pixel electrode. Below, for convenience of explanation, it is assumed that the anode electrode (AE) is a pixel electrode and the cathode electrode (CE) is a common electrode.

For example, the light emitting device (OLED) may be an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting device. When the light emitting device (OLED) is an organic light emitting diode, the light emitting layer (EL) in the light emitting device (OLED) may include an organic light emitting layer containing an organic material.

The scan transistor SCT is controlled on-off by the scan signal SCAN, which is a gate signal applied through the gate line GL. The scan transistor (SCT) may be configured to switch the electrical connection between the first node (N1) of the driving transistor (DRT) and the data line (DL).

The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

As shown in FIG. 2, each sub-pixel (PXL) may have a 2T (Transistor) 1C (Capacitor) structure including two transistors (DRT, SCT) and one capacitor (Cst). Depending on the embodiment, at least one sub-pixel may further include one or more transistors or one or more capacitors.

The storage capacitor Cst is not a parasitic capacitor, which is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DRT, but is an external capacitor of the driving transistor DRT. It may be an external capacitor intentionally designed.

Each of the driving transistor (DRT) and scan transistor (SCT) may be an n-type transistor or a p-type transistor.

Since the circuit elements (especially the light-emitting element (OLED)) within each sub-pixel (PXL) are vulnerable to external moisture or oxygen, it is difficult for external moisture or oxygen to penetrate the circuit elements (especially the light-emitting element (ED)). An encapsulation layer (ENCAP) may be disposed on the display panel (eg, the display panel 10 of FIG. 1) to prevent the display panel from being damaged. The encapsulation layer (ENCAP) may be disposed to cover the light emitting devices (OLED). For example, the encapsulation layer (ENCAP) may be disposed to completely cover the light emitting devices (OLED).

Figure 3 shows an example of a pixel circuit of a display device according to an embodiment of the present specification. Figure 3 is a diagram illustrating an equivalent circuit of a sub-pixel as an example.

Referring to FIG. 3, the sub-pixel (PXL) of the display device according to an embodiment of the present specification includes first to sixth switching transistors (T1-T6), a driving transistor (DRT), a storage capacitor (Cst), and light emission. Includes element (ED).

Here, the light emitting device (ED) may be a self-light emitting device that can emit light on its own, such as an organic light emitting diode (OLED).

In the sub-pixel (PXL) according to an embodiment of the present specification, the second to fourth switching transistors (T2-T4), the sixth switching transistor (T6), and the driving transistor (DRT) may be P-type transistors. Additionally, the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

P-type transistors are relatively more reliable than N-type transistors. In the case of a P-type transistor, there is an advantage that the current flowing through the light emitting device (ED) is not shaken by the capacitor (Cst) because the drain electrode is fixed to the high potential driving voltage (VDD). Therefore, it is easy to supply current stably.

For example, the P-type transistor may be connected to the anode electrode of the light emitting device (ED). At this time, when the transistors (T4, T6) connected to the light emitting device (ED) operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the light emitting device (ED), so reliability is high. Relatively high.

In this sub-pixel (PXL) structure, the N-type transistors (T1, T5) are oxide transistors formed using a semiconducting oxide (e.g., a channel formed from a semiconducting oxide such as indium, gallium, zinc oxide, or IGZO). transistors), and other P-type transistors (DRT, T2-T4, T6) are silicon transistors formed from semiconductors such as silicon (e.g., formed using a low-temperature process referred to as LTPS or low-temperature polysilicon). transistor with a polysilicon channel).

Oxide transistors have a relatively lower leakage current than silicon transistors, so when implementing a transistor using an oxide transistor, current leakage from the gate electrode of the driving transistor (DRT) is prevented, thereby improving image quality such as flicker. It has the effect of reducing defects.

Except for the first switching transistor (T1) and the fifth switching transistor (T5) corresponding to the N-type transistors, the remaining P-type transistors (DRT, T2-T4, T6) may be made of low-temperature poly silicon.

The gate electrode of the first switching transistor T1 receives the first scan signal SCAN1. The drain electrode of the first switching transistor (T1) is connected to the gate electrode of the driving transistor (DRT).

The source electrode of the first switching transistor (T1) is connected to the source electrode of the driving transistor (DRT).

The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT through the high potential driving voltage VDD stored in the storage capacitor Cst.

The first switching transistor T1 may be made of an N-type MOS transistor to form an oxide transistor. Because the N-type MOS transistor uses electrons rather than holes as carriers, the mobility is faster than the P-type MOS transistor, so the switching speed can be fast.

The gate electrode of the second switching transistor T2 receives the second scan signal SCAN2. The drain electrode of the second switching transistor T2 may be supplied with a data voltage (Vdata) or a bias voltage (VOBS). The source electrode of the second switching transistor (T2) is connected to the drain electrode of the driving transistor (DRT).

The second switching transistor T2 is turned on by the second scan signal SCAN2 and supplies the data voltage Vdata to the drain electrode of the driving transistor DRT.

The gate electrode of the third switching transistor T3 receives the light emission signal EM. The drain electrode of the third switching transistor (T3) is supplied with a high potential driving voltage (VDD). The source electrode of the third switching transistor (T3) is connected to the drain electrode of the driving transistor (DRT).

The third switching transistor T3 is turned on by the light emission signal EM and supplies the high potential driving voltage VDD to the drain electrode of the driving transistor DRT.

The gate electrode of the fourth switching transistor T4 receives the light emission signal EM. The drain electrode of the fourth switching transistor (T4) is connected to the source electrode of the driving transistor (DRT). The source electrode of the fourth switching transistor (T4) is connected to the anode electrode of the light emitting element (ED).

The fourth switching transistor T4 is turned on by the light emitting signal EM to supply a driving current to the anode electrode of the light emitting element ED.

The gate electrode of the fifth switching transistor T5 receives the third scan signal SCAN3.

Here, the third scan signal SCAN3 may be the first scan signal SCAN1 supplied to the sub-pixel PXL at a different location. For example, when the first scan signal (SCAN1) is applied to the n-th gate line, the third scan signal (SCAN3) is the first scan signal (SCAN1[n-9]) applied to the n-9th gate line. It can be. For example, the third scan signal SCAN3 may use the first scan signal SCAN1 that varies the gate line GL depending on the phase in which the display panel 110 is driven.

The drain electrode of the fifth switching transistor (T5) is supplied with the stabilization voltage (Vini). The source electrode of the fifth switching transistor (T5) is connected to the gate electrode of the driving transistor (DRT) and the storage capacitor (Cst).

The fifth switching transistor T5 is turned on by the third scan signal SCAN3 and supplies the stabilization voltage Vini to the gate electrode of the driving transistor DRT.

The gate electrode of the sixth switching transistor T6 receives the fourth scan signal SCAN4.

Here, the fourth scan signal SCAN4 may be the second scan signal SCAN2 supplied to the sub-pixel PXL at a different location. For example, when the second scan signal SCAN2 is applied to the nth gate line, the fourth scan signal SCAN4 is the second scan signal SCAN2[n-1] applied to the n-1th gate line. It can be. For example, the fourth scan signal SCAN4 may use the second scan signal SCAN2 that varies the gate line GL depending on the phase in which the display panel 110 is driven.

The drain electrode of the sixth switching transistor (T6) is supplied with a reset voltage (VAR). The source electrode of the sixth switching transistor (T6) is connected to the anode electrode of the light emitting element (ED).

The sixth switching transistor T6 is turned on by the fourth scan signal SCAN4 and supplies the reset voltage VAR to the anode electrode of the light emitting device ED.

The gate electrode of the driving transistor (DRT) is connected to the drain electrode of the first switching transistor (T1). The drain electrode of the driving transistor (DRT) is connected to the source electrode of the second switching transistor (T2). The source electrode of the driving transistor (DRT) is connected to the source electrode of the first switching transistor (T1).

The driving transistor DRT is turned on by the voltage difference between the source electrode and the drain electrode of the first switching transistor T1, and a driving current is applied to the light emitting element ED.

A high-potential driving voltage (VDD) is applied to one side of the storage capacitor (Cst), and the other side is connected to the gate electrode of the driving transistor (DRT). The storage capacitor (Cst) stores the voltage of the gate electrode of the driving transistor (DRT).

The anode electrode of the light emitting element (ED) is connected to the source electrode of the fourth switching transistor (T4) and the source electrode of the sixth switching transistor (T6). A low potential driving voltage (VSS) is applied to the cathode electrode of the light emitting device (ED).

The light emitting element (ED) emits light with a predetermined brightness by a driving current flowing through the driving transistor (DRT).

At this time, the stabilization voltage (Vini) is supplied to stabilize the change in capacitance formed on the gate electrode of the driving transistor (DRT), and the reset voltage (VAR) is supplied to reset the anode electrode of the light emitting element (ED). supplied.

With the fourth switching transistor (T4) located between the anode electrode of the light emitting device (ED) and the driving transistor (DRT) and controlled by the light emitting signal (EM) turned off, the anode electrode of the light emitting device (ED) is switched on. When the reset voltage VAR is supplied, the anode electrode of the light emitting element ED may be reset.

The sixth switching transistor (T6) that supplies the reset voltage (VAR) is connected to the anode electrode of the light emitting device (ED).

A third scan signal ( SCAN3) and the fourth scan signal (SCAN4) for controlling the supply of the reset voltage (VAR) to the anode electrode of the light emitting device (ED) are separated from each other.

At this time, when turning on the switching transistors (T5, T6) that supply the stabilization voltage (Vini) and reset voltage (VAR), the source electrode of the driving transistor (DRT) and the anode electrode of the light emitting element (ED) are connected. The fourth switching transistor (T4) is turned off to block the driving current of the driving transistor (DRT) from flowing to the anode electrode of the light emitting element (ED), and the anode electrode is blocked by a voltage other than the reset voltage (VAR). The sub-pixel (PXL) can be configured so that there is no effect.

In this way, the sub-pixel (PXL) consisting of seven transistors (DRT, T1, T2, T3, T4, T5, T6) and one capacitor (Cst) can be said to have a 7T1C structure.

Here, the 7T1C structure is shown as an example among the various structures of sub-pixel (PXL) circuits, and the structure and number of transistors and capacitors that make up the sub-pixel (PXL) may be changed in various ways. Each of the plurality of sub-pixels (PXL) may have the same structure, or some of the plurality of sub-pixels (PXL) may have a different structure.

FIG. 4 is a cross-sectional view of at least a portion of a display device according to an embodiment of the present specification.

Referring to FIG. 4, thin film transistors 102, 104, 106, and 108 and organic light emitting devices 112, 114, and 116 are located on the substrate 101.

The substrate 101 may be a glass or plastic substrate. In the case of a plastic substrate, a polyimide-based or polycarbonate-based material may be used to provide flexibility.

The thin film transistor may have a semiconductor layer 102, a gate insulating film 103, a gate electrode 104, an interlayer insulating film 105, and source and drain electrodes 206 and 208 arranged sequentially on a substrate 101. and the embodiments of the present specification are not limited thereto.

The semiconductor layer 102 may be made of polysilicon (p-Si), in which case a predetermined region may be doped with impurities. Additionally, the semiconductor layer 102 may be made of amorphous silicon (a-Si), or may be made of various organic semiconductor materials such as pentacene. For another example, the semiconductor layer 102 may be made of oxide. When the semiconductor layer 102 is formed of polysilicon, amorphous silicon is formed and crystallized to change it into polysilicon. Crystallization methods include LTA (Lapid Thermal Annealing), MILC (Methal Induced Lateral Crystallization), or SLS (Sequential Lateral Crystallization). Various methods such as solidification may be applied, and the embodiments of the present specification are not limited thereto.

The gate insulating film 103 may be formed of an insulating material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx), and may also be formed of an insulating organic material. The gate electrode 104 is made of various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or It may be formed of these alloys, etc., and the embodiments of the present specification are not limited thereto.

The interlayer insulating film 105 may be formed of an insulating material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx), and may also be formed of an insulating organic material. By selectively removing the interlayer insulating film 105 and the gate insulating film 103, a contact hole exposing the source and drain regions may be formed.

The source and drain electrodes 206 and 208 are formed in a single-layer or multi-layer shape using a material for the gate electrode 104 on the interlayer insulating film 105 so that contact holes are filled.

A protective film 107 may be located on the thin film transistor. The protective film 107 protects and flattens the thin film transistor. The protective film 107 may be composed of various forms. It may be formed of an organic insulating film such as BCB (Benzocyclobutene) or acryl, or an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed as a single layer. Various modifications are possible, such as being formed of double or multiple layers, and the embodiments of the present specification are not limited thereto.

The organic light-emitting device includes a first electrode 112, an organic light-emitting layer 114, and a second electrode 116 arranged sequentially. For example, the organic light emitting device includes a first electrode 112 formed on the protective film 107, an organic light emitting layer 114 located on the first electrode 112, and a second electrode 116 located on the organic light emitting layer 114. ) is composed of.

The first electrode 112 is electrically connected to the drain electrode 108 of the driving thin film transistor through a contact hole. This first electrode 112 may be made of an opaque conductive material with high reflectivity. For example, the first electrode 112 is made of silver (Ag), aluminum (Al), aluminum nitride (AlN), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or these. It may be formed of at least some of the alloys, etc., and the embodiments of the present specification are not limited thereto.

The bank 110 is formed in the remaining area excluding the light emitting area. Accordingly, the bank 110 has a bank hole that exposes the first electrode 112 corresponding to the light emitting area. The bank 110 may be formed of an inorganic insulating material such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx), or an organic insulating material such as BCB, acrylic resin, or imide resin, and the embodiments of the present specification are not limited thereto. No.

The organic light emitting layer 114 is located on the first electrode 112 exposed by the bank 110. The organic light-emitting layer 114 may include a light-emitting layer, an electron injection layer, an electron transport layer, a hole transport layer, and/or a hole injection layer, and the embodiments of the present specification are not limited thereto.

The second electrode 116 is located on the organic light emitting layer 114. The second electrode 116 is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), thereby emitting light generated in the organic light-emitting layer 114. Light is emitted to the top of the second electrode 116.

An upper encapsulation layer 120 is located on the second electrode 116. At this time, the upper encapsulation layer 120 may be composed of an inorganic film made of glass, metal, aluminum oxide (AlOx), or silicon (Si)-based material, or may have a structure in which organic films and inorganic films are alternately stacked, as described herein. The embodiments are not limited to this. The upper encapsulation layer 120 prevents oxygen and moisture from penetrating from the outside to prevent oxidation of the light emitting material and electrode material. When an organic light-emitting device is exposed to moisture or oxygen, pixel shrinkage, which reduces the light-emitting area, may occur, or dark spots may appear within the light-emitting area.

The barrier film 150 is positioned on the upper encapsulation layer 120 to encapsulate the entire substrate 101 including the organic light emitting device. The barrier film 150 may be a retardation film or an optically isotropic film. If the barrier film has optical isotropic properties, the incident light passing through the barrier film is transmitted without phase delay. Additionally, an organic layer or an inorganic layer may be further positioned on the upper or lower surface of the barrier film. The inorganic layer may include a silicon oxide layer (SiOx) or a silicon nitride layer (SiOx). The organic layer may include a polymer material such as acrylic resin, epoxy resin, polyimide, or polyethylene, but the embodiments of the present specification are not limited thereto. The organic or inorganic film formed on the upper or lower surface of the barrier film serves to block the penetration of external moisture or oxygen.

The adhesive layer 140 may be positioned between the barrier film 150 and the upper encapsulation layer 120. The adhesive layer 140 adheres the upper encapsulation layer 120 and the barrier film 150. The adhesive layer 140 may be a heat-curing type or a natural-curing type adhesive, and the embodiments of the present specification are not limited thereto. For example, the adhesive layer 140 may be made of a material such as B-PSA (Barrier pressure sensitive adhesive), but embodiments of the present specification are not limited thereto.

A lower adhesive layer 160 and a lower encapsulation layer 170 may be sequentially formed on the lower part of the substrate 101. The lower encapsulation layer 170 is made of polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyethylene ether phthalate, polycarbonate, polyarylate, poly It may be formed of one or more organic materials such as polyether imide, polyether sulfonate, polyimide, or polyacrylate, and the embodiments of the present specification are not limited thereto. The lower encapsulation layer 170 serves to prevent moisture or oxygen from penetrating into the substrate from the outside.

The lower adhesive layer 160 is formed of a heat-curing or natural-curing adhesive, and serves to bond the substrate 101 and the lower encapsulation layer 170. For example, the lower adhesive layer 160 may be formed of a material such as OCA (Optical Cleared Adhesive).

Figure 5 is an example of optical compensation data used in a display device according to an embodiment of the present specification. Figure 5 shows the values of the data voltage 501 and the emission duty cycle 502 (EM Duty) according to the dimming level.

Referring to FIG. 5, in the optical compensation data 500, the x-axis represents the dimming level, the first y-axis (or left y-axis) of FIG. 5 represents the data voltage value, and the second y-axis (or The y-axis on the right) represents the emission duty cycle (EM duty, EM Cycle, or EM duty ratio) value.

Dimming is to adjust luminance step by step, and the dimming level may represent each step adjusted when dimming is performed. For example, when the overall brightness is adjusted in 10 levels, the dimming level may be composed of levels corresponding to each of the 10 levels, for example, 10 levels. The dimming levels in FIG. 5 are shown assuming that all dimming levels adjustable in the display device are 100%.

The data voltage 501 represents a voltage provided to the display panel (or a circuit of a sub-pixel) through a data line (eg, data line 14 in FIG. 1). The data voltage 501 may be provided to the display panel through a data driver (eg, data driver 12 in FIG. 1). The data voltage 501 in FIG. 5 is represented by assuming that the maximum data voltage value that can be provided by the display device is 100% and the minimum data voltage value is 0%.

The light emission duty cycle 502 represents the duty cycle (or duty ratio) of the light emission signal (or EM signal) provided to the display panel (or circuit of the sub-pixel). Here, the light-emitting signal may include a signal provided to the display panel through a gate line (eg, gate line 15 in FIG. 1). The light emitting signal may be provided to the display panel through a gate driver (eg, gate driver 13 in FIG. 1). The light emission duty cycle 502 of FIG. 5 is shown assuming that the maximum duty cycle of the light emission signal that can be provided by the display device is 100% and the minimum duty cycle is 0%.

In an embodiment, the dimming level section of the optical compensation data 500 may be divided into a plurality of sections. For example, the dimming level section may be divided into a first section 510, a second section 520, a third section 530, and a fourth section 540. To be more specific, the dimming level section of the optical compensation data 500 includes the first section 510, the second section 520, the third section 530, and the fourth dimming level sequentially from 100% to 0%. It can be divided into sections 540. For example, the first section 510 may include a section where the dimming level is between 0% and 25%. The second section 520 may include a section where the dimming level is above 25% and below 50%. The third section 530 may include a section where the dimming level is greater than 50% and less than 75%. The fourth section 540 may include a section where the dimming level is greater than 75% and less than 100%.

In the first section 510, the data voltage 501 may change and the light emission duty cycle 502 may have a first value. In the first section 510, the data voltage 501 may change linearly. For example, the data voltage value may have a first value at the first point of the first section 510, but may change linearly to have a second value smaller than the first value at the second point. Here, the first point may correspond to a point where the dimming level is 100%, and the second point may correspond to a point where the first section 510 and the second section 520 are connected (or adjacent to). For example, the data voltage 501 in the first section may decrease as it approaches the second section. In the first section 510, the light emission duty cycle 502 may be maintained at 100%, for example.

In each of the second section 520 and the third section 530, the data voltage 501 may change and the light emission duty cycle 502 may have a first value. As an example, the data voltage 501 linearly extends from the first point of the first section 510, where the dimming level corresponds to 100%, to the third point (or end point) of the third section 530, as shown. It can change. Here, the third point of the third section 530 may correspond to the point where the third section 530 ends and the fourth section 540 begins. For example, the third point of the third section 530 may correspond to a point where the dimming level is 25%. The data voltage value corresponding to the third point may be a third value, and the third value may be smaller than the above-described second value. In the second section 520 and the third section 530, the light emission duty cycle 502 may be maintained at, for example, 100%.

In the fourth section 540, the data voltage 501 has a third value and the light emission duty cycle 502 may change. As an example, the data voltage 501 may maintain the third value in the fourth section 540. The light emission duty cycle 502 may change to have a first value at the start point of the fourth section 540 and a fourth value at the end point of the fourth section 540 . Here, the starting point of the fourth section 540 may correspond to the point where the third section 530 ends and the fourth section 540 begins. The end point of the fourth section 540 may correspond to a point where the dimming level is 0%.

The display device according to an embodiment of the present specification can perform optical compensation efficiently by performing optical compensation using optical compensation data divided into at least four sections.

In one embodiment, when the dimming level is low, such as in the fourth section 540, the pixel does not have enough charging time according to the light emission duty cycle, resulting in a reddish phenomenon in which at least a portion of the display panel is displayed in red. It can happen. In this case, the optical compensation data of FIG. 6 can be used to further optimize the color coordinates. Hereinafter, in FIG. 6, content that overlaps with the content described in FIG. 5 may be omitted.

Figure 6 is another example of optical compensation data used in a display device according to an embodiment of the present specification.

Referring to FIG. 6, optical compensation data 600 may include at least four dimming level sections. For example, at least four dimming level sections are sequentially divided into a first section 610, a second section 620, a third section 630, and a fourth section 640 in which the dimming level ranges from 100% to 0%. can be distinguished. For example, the first section 610 may include a section where the dimming level is between 0% and 25%. The second section 620 may include a section where the dimming level is above 25% and below 50%. The third section 630 may include a section where the dimming level is greater than 50% and less than 75%. The fourth section 640 may include a section where the dimming level is greater than 75% and less than 100%. Each of the first section 610, the second section 620, the third section 630, and the fourth section 640 may have the same length.

The data voltage 601 may change in at least one dimming level section among at least four dimming level sections of the optical compensation data 600. For example, the data voltage 601 may change in the first section 610, the second section 620, and the fourth section 640 of the optical compensation data 600. The data voltage 601 may maintain a constant value in at least one other dimming level section among at least four dimming level sections of the optical compensation data 600. For example, in the third section 630 of the optical compensation data 600, the data voltage 601 may maintain a constant value.

The light emission duty cycle 602 may change in at least one dimming level section among at least four dimming level sections of the optical compensation data 600. For example, the light emission duty cycle 602 may change in the third section 630 of the optical compensation data 600. The light emission duty cycle 602 may maintain a constant value in at least one other dimming level section among the at least four dimming level sections of the optical compensation data 600. For example, the light emission duty cycle may maintain a constant value in the first section 610, the second section 620, and the fourth section 640 of the optical compensation data 600.

In an embodiment, the light emission duty cycle 602 may have a first value in the first interval 610 and the second interval 620. For example, the light emission duty cycle 602 may be maintained at 100% in the first section 610 and the second section 620. The light emission duty cycle 602 may change from a first value to a second value in the third section 630. The light emission duty cycle 602 may linearly change from a first value to a second value in the third section 630. For example, the luminescence duty cycle 602 may vary linearly to have a first value at the start point of the third interval 630 and a second value (or n value) at the end point of the third interval 630. You can. In one embodiment, the first value is greater than the second value. In this case, the light emission duty cycle 602 may decrease in response to a decrease in the dimming level value in the third section 630. The light emission duty cycle 602 may have a second value in the fourth section. For example, the light emission duty cycle 602 may maintain the second value in the fourth section 640.

In embodiments, the second value (or n value) may be included in a range of 25% to 50%. The second value may be preset within a range of 25% to 50%.

In an embodiment, the data voltage 601 may change from a third value to a fourth value in the first section 610 and the second section 620. The data voltage 601 may linearly change from a third value to a fourth value in the first section 610 and the second section 620. For example, the data voltage 601 may change linearly to have a third value at the start point of the first section 610 and a fourth value at the end point of the second section 620. The data voltage 601 may have a fourth value in the third section 630. For example, the data voltage 601 may maintain the fourth value in the third section 630. The data voltage 601 may change from the fourth value to the fifth value in the fourth section 640. The data voltage 601 may linearly change from the fourth value to the fifth value in the fourth section 640.

In one embodiment, the third value is greater than the fourth value and the fourth value is greater than the fifth value. The third value may be the same as the first value. For example, both the third value and the first value may correspond to 100%. For example, the fourth value may be included in a range of 50% or less and 25% or more. The fourth value may be set to a specific value within the range of 50% or less and 25% or more, for example, 40%. The fifth value may correspond to 0%.

In the case of the optical compensation data 600 of FIG. 6, the light emission duty cycle 602 is variable or changed in the third section 630, and the light emission duty cycle 602 can be set to a second value in the fourth section 640. . In this case, additional optical compensation can be performed in the fourth section 640 rather than the optical compensation data 500 of FIG. 5, and the difference in charging time for each color of the light emitting device, for example, the sub-pixel, can be compensated. there is.

In an embodiment, in relation to the portion where the data voltage 601 and the light emission duty cycle 602 change linearly, the data voltage value and the light emission duty cycle value corresponding to the dimming level value may be determined based on interpolation. .

For specific examples of light emission signals generated according to the light emission duty cycle of each dimming level section in FIG. 6, refer to FIGS. 9 to 11.

Optical compensation data 600 may be stored in the memory of a display device (eg, display device 1 in FIG. 1). For example, the optical compensation data 600 may be stored in a memory to be connected to a timing controller (eg, timing controller 11 in FIG. 1). The memory may include non-volatile memory, for example, electrically erasable programmable read-only memory (EEPROM).

In an embodiment, the form of the optical compensation data 600 stored in the memory is not limited to the form of the graph as shown in FIG. 6. For example, the optical compensation data 600 may be stored in various forms, such as tables, charts, or codes, by matching the dimming level with the values of the data voltage and emission duty cycle corresponding to the dimming level.

FIG. 7 is a diagram illustrating the step-by-step flow of a method of operating a display device according to an embodiment of the present specification. The operator of each step in FIG. 7 may include, but is not limited to, a processor (or control unit) included in the display device. Additionally, each step may be performed in a different order depending on the case, and at least one additional step may be included before and/or after some steps.

Referring to FIG. 7, in step 710, a display device (eg, display device 1 of FIG. 1) can check the dimming level. The display device may check the dimming level value corresponding to the preset condition based on whether the display device satisfies the preset condition. Here, the preset condition may include a predetermined light amount range detected by the display device.

As an example, the display device may check whether the surrounding brightness is within the first light amount range. For example, if the display device is a vehicle, the surrounding brightness may change when the vehicle enters a dark place such as a tunnel. In this case, the display device can sense the surrounding brightness and check whether the surrounding brightness is included in the first light amount range.

The display device may check the dimming level value corresponding to the first light amount range in response to the fact that the surrounding brightness is included in the first light amount range. The display device pre-stores information about the dimming level according to the surrounding brightness. Accordingly, the display device can confirm the dimming level value corresponding to the confirmed brightness based on the surrounding brightness being confirmed. In this case, the above-mentioned preset condition may include the first light amount range.

In an embodiment, the step of FIG. 7 may be terminated when the ambient brightness is not included in the first light amount range. For example, you can maintain the current panel brightness. The first light amount range may be set in advance. For example, the first light amount range may correspond to a luminance of 2.0 cd/m2 or more and less than 3.0 cd/m2. For another example, the first light amount range may include a light amount range corresponding to the inside of a tunnel or a light amount range corresponding to a night when the sun has set.

In an embodiment, the dimming level value corresponding to the light amount range may be proportional to the value included in the light amount range. For example, when the light quantity value included in the light quantity range is large, for example, indicating brighter brightness, the dimming level value may indicate a dimming level value at which the brightness of the screen of the display device is brighter.

In this case, the display device can be controlled so that the brightness of the display panel becomes brighter as the surrounding brightness increases. The display device can control the brightness of the display panel to become darker as the surrounding brightness becomes darker.

In step 720, the display device may check the light emission duty cycle and data voltage value corresponding to the confirmed dimming level value. The display device displays a light emission duty cycle value and a data voltage value corresponding to the dimming level value confirmed using pre-stored optical compensation data (e.g., optical compensation data 500 in FIG. 5 and optical compensation data 600 in FIG. 6). can confirm.

In an embodiment, the display device may read optical compensation data stored in memory through a timing controller. The display device can check the light emission duty cycle and data voltage value corresponding to the dimming level value confirmed in the optical compensation data through the timing controller.

In step 730, the display device may generate a data voltage based on the confirmed data voltage value and generate a light emission signal using the confirmed light emission duty cycle value. The display device may provide information about the confirmed data voltage value to a data driver (eg, data driver 12 in FIG. 1). The display device may generate a data voltage having a confirmed data voltage value using a data driver. The display device may provide information about the confirmed light emission duty cycle value to a gate driver (eg, gate driver 13 in FIG. 1). The display device may generate a light emission signal (eg, the light emission signal EM of FIG. 1) having a confirmed light emission duty cycle value using a gate driver.

In step 740, the display device may provide a data voltage and a light emission signal to the pixel circuit. The display device may provide the data voltage generated by the data driver to the pixel circuit. The display device may provide a data voltage from the data driver to the pixel circuit through a data line connecting the pixel circuit and the data driver. A display device can provide a light-emitting signal generated by a gate driver to a pixel circuit. The display device may provide a light emitting signal from the gate driver to the pixel circuit through a gate line connecting the pixel circuit and the gate driver. Data voltage and light emission signals may be provided in sub-pixel units. Each sub-pixel may emit light based on the received data voltage and light emission signal.

As an example, when explaining using FIG. 3, the data voltage generated by the data driver (e.g., the data voltage (Vdata) in FIG. 3) is a transistor connected to the data line among the components of the pixel circuit (e.g., the second transistor in FIG. 3). It may be provided as one end of a switching transistor (T2). The light emission signal (e.g., the light emission signal (EM) of FIG. 3) generated by the gate driver is transmitted through a transistor (e.g., the third switching transistor (T3), the fourth switching transistor) connected to the gate line that provides the light emission signal among the components of the pixel circuit. It may be provided as one end of a transistor (T4). The pixel circuit may be driven based on a provided data voltage, a light emission signal, and other signals, such as a scan signal, an initialization voltage, or a reference voltage, to cause the light emitting element ED to emit light.

FIG. 8 is a diagram illustrating the step-by-step flow of a method of operating a timing controller included in a display device according to an embodiment of the present specification. Each step described below may be performed in a different order depending on the case, and at least one additional step may be included before and/or after some steps.

Referring to FIG. 8, in step 810, the timing controller may obtain information about the dimming level. The timing controller can obtain information about the dimming level for controlling the display panel. The timing controller may check information about the dimming level determined based on the brightness around the display device. The information about the dimming level may include a dimming level value and may be provided from another component included in the display device, for example, a microprocessor or controller.

In step 820, the timing controller may check the light emission duty cycle value and data voltage value corresponding to the dimming level using the optical compensation data. When the timing controller obtains information about the dimming level, it can check the light emission duty cycle value and data voltage value corresponding to the dimming level from the optical compensation data.

Optical compensation data may be pre-stored in a memory connected to the timing controller, for example, EEPROM. The optical compensation data may include information about the light emission duty cycle value and data voltage value according to the dimming level value.

In step 830, the timing controller may provide information about the light emission duty cycle value to the gate driver and information about the data voltage value to the data driver. The timing controller can provide information about the confirmed light emission duty cycle value to the gate driver. The timing controller can provide information about the confirmed data voltage value to the data driver.

The gate driver may generate a light emitting signal using information about the provided light emission duty cycle value. The data driver can generate a data voltage using information about the provided data voltage value. The generated light emission signal and data voltage may be provided to the pixel circuit of the sub-pixel. The pixel circuit may emit light based on the provided light emission signal and data voltage.

FIG. 9 is a diagram for explaining signals in the first section and the second section among the dimming level sections of the display device according to an embodiment of the present specification. FIG. 9 is a diagram for explaining an emission signal (EM) generated based on emission duty cycle values corresponding to the first and second sections of optical compensation data according to FIG. 6.

In the first and second sections of the optical compensation data of FIG. 6, the light emission duty cycle has a first value. Accordingly, the emission duty cycle of the emission signal EM of FIG. 9 may have a first value. The first value corresponds to 100%. A light emission duty cycle value of 100% may indicate a case where the section in which the light emission signal (EM) is turned on is the maximum.

According to the embodiment of FIG. 9, the section in which the light emitting signal EM is turned on may be maximum, and the section in which the light emitting signal EM is turned off may be minimum. The length of the section in which the light emitting signal EM is turned off may be referred to as a first length, and may be shorter than the length of the section in which the light emitting signal EM is turned off in FIGS. 10 and 11 described later.

In an embodiment, the emission signal EM may be turned off at the first point 901. At the first point 901, the first clock signal (ECLK1) and the first scan signal (SCAN1) may be turned on. The light emitting signal EM may remain in an off state for a time corresponding to the first length. The light emitting signal (EM) may be turned on at the second point 902. The second clock signal ECLK2 may be turned on at the second point 902.

In an embodiment, the start signal EVST may include a start signal for the operation of the gate driver. The first clock signal (ECLK1) and the second clock signal (ECLK2) may include signals for synchronizing the operation of the gate driver.

The first scan signal SCAN1 and the second scan signal SCAN2 in FIG. 9 are shown as examples, and the signal flow may change depending on the circuit configuration of the gate driver.

FIG. 10 is a diagram for explaining a signal in a third section among the dimming level sections of a display device according to an embodiment of the present specification. FIG. 9 is a diagram for explaining the light emission signal (EM) generated based on the light emission duty cycle value corresponding to the third section of the optical compensation data according to FIG. 6. Hereinafter, content that overlaps with the content described through FIG. 9 may be omitted.

FIG. 10 shows an emission signal (EM) generated according to an emission duty cycle corresponding to a point in the third section of the optical compensation data of FIG. 6. Referring to FIG. 10, the light emitting signal EM may be turned off for a second length. The second length may be longer than the first length in FIG. 9.

In this case, the third point 1003 where the light emitting signal EM is turned on may lag the second point 902 where the light emitting signal EM is turned on in FIG. 9 . In this case, the length of the section in which the light emitting signal EM is maintained on may be shorter than the length of the section in which the light emitting signal EM is maintained on in FIG. 9 .

In the third section of the optical compensation data in FIG. 6, the larger the dimming level, the larger the light emission duty cycle. Accordingly, the length of the section in which the light emitting signal EM is kept off may be determined in response to the dimming level within a range that is longer than the first length and shorter than the third length of FIG. 11, which will be described later. For example, within a range that is longer than the first length and shorter than the third length of FIG. 11, which will be described later, as the dimming level has a larger value, the length of the section in which the light emitting signal EM is kept off may be shorter. For another example, within a range that is longer than the first length and shorter than the third length of FIG. 11 described later, the length of the section in which the light emitting signal EM is kept off may be inversely proportional to the dimming level value.

FIG. 11 is a diagram for explaining a signal in a fourth section among the dimming level sections of a display device according to an embodiment of the present specification. FIG. 9 is a diagram for explaining an emission signal (EM) generated based on an emission duty cycle value corresponding to the fourth section of optical compensation data according to FIG. 6. Hereinafter, content that overlaps with the content described through FIGS. 9 and 10 may be omitted.

FIG. 11 shows an emission signal (EM) generated according to an emission duty cycle corresponding to the fourth section of the optical compensation data of FIG. 6.

Referring to FIG. 11, the light emitting signal EM may be turned off for a third length. The third length may be longer than the second length in FIG. 10. For example, the length of the section in which the light emitting signal EM is kept off may be longer than the length of the section in which the light emitting signal EM is kept off in FIG. 10 .

In this case, the fourth point 1104 where the light emitting signal EM is turned on may lag the third point 1003 where the light emitting signal EM is turned on in FIG. 10 . The length of the section in which the light emitting signal EM is maintained on may be shorter than the length of the section in which the light emitting signal EM is maintained on in FIG. 10 .

Figure 12 shows the results of an experiment on the amount of color coordinate variation of a display device according to an embodiment of the present specification. FIG. 12 shows the color coordinate variation (y-axis) according to the gray value (x-axis) based on the optical compensation data 500 of FIG. 5 and the optical compensation data 600 of FIG. 6.

Referring to FIG. 12, comparing the color coordinate variation of the optical compensation data 500 according to FIG. 5 and the optical compensation data 600 according to FIG. 6, when the gray value is low, the color coordinate variation of the optical compensation data 600 is less than the optical compensation data 600. It can be seen that the amount of change in color coordinates of data 500 is less.

For example, the display device can improve display quality and stably perform a light emission operation by performing a light emission operation using the optical compensation data 600 at low gray scale.

A display device and a method of operating the display device according to an embodiment of the present specification can be described as follows.

A display device according to an embodiment of the present specification includes a display panel on which a pixel circuit including a light-emitting element and at least one transistor is disposed; A gate driver that generates a light emitting signal and provides it to the display panel; a data driver that generates data voltage and provides it to the display panel; and confirming the light emission duty cycle value and data voltage value corresponding to a predetermined dimming level value using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections, and obtaining the light emission duty cycle value. It includes a timing controller that provides information about the data voltage value to the gate driver and provides information about the data voltage value to the data driver, where the gate driver generates a light emitting signal based on the light emitting duty cycle value received from the timing controller, and the data driver Can generate a data voltage based on the data voltage value received from the timing controller.

According to some embodiments of the present specification, at least four dimming level sections may be sequentially divided into a first section, a second section, a third section, and a fourth section with dimming levels ranging from 100% to 0%. The light emission duty cycle may have a first value in the first section and the second section, change from the first value to the second value in the third section, and have a second value in the fourth section.

According to some embodiments of the present specification, the light emission duty cycle may vary linearly from a first value to a second value in a third section. The first value may be greater than the second value. The length of the off section of the light emitting signal generated based on the light emission duty cycle value corresponding to at least one dimming level section among the first section and the second section is in at least one dimming level section among the third section and the fourth section. It may be longer than the length of the off section of the light emission signal generated based on the corresponding light emission duty cycle value.

According to some embodiments of the present specification, the data voltage changes from a third value to a fourth value in the first section and the second section, has a fourth value in the third section, and starts from the fourth value in the fourth section. The value can vary up to 5. The data voltage may linearly change from the third value to the fourth value in the first and second sections, and may linearly change from the fourth value to the fifth value in the fourth section. The third value may be greater than the fourth value, and the fourth value may be greater than the fifth value.

According to some embodiments of the present specification, the length of each of the first section, the second section, the third section, and the fourth section may be the same.

A display device according to an embodiment of the present specification includes a display panel on which a pixel circuit including a light-emitting element and at least one transistor is disposed; And the light emission duty cycle value and data voltage value corresponding to a predetermined dimming level value can be confirmed using optical compensation data in which the light emission duty cycle changes in at least one section among at least four dimming level sections. The display device may include a control unit that generates a light emitting signal based on the confirmed light emission duty cycle value, generates a data voltage based on the confirmed data voltage value, and provides the generated light emitting signal and the generated data voltage to the display panel. You can.

According to some embodiments of the present specification, the dimming level section may be sequentially divided into a first section, a second section, a third section, and a fourth section where the dimming level ranges from 100% to 0%. The light emission duty cycle may have a first value in the first section and the second section, change linearly from the first value to the second value in the third section, and have a second value in the fourth section.

According to some embodiments of the present specification, the length of the off section of the light emitting signal generated based on the light emission duty cycle value corresponding to the dimming level section of at least one of the first section and the second section is the third section and the fourth section. It may be longer than the length of the off section of the light emitting signal generated based on the light emission duty cycle value corresponding to at least one dimming level section of the section.

According to some embodiments of the present specification, the data voltage changes linearly from a third value to a fourth value in the first section and the second section, has a fourth value in the third section, and has a fourth value in the fourth section. It can vary linearly from to the fifth value. The third value may be greater than the fourth value, and the fourth value may be greater than the fifth value.

According to some embodiments of the present specification, the controller may check a predetermined dimming level value according to preset conditions. The preset condition includes a predetermined light amount range detected by the display device, and the preset dimming level value may correspond to the preset condition.

A method of operating a display device according to an embodiment of the present specification includes checking whether a preset condition is satisfied; Confirming a dimming level value corresponding to a preset condition; Confirming the light emission duty cycle value and data voltage value corresponding to the confirmed dimming level value using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections; generating a light emitting signal based on the confirmed light emission duty cycle and generating a data voltage based on the confirmed data voltage value; and driving the pixel circuit using the generated light emission signal and the generated data voltage.

According to some embodiments of the present specification, the preset condition includes a predetermined light amount range detected by the display device, the preset dimming level value corresponds to the preset condition, and at least four dimming level sections have a dimming level of 100. It includes a first section, a second section, a third section, and a fourth section sequentially divided from % to 0%, and at least one dimming level section may include a third section.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present specification. Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present specification, but are for illustrative purposes, and the scope of the technical idea of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of this specification should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

10: Display panel 11: Timing controller
12: data driver 13: gate driver
14: data lines 15: gate lines
500, 600: Optical compensation data 501, 601: Data voltage
502, 602: Luminous duty cycle

Claims (20)

A display panel on which a pixel circuit including a light emitting element and at least one transistor is disposed;
a gate driver that generates a light emitting signal and provides it to the display panel;
a data driver that generates a data voltage and provides it to the display panel; and
The light emission duty cycle value and data voltage value corresponding to a predetermined dimming level value are confirmed using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections, and the light emission duty cycle value is determined. A timing controller that provides information about the data voltage value to the gate driver and provides information about the data voltage value to the data driver,
The gate driver generates the light emission signal based on the light emission duty cycle value received from the timing controller,
The data driver generates the data voltage based on the data voltage value received from the timing controller.
According to paragraph 1,
The display device wherein the at least four dimming level sections are sequentially divided into a first section, a second section, a third section, and a fourth section with dimming levels ranging from 100% to 0%.
According to paragraph 2,
The light emission duty cycle has a first value in the first section and the second section, changes from the first value to a second value in the third section, and has a second value in the fourth section, display device.
According to paragraph 3,
The display device wherein the light emission duty cycle changes linearly from the first value to the second value in the third section.
According to paragraph 3,
The first value is greater than the second value.
According to clause 5,
The length of the off section of the light emitting signal generated based on the light emission duty cycle value corresponding to the dimming level section of at least one of the first section and the second section is at least one of the third section and the fourth section. The display device is longer than the length of the off section of the light emission signal generated based on the light emission duty cycle value corresponding to the above dimming level section.
According to paragraph 2,
The data voltage changes from a third value to a fourth value in the first section and the second section, has the fourth value in the third section, and has a fourth value to a fifth value in the fourth section. The display device changes up to.
In clause 7,
The data voltage changes linearly from the third value to the fourth value in the first section and the second section, and linearly changes from the fourth value to the fifth value in the fourth section. .
In clause 7,
The third value is greater than the fourth value, and the fourth value is greater than the fifth value.
According to paragraph 2,
The first section, the second section, the third section, and the fourth section each have the same length.
A display panel on which a pixel circuit including a light emitting element and at least one transistor is disposed; and
The light emission duty cycle value and data voltage value corresponding to a predetermined dimming level value are confirmed using optical compensation data in which the light emission duty cycle changes in at least one dimming level section among at least four dimming level sections, and the light emission duty cycle value is determined. A display device comprising a control unit that generates a light emitting signal based on and generates a data voltage based on the data voltage value, and provides the light emitting signal and the data voltage to the display panel.
According to clause 11,
The dimming level section is sequentially divided into a first section, a second section, a third section, and a fourth section where the dimming level ranges from 100% to 0%.
According to clause 12,
The light emission duty cycle has a first value in the first section and the second section, changes linearly from the first value to a second value in the third section, and has a second value in the fourth section. , display device.
According to clause 12,
The length of the off section of the light emitting signal generated based on the light emission duty cycle value corresponding to the dimming level section of at least one of the first section and the second section is at least one of the third section and the fourth section. The display device is longer than the length of the off section of the light emission signal generated based on the light emission duty cycle value corresponding to the above dimming level section.
According to clause 12,
The data voltage changes linearly from a third value to a fourth value in the first section and the second section, has the fourth value in the third section, and starts from the fourth value in the fourth section. Indicator that changes linearly up to 5 values.
According to clause 15,
The third value is greater than the fourth value, and the fourth value is greater than the fifth value.
According to clause 11,
The control unit checks the predetermined dimming level value according to preset conditions.
According to clause 17,
The preset condition includes a predetermined light amount range detected by the display device, and the predetermined dimming level value corresponds to the preset condition.
Checking whether preset conditions are satisfied;
Confirming a dimming level value corresponding to the preset condition;
Using optical compensation data whose light emission duty cycle changes in at least one dimming level section among at least four dimming level sections, confirming a light emission duty cycle value and a data voltage value corresponding to the confirmed dimming level value;
generating a light emitting signal based on the confirmed light emission duty cycle and generating a data voltage based on the confirmed data voltage value; and
A method of operating a display device, comprising driving a pixel circuit using the generated light emission signal and the generated data voltage.
According to clause 19,
The preset condition includes a predetermined light amount range detected by the display device,
The predetermined dimming level value corresponds to the preset condition,
The at least four dimming level sections include a first section, a second section, a third section, and a fourth section where the dimming levels are sequentially divided from 100% to 0%,
The at least one dimming level section includes the third section.

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