KR20240011387A - Structure of GaN device for high voltage robustness and its fabrication method - Google Patents

Abstract

The present invention relates to a GaN semiconductor device and a method of manufacturing the same, and includes a mesa structure including a spacer layer located on top of an active layer, and p-GaN in the form of a planar track disposed on an upper part of the spacer layer of the mesa structure. A gate, a source metal layer located outside the p-GaN gate, a drain metal layer located inside the p-GaN gate, an isolation formed by ion implantation around the mesa structure, and the p-GaN gate. It may include a source field plate located on the upper side of the area between the drain metal layers.

Description

Structure of GaN semiconductor device resistant to high voltage and its manufacturing method {Structure of GaN device for high voltage robustness and its fabrication method}

The present invention relates to a GaN semiconductor device and a method of manufacturing the same, and more specifically, to a GaN semiconductor that can implement a high-performance power semiconductor that is resistant to high voltage by using the HEMT-type epi structure of a wide band gap (WBG) semiconductor. It relates to the structure of the device and its manufacturing method.

Since the advent of semiconductor power devices, most power semiconductor devices have been developed and used using Si semiconductors, which are inexpensive and have superior reliability and stability. However, as the importance of eco-friendliness and energy efficiency increases in modern and future times, the electric vehicle, drone, and robot industries are growing. These highly mobile applications and systems require more efficient, smaller, and lighter power semiconductors. Therefore, attempts to develop and use new power semiconductors using WBG semiconductor materials such as SiC, GaN, and Ga ₂ O ₃ are very active.

A review of conventional GaN semiconductor devices and their manufacturing methods is as follows.

In the US published patent US2010/0019279 A1 (2010. 1. 28, Integrated HEMT and lateral field-effect rectifier combinations, and systems), a rectifier is created with an anode connected to Ohmic and Schottky, and at the same time, the same Schottky is used as a gate. We presented a GaN HEMT device to be manufactured.

To drive the enhancement mode (normally-off), a method of controlling the threshold voltage is used by implanting F ^- ions into the lower part of the Schottky.

However, although the Schottky gate formed of F ^- ions controls the threshold voltage to move to some positive value, this causes problems such as a decrease in transconductance or insufficient reliability of device operation. It is predictable.

In addition, US registered patent US 8,319,256 B2 (Nov. 27, 2012, Layout design for a high power GaN-based FET) proposes a structure in which the source, gate, and drain, which are typical finger-shaped structures, are arranged and connected with pad metal. did.

It does not include a method to reduce stray current between source and drain or to improve isolation function outside the active region.

However, the active area is defined by etching the GaN channel in a mesa shape. By adjusting the gap between the gate and drain, the cut-off frequency is adjusted to 1~2GHz and the breakdown voltage is adjusted to 400V.

A paper related to the present invention is Effect of device layout on the switching of enhancement mode GaN HEMTs (L. Efthymiou, G. Camuso, F. Udrea, M. Chen, K. Terrill, Proceedings of the 30 ^th Inrenational Symposium on Power Devices & ICs, May 13-17 (USA)).

In the GaN HEMT device, the D-S-D structure of the electrode arrangement showed strong characteristics against oscillation, but the turn-on resistance was shown to be slightly increased.

In addition, in the Recessed-gate structure approach toward normally off high-voltage AlGaN/GaN HEMT for power electronic applications (S. Saito, Y. Takada, I. Omura IEEE Trans. on Electronic Devices 2006), the conventionally used recess It describes the gate element. Like trench etching, recess etching also has problems with reproducibility and uniformity, and furthermore, because the recessed area is large, source-gate resistance and gate-drain resistance increase, which reduces device performance.

Leakage current paths in isolated AlGaN/GaN heterostructures(J.Moereke, E. Morvan, W. Vandendaele, F. Allain, A. Torres, M. Charles, M. Plissonnier IEEE Trans. on Semiconductor Manufacturing, Vol. 29,No. 4, Nov. 2016) classifies the path types of leakage current in the AlGaN/GaN heterostructure (surface current, 2DEG current, GaN buffer current, and nucleation layer current) and describes the components of leakage current flowing before and after heat treatment. interpreted.

Defects created by ion implantation of Ar ions are heat treated at 400 ^o C to reduce the density of traps and reduce leakage current.

The structure of a conventional GaN FET will be described with reference to the drawings as follows.

Figure 1 is a top view and equivalent circuit diagram of a conventional GaN FET.

Referring to Figure 1, the active layer of the device is defined by mesa etching or ion implantation, and the source 100, gate 101, and drain 102 are manufactured.

In this device structure, when a high voltage is applied, a stray current 104 is generated at the edge of the gate, which increases the leakage current of the gate drain current (Igd) and drain-source current (Ids) and is disadvantageous in increasing the breakdown voltage. and has the problem of reduced reliability.

A source field plate (SFP: Source Field Plate) 103 is disposed to alleviate the degree to which traps, current collapse, and changes in threshold voltage are caused by hot electrons.

However, the source-gate capacitance (Cgs), which is a parasitic capacitance occurring between the source field plate and the gate electrode, reduces the operating speed of the device.

As described above, conventional technologies are evolving into various forms. An attempt was made to use a WBG semiconductor with a heterojunction HEMT structure and apply horizontal, vertical, metal-semiconductor junctions, and field-plates.

However, GaN FET power semiconductor devices that operate high-frequency and high-power signals with high efficiency are still required to improve performance through many technological developments, such as reliability, high voltage resistance, and ESD resistance.

The technical problem to be solved by the present invention is to provide a GaN semiconductor device structure and manufacturing method that can solve the problems of the prior technologies described above.

In particular, the present invention uses a semiconductor structure with a wide band gap to increase the breakdown voltage to several kV in a device of the same size, and the structure and structure of a GaN semiconductor device that can minimize the range of current fluctuation. The purpose is to provide a manufacturing method.

In addition, in the case of devices having the same breakdown voltage, the present invention can reduce the size of the device compared to the prior art, so it is advantageous to apply to recent portable devices and wearable devices, and increases power efficiency to save energy and eco-friendly electrical and electronic products. Another purpose is to provide a structure and manufacturing method of a Gan semiconductor device applicable to .

The structure of a GaN semiconductor device according to one aspect of the present invention for solving the above problems includes a mesa structure including a spacer layer located on top of an active layer, and a mesa structure disposed on an upper part of the spacer layer of the mesa structure. An isolation formed by ion implantation around the p-GaN gate in the form of a planar track, a source metal layer located on the outside of the p-GaN gate, a drain metal layer located on the inside of the p-GaN gate, and the mesa structure. And, it may include a source field plate located on the upper side of the area between the p-GaN gate and the drain metal layer.

In an embodiment of the present invention, a source ion implantation layer and a drain ion implantation layer are located below each of the source metal layer and the drain metal layer, and the source ion implantation layer, the source metal layer, the drain ion implantation layer, and the drain metal layer are each in ohmic contact. can be formed.

In an embodiment of the present invention, a Schottky diode may be connected in series to the p-GaN gate.

In addition, the method of manufacturing a GaN semiconductor device according to another aspect of the present invention includes a) sequentially forming a spacer layer and a p-GaN epi layer on top of the active layer, and then forming the p-GaN epi layer, the spacer layer, and the active layer. forming a mesa structure by etching a portion, b) patterning the p-GaN epi layer to form a p-GaN gate in the shape of a planar track, and c) forming a source and drain of an ohmic junction structure. Then, forming an isolation around the mesa structure; d) forming a source field plate on the upper part of the region between the p-GaN gate and the drain, and forming a wiring pattern connecting the source field plate and the gate. May include steps.

In an embodiment of the present invention, the source and drain of the ohmic junction structure in step c) are manufactured by forming a source ion implantation layer and a drain ion implantation layer through ion implantation, and then forming the source ion implantation layer and the drain ion implantation layer. A source metal layer and a drain metal layer, which are ohmic metals, may be formed thereon.

In an embodiment of the present invention, the source ion implantation layer may be manufactured to be located outside the track-type p-GaN gate, and the drain ion implantation layer may be manufactured to be located inside the p-GaN gate.

In an embodiment of the present invention, in step c), the production of the isolation can be activated through high-energy ion implantation and heat treatment.

The present invention provides GaN power that can solve the problems of conventional semiconductor devices by using a 2DEG (Two Dimensional Electron Gas) channel with high carrier mobility in a semiconductor with a wide band gap (WBG) heterojunction structure. It has the effect of providing a semiconductor device structure and its manufacturing method.

In particular, the present invention can increase the breakdown voltage to several kV for the same size by using a semiconductor with a wide band gap, minimize the range of current fluctuation, and minimize the size of the device, making it possible to use the latest portable device. , It is advantageous to be mounted on wearable devices and has the effect of further increasing power efficiency, which can save energy and develop into eco-friendly electrical and electronic products.

1 is a plan view and equivalent circuit diagram of a conventional GaN semiconductor device.
2 to 7 are cross-sectional views showing the manufacturing process of a GaN semiconductor device according to a preferred embodiment of the present invention.
Figure 8 is a plan view of the GaN semiconductor device of the present invention.
Figure 9 is a partial cross-sectional view of the present invention.
Figure 10 is a plan layout diagram and equivalent circuit of a power device chip designed to manufacture the present invention.
11 to 13 are graphs comparing characteristics of the present invention and conventional GaN semiconductor devices.

Hereinafter, the structure and manufacturing method of the GaN semiconductor device of the present invention will be described in detail with reference to the attached drawings.

The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art, and the embodiments described below may be modified into various other forms, and the embodiments of the present invention may be modified. The scope is not limited to the examples below. Rather, these examples are provided to make the present invention more faithful and complete and to fully convey the spirit of the present invention to those skilled in the art.

The terms used herein are used to describe specific embodiments and are not intended to limit the invention. As used herein, the singular forms include the plural forms unless the context clearly indicates otherwise. Additionally, when used herein, “comprise” and/or “comprising” means specifying the presence of stated features, numbers, steps, operations, members, elements and/or groups thereof. and does not exclude the presence or addition of one or more other shapes, numbers, operations, members, elements and/or groups. As used herein, the term “and/or” includes any one and all combinations of one or more of the listed items.

Although terms such as first, second, etc. are used herein to describe various members, regions, and/or portions, it is obvious that these members, parts, regions, layers, and/or portions are not limited by these terms. . These terms do not imply any particular order, superiority or inferiority, or superiority or inferiority, and are used only to distinguish one member, region or portion from another member, region or portion. Accordingly, a first member, region or portion described below may refer to a second member, region or portion without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to drawings schematically showing embodiments of the present invention. In the drawings, variations of the depicted shape may be expected, for example, depending on manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be construed as being limited to the specific shape of the area shown in this specification, but should include, for example, changes in shape resulting from manufacturing.

2 to 7 are cross-sectional views showing the manufacturing process of a GaN semiconductor device according to a preferred embodiment of the present invention.

Referring to FIGS. 2 to 7 , first, a buffer layer 2 and an active layer 3 are grown on top of the semiconductor substrate 1 as shown in FIG. 2, and a spacer layer is grown on top of the active layer 3. (4) and the p-GaN epi layer (5) are grown sequentially.

The semiconductor substrate 1 may use known semiconductor wafers such as Si, sapphire, SiC, and AlN.

Next, when forming the undoped GaN layer, which is the active layer 3, stress is generated between the substrate and the epi layer due to differences in lattice constants and thermal expansion coefficients depending on the type of substrate 1. Due to this stress, the entire substrate is bent and, in severe cases, cracks occur. Therefore, the buffer layer 2 is grown during the epitaxial growth process to minimize problems caused by differences in lattice constant and thermal expansion coefficient.

The buffer layer 2 used at this time can be grown in a structure such as low-temperature GaN, Al _y Ga _1-y N, or GaN/Al _y Ga _1-y N superlattice layer, and can also be used as a composite multi-layer structure. can be manufactured.

Next, undoped-GaN is grown to form the active layer (3). The epitaxial growth of the active layer 3 and the buffer layer 2 for stress relief can utilize conventionally known epitaxial technology.

Subsequently, a spacer layer 4 of Al _x Ga _1-x N is continuously grown on top of the active layer 3. Here, _{the Al}

On top of the spacer layer 4, a p-GaN epi layer 5 doped with p-type impurities at 10 ¹⁷ to 10 ¹⁹ cm ^-3 is grown.

In the spacer layer 4 for forming 2DEG, the Al content (x) is controlled between 0.1 and 0.4, and the thickness is controlled between 10 and 40 nm to control the density and mobility of 2DEG, which is the channel layer of the carrier.

As a result, 2DEG is formed on the GaN side between GaN/Al _x Ga _1-x N, completing the HEMT epi structure for device fabrication.

In the present invention, the HEMT epistructure is grown to a level where the electron density of the 2DEG layer is >9x10 ¹² cm ^-2 and the mobility is >1900 cm ² /Vsec.

Next, as shown in FIG. 3, the p-GaN epitaxial layer 5 and a portion of the spacer layer 4 and active layer 3 below are etched to form a mesa pattern.

The etching used to form the mesa pattern is done using ICP (Inductive Coupled Plasma), which uses BCl ₃ and Cl ₂ as main reaction gases. The height of the mesa pattern should be 100 to 500 nm.

Next, as shown in FIG. 4, a PR (Photoresist) pattern is formed by optical photo transfer, and the p-GaN epi layer 5 is etched using this PR pattern to form a p-GaN gate 6. do.

Here, the photoresist pattern used as the etching mask uses a process commonly used in the semiconductor process called photophotographic transfer. In addition, optical photo transfer is also used in the manufacturing process steps below, and since it is not a technology specifically limited to the present invention but a type of common technology, no detailed explanation will be given regarding the photo photo transfer in the entire manufacturing process below.

Next, a source ion implantation layer 7 and a drain ion implantation layer 8 are formed as shown in FIG. 5.

The planar shape of the p-GaN gate 6 may be in the shape of a square window frame, and the source ion implantation layer 7 is implanted up to a portion of the active layer 3 below the circumferential side of the p-GaN gate 6. .

As will be explained later, the p-GaN gate 6 may have an overall oval shape with a portion of the square window frame in plan being round.

Additionally, the drain ion implantation layer is formed by implanting ions into a portion of the active layer 3 below the inner region of the p-GaN gate 6.

At this time, ion injection injects n-type ions.

In particular, Si ⁺ as an n-type impurity is ion implanted under low energy conditions of 10 to 30 keV.

Next, an insulating film (not shown) is deposited, and the ion-implanted Si dopant is activated by heat treatment at a high temperature of 900 to 1200°C for 1 to 5 minutes using passivation of the insulating film.

The insulating film uses a dielectric thin film of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), and the thickness is adjusted to 30-200 nm. The insulating film stabilizes the surface, eliminates the current collapse phenomenon, and keeps the characteristics of Schottky contact constant.

The unstable state of the wide bandgap (WBG) semiconductor surface causes its electrical properties to change during operation, so passivation of the interface and surface and passivation by thin film deposition are important for manufacturing stable devices.

Atomic bonds or traps present on the surface of a semiconductor create a shape that captures or releases carriers depending on the voltage applied to the semiconductor, resulting in a change in the current density flowing through the device.

The surface can be stabilized through the above heat treatment.

Next, an insulating layer is deposited, a pattern is formed by optical photo transfer, and then a window exposing the top of the source ion implantation layer 7 and the drain ion implantation layer 8 is formed through etching.

To solve the problem of defects being created by plasma in the ohmic contact area when forming a window, a combination of ICP (Inductive Coupled Plasma) dry etching and wet etching can be used.

Next, a metal layer is deposited and etched to form a source metal layer 9 located on top of the source ion implantation layer 7 and a drain metal layer 10 located on top of the drain ion implantation layer 8.

The source metal layer 9 is in ohmic contact with the source ion implantation layer 7, and similarly, the drain metal layer 10 is in ohmic contact with the drain ion implantation layer 8.

Use a single layer of Ti, Ni, Al, Pt, Pd, Mo, Ta or Au as the metal for ohmic contact, or two or more composite layers such as Ti/TiN, Ti/Ni/Ti/Al, Ti/Au/TiN can be used.

After forming the source metal layer 9 and the drain metal layer 10, they are rapidly heat treated at a high temperature of 400 to 900 ^o C for 1 to 5 min to form an ohmic contact with low resistance.

When using a metal such as Au for ohmic, a lift-off process can be used, unlike the above process.

When using a lift-off process, lithography must be performed to form a PR pattern for lift-off, an ohmic metal is deposited, and the deposited ohmic metal is lifted off with a solvent solution.

The reason for using ohmic junction is to reduce the contact resistance in order to minimize the heat generated when a constant current flows, and also to ensure stable operation of the device from electrical and thermal shock, it is preferable to use an electromagnetic junction with low contact resistance and a physically stable electromagnetic junction. This is because metal bonding that is resistant to migration (electro-migration) is important.

Next, as shown in FIG. 6, high-energy ions are locally injected along the perimeter of the mesa structure to form isolation 11.

^{More specifically , isolation ( _ _} 11) is formed.

After ion implantation, heat treatment is performed at a temperature of 400 to 800 ^o C to stabilize the hardness and trap, which are unstable at low temperatures.

Next, as shown in FIG. 7, a multi-layer insulating layer (not shown) is formed and patterned to form a wiring pattern 12 connected to each of the source metal layer 9 and the drain metal layer 10, as well as wiring A source field plate 13 located in the lower part of the pattern 12 is formed.

The wiring pattern 12 and the source field plate 13 can be manufactured through known metal bonding and wiring steps. For example, a SiO ₂ oxide film is deposited, a pattern is formed by optical photo transfer, and a tungsten plug (W-plug) is formed in the contact window for the wiring pattern using a CMP (Chemical Mechanical Polishing) process by etching. Afterwards, a metal thin film with a thickness of 2 to 6 μm is deposited to create a pattern and etched to form the wiring pattern 12 and the source field plate 13.

The source field plate 13 is located only at the bottom of the wiring pattern 12 connected to the source metal layer 9.

The wiring pattern 12 connected to the source metal layer 9 has a structure extending beyond the top of the p-GaN gate 6 toward the drain metal layer 10, and the source field plate 13 is connected to the p-GaN gate 6. It is assumed to be located in the area between and the drain metal layer 10.

The metal material for forming the wiring pattern 12 and the source field plate 13 may have a single-layer or multi-layer structure of various structures such as Al, Ti/Al, Ni/Au, and Ti/Al/Ni/Au. You can.

At this time, a method of forming a pattern by etching or a lift-off process technique can be used.

FIG. 8 is a plan view of the GaN semiconductor device of the present invention, and FIG. 9 is a cross-sectional view showing the A-A cross section and the B-B cross section in FIG. 8.

As shown in FIGS. 8 and 9, respectively, the p-GaN gate 6 is formed in a track structure (track of an athletics stadium) with rounded corners, and the source field plate 13 is formed on the p-GaN gate 6. and the drain metal layer 10.

Therefore, when a high voltage is applied to the drain metal layer 10, a constant and uniform electric field can be maintained by the source field plate 13 and the track-shaped p-GaN gate 6.

In addition, in the present invention, isolation 11 is formed at both ends of the round of the p-GaN gate 6, thereby restricting the drain current to the inner region of the track-type p-GaN gate 6.

Therefore, stray current that may occur at the edges of both ends of the p-GaN gate 6 is almost eliminated.

In addition, isolation 11 is formed around the mesa structure, so insulation performance can be improved.

Figure 10 is a plan layout diagram and equivalent circuit of a power device chip designed to manufacture the present invention.

Referring to FIG. 10, the threshold voltage of the gate is adjusted by connecting one or more Schottky diodes in series to the gate.

A pn diode is placed between the gate and source to protect the gate electrode from high voltage ESD.

The PN diode is placed in the lower area of the source pad to match the manufacturing process of the FET device and is adjusted to minimize the chip area.

Figure 11 is a graph comparing I-V characteristics of the present invention and a conventional GaN semiconductor device.

Referring to FIG. 11, it can be seen that the drain current of a conventional GaN semiconductor device gradually increases even though it is in a saturation operating region where a certain voltage or more is applied.

This can be interpreted as being caused by the modulation of the gate voltage and the stray current component, and is disadvantageous in improving linearity and reliability in circuit applications.

In contrast, in the GaN semiconductor device according to the present invention, the stray current is reduced and the linearity of the drain current in the saturation region is improved, thereby reducing current crowding and increasing the breakdown voltage.

With these improved IV characteristics, the GaN semiconductor device according to the present invention has excellent linearity, greatly improving stability for long-term operation or operation at high temperatures.

Figure 12 is a graph comparing the transconductance with respect to gate bias of the present invention and a conventional GaN semiconductor device.

The GaN semiconductor device according to the present invention operates in a direction in which the threshold voltage increases as the gate bias increases due to the Schottky diode disposed on the gate.

In contrast, the threshold voltage of conventional GaN semiconductor devices does not change.

This means that in the present invention, the maximum peak value (Gm,max) is reduced by the Schottky junction added to the gate, but the width of the device driving voltage is expanded by increasing the driving voltage of the gate.

Therefore, the present invention increases convenience, efficiency, and stability in circuit design.

The metal material of the Schottky gate, which is formed by metal bonding to a GaN semiconductor device, uses a multilayer structure of Ni, Pd, W, Ti, Pt, Mo, or a combination of one or more thereof. As the metal materials that make up the Schottky gate each have different work functions, they can be manufactured to generate a voltage difference of about 0.5 to 0.7 V in one Schottky diode depending on their type and combination.

Figure 13 is a graph comparing the ESD performance of the present invention and a conventional GaN semiconductor device.

ESD performance is TLP (Transmission Line Pulse) measurement data at the gate stage of each GaN semiconductor device, and the ESD I-V performance of the device can be confirmed.

In the case of conventional GaN semiconductor devices, Vt (triggering voltage) and Ipp (peak pulse current) are small and show weak characteristics against ESD.

However, in the case of the GaN semiconductor device of the present invention, the dynamic resistance (Rd) is greatly reduced and Ipp is greatly increased, resulting in strong ESD resistance.

This is because it has a larger threshold voltage than the conventional threshold voltage due to a bypass effect caused by the PN diode placed between the source and gate, and ESD can be quickly resolved.

Therefore, the value of dynamic on-resistance (Ron,ta) according to the present invention can be greatly reduced compared to the dynamic on-resistance (Ron,pa) according to the conventional technology. This reduced dynamic on-resistance increases Ipp and reduces Vhold (holding voltage), ultimately increasing ESD resistance.

In this way, the present invention with enhanced ESD resistance satisfies the HBM (Human Body Model) level of 8kV. Through the integration of these additional devices, it is possible to ensure the operation of GaN devices that meet the specifications of AEC Q101 and can be used in consumer products as well as industrial products such as automobiles.

It is obvious to those skilled in the art that the present invention is not limited to the above-mentioned embodiments and can be implemented with various modifications and variations without departing from the technical gist of the present invention. will be.

1: Semiconductor substrate 2: Buffer layer
3: Active layer 4: Spacer layer
5:p-GaN epi layer 6:p-GaN gate
7: Source ion implantation layer 8: Drain ion implantation layer
9: Source metal layer 10: Drain metal layer
11: Isolation 12: Wiring pattern
13: Source field plate

Claims (7)

A mesa structure including a spacer layer located on top of the active layer;
a p-GaN gate in the form of a planar track disposed on an upper portion of the spacer layer having a mesa structure;
a source metal layer located outside the p-GaN gate;
A drain metal layer located inside the p-GaN gate;
Isolation formed around the mesa structure by ion implantation; and
A GaN semiconductor device including a source field plate located on an upper side of a region between the p-GaN gate and the drain metal layer. According to paragraph 1,
A source ion implantation layer and a drain ion implantation layer are located below each of the source metal layer and the drain metal layer,
A GaN semiconductor device in which the source ion implantation layer, source metal layer, drain ion implantation layer, and drain metal layer each form ohmic contact. According to paragraph 1,
A GaN semiconductor device characterized in that a Schottky diode is connected in series to the p-GaN gate. a) sequentially forming a spacer layer and a p-GaN epi layer on top of the active layer, then etching a portion of the p-GaN epi layer, spacer layer, and active layer to form a mesa structure;
b) patterning the p-GaN epitaxial layer to form a p-GaN gate in a planar track shape;
c) forming an isolation around the mesa structure after forming the source and drain of the ohmic junction structure; and
d) A GaN semiconductor device manufacturing method comprising forming a source field plate on an upper part of a region between the p-GaN gate and the drain, and forming a wiring pattern connecting the source field plate and the gate. According to clause 4,
The source and drain fabrication of the ohmic junction structure in step c) includes,
After forming a source ion implantation layer and a drain ion implantation layer through ion implantation,
A method of manufacturing a GaN semiconductor device, characterized in that forming a source metal layer and a drain metal layer of an ohmic metal on the source ion implantation layer and the drain ion implantation layer. According to clause 5,
The source ion implantation layer is located outside the track-type p-GaN gate,
A GaN semiconductor device manufacturing method, characterized in that the drain ion implantation layer is manufactured to be located inside the p-GaN gate. According to clause 4,
In step c) above,
Manufacturing of the isolation is,
A GaN semiconductor device manufacturing method characterized by activation through high-energy ion implantation and heat treatment.

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