KR20240010042A - Data access methods, devices, and non-transitory computer-readable storage media - Google Patents

Abstract

The present invention provides a data access method, apparatus, and non-transitory computer-readable storage medium, wherein the method comprises obtaining a plurality of instructions to be processed, wherein each instruction to be processed includes an address to be accessed. , determining an instruction to be merged among the plurality of instructions to be processed, obtaining a merge instruction by merging the instructions to be merged, and performing data access according to an access address corresponding to the merge instruction. Thus, the overhead of the command can be reduced, command processing efficiency can be improved, and the performance of the electronic device can be effectively improved.

Description

Data access methods, devices, and non-transitory computer-readable storage media

The present invention relates to the field of electronic device technology, and more particularly to data access methods, devices, and non-transitory computer-readable storage media.

<Cross-citation of related applications>

The present invention is filed based on a Chinese patent application with application number 202111543913.4 and application date 2021/12/16, and claims priority of the Chinese patent application. All contents of the Chinese patent application are hereby incorporated by reference in the present invention. It is brought in.

As technology develops, memories (eg, Nand flash) based on the Joint Electron Device Engineering Council (JEDEC) protocol are widely applied to electronic devices such as mobile terminals.

Currently, after generating an instruction to be processed in a process on an electronic device, the instruction to be processed is sent to a memory based on the JEDEC protocol, and the instruction to be processed is processed in the memory, that is, to the address to be accessed of the instruction to be processed. Access, i.e. read and write data.

However, when the number of instructions to be processed is multiple, it is necessary to transmit the instructions to be processed one by one to the corresponding memory, resulting in an increase in instruction overhead, and the memory can only process the instructions to be processed one by one, thus improving the efficiency of instruction processing. deteriorates and affects the performance of electronic devices.

In view of this, the present invention provides a data access method, device, and non-transitory computer-readable storage medium that can efficiently improve the performance of electronic devices.

According to a first aspect of an embodiment of the present invention, there is provided a data access method applied to an electronic device, the method comprising:

acquiring a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed;

determining an instruction to be merged among the plurality of instructions to be processed, merging the instructions to be merged, and obtaining a merge instruction; and

and performing data access according to the access scheduled address corresponding to the merge command.

Optionally, the step of determining an instruction to be merged among the plurality of instructions to be processed includes:

Obtaining a first instruction, wherein the first instruction is one of the instructions to be processed,

A second instruction is acquired by traversing an instruction to be processed other than the first instruction, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly consecutive, and the access scheduled address of the second instruction is A step in which the address is not consecutive with the access scheduled address of the first instruction through the access scheduled address of another instruction to be processed, and

In response to the second instruction and the first instruction meeting the first predetermined merging condition, determining the second instruction and the first instruction to be the instruction to be merged.

Optionally, in response to the second instruction and the first instruction meeting a first predetermined merge condition, determining the second instruction and the first instruction as instructions to be merged comprises:

At least one of obtaining a storage interval and obtaining a currently accessed total data amount, wherein the storage interval represents a distance between the access scheduled address of the first instruction and the access scheduled address of the second instruction, A step where the current access total data amount represents the sum of the access scheduled data amounts corresponding to all merge scheduled instructions, and

If the storage interval is at least one of the first predetermined threshold and the current access total data amount is less than the second predetermined threshold, the second instruction and the first instruction are merged into the instruction to be merged. It includes a decision step.

Optionally, the method:

If the current access total data amount is greater than or equal to the second predetermined threshold, stopping traversing of instructions to be processed other than the first instruction.

Optionally, the method:

Obtaining a first duration, obtaining a first time threshold corresponding to the first instruction, the first duration representing the duration starting from the determination of acquisition of the first instruction to the current time;

In response to the first duration being less than a first time threshold, continuing to traverse instructions scheduled to be processed other than the first instruction, and

In response to the first duration being greater than or equal to the first time threshold, stopping traversing of instructions to be processed other than the first instruction.

Optionally, the method:

Obtaining a difference value between the scheduled access address of the second instruction and the scheduled access address of the first instruction, wherein the scheduled access address is a logical address,

obtaining the size of a predetermined storage unit, and

It further includes obtaining the storage interval according to the difference value and the size of the predetermined storage unit.

Optionally, the method:

Obtaining a first instruction, wherein the first instruction is one of the instructions to be processed,

Traversing instructions to be processed other than the first instruction, and

In response to the currently traversing to-be-processed instruction and the first instruction meeting a second predetermined merging condition, determining the currently traversing to-be-processed instruction and the first instruction to be the merging instruction. Includes.

Optionally, the method:

Storing the command to be processed in a predetermined command queue,

In the predetermined command queue,

A second duration corresponding to the instruction to be processed is greater than a second time threshold, and the second duration represents a storage duration of the instruction to be processed in the predetermined instruction queue, and

A step of setting, as the first instruction, an instruction to be processed that satisfies at least one condition: the instruction to be processed is located at a set position in a predetermined instruction queue, and the set position is a head position of the queue or a tail position of the queue. It further includes.

Optionally, the step of acquiring a merge instruction by merging the plurality of instructions to be merged includes:

It includes generating a merge processing result according to the access address of each scheduled merge instruction, encapsulating the merge processing result in a set instruction format, and obtaining the merge instruction.

Optionally, the method:

acquiring the access scheduled data amount corresponding to each of the merge scheduled instructions, and

It further includes adding the amount of data to be accessed corresponding to each of the commands to be merged to the merge processing result.

According to a second aspect of an embodiment of the present invention, there is provided a data access device applied to an electronic device, the device comprising a command acquisition module, a command merging module, and a command transmission module;

The instruction acquisition module is configured to acquire a plurality of instructions to be processed, each of the instructions to be processed includes an address to be accessed,

The instruction merge module is configured to determine an instruction to be merged among the plurality of instructions to be processed, and obtain a merge instruction by merging the instructions to be merged,

The command transmission module is configured to perform data access according to the access scheduled address corresponding to the merge command.

Optionally, the instruction merge module specifically

Obtain a first instruction, wherein the first instruction is one of the instructions to be processed,

A second instruction is acquired by traversing an instruction to be processed other than the first instruction, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly consecutive, and the access scheduled address of the second instruction is The address is not continuous with the access address of the first instruction through the access address of another instruction to be processed,

In response to the second instruction and the first instruction meeting the first predetermined merging condition, determine the second instruction and the first instruction as the instruction to be merged.

Optionally, the instruction merge module also:

At least one of obtaining a storage interval and obtaining a currently accessed total data amount, wherein the storage interval represents the distance between the access scheduled address of the first instruction and the access scheduled address of the second instruction. , where the current access total data amount represents the sum of the access scheduled data amounts corresponding to all merge scheduled instructions,

If the storage interval is at least one of the first predetermined threshold and the current access total data amount is less than the second predetermined threshold, the second instruction and the first instruction are merged into the instruction to be merged. It is configured to decide.

Optionally, the instruction merge module also:

and stop traversing of instructions to be processed other than the first instruction when the current access total data amount is greater than or equal to the second predetermined threshold.

Optionally, the instruction merge module also:

Obtain a first duration, obtain a first time threshold corresponding to the first instruction, wherein the first duration represents the duration starting from the determination of acquisition of the first instruction to the current time, and

In response to the first duration being less than a first time threshold, continue traversing instructions to be processed other than the first instruction;

In response to the first duration being greater than or equal to the first time threshold, stop traversing instructions to be processed other than the first instruction.

Optionally, the instruction merge module also:

Obtain a difference value between the access scheduled address of the second instruction and the access scheduled address of the first instruction, and the access scheduled address is a logical address,

Obtain the size of a predetermined storage unit,

and obtain the storage interval according to the difference value and the size of the predetermined storage unit.

Optionally, the instruction merge module specifically

Obtain a first instruction, wherein the first instruction is one of the instructions to be processed,

Traversing instructions to be processed other than the first instruction,

In response to the currently traversed instruction to be processed and the first instruction meeting a second predetermined merging condition, determine the currently traversed instruction to be processed and the first instruction to be the instruction to be merged.

Optionally, the instruction merge module also:

Storing the command to be processed in a predetermined command queue,

In the predetermined command queue

A second duration corresponding to the instruction to be processed is greater than a second time threshold, and the second duration represents a storage duration of the instruction to be processed in the predetermined instruction queue, and

The instruction to be processed is located at a set position in a predetermined instruction queue, and the set position is the head position of the queue or the tail position of the queue, so that the instruction to be processed that satisfies at least one condition is used as the first instruction. It is composed.

Optionally, the instruction merge module specifically:

It is configured to generate a merge processing result according to the access address of each scheduled merge instruction, encapsulate the merge processing result in a set instruction format, and obtain the merge instruction.

Optionally, the instruction merge module also:

Obtaining the access scheduled data amount corresponding to each of the merge scheduled instructions, respectively,

It is configured to add the amount of data to be accessed corresponding to each of the commands to be merged to the merge processing result.

According to a third aspect of the embodiment of the present invention, there is provided a temporary computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the data access method described in any of the first aspects.

According to a fourth aspect of an embodiment of the present invention, there is provided a data access device including a processor and a memory for storing instructions executable by the processor,

The processor,

Acquire a plurality of instructions to be processed, each of the instructions to be processed includes an address to be accessed,

Determining an instruction to be merged among the plurality of instructions to be processed, merging the instructions to be merged to obtain a merge instruction,

Data access is performed according to the access scheduled address corresponding to the merge command.

According to a fifth aspect of the embodiments of the present invention, there is provided a computer program product comprising a computer program that, when executed by a processor, implements the steps of the data access method described in any of the first aspects above.

The technical solutions provided by the embodiments of the present invention can realize the following beneficial effects. When obtaining a plurality of instructions to be processed, an instruction to be merged is determined among the plurality of instructions to be processed, that is, at least two instructions to be merged are determined, the determined instructions to be merged are merged, a merge instruction is obtained, and the instructions of the instruction are determined. By reducing the number, the overhead of instructions can be reduced accordingly. By performing data access according to the access scheduled address corresponding to the merge instruction, multiple access scheduled addresses can be accessed based on one instruction, that is, multiple instructions to be processed can be processed simultaneously, thereby improving the efficiency of instruction processing. can be improved, and thus the performance of electronic devices can be effectively improved.

It should be understood that the above general description and the following detailed description are merely illustrative and interpretive and do not limit the present invention.

The accompanying drawings, which are included in and constitute a part of this specification, illustrate embodiments consistent with the subject matter of the invention and, together with the specification, serve to explain the principles of the invention.
1 is a schematic diagram showing the location layout of a file according to an embodiment of the present invention.
Figure 2 is a flowchart of a data access method according to an embodiment of the present invention.
Figure 3 is a schematic diagram of a sequential read and write process according to an embodiment of the present invention.
Figure 4 is a flowchart of another data access method according to an embodiment of the present invention.
Figure 5 is a schematic diagram of a random read and write process according to an embodiment of the present invention.
Figure 6 is a schematic diagram of another random read and write process according to an embodiment of the present invention.
Figure 7 is a block diagram of a data access device according to an embodiment of the present invention.
Figure 8 is a configuration diagram of a data access device according to an embodiment of the present invention.

Herein, exemplary embodiments shown in the drawings will be described in detail. Where the following description relates to drawings, unless otherwise noted, the same numbers in different drawings indicate the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of devices and methods consistent with some aspects of the invention as set forth in detail in the appended claims.

The terms used in the present invention are intended to describe specific embodiments and are not intended to limit the present invention. As used in this invention and the appended claims, the singular forms "a", "the" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. As used herein, the term “and/or” should be understood to mean and include any or all possible combinations of one or more associated listed items.

In the present invention, terms such as first, second, third, etc. may be used to describe various information, but please understand that such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present invention, the first information may be called second information, and similarly, the second information may be called first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to a decision."

In the prior art, after obtaining the instruction to be processed generated in the process on the electronic device, the instruction to be processed is transmitted to a memory based on the JEDEC protocol, and the instruction to be processed is processed in the memory, that is, the instruction to be processed is scheduled to be accessed. Performs access to an address.

Here, the memory based on the JEDEC protocol, that is, the memory chip, is accessed block by block. As shown in Figure 1, the storage unit of data in the file system of an electronic device (e.g., F2FS (Flash) Friendly File System) is 4KB, the size of file 1 is 24KB, and the data in file 1 is stored in LBA 1. It can be placed at the location of ~LBA 6 and addresses 1~6, respectively.

Optionally, Nand flash memory based on the JEDEC protocol includes an Embedded Multi Media Card (EMMC) storage chip and a Universal Flash Storage (UFS) storage chip.

However, when the number of instructions to be processed is multiple, it is necessary to transmit the instructions to be processed one by one to memory based on the JEDEC protocol, which increases instruction overhead, that is, the resources required to transmit related instructions to memory increase, and JEDEC Protocol-based memory can only process commands to be processed one by one, reducing the efficiency of command processing and affecting the performance of electronic devices.

Therefore, in response to the above-described problem, the embodiment of the present invention proposes a data access method to acquire a plurality of instructions to be processed and then merge the instructions to be processed to obtain a merge instruction including the access address of the plurality of instructions to be processed. I'm doing it. By transmitting merge instructions to memory based on the JEDEC protocol, instruction overhead is reduced. The memory based on the corresponding JEDEC protocol is accessed according to a plurality of access scheduled addresses in the merge instruction, realizing simultaneous processing of instructions to be processed, improving the efficiency of instruction processing, and thereby improving the performance of the electronic device, that is, Improves IO (Input/Output) performance of the entire system.

As shown in Figure 2, Figure 2 is a flowchart of a data access method in an exemplary embodiment of the present invention, the method is applied to an electronic device, and specifically applied to a processor of the electronic device, the method is as follows: Includes steps.

Step S201, obtain a plurality of instructions to be processed. Here, each instruction to be processed includes an address to be accessed.

Step S202, an instruction to be merged is determined among a plurality of instructions to be processed, and the instructions to be merged are merged to obtain the merge instruction.

In an embodiment of the present invention, the electronic device supports multitasking parallel processing, and during execution, each process of the electronic device simultaneously generates read and write operation requests for various data, that is, instructions to be processed. After obtaining a plurality of instructions to be processed, that is, a plurality of instructions to be processed, a command to be processed that can be merged is determined from the plurality of instructions to be processed, that is, at least two instructions to be processed are set to an instruction to be merged, and merged. The scheduled instructions are merged, that is, a plurality of instructions are merged into one instruction, and the merged instruction is called a merge instruction. The merge instruction includes a plurality of access scheduled addresses, and the plurality of access scheduled addresses are each Contains the access address of the instruction to be merged.

Here, the instruction to be processed includes a scheduled access address, that is, there is a scheduled access address corresponding to each instruction to be processed. The access scheduled address represents the data address that needs to be accessed, that is, the address that requires reading and writing data.

Optionally, the address to be accessed is a logical address.

Step S203, data access is performed according to the access scheduled address corresponding to the merge instruction.

In this embodiment, data access is performed according to the access address of each instruction to be merged among the merge instructions, that is, the access address of each instruction to be merged is accessed to perform corresponding data read and write operations. By doing so, it is possible to access the access addresses of multiple instructions to be processed using a single instruction, and simultaneous processing of instructions can be realized without the need to access multiple access addresses based on multiple instructions, allowing data access. improves efficiency.

Optionally, when performing data access based on a merge instruction, the data access may be performed using memory, that is, by transmitting the merge instruction to the target memory, the target memory may be configured to access the scheduled access of each instruction to be merged among the merge instructions. Data access can be performed based on the address.

Specifically, after obtaining the merge command, the merge command is transmitted to the target memory. The target memory executes the merge instruction, that is, interprets the merge instruction, obtains a plurality of access scheduled addresses in the merge instruction, accesses the plurality of access scheduled addresses in the merge instruction, and performs read and write operations of the corresponding data. By performing this, the efficiency of instruction processing is improved and the concurrent processing capacity of the target memory is sufficiently utilized to improve the concurrency of the target memory.

Here, the target memory includes memory based on the JEDEC protocol, for example, Nand flash. Specifically, the target memories include EMMC (Embedded Multi Media Card) memory chips and UFS (Universal Flash Storage) memory chips.

Optionally, the electronic device includes products that include target memory, such as mobile terminals (eg, cell phones, tablet computers, etc.), terminal devices (eg, computers, servers), etc.

The access method to the target memory includes random access (i.e. random read and write), where random read and write means discrete random address access to the memory. For example, if the target memory is Nand flash memory, after obtaining the instructions to be processed generated by the process, the instructions to be processed are cached. If the access address of the cached instruction to be processed is not a contiguous address, it indicates that access is required by the random access method, and in multi-instruction mode, that is, each instruction to be processed is sent to Nand flash memory, that is, Nand flash. Each access to memory increases the overhead of instructions, and since Nand flash memory can only process one instruction to be processed each time, the simultaneous processing capacity of Nand flash memory cannot be fully utilized, which reduces the throughput of random access in the system. affects. For example, as shown in FIG. 3, process A generates instruction 1 whose intended access address is address 1 (i.e., address 1 in FIG. 1). Process B generates instruction 2 whose intended access address is address 3 (i.e., address 3 in FIG. 1). Process C generates instruction 3 whose intended access address is address 5 (i.e., address 5 in FIG. 1). Processes A, B, and C access data in logical addresses 1, 3, and 5 of file 1 in Figure 1. Since address 1, address 3, and address 5 are not consecutive, they cannot be merged, and command 1, command 2, and command 3 must be transmitted respectively to the Nand flash memory. In the present invention, by performing merge processing on instructions to be processed whose access addresses are not consecutive, one instruction is obtained by merging a plurality of instructions to be processed, that is, the overhead of the instruction is reduced by obtaining a merge instruction. By sending the merge command to the Nand flash memory, the Nand flash memory can access multiple access addresses at once, improving the efficiency of command processing.

From the above description, when obtaining a plurality of instructions to be processed, an instruction to be merged among the plurality of instructions to be processed is determined, that is, at least two instructions to be merged are determined, the determined instructions to be merged are merged, and the merge instruction is You can reduce the number of instructions and reduce instruction overhead. By performing data access according to the access address corresponding to the merge instruction and accessing the access address of multiple instructions to be processed based on one instruction, simultaneous processing of instructions is realized, improving the efficiency of instruction processing. and thereby effectively improve the performance of electronic devices.

As shown in Figure 4, Figure 4 is a flow diagram illustrating another data access method in one embodiment of the present invention. When performing random access based on the embodiment of FIG. 2, discontinuous instructions of the access scheduled address can be merged as shown in FIG. 4. The process will be described in relation to the specific embodiment below, The method includes the following steps:

Step S401, obtain a plurality of instructions to be processed. Here, each instruction to be processed includes an address to be accessed.

Step S402, obtain the first instruction. Here, the first command is one of the commands to be processed.

In an embodiment of the present invention, one instruction to be processed is selected from the acquired instructions to be processed, and the selected instruction to be processed is set as the first instruction.

Optionally, in order to improve the efficiency of data access, after obtaining the instructions to be processed, the instructions to be processed can be stored in a predetermined instruction queue, so that instruction caching can be performed and merging of instructions to be processed can be facilitated. . One instruction to be processed is selected as the first instruction from a predetermined instruction queue storing instructions to be processed, that is, the first instruction is determined. Here, the process of determining the first command is, specifically, storing the command to be processed in a predetermined command queue. An instruction to be processed that satisfies at least one of the following conditions among the predetermined instruction queue is set as the first instruction. The second duration corresponding to the instruction scheduled to be processed is greater than the second time threshold. Here, the second duration represents the storage duration of the command to be processed in a predetermined command queue. The command to be processed is located at a set position in a predetermined command queue. Here, the setting position is the head position of the cue or the tail position of the cue.

Here, instructions to be processed in a predetermined instruction queue may be arranged based on a predetermined address sorting rule. Predetermined address sorting rules include an address sorting rule from large to small (i.e., the accessed addresses of instructions scheduled to be accessed in a given instruction queue are sorted from large to small), and an address sorting rule from small to large. Rules (i.e., the access scheduled addresses of the access scheduled instructions in a predetermined instruction queue are sorted from small to large), etc. are included.

Optionally, if the number of instructions to be processed that satisfies the condition is plural, the instruction to be processed with the longest second duration may be set as the first instruction, and the second duration is stored in a predetermined instruction queue of the instruction to be processed. Indicates duration. Here, the logical addresses are named sequentially. For example, there are 1000 storage blocks in the target memory, and the 1000 memory blocks are named based on 1 to 1000, and the corresponding logical addresses are 1 to 1000. Since the accessed address is a logical address, the accessed address can be sorted according to the size of the accessed address, and the instructions to be processed can be sorted according to the order of the accessed address.

Optionally, the setting location may be another location, but is not limited here.

Optionally, the condition for determining the first instruction from a predetermined instruction queue may include other conditions, for example, the second duration corresponding to the instruction to be processed is the longest, that is, the storage time is the longest among the predetermined instruction queues. The instruction to be processed may be referred to as the first instruction.

Optionally, after obtaining the instruction to be processed, first perform related processing on the instruction to be processed (e.g., determine whether the instruction format is standardized, determine whether memory is congested, etc.), and then store the processed instruction to be processed in a predetermined format. It can be stored in the command queue.

Step S403, instructions to be processed other than the first instruction are traversed to obtain the second instruction. Here, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly consecutive, and the access scheduled address of the second instruction is connected to the access scheduled address of the first instruction through the access scheduled address of another instruction to be processed. It is not continuous.

In an embodiment of the present invention, instructions to be processed other than the first instruction in a predetermined instruction queue are traversed to determine whether there is a second instruction whose address corresponding to the first instruction is not consecutive among the instructions to be processed other than the first instruction. By determining, when it is determined that the second instruction exists, the instruction to be merged is determined based on the second instruction, that is, the first instruction and the second instruction are determined to be the instruction to be merged. For example, the first instruction is an instruction at the head of the queue in a given instruction queue, and by traversing instructions at other positions in the given instruction queue, the first instruction is issued to an instruction at another position in the given instruction queue. 2 Determine whether the command exists.

Here, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly consecutive, and the access scheduled address of the second instruction is connected to the access scheduled address of the first instruction through the access scheduled address of another instruction to be processed. It is not continuous.

Here, indirect continuation indicates that the access scheduled address of the second instruction is continuous with the access scheduled address of the first instruction through another logical address, that is, the access scheduled address of the second instruction is continuous with the access scheduled address of the first instruction. It doesn't work. For example, the scheduled access address of the instruction to be processed that is currently traversed is 4, the scheduled access address of the first instruction is 1, and the scheduled access address of the instruction to be processed that is currently traversed is another logical address (i.e., logical address 2). and 3), if it is necessary to be continuous with the access scheduled address of the first instruction, it is determined that the access scheduled address of the currently traversed instruction to be processed and the access scheduled address of the first instruction are indirectly continuous.

Here, if the scheduled access address of the instruction to be processed currently traversing is 2 and the scheduled access address of the first instruction is 1, the scheduled access address of the instruction to be processed currently traversed and the scheduled access address of the first instruction are consecutive. Decide that it will work.

In an embodiment of the present invention, in the process of traversing an instruction to be processed other than the first instruction, it is determined whether the access scheduled address of the currently traversed instruction to be processed and the scheduled access address of the first instruction are indirectly continuous, If the access scheduled address of the currently traversed instruction to be processed and the access scheduled address of the first instruction are not indirectly contiguous, the access scheduled address of the currently traversed instruction to be processed and the scheduled access address of the first instruction are contiguous. indicates that the instruction to be processed that is currently traversed is a sequential access instruction corresponding to the first instruction, that is, it is determined that it is not the second instruction. If the access address of the currently traversed instruction to be processed and the access address of the first instruction are indirectly consecutive, the access address of the currently traversed instruction to be processed is accessed through the access address of the other instruction to be processed. 1 Determine whether the access address of the instruction is continuous, and if the access address of the instruction to be currently traversed is contiguous with the access address of the first instruction through the access address of another instruction to be processed, the current traverse If it is determined that the instruction to be processed is not a second instruction, and the access address of the instruction to be currently traversed is not continuous with the address to be accessed of the first instruction through the access address of the instruction to be processed, the instruction to be processed is currently traversed. It is determined that the instruction to be processed that is traversed is the second instruction. For example, instructions to be processed include instruction 1, instruction 2, and instruction 3. The scheduled access address of instruction 1 is 1, the scheduled access address of instruction 2 is 2, and the scheduled access address of instruction 3 is 3. Instruction 3 is the currently traversed instruction to be processed, and instruction 1 is the first instruction. It is determined that the access address of instruction 3 and the access address of instruction 1 are not contiguous, that is, indirectly contiguous, and the access address of instruction 3 is determined to be the access address of instruction 1 through the access address of another instruction to be processed. Continue to decide whether to continue. Since the access address of instruction 3 is continuous with the access address of instruction 1 through the access address of instruction 2, it is determined that instruction 3 is not the second instruction.

Optionally, when the instructions to be processed are arranged according to a predetermined address alignment rule, in the process of traversing the instructions to be processed other than the first instruction, the access address of the instruction to be processed that is currently traversed and the access of the first instruction Determine whether the scheduled addresses are consecutive, and if the access scheduled address of the instruction to be processed that is currently traversed and the scheduled access address of the first instruction are consecutive, the instruction to be processed that is currently traversed is sequentially corresponding to the first instruction. If it is determined that it is an access instruction, that is, not a second instruction, and the access scheduled address of the currently traversed instruction to be processed is not contiguous with the access scheduled address of the first instruction, the access scheduled corresponding to the currently traversed instruction to be processed is not consecutive. It continues to determine whether the address and the access address of the instruction to be processed that were traversed immediately before are contiguous. If the access address corresponding to the currently traversed instruction to be processed and the access address of the instruction to be processed immediately traversed are consecutive, the access address of the instruction to be processed immediately traversed is the access address of the first instruction. If the access scheduled address of the sequential or traversed instruction to be processed is continuous with the access address of the first instruction, the currently traversed instruction to be processed is a sequential access data instruction corresponding to the first instruction, and the second instruction is If it is determined that no, and the access scheduled address corresponding to the currently traversed instruction to be processed and the processing address scheduled to be traversed immediately before are not consecutive, it is determined that the currently traversed instruction to be processed is the second instruction.

Optionally, the access method corresponding to the target memory also includes sequential access (ie, sequential read and write). Here, sequential access refers to sequential address access to memory, and random read and write refers to discrete random address access to memory. If it is determined that none of the instructions scheduled to be processed other than the first instruction in the predetermined instruction queue is the second instruction, it indicates that the instructions scheduled to be processed other than that are all sequential access instructions of the first instruction, that is, the instructions scheduled to be processed other than that are scheduled to be processed. It indicates that the access scheduled address of the instruction and the access scheduled address of the first instruction are sequentially accessible, and according to the sequential access rule, the instruction to be processed where the corresponding first instruction and the scheduled access address and the scheduled access address of the first instruction are consecutive are merged. Using the scheduled instructions, the instructions scheduled to be merged are merged to obtain a merge instruction. Data access is performed according to the access address of each instruction to be merged in the merge instruction.

Here, sequential access rules can be defined based on actual demand, and for example, all or some instructions to be processed other than the first instruction can be made into instructions to be merged.

Specifically, to improve the efficiency of data read and write access, instructions scheduled to be processed generated by each process can be cached. For example, if the target memory is Nand flash memory, if the access address of the cached instruction to be processed is an adjacent and consecutive address, it indicates that access is possible through sequential access, and the address scheduled to be processed is consecutively adjacent, that is, the instruction to be processed is By merging, the Nand flash memory can be accessed sequentially based on the instructions scheduled to be processed after merging, that is, the addresses after merging. Accordingly, a small number of instructions can be used as much as possible, and the addresses accessed by each instruction and the instructions before and after are By ensuring continuity, the concurrency of data processed by memory is improved and the overhead of instructions is reduced. For example, as shown in Figure 5, process A generates instruction 1, the intended access address in instruction 1 is address 1 (i.e., address 1 in Figure 1), and process B generates instruction 2. And, the address to be accessed in instruction 2 is address 2 (i.e., address 2 in Figure 1), process C generates instruction 3, and the address to be accessed in instruction 3 is address 3 (i.e., address in Figure 1). 3). Processes A, B, and C access data in logical addresses 1, 2, and 3 of file 1 in Figure 1. Since address 1, address 2, and address 3 are adjacent and consecutive, instruction 1, instruction 2, and instruction 3 are merged to obtain an instruction including address 1, address 2, and address 3, that is, request A, and send request A to Nand flash By transferring to memory, Nand flash memory can be accessed sequentially based on request A.

Step S404, in response to the second instruction and the first instruction satisfying the first predetermined merging condition, the second instruction and the first instruction are determined as instructions to be merged.

In an embodiment of the present invention, when it is determined that the instruction to be processed that is currently traversed is a second instruction, it is determined whether the second instruction is an instruction to be merged, that is, the second instruction and the first instruction are merged into the first predetermined merge. Continue to determine whether the conditions are met. If the second instruction and the first instruction satisfy the first predetermined merging condition, the corresponding second instruction, that is, the instruction to be processed that is currently traversing, and the first instruction can be merged, that is, simultaneous access can be performed. Indicates that the second instruction and the first instruction are set as instructions to be merged, and instructions to be processed other than the first instruction are continued to be traversed, that is, instructions to be processed other than the next first instruction are traversed, and the next instruction is to be merged. Determine whether the command to be processed is a second command.

In response to the second instruction and the first instruction not meeting the first predetermined merge condition, continue traversing instructions to be processed other than the first instruction to determine whether the next instruction to be processed is the second instruction. .

Optionally, when continuing to traverse instructions scheduled to be processed other than the first instruction, determine whether the time to cache the first instruction exceeds the time to wait for execution of the first instruction, that is, obtain the first duration. Therefore, it is necessary to obtain the first time threshold corresponding to the first instruction. Here, the first duration represents the duration starting from the decision to acquire the first command to the current time. Responding that the first duration is less than the first time threshold indicates that the time that can wait for execution of the instruction, i.e., the time that the instruction can be cached, has not yet been exceeded, and that instructions scheduled to be processed other than the first instruction Continue traversing. Responding that the first duration is greater than or equal to the first time threshold indicates that the cache time of the instruction, i.e., the time that can wait for execution of the instruction, has been exceeded, and traversing of instructions scheduled to be processed other than the first instruction is stopped. And, the instructions to be merged determined during the traversing process are merged.

Here, the first time threshold represents the upper limit of the waiting time for instruction execution. The first time threshold may be set according to the real-time requirements of the relevant application corresponding to the process, and represents the upper limit of the waiting time of instruction execution, that is, the longest time for which the instruction can be cached.

Specifically, since real-time demands vary depending on the process, the first time threshold can be determined based on the process corresponding to the first instruction, that is, when the first time threshold corresponding to the first instruction is obtained, The target process corresponding to the first instruction, that is, the process that generates the first instruction, may be obtained, and the process type (eg, video application type, notepad application type) corresponding to the target process may be determined. The time threshold corresponding to the corresponding process type is set as the first time threshold corresponding to the first instruction.

Optionally, in response to the second instruction and the first instruction meeting a first predetermined merge condition, determining the second instruction and the first instruction as instructions to be merged comprises:

It includes at least one of obtaining a storage interval and obtaining a currently accessed total data amount. Here, the storage interval represents the distance between the scheduled access address of the first instruction and the scheduled access address of the second instruction. The current access total data amount represents the sum of the access scheduled data amount corresponding to all determined merge scheduled instructions.

If the storage interval is at least one of less than the first predetermined threshold and the current total access data amount is less than the second predetermined threshold, it is determined that the second instruction and the first instruction are instructions to be merged.

As an example, the first predetermined merging condition includes that the storage interval is less than the first predetermined threshold. Obtain storage interval. It is determined whether the storage interval is smaller than a first predetermined threshold. Responding to the storage interval being less than the first predetermined threshold indicates simultaneous access of the currently traversed instruction to be processed, that is, determining that the second instruction and the first instruction are to be merged instructions. Responding that the storage interval is greater than or equal to the first predetermined threshold indicates that the instruction to be processed that is currently traversed cannot be accessed at the same time, and the corresponding second instruction is not an instruction to be merged, and is merged with the first instruction. Decide you can't do it.

As an example, the first predetermined merging condition is that the current access total data amount is less than the second predetermined threshold, and the current access total data amount is obtained. It is determined whether the current total amount of accessed data is less than a second predetermined threshold. Responding to the fact that the total data amount currently accessed is less than the second predetermined threshold indicates that the instruction to be processed that is currently traversed can be accessed simultaneously, and it is determined that the second instruction and the first instruction are to be merged instructions. . In response to the currently accessed total data amount being greater than or equal to the second predetermined threshold, it is determined that the instruction scheduled to be currently traversed cannot be accessed simultaneously, and the second instruction is not an instruction scheduled to be merged.

As an example, the first predetermined merging condition includes that the storage interval is less than the first predetermined threshold and the current access total data amount is less than the second predetermined threshold, and the storage interval and the current access total data amount are set as an example. acquire. It is determined whether the storage interval is less than a first predetermined threshold, and further, it is determined whether the total amount of currently accessed data is less than a second predetermined threshold. Responding to the storage interval being less than the first predetermined threshold and the currently accessed total data amount being less than the second predetermined threshold indicates that the currently traversed instruction to be processed can be accessed simultaneously, and the second instruction is and determine that the second instruction and the first instruction are instructions to be merged. In response to at least one of the storage interval being greater than or equal to the first predetermined threshold, and the currently accessed total data amount being greater than or equal to the second predetermined threshold, the currently traversed instruction to be processed can be simultaneously accessed. It indicates that the second instruction cannot be merged, and it is determined that the second instruction is not an instruction scheduled to be merged.

Here, the first predetermined threshold represents the upper limit of the distance of the merged address, and the merged address represents the difference between the two merged logical addresses. The first predetermined threshold is determined based on the cache size in the memory and ensures that data accessed each time can be simultaneously processed by the target memory at once. Specifically, the first predetermined threshold may be provided by a corresponding provider of the target memory. For example, the first predetermined threshold is 300M, which means that the target memory can transmit data of 300M size once. This indicates that the corresponding address can be accessed from the cached data.

Here, the second predetermined threshold represents the upper limit of the amount of data for one access, that is, the maximum amount of data for one simultaneous access. The second predetermined threshold needs to refer to the hardware support of the target memory, and can be provided by the provider corresponding to the target memory, and the second predetermined threshold is, for example, 128K.

Optionally, before obtaining the storage interval, it is necessary to calculate the storage interval, and the calculation of the storage interval is as follows. The difference value between the access scheduled address of the second instruction and the access scheduled address of the first instruction is acquired. Here, the access scheduled address is a logical address. Obtains the size of a given storage unit. The storage interval is obtained by calculating the product of the difference value and the size of the predetermined storage unit, that is, the difference value and the size of the predetermined storage unit. For example, if the scheduled access address of the second instruction is 3, the scheduled access address of the first instruction is 1, and the size of the predetermined storage unit is 4KB, the storage interval is (3-1) * 4KB = 8KB. .

Here, since the target memory is accessed in units of blocks, that is, storage blocks, the size of the given storage unit is the size of the storage block, for example, 4KB.

Optionally, before obtaining the current access total data amount, the current access total data amount must be calculated. The calculation process of the current access total data amount is as follows. The sum of the scheduled access data amount corresponding to each of the determined merged instructions (i.e., the first instruction and the second instruction) is calculated to obtain the current total accessed data amount.

Here, the amount of data to be accessed indicates the address length corresponding to the address to be accessed, which can indicate the size of data that needs to be accessed. For example, if data with a size of 24KB is written from the address to be accessed, the corresponding 24KB is It may be the amount of data to be accessed, and of course the amount of data to be accessed may also indicate an address offset, and only through the amount of data to be accessed can the amount of data to be accessed be determined.

Here, the amount of data to be accessed may be acquired from an instruction to be processed, that is, the instruction to be processed may include the amount of data to be accessed, and may be acquired independently, but this is not limited here.

For example, the first instruction is instruction 1, instructions to be processed other than the first instruction include instruction 2 and instruction 3, and after determining that instruction 2 is an instruction to be merged, determine whether instruction 3 is the second instruction. do. If instruction 3 is the second instruction, calculate the storage interval and calculate the currently accessed total data amount. When calculating the current total access data amount, calculate the sum of the scheduled access data amount corresponding to the determined merged command, that is, the sum of the scheduled access data amount corresponding to instruction 2 and the scheduled access data amount corresponding to instruction 1, Get the total amount of data currently scheduled to be accessed.

Optionally, when merging the first instruction and the second instruction that satisfy the first predetermined merging condition, only the first instruction and the second instruction that satisfy the first predetermined merging condition may be merged, and the first instruction and the second instruction that satisfy the first predetermined merging condition may be merged. Sequential access instructions between the first instruction and the second instruction that satisfy the merging conditions may be merged. Correspondingly, the determined instructions to be merged also include merged sequential access instructions.

For example, the first instruction is instruction 1, instructions to be processed other than the first instruction include instruction 2 and instruction 3, the scheduled access address in instruction 1 is address 1 in FIG. 1, and the scheduled access address in instruction 2 is The address is address 2 in FIG. 1, and the address to be accessed in instruction 3 is address 4 in FIG. 1. Traversing instructions to be processed other than the first instruction, determining that the instruction to be processed that is currently traversing is instruction 2, and that instruction 2 is a sequential access instruction corresponding to instruction 1, that is, the address to be accessed in instruction 2 is the instruction. Subsequent to 1, the next instruction to be processed, that is, instruction 3, is traversed, and it is determined that instruction 3 is the second instruction. In the process of calculating the current access total data amount, the access scheduled address of instruction 2 is between the access scheduled address of instruction 1 and the access scheduled address of instruction 3, so the determined merged instruction includes instruction 2 and instruction 1, The current total access data amount is the sum of the scheduled access data amount corresponding to instruction 2 and the scheduled access data amount corresponding to instruction 1.

Optionally, if the current total access data amount is greater than or equal to the second predetermined threshold, it indicates that the required access data amount is reaching the upper limit when the target memory performs one access based on the determined merge scheduled instruction. , there is no need to merge instructions, that is, there is no need to determine instructions to be merged, and traversing of instructions to be processed other than the first instruction is stopped.

Optionally, when determining the instruction to be merged from the instruction to be processed, the first instruction may be obtained. Here, the first command is one of the commands to be processed. Traverse instructions scheduled to be processed other than the first instruction. Determine whether the currently traversed instruction to be processed and the first instruction satisfy a second predetermined merging condition, and respond to the fact that the currently traversed instruction to be processed and the first instruction satisfy a second predetermined merging condition Thus, the first instruction and the currently traversed instruction to be processed are determined as the instruction to be merged.

Here, the process of determining whether the first instruction and the instruction to be processed that is currently traversing satisfies the second predetermined merging condition determines whether the first instruction and the second instruction satisfy the first predetermined merging condition. It is similar to the judgment process, and explanation is omitted here.

Step S405, merge instructions to be merged are processed to obtain merge instructions.

In an embodiment of the present invention, a merge processing result is generated according to the access address of each scheduled merge instruction, and the merge processing result is encapsulated in a configuration instruction format to obtain the merge instruction.

In an embodiment of the present invention, after determining instructions to be merged, a merge processing result is generated according to the scheduled access address of each instruction to be merged, and the merge processing result includes the scheduled access address of each instruction to be merged. Based on the configuration instruction format, the merge processing result is encapsulated, a merge instruction is obtained, and instruction merge is realized.

Here, in the process of generating a merge processing result according to the access address of each instruction to be merged, a merge processing result including the scheduled access address of each instruction to be merged may be generated based on a predetermined structure type. .

Here, the predetermined structure type includes a linked list structure type, a tree structure type, an array structure type, etc., so the user can set it according to actual needs, and is not limited here.

Optionally, the setup command format is a format in which the target memory can be identified, such as a custom Write Buffer command format specified in JDECE.

Optionally, the amount of data to be accessed corresponding to the instruction to be merged may be stored in the merge processing result, that is, the amount of data to be accessed corresponding to each instruction to be merged may be acquired respectively. The amount of data to be accessed corresponding to each instruction to be merged is added to the merge processing result, that is, the result of the merge processing includes the amount of data to be accessed and the address to be accessed corresponding to the instruction to be merged.

Taking a specific application scenario as an example, as shown in Figure 6, when processes A, B, and C need to access data in logical address 1, 3, and 5 parts of the file, instruction 1, instruction 2, and instruction 3 This is created. The scheduled access address of instruction 1 is address 1, the scheduled access data amount corresponding to instruction 1 is the length of address 1, the scheduled access address of instruction 2 is address 3, and the scheduled access data amount corresponding to instruction 2 is address 3. is the length, the scheduled access address of instruction 3 is address 5, the scheduled access data amount corresponding to instruction 3 is the length of address 5, instruction 1 is the first instruction, instruction 2 and instruction 3 are both second instructions, and , it is determined that instruction 2 and instruction 3 are both instructions to be merged, and address 1 and the length of address 1 corresponding to instruction 1, address 3 and the length of address 3 corresponding to instruction 2, and address 5 and By adding the length of address 5 to list A, merging of instructions is realized.

Step S406, data access is performed according to the access scheduled address corresponding to the merge instruction.

In this embodiment, after obtaining the merge instruction, the merge instruction is transmitted to the target memory, so that the target memory accesses data according to the scheduled access address of each merge instruction among the merge instructions.

In an embodiment of the present invention, in a random read and write scenario, that is, when it is determined that a second instruction exists in instructions to be processed other than the first instruction, the first instruction and the second instruction for discrete access are merged and processed to generate a merge instruction. Obtain and store the merge instructions in the target memory device, reduce the number of instructions sent to the target memory, reduce instruction overhead of random reads and writes, and the target memory is scheduled to be accessed by a plurality of the merge instructions. It can be accessed according to address, improving the concurrency of the target memory and further improving the throughput of random reads and writes in the system, that is, improving the IO performance of the entire system.

In an embodiment of the present invention, when it is determined that there is no second instruction in the instructions to be processed other than the first instruction, that is, in a sequential read and write scenario, instructions that can be sequentially read and written, that is, instructions to be processed, are merged to create a merge instruction. Obtaining and transmitting the merge instruction to the target memory, reducing the number of instructions sent to the target memory, reducing instruction overhead of sequential reading and writing, and the target memory is connected to a plurality of addresses scheduled to be accessed in the merge instruction. It can be accessed sequentially, improving the concurrency of memory processing data and reducing the system's command overhead, effectively improving the IO performance of the entire system.

In an embodiment of the present invention, after obtaining the access scheduled instruction, the access scheduled instruction is stored in a predetermined instruction queue, the access scheduled instruction at the head position of the predetermined instruction queue is set as the first instruction, and the access scheduled instruction is set to the predetermined instruction queue. The remaining instructions scheduled to be accessed are traversed in the reverse direction. Among the remaining access scheduled instructions, determine whether there is a second instruction whose access scheduled address is not consecutive, and if present, indicate that random access is required, merge the second instruction and the first instruction to obtain a corresponding merge instruction, Reduces the number of instructions, thereby reducing instruction overhead. By storing the corresponding merge instructions in the Nand flash memory, the Nand flash memory can single access each access scheduled address in the merge instructions, realize simultaneous processing of instructions, improve the efficiency of instruction processing, and thus random access. Effectively improves throughput, that is, improves the IO performance of the entire system.

Although the embodiments of each of the above-described methods are described as a series of combinations of operations for simple explanation, it is understood by those skilled in the art that, according to the present invention, some steps may adopt a different order or be executed simultaneously, and are not limited by the order of the described operations. must be recognized.

Next, those skilled in the art should recognize that the embodiments described in this specification are all optional embodiments, and related operations and modules are not necessarily required for the present invention.

Corresponding to the embodiments of the above application function realization methods, the present invention provides embodiments of application function realization devices and corresponding terminals.

Referring to the block diagram of the data access device according to the example embodiment of FIG. 7, the device includes an instruction acquisition module 710, an instruction merge module 720, and an instruction transmission module 730,

The command acquisition module 710 is configured to acquire a plurality of commands to be processed. Here, each instruction to be processed includes an address to be accessed.

The command merging module 720 is configured to determine an instruction to be merged among a plurality of instructions to be processed, and obtain the merge instruction by merging the instructions to be merged.

The command transmission module 730 is configured to perform data access according to the access scheduled address corresponding to the merge command.

Optionally, instruction merge module 720 specifically:

configured to obtain a first instruction. Here, the first command is one of the commands to be processed.

The second instruction is acquired by traversing instructions to be processed other than the first instruction. Here, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly continuous, and the access scheduled address of the second instruction is continuous with the access scheduled address of the first instruction through the access scheduled address of another instruction to be processed. It doesn't work.

In response to the second instruction and the first instruction satisfying the first predetermined merging condition, the second instruction and the first instruction are determined as instructions to be merged.

Optionally, instruction merge module 720 specifically:

It consists of at least one of obtaining a storage interval, and obtaining a currently accessed total data amount. Here, the storage interval represents the distance between the scheduled access address of the first instruction and the scheduled access address of the second instruction. The current total amount of accessed data represents the sum of the amount of data scheduled to be accessed corresponding to all commands scheduled to be merged.

If the storage interval is at least one of less than the first predetermined threshold and the current total access data amount is less than the second predetermined threshold, the second instruction and the first instruction are determined as instructions to be merged.

Optionally, instruction merge module 720 may also:

A first duration is acquired, and a first time threshold corresponding to the first instruction is acquired. Here, the first duration represents the duration starting from the decision to acquire the first command to the current time.

In response to the first duration being less than the first time threshold, traversing instructions scheduled to be processed other than the first instruction continues.

In response to the first duration being greater than or equal to the first time threshold, traversing of instructions scheduled to be processed other than the first instruction is stopped.

Optionally, instruction merge module 720 may also:

If the current access total data amount is greater than or equal to the second predetermined threshold, traversing of instructions to be processed other than the first instruction is stopped.

Optionally, instruction merge module 720 may also:

The difference value between the access scheduled address of the second instruction and the access scheduled address of the first instruction is acquired. Here, the access scheduled address is a logical address.

Obtains the size of a given storage unit.

The storage interval is obtained according to the difference value and the size of the predetermined storage unit.

Optionally, instruction merge module 720 specifically:

Acquire the first instruction. Here, the first command is one of the commands to be processed.

Traverse instructions scheduled to be processed other than the first instruction.

In response to the currently traversed instruction to be processed and the first instruction satisfying a second predetermined merge condition, the first instruction and the currently traversed instruction to be processed are determined as instructions to be merged.

Optionally, instruction merge module 720 may also:

Commands to be processed are stored in a predetermined command queue.

In a predetermined instruction queue, an instruction to be processed that satisfies at least one of the following conditions is set as the first instruction.

The second duration corresponding to the instruction scheduled to be processed is greater than the second time threshold. Here, the second duration represents the storage duration of the command to be processed in a predetermined command queue.

The command to be processed is located at a set position in a predetermined command queue. Here, the setting position is the head position of the cue or the tail position of the cue.

Optionally, instruction merge module 720 specifically:

A merge processing result is generated according to the access address of each scheduled merge instruction, and the merge instruction is obtained by encapsulating the merge processing result in a set instruction format.

Optionally, instruction merge module 720 may also:

The amount of data scheduled to be accessed corresponding to each scheduled instruction to be merged is acquired.

The amount of data to be accessed corresponding to each instruction to be merged is added to the merge processing result.

The device embodiments basically correspond to the method embodiments, so related points may refer to the description of the method embodiments. The above-described device embodiments are merely examples, and the units described as separate parts may or may not be physically separate, and the parts indicated as units may or may not be physical units. , that is, it may be located in one location, or may be distributed across multiple network units. The purpose of the present invention can be achieved by selecting some or all of the modules according to actual needs. A person skilled in the art can understand and implement this without assigning creative labor.

Accordingly, in one aspect, an embodiment of the present invention provides a data access device including a processor and a memory for storing instructions executable by the processor, the processor comprising:

Acquires multiple commands to be processed. Here, each instruction to be processed includes an address to be accessed.

Among the plurality of instructions to be processed, an instruction to be merged is determined, and the instructions to be merged are merged to obtain a merge instruction.

Data access is performed according to the access scheduled address corresponding to the merge instruction.

Fig. 8 is a schematic configuration diagram of a data access device 1500 according to an exemplary embodiment.

For example, device 800 may be an electronic device, specifically a cell phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness device, and personal digital association. and wearable devices such as smart watches, smart glasses, smart bracelets, and smart running shoes.

8, device 800 includes a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, and an input/output (I/O) interface 812. , may include one or more components of a sensor component 814 and a communication component 816.

Processing component 802 controls the overall operation of device 800, typically associated with displays, phone calls, data communications, camera operations, recording operations, etc. Processing component 802 may include one or more processors 820 that perform instructions to complete all or part of the steps of the method described above. Additionally, processing component 802 may include one or more modules that facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

Memory 804 is configured to store various types of data to support operations in device 800. Examples of such data include instructions for any application or method for operating on device 800, contact data, phone book data, messages, photos, videos, etc. Memory 804 may include static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk, It may be implemented by any type of volatile or non-volatile storage device, such as an optical disk, or a combination thereof.

Power component 806 supplies power to various components of device 800. Power component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for device 800 .

The multimedia component 808 includes a screen that provides an output interface between the device 800 described above and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). When the screen includes a touch panel, the screen is implemented as a touch screen and can receive input signals from the user. The touch panel includes one or more touch sensors for detecting touches, slides, and gestures on the touch panel. The touch sensor may not only detect the boundaries of a touch or slide motion, but also detect the duration and pressure associated with the touch or slide motion. In some embodiments, multimedia component 808 includes a front camera and/or a back camera. When the device 800 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the back camera can receive external multimedia data. Each front and back camera may be a fixed optical lens system or may have focus and optical zoom capabilities.

Audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a microphone (MIC) configured to receive an external audio signal when the device 800 is in an operating mode, such as a call mode, a recording mode, or a voice recognition mode. The received audio signal may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 further includes a speaker for outputting audio signals.

I/O interface 812 provides an interface between processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, the homepage button, volume buttons, start button, and lock button.

Sensor component 814 includes one or more sensors to provide various aspects of condition assessment to device 800. For example, sensor component 814 may detect the on/off state of device 800, the relative positions of components such as the display and keypad of device 800, and sensor component 814 may detect device 800 or A change in the position of one of the components of the device 800, whether a user is touching the device 800, the orientation or acceleration/deceleration of the device 800, and a change in the temperature of the device 800 may also be detected. Sensor component 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor component 814 may include an optical sensor, such as a CMOS or CCD image sensor for use in imaging applications. In some embodiments, sensor component 814 may include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

Communication component 816 is configured to facilitate wired or wireless communication between device 800 and other devices. Device 800 may access wireless networks based on communication standards such as WiFi, 2G or 3G, 4G LTE, 5G NR, or a combination thereof. In an example embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 816 described above further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data communication (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

In an exemplary embodiment, device 800 may include one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), and programmable logic devices (PLDs) to perform the methods described above. ), may be implemented by a field programmable gate array (FPGA), controller, microcontroller, microprocessor, or other electronic components.

An example embodiment provides a non-transitory computer-readable storage medium, e.g., a memory 804 containing instructions, when the instructions in the storage medium are executed by the processor 820 of the device 800, device ( 800) may execute a data access method, the method comprising:

Obtaining a plurality of instructions to be processed, where each instruction to be processed includes an address to be accessed,

determining an instruction to be merged among a plurality of instructions to be processed, merging the instructions to be merged, and obtaining the merge instruction; and

It includes performing data access according to the access scheduled address corresponding to the merge instruction.

The non-transitory computer-readable storage medium may be ROM, random access memory (RAM), CD ROM, magnetic tape, floppy disk, optical data storage device, etc.

In an exemplary embodiment, a computer program product is also provided that includes a computer program that, when executed by a processor, implements the steps of the method described above.

Those skilled in the art will be able to easily think of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The purpose of the present invention is to cover any modifications, uses or adaptive changes of the present invention, including known common sense or common technical means in the relevant technical field that are not disclosed in the present invention, in accordance with the general principles of the present invention. . The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the invention is defined by the following claims.

Please understand that the present invention is not limited to the precise structure shown in the above drawings, and that various modifications and changes are possible without departing from the scope. The scope of the invention is limited only by the appended claims.

Claims (15)

In a data access method applied to an electronic device,
acquiring a plurality of instructions to be processed, each of the instructions to be processed including an address to be accessed;
determining an instruction to be merged among the plurality of instructions to be processed, merging the instructions to be merged, and obtaining a merge instruction; and
Comprising the step of performing data access according to the access scheduled address corresponding to the merge command.
A data access method characterized by: According to paragraph 1,
The step of determining an instruction to be merged among the plurality of instructions to be processed is:
Obtaining a first instruction, wherein the first instruction is one of the instructions to be processed,
A second instruction is acquired by traversing an instruction to be processed other than the first instruction, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly consecutive, and the access scheduled address of the second instruction is The address is not consecutive to the access scheduled address of the first instruction through the access scheduled address of another instruction to be processed, and
In response to the second instruction and the first instruction meeting the first predetermined merge condition, determining the second instruction and the first instruction as the instruction to be merged.
A data access method characterized by: According to paragraph 2,
In response to the second instruction and the first instruction meeting the first predetermined merge condition, determining the second instruction and the first instruction as the instruction to be merged includes:
At least one of obtaining a storage interval and obtaining a currently accessed total data amount, wherein the storage interval represents a distance between the access scheduled address of the first instruction and the access scheduled address of the second instruction, A step where the current access total data amount represents the sum of the access scheduled data amounts corresponding to all merge scheduled instructions, and
If the storage interval is at least one of the first predetermined threshold and the current access total data amount is less than the second predetermined threshold, the second instruction and the first instruction are merged into the instruction to be merged. which includes the step of deciding
A data access method characterized by: According to paragraph 3,
If the current access total data amount is greater than or equal to the second predetermined threshold, stopping traversing of instructions to be processed other than the first instruction.
A data access method characterized by: According to paragraph 3,
Obtaining a difference value between the scheduled access address of the second instruction and the scheduled access address of the first instruction, wherein the scheduled access address is a logical address,
obtaining the size of a predetermined storage unit, and
Further comprising obtaining the storage interval according to the difference value and the size of the predetermined storage unit,
A data access method characterized by: According to paragraph 2,
Obtaining a first duration, obtaining a first time threshold corresponding to the first instruction, the first duration representing the duration starting from the determination of acquisition of the first instruction to the current time;
In response to the first duration being less than a first time threshold, continuing to traverse instructions scheduled to be processed other than the first instruction, and
In response to the first duration being greater than or equal to the first time threshold, stopping traversing of instructions scheduled to be processed other than the first instruction.
A data access method characterized by: According to paragraph 1,
Obtaining a first instruction, wherein the first instruction is one of the instructions to be processed,
Traversing instructions to be processed other than the first instruction, and
In response to the currently traversing to-be-processed instruction and the first instruction meeting a second predetermined merge condition, determining the currently traversing to-be-processed instruction and the first instruction to be the merging instruction to be merged. containing
A data access method characterized by: According to any one of claims 2 to 7,
Storing the command to be processed in a predetermined command queue,
In the predetermined command queue,
A second duration corresponding to the instruction to be processed is greater than a second time threshold, and the second duration represents a storage duration of the instruction to be processed in the predetermined instruction queue, and
The first instruction is an instruction to be processed that satisfies at least one condition: the instruction to be processed is located at a set position in a predetermined instruction queue, and the set position is a head position of the queue or a tail position of the queue. containing more
A data access method characterized by: According to paragraph 1,
The step of acquiring a merge instruction by merging the plurality of instructions scheduled to be merged,
Generating a merge processing result according to the access address of each scheduled merge instruction, encapsulating the merge processing result in a set instruction format, and obtaining the merge instruction.
A data access method characterized by: According to clause 9,
acquiring an access scheduled data amount corresponding to each of the merge scheduled instructions, and
Further comprising adding the amount of data to be accessed corresponding to each of the scheduled merge instructions to the merge processing result.
A data access method characterized by: A data access device comprising a command acquisition module, a command merging module, and a command transmission module,
The instruction acquisition module is configured to acquire a plurality of instructions to be processed, and each instruction to be processed includes an address to be accessed,
The instruction merging module is configured to determine an instruction to be merged among the plurality of instructions to be processed, and obtain a merge instruction by merging the instructions to be merged,
The command transmission module is configured to perform data access according to the access scheduled address corresponding to the merge command.
A data access device characterized in that. According to clause 11,
The command transmission module is
Obtain a first instruction, wherein the first instruction is one of the instructions to be processed,
A second instruction is acquired by traversing an instruction to be processed other than the first instruction, the access scheduled address of the second instruction and the access scheduled address of the first instruction are indirectly consecutive, and the access scheduled address of the second instruction is The address is not continuous with the access address of the first instruction through the access address of another instruction to be processed,
In response to the second instruction and the first instruction meeting the first predetermined merge condition, determine between the second instruction and the first instruction.
A data access device characterized in that. According to clause 12,
The command transmission module also,
At least one of obtaining a storage interval and obtaining a currently accessed total data amount, wherein the storage interval represents a distance between the access scheduled address of the first instruction and the access scheduled address of the second instruction, The current access total data amount represents the sum of the access scheduled data amount corresponding to all merge scheduled instructions,
If the storage interval is less than the first predetermined threshold and the current access total data amount is less than the second predetermined threshold, determine the second instruction and the first instruction as the instruction to be merged.
A data access device characterized in that. A computer program is stored that, when executed by a processor, implements the steps of the data access method according to any one of claims 1 to 10.
A non-transitory computer-readable storage medium characterized in that. In a data access device including a processor and memory for storing instructions executable by the processor,
The processor,
Acquire a plurality of instructions to be processed, each of the instructions to be processed includes an address to be accessed,
Determining an instruction to be merged among the plurality of instructions to be processed, merging the instructions to be merged to obtain a merge instruction,
Configured to access data according to the access scheduled address corresponding to the merge command
A data access device characterized in that.