CN112445766A

CN112445766A - Terminal fragment sorting method and device and terminal

Info

Publication number: CN112445766A
Application number: CN201910820097.3A
Authority: CN
Inventors: 任立鹏; 党健; 薛凯; 刘闯
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-08-31
Filing date: 2019-08-31
Publication date: 2021-03-05

Abstract

The embodiment of the application provides a terminal fragment sorting method, a terminal fragment sorting device and a terminal, relates to the field of terminals and aims to improve the performance of the terminal by solving the fragmentation problem inside the terminal. The method is applied to a terminal with a flash memory storage device and a management device, wherein the flash memory storage device comprises a flash memory controller and a storage medium; the method comprises the following steps: when the terminal is in a performance recovery mode, the flash memory controller receives a first operation instruction which is sent by the management equipment and used for indicating the flash memory controller to arrange the storage space of the storage medium; in response to the first operation instruction, the flash controller determines a plurality of fragmented files stored in M of the Q memory blocks; corresponding first physical addresses of the plurality of fragmented files in the M storage blocks are not continuous; the flash memory controller stores the plurality of fragment files in N storage blocks of the Q storage blocks according to the sizes of the plurality of fragment files, and corresponding second physical addresses of the plurality of fragment files in the N storage blocks are continuous.

Description

Terminal fragment sorting method and device and terminal

Technical Field

The embodiment of the application relates to the field of terminals, in particular to a terminal defragmentation method and device and a terminal.

Background

Terminals (e.g., mobile phones, etc.) adopting an android system are becoming the mainstream of the terminal market. Current android systems typically use embedded multimedia memory cards (eMMC) or Universal Flash Storage (UFS) as Flash memory Storage devices.

eMMC and UFS belong to different categories of flash memory (flash memory). The flash memory storage medium contains one or more memory blocks for storing data. One characteristic of flash memory storage is that the original data needs to be erased before the data can be written. With the long-term use of the terminal, repeated reading, writing and erasing operations cause the fragmentation phenomenon of the flash memory device to be more and more serious, and a large number of fragmented files are stored in the flash memory device and occupy limited storage space, thereby causing the storage space to be tense. When the storage space of the flash memory is insufficient, in order to reclaim the storage space, the terminal needs to perform a Garbage Collection (GC) operation on the flash memory storage device. The purpose of this GC operation is to reclaim physical pages in the memory block that have been invalidated, and to reuse the invalidated physical pages to store data. The GC operation causes that data of the terminal read-write request cannot be responded in time, so that the system is directly blocked, and the response speed of the android system is gradually reduced.

At present, when the fragmentation of an internal block of the eMMC reaches a preset threshold (generally, the number of usable storage blocks is less than 10), and the eMMC is in an emergency (URGENT) mode, a terminal may sort a fragmented file when the eMMC is in an idle state, and stop sorting after the fragmentation reaches a preset proportion. At this time, the writing operation of the electronic device is quickly completed, but after the electronic device is used for a period of time, the writing operation is interrupted by the GC operation. This is because the number of the just sorted storage blocks is small or the inside of the device is not thoroughly sorted, so that the application creates new files, and the new storage blocks are easy to use up. So that the jamming of the terminal is still frequent.

Disclosure of Invention

The embodiment of the application provides a terminal defragmentation method, a terminal defragmentation device and a terminal, which are used for improving the terminal performance by solving the problem of defragmentation inside the terminal.

In order to solve the above technical problem, an embodiment of the present application provides the following technical solutions:

in a first aspect, an embodiment of the present application provides a terminal defragmentation method, which is applied to a terminal having a flash memory device and a management device, where the flash memory device includes a flash memory controller and a storage medium, the storage medium includes Q storage blocks, and Q is an integer greater than or equal to 1; the method provided by the embodiment of the application comprises the following steps: when the terminal is in a performance recovery mode, the flash memory controller receives a first operation instruction sent by the management equipment; the first operation instruction is used for instructing the flash memory controller to arrange the storage space of the storage medium; in response to the first operation instruction, the flash controller determines a plurality of fragmented files stored in M of the Q memory blocks; q is more than or equal to M and more than or equal to 1, and M is an integer; corresponding first physical addresses of the plurality of fragmented files in the M storage blocks are not continuous; and the flash memory controller stores the plurality of fragment files in N storage blocks in the Q storage blocks according to the sizes of the plurality of fragment files. M is larger than or equal to N and larger than or equal to 1, N is an integer, and the corresponding second physical addresses of the fragment files in the N storage blocks are continuous.

The embodiment of the application provides a terminal defragmentation method, and after a flash memory device is used for a period of time, as files are repeatedly written and deleted, continuous unoccupied storage space in the flash memory device is smaller and smaller, so that the same file cannot be integrally stored in the continuous unoccupied storage space, but is scattered into a plurality of fragmented files to be stored in different free spaces of the flash memory device. In this embodiment of the present application, when the terminal is in the performance recovery mode, the flash controller receives a first operation instruction sent by the management device and used for instructing the flash controller to sort the fragmented files stored in the storage medium, and determines, according to the first operation instruction, a plurality of fragmented files stored in the storage medium, where first physical addresses corresponding to the plurality of fragmented files are not consecutive, and then, according to the sizes of the plurality of fragmented files, the flash controller stores the plurality of fragmented files in N storage blocks of the Q storage blocks. In addition, because the corresponding second physical addresses of the plurality of fragmented files in the N storage blocks are continuous, the storage space of the storage medium can be fully utilized, the number of the remaining unoccupied storage blocks is increased, and the performance of the terminal is improved.

In one possible implementation, the first physical address of any fragmented file is a physical address when any fragmented file is stored in M storage blocks; the second physical address of any one of the fragmented files is a physical address when any one of the fragmented files is stored in the N memory blocks.

In one possible implementation, the addresses of the N memory blocks are consecutive, and the addresses of the M memory blocks are not consecutive. The storage space of the flash memory device can be saved by storing a plurality of fragmented files in N memory blocks having consecutive addresses.

In one possible implementation, the determining, by the flash controller, a plurality of fragmented files stored in M of the Q memory blocks comprises: the flash memory controller determines the storage position of each fragmented file in the plurality of fragmented files in the storage block where the fragmented file is located; and the flash memory controller determines a plurality of fragment files stored in the M storage blocks according to the storage positions of each fragment file in the storage block where the fragment file is located.

In one possible implementation, the determining, by the flash controller, a storage location of each of the plurality of fragmented files in the respective storage block includes: the flash memory controller determines a first physical address corresponding to each fragment file; and the flash memory controller determines the storage position of each fragment file in the storage block in which the fragment file is located according to the first physical address corresponding to each fragment file.

In one possible implementation manner, the determining, by the flash controller, a first physical address corresponding to each fragmented file includes: determining a logic address corresponding to each fragment file by a flash memory controller; the flash memory controller determines a first physical address corresponding to each fragmented file according to the address mapping table and the logic address corresponding to each fragmented file; the address mapping table at least comprises a mapping relation between a logical address corresponding to each fragmented file and a first physical address of each fragmented file.

In a possible implementation manner, after the flash memory controller stores the plurality of fragmented files in N storage blocks of the Q storage blocks according to sizes of the plurality of fragmented files, the method provided in the embodiment of the present application further includes: and the flash memory controller updates the address mapping table according to the second physical address of each fragment file in the N storage blocks respectively. Wherein, the updated address mapping table at least comprises: and mapping relation between the second physical address corresponding to each fragmented file and the logical address corresponding to each fragmented file.

In a possible implementation manner, the flash memory controller receives an inquiry command sent by the management device, where the inquiry command is used to inquire whether the controller finishes organizing the storage space of the storage medium. And the flash memory controller sends an inquiry response to the management device, wherein the inquiry response is used for indicating the progress of the flash memory controller in sorting the storage space of the storage medium. For example, the query response is used to indicate that the storage space of the storage medium has been sorted, or the query response is used to indicate that the storage space of the storage medium has not been sorted. This allows the management device to determine the performance recovery progress.

In a possible implementation manner, after a physical address of any one of the plurality of fragmented files is changed from a first physical address to a second physical address, the method provided in the embodiment of the present application further includes: and the flash memory controller erases the fragment file stored on the storage space corresponding to the first physical address.

In a second aspect, an embodiment of the present application provides a method for defragmenting a file, which is applied to a terminal having a flash memory device and a management device, where the flash memory device includes a controller and a storage medium, the storage medium includes Q storage blocks, and Q is an integer greater than or equal to 1, and the method further includes: the management equipment determines that the system performance of the terminal is less than or equal to a preset threshold; the management equipment controls the terminal to be in a performance recovery mode; the management device sends a first operation instruction to the controller, wherein the first operation instruction is used for instructing the controller to arrange the storage space of the storage medium.

In one possible implementation, the method for controlling, by a management device, a terminal to be in a performance recovery mode includes: the management equipment displays a first prompt message on a display screen of the terminal, wherein the first prompt message is used for prompting whether the user agrees with the terminal. The management equipment determines that an instruction for confirming entering the performance recovery mode is received from a user, and the management equipment controls the terminal to be in the performance recovery mode.

In a possible implementation manner, the method provided in the embodiment of the present application further includes: and the management equipment displays a second prompt message on a display screen of the terminal, wherein the second prompt message is used for prompting the user that the terminal cannot be operated during the period that the terminal is in the performance recovery mode.

In a possible implementation manner, the method provided in the embodiment of the present application further includes: the management equipment sends an inquiry command to the controller periodically according to a preset period, and the inquiry command is used for inquiring whether the controller finishes sorting the fragmented files stored in the storage medium. The management device receives a query response sent by the flash memory storage device, wherein the query response is used for indicating that the storage space of the storage medium is sorted, or the query response is used for indicating that the storage space of the storage medium is not sorted.

In a possible implementation manner, the method provided in the embodiment of the present application further includes: the management equipment determines that the controller finishes sorting the fragmented files stored in the storage medium, controls the terminal to exit the performance recovery mode and controls the terminal to be started.

In a third aspect, an embodiment of the present application provides a flash memory device, which is applied to a terminal having a management device, where the flash memory device includes a flash memory controller and a storage medium, the storage medium includes Q storage blocks, and Q is an integer greater than or equal to 1; the flash memory controller includes: a processor and a communication interface; the terminal is in a performance recovery mode, and the communication interface is used for receiving a first operation instruction sent by the management equipment; the first operation instruction is used for instructing the flash memory controller to arrange the storage space of the storage medium; in response to the first operation instruction, a processor for determining a plurality of fragmented files stored in M of the Q memory blocks; q is more than or equal to M and more than or equal to 1, and M is an integer; corresponding first physical addresses of the plurality of fragmented files in the M storage blocks are not continuous; the processor is further used for storing the plurality of fragmented files in N storage blocks in the Q storage blocks according to the sizes of the plurality of fragmented files; m is larger than or equal to N and larger than or equal to 1, N is an integer, and the corresponding second physical addresses of the fragment files in the N storage blocks are continuous.

In one possible implementation, the addresses of the N memory blocks are consecutive, and the addresses of the M memory blocks are not consecutive.

In a possible implementation manner, the processor is specifically configured to determine a storage location of each of the plurality of fragmented files in the respective storage block, and to determine a plurality of fragmented files stored in the M storage blocks according to the storage location of each of the plurality of fragmented files in the respective storage block.

In a possible implementation manner, the processor is specifically configured to determine a first physical address corresponding to each fragmented file, and to determine, according to the first physical address corresponding to each fragmented file, a storage location of each fragmented file in the respective storage block.

In a possible implementation manner, the processor is specifically configured to determine a logical address corresponding to each fragmented file; the method comprises the steps of determining a logical address corresponding to each fragmented file according to an address mapping table and the logical address corresponding to each fragmented file; the address mapping table at least comprises a mapping relation between a logical address corresponding to each fragmented file and a first physical address of each fragmented file.

In a possible implementation manner, the processor is further configured to update the address mapping table according to a second physical address of each fragmented file in the N storage blocks; wherein, the updated address mapping table at least comprises: and mapping relation between the second physical address corresponding to each fragmented file and the logical address corresponding to each fragmented file.

In a possible implementation manner, the communication interface is further configured to receive an inquiry command sent by the management device, where the inquiry command is used to inquire whether the flash memory controller finishes organizing the storage space of the storage medium. And the flash memory controller sends an inquiry response to the management device, wherein the inquiry response is used for indicating the progress of the flash memory controller in sorting the storage space of the storage medium.

In a possible implementation manner, the communication interface is further configured to receive an inquiry command sent by the management device, where the inquiry command is used to inquire whether the controller finishes organizing the storage space of the storage medium. And the communication interface is further used for sending a query response to the management device, wherein the query response is used for indicating that the storage space of the storage medium is sorted, or the query response is used for indicating that the storage space of the storage medium is not sorted.

In a possible implementation manner, after the physical address of any one of the fragmented files is changed from the first physical address to the second physical address, the processor is further configured to erase the fragmented file stored in the storage space corresponding to the first physical address.

In the embodiment of the present application, the communication interface in the third aspect may be replaced with a communication unit, and the processor in the third aspect may be replaced with a processing unit. In this embodiment, the communication interface in the third aspect may be replaced with a communication module, and the processor in the third aspect may be replaced with a processing module.

In a fourth aspect, an embodiment of the present application provides a management device, which is applied to a terminal having a flash memory storage device, where the flash memory storage device includes a flash memory controller and a storage medium, the storage medium includes Q storage blocks, and Q is an integer greater than or equal to 1, and the management device includes: a processor for determining that a system performance of the terminal is less than or equal to a preset threshold; a processor for controlling the terminal to be in a performance recovery mode; the communication interface is used for sending a first operation instruction to the flash memory controller, and the first operation instruction is used for instructing the controller to arrange the storage space of the storage medium.

In a possible implementation manner, the processor is further configured to display a first prompt message on a display screen of the terminal, where the first prompt message is used to prompt a user whether to approve the terminal to enter a performance recovery mode. And the processor is used for specifically determining that the communication interface receives an instruction for confirming to enter the performance recovery mode from the user and controlling the terminal to be in the performance recovery mode.

In a possible implementation manner, the processor is further configured to display a second prompt message on the display screen of the terminal, where the second prompt message is used for prompting a user that the terminal cannot be forcibly operated during the terminal being in the performance recovery mode.

In a possible implementation manner, the communication interface is further configured to send, to the controller, an inquiry command periodically according to a preset period, where the inquiry command is used to inquire whether the controller finishes finishing the storage space of the storage medium, or, and is further configured to receive an inquiry response sent by the flash memory device, where the inquiry response is used to indicate that the storage space of the storage medium is finished, or, the inquiry response is used to indicate that the storage space of the storage medium is not finished.

In a possible implementation manner, the processor is further configured to determine that the controller finishes organizing the storage space of the storage medium, control the terminal to exit the performance recovery mode, and control the terminal to power on.

In the embodiment of the present application, the communication interface in the fourth aspect may be replaced with a communication unit, and the processor in the fourth aspect may be replaced with a processing unit. In the embodiment of the present application, the communication interface in the fourth aspect may be replaced with a communication module, and the processor in the third aspect may be replaced with a processing module.

In a fifth aspect, embodiments of the present application provide a communication device, which includes a processor and a storage medium, where the storage medium stores instructions that, when executed by the processor, implement the method as described in the first aspect or various possible implementation manners of the first aspect.

In a sixth aspect, the present application provides a communication device, which includes a processor and a storage medium, where the storage medium stores instructions that, when executed by the processor, implement the method as described in the second aspect or various possible implementation manners of the second aspect.

In a seventh aspect, an embodiment of the present application provides a communication apparatus, where the communication apparatus includes one or more modules, configured to implement the methods of the first aspect and the second aspect, where the one or more modules may correspond to each step in the methods of the first aspect and the second aspect.

In an eighth aspect, embodiments of the present application provide a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a computer program or instructions to implement the method described in the second aspect or in various possible implementations of the second aspect. The communication interface is used for communicating with other modules outside the chip.

In particular, the chip provided in the embodiments of the present application further includes a memory for storing a computer program or instructions.

In a ninth aspect, embodiments of the present application provide a chip, which includes a processor, a memory, and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a computer program or instructions to implement the first aspect or one of the methods described in the various possible implementations of the first aspect. The communication interface is used for communicating with other modules outside the chip.

Any one of the above-provided apparatuses, computer storage media, computer program products, chips, or communication systems is configured to execute the above-provided corresponding methods, and therefore, the beneficial effects that can be achieved by the apparatuses, the computer storage media, the computer program products, the chips, or the communication systems can refer to the beneficial effects of the corresponding schemes in the above-provided corresponding methods, and are not described herein again.

Drawings

Fig. 1 is a schematic structural diagram provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a terminal according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a terminal defragmentation method according to an embodiment of the present application;

fig. 4 is a schematic diagram illustrating storage of a fragmented file in a storage block according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating storage of another fragmented file in a storage block according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating storage of another fragmented file in a storage block according to an embodiment of the present application;

fig. 7 is a schematic flowchart of another terminal defragmentation method according to an embodiment of the present application;

fig. 8 is a schematic diagram of a display interface provided in an embodiment of the present application;

FIG. 9 is a schematic view of another display interface provided in an embodiment of the present application;

FIG. 10 is a schematic view of another display interface provided in an embodiment of the present application;

FIG. 11 is a schematic view of another display interface provided in an embodiment of the present application;

FIG. 12 is a schematic view of another display interface provided in an embodiment of the present application;

FIG. 13 is a schematic diagram of an apparatus according to an embodiment of the present disclosure;

FIG. 14 is a schematic structural diagram of another apparatus provided in an embodiment of the present application;

fig. 15 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

Before describing the embodiments of the present application, the terms related to the embodiments of the present application will be explained as follows:

the fragmented file means: fragmented data on a flash memory device. Files are scattered in a flash memory storage device over many different storage areas, i.e., fragmented files, which are the result of non-contiguous application or file storage, i.e., different portions of a given application or file are not stored in a set of contiguous memory blocks on the flash memory storage device.

In the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same or similar items having substantially the same function and action. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

The network architecture and the service scenario described in the embodiment of the present application are for more clearly illustrating the technical solution of the embodiment of the present application, and do not form a limitation on the technical solution provided in the embodiment of the present application, and as a person of ordinary skill in the art knows that along with the evolution of the network architecture and the appearance of a new service scenario, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

The method provided by the embodiment of the application can be applied to a terminal, as shown in fig. 1, the terminal includes: a management device 10 and a flash memory storage device 20.

As shown in fig. 1, the management device 10 may include a processor 110 and a storage controller 120. The management device 10 may be a chip with a memory controller. For example, the management apparatus 10 may be a system on chip (SoC).

Illustratively, the flash memory storage device 20 may include a flash controller 210 and at least one storage medium. The flash memory device 20 may be, for example, an eMMC memory device or a UFS memory device. The storage medium may be a NAND flash memory chip for storing data. The flash memory controller 210 is responsible for controlling and communicating between the inside and the outside, mainly controlling reading, writing, erasing operations and address space management of the storage medium for the inside, and mainly communicating with the terminal for the outside, receiving and responding to a command of the terminal, and realizing that data to be stored in the terminal is stored in the corresponding storage medium and data to be read by the terminal is taken out from the corresponding storage medium and sent to the terminal. The flash memory device is used for storing software, data and the like in a mobile phone and a tablet computer, such as operating system software, application software, pictures, documents and the like.

The terminal shown in fig. 1 may be: smart phones (e.g., Android phones, iOS phones)), wearable devices, AR (augmented reality) \ VR (virtual reality) devices, ultra-mobile personal computers (UMPCs), netbooks, Personal Digital Assistants (PDAs), tablet computers, palmtop computers, and Mobile Internet Devices (MIDs), etc., using the flash memory storage device 20.

As shown in fig. 2, the terminal in the embodiment of the present application may be a mobile phone 100. The embodiment will be specifically described below by taking the mobile phone 100 as an example. It should be understood that the illustrated handset 100 is only one example of a terminal and that the handset 100 may have more or fewer components than shown in the figures, may combine two or more components, or may have a different configuration of components.

As shown in fig. 2, the mobile phone 100 may specifically include: processor 101, Radio Frequency (RF) circuitry 102, memory 103, touch screen 104, bluetooth device 105, one or more sensors 106, Wi-Fi device 107, positioning device 108, audio circuitry 109, peripherals interface 110, and power system 111. These components may communicate over one or more communication buses or signal lines (not shown in fig. 2). Those skilled in the art will appreciate that the hardware configuration shown in fig. 2 is not intended to be limiting, and that the handset 100 may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

The following describes the components of the handset 100 in detail with reference to fig. 2:

the processor 101 is a control center of the mobile phone 100, connects various parts of the mobile phone 100 by various interfaces and lines, and executes various functions of the mobile phone 100 and processes data by running or executing an application program (hereinafter, may be abbreviated as App) stored in the memory 103 and calling data stored in the memory 103. In some embodiments, processor 101 may include one or more processing units; for example, the processor 101 may be an kylin 960 chip manufactured by Huanti technologies, Inc.

The rf circuit 102 may be used for receiving and transmitting wireless signals during the transmission and reception of information or calls. In particular, the rf circuit 102 may receive downlink data of the base station and then process the received downlink data to the processor 101; in addition, data relating to uplink is transmitted to the base station. Typically, the radio frequency circuitry includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency circuitry 102 may also communicate with other devices via wireless communication. The wireless communication may use any communication standard or protocol including, but not limited to, global system for mobile communications, general packet radio service, code division multiple access, wideband code division multiple access, long term evolution, email, short message service, and the like.

The memory 103 is used for storing application programs and data, and the processor 101 executes various functions and data processing of the mobile phone 100 by running the application programs and data stored in the memory 103. The memory 103 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system and application programs (such as a sound playing function and an image playing function) required by at least one function; the storage data area may store data (e.g., audio data, a phonebook, etc.) created from use of the handset 100. Further, the memory 103 may include high speed random access memory, and may also include non-volatile memory, such as a magnetic disk storage device, a flash memory device, or other volatile solid state storage device. The memory 103 may store various operating systems, such as those developed by apple Inc

Operating System, developed by Google

An operating system, etc.

The touch screen 104 may include a touch pad 104-1 and a display 104-2. Wherein the touch pad 104-1 can capture touch events on or near the touch pad 104-1 by a user of the cell phone 100 (e.g., user operation on or near the touch pad 104-1 using any suitable object such as a finger, a stylus, etc.), and transmit the captured touch information to other devices, such as the processor 101. Among them, a touch event of a user near the touch pad 104-1 can be called a hover touch; hover touch may refer to a user not needing to directly contact the touchpad in order to select, move, or drag a target (e.g., an icon, etc.), but only needing to be located near the terminal in order to perform a desired function. In the context of a hover touch application, the terms "touch," "contact," and the like do not imply a direct contact to the touch screen, but rather a nearby or near contact. The touch panel 104-1 capable of floating touch can be implemented by using capacitive type, infrared light sensing, ultrasonic wave, and the like. In addition, the touch pad 104-1 can be implemented by various types, such as resistive, capacitive, infrared, and surface acoustic wave. Display (also referred to as a display screen) 104-2 may be used to display information entered by or provided to the user as well as various menus for handset 100. The display 104-2 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The trackpad 104-1 may be overlaid on the display 104-2, and when the trackpad 104-1 detects a touch event thereon or nearby, it is communicated to the processor 101 to determine the type of touch event, and the processor 101 may then provide a corresponding visual output on the display 104-2 based on the type of touch event. Although in FIG. 2, the touch pad 104-1 and the display screen 104-2 are shown as two separate components to implement the input and output functions of the cell phone 100, in some embodiments, the touch pad 104-1 and the display screen 104-2 may be integrated to implement the input and output functions of the cell phone 100. It is understood that the touch screen 104 is formed by stacking multiple layers of materials, and only the touch pad (layer) and the display screen (layer) are shown in the embodiment of the present application, and other layers are not described in the embodiment of the present application. In addition, in some other embodiments of the present application, the touch pad 104-1 may be covered on the display 104-2, and the size of the touch pad 104-1 is larger than that of the display screen 104-2, so that the display screen 104-2 is completely covered under the touch pad 104-1, or the touch pad 104-1 may be disposed on the front surface of the mobile phone 100 in a full-panel manner, that is, the touch of the user on the front surface of the mobile phone 100 can be sensed by the mobile phone, so that the full-touch experience on the front surface of the mobile phone can be achieved. In other embodiments, the touch pad 104-1 is disposed on the front surface of the mobile phone 100 in a full-panel manner, and the display screen 104-2 may also be disposed on the front surface of the mobile phone 100 in a full-panel manner, so that a Bezel-free (Bezel) structure can be implemented on the front surface of the mobile phone.

In the embodiment of the present application, the mobile phone 100 may further have a fingerprint recognition function. For example, the fingerprint acquisition device 112 may be configured in the touch screen 104 to implement the fingerprint identification function, i.e., the fingerprint acquisition device 112 may be integrated with the touch screen 104 to implement the fingerprint identification function of the mobile phone 100. In this case, the fingerprint acquisition device 112 is disposed in the touch screen 104, may be a part of the touch screen 104, and may be disposed in the touch screen 104 in other manners. Additionally, the fingerprint acquisition device 112 may also be implemented as a full panel fingerprint acquisition device. Thus, the touch screen 104 can be viewed as a panel that can be fingerprinted anywhere. The fingerprint acquisition device 112 may send the acquired fingerprint to the processor 101 for processing (e.g., fingerprint verification, etc.) by the processor 101. The main component of the fingerprint acquisition device 112 in the present embodiment is a fingerprint sensor, which may employ any type of sensing technology, including but not limited to optical, capacitive, piezoelectric, or ultrasonic sensing technologies, among others.

The handset 100 may also include a bluetooth device 105 for enabling data exchange between the handset 100 and other short-range terminals (e.g., cell phones, smart watches, etc.). The bluetooth device in the embodiment of the present application may be an integrated circuit or a bluetooth chip.

The handset 100 may also include at least one sensor 106, such as a light sensor, motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor that adjusts the brightness of the display of the touch screen 104 according to the brightness of ambient light, and a proximity sensor that turns off the power of the display when the mobile phone 100 is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone 100, further description is omitted here.

The Wi-Fi device 107 is used for providing network access for the mobile phone 100 according to Wi-Fi related standard protocols, the mobile phone 100 can be accessed to a Wi-Fi access point through the Wi-Fi device 107, so that the mobile phone helps a user to send and receive e-mails, browse webpages, access streaming media and the like, and wireless broadband internet access is provided for the user. In other embodiments, the Wi-Fi device 107 can also act as a Wi-Fi wireless access point and can provide Wi-Fi network access to other terminals.

And a positioning device 108 for providing a geographical position for the handset 100. It is understood that the positioning device 108 may be a receiver of a Global Positioning System (GPS) or a positioning system such as the beidou satellite navigation system, russian GLONASS, etc. After receiving the geographical location transmitted by the positioning system, the positioning device 108 transmits the information to the processor 101 for processing or transmits the information to the memory 103 for storage. In still other embodiments, the positioning device 108 may also be a receiver of an Assisted Global Positioning System (AGPS) that assists the positioning device 108 in performing ranging and positioning services by acting as an assistance server, in which case the assistance positioning server provides positioning assistance by communicating with the positioning device 108 (i.e., GPS receiver) of the terminal, such as the handset 100, over a wireless communication network. In other embodiments, the location device 108 may also be a Wi-Fi access point based location technology. Each Wi-Fi access point has a globally unique MAC address, so that the terminal can scan and collect broadcast signals of the surrounding Wi-Fi access points under the condition of starting Wi-Fi, and the MAC address broadcasted by the Wi-Fi access points can be acquired; the terminal sends the data (such as the MAC address) capable of indicating the Wi-Fi access point to the location server through the wireless communication network, the location server retrieves the geographical location of each Wi-Fi access point, and calculates the geographical location of the terminal according to the strength of the Wi-Fi broadcast signal and sends the geographical location of the terminal to the positioning device 108 of the terminal.

The audio circuitry 109, speaker 113, microphone 114 can provide an audio interface between a user and the handset 100. The audio circuit 109 may transmit the electrical signal converted from the received audio data to the speaker 113, and convert the electrical signal into a sound signal by the speaker 113 for output; on the other hand, the microphone 114 converts the collected sound signal into an electrical signal, converts the electrical signal into audio data after being received by the audio circuit 109, and outputs the audio data to the RF circuit 102 to be transmitted to, for example, another cellular phone, or outputs the audio data to the memory 103 for further processing.

Peripheral interface 110, which is used to provide various interfaces for external input/output devices (e.g., keyboard, mouse, external display, external memory, SIM card, etc.). For example, a mouse via a Universal Serial Bus (USB) interface, and a subscriber identity module card (SIM) card provided by a telecommunications carrier via metal contacts on a SIM card slot. Peripheral interface 110 may be used to couple the aforementioned external input/output peripherals to processor 101 and memory 103.

The mobile phone 100 may further include a power supply device 111 (such as a battery and a power management chip) for supplying power to each component, and the battery may be logically connected to the processor 101 through the power management chip, so as to implement functions of managing charging, discharging, and power consumption through the power supply device 111.

Although not shown in fig. 2, the mobile phone 100 may further include a camera (front camera and/or rear camera), a flash, a micro-projector, a Near Field Communication (NFC) device, and the like, which are not described in detail herein.

As is known, as the terminal is used for a longer time, the file reading, writing and erasing operations are repeated, so that the continuous free storage space in the flash memory storage device of the terminal is smaller and smaller, and thus the same file cannot be stored in the continuous free storage space in a whole, but is scattered into a plurality of fragments to be stored in different free storage spaces of the flash memory storage device. After deletion of files of sizes 32KB and 16KB, 48KB of free memory is formed, however the physical addresses of the 48KB of free memory may not be contiguous. If a file 1 with a size of 48KB is to be newly written, the file 1 needs to be split into 2 blocks (i.e. the size of the file block 1 is 32KB, and the size of the file 2 is 16KB), the file block 1 needs to be written into a free storage space with a size of 32KB, and the file block 2 needs to be written into a free storage space with a size of 16 KB. Thus, when reading the 48KB file, the subsequent terminal needs to respectively read the file in two different storage spaces. Compared with the reading of a single storage space, the number of times of reading files is increased, so that the reading and writing performance is sharply reduced. In order to solve the above problem, the present application document proposes a terminal defragmentation method.

In the terminal defragmentation method provided in the embodiments of the present application, the steps executed by the management device may also be executed by a chip applied to the management device, the steps executed by the flash memory controller may also be executed by a chip applied to the flash memory controller, and the following embodiments take the flash memory controller and the management device as an example of an execution subject.

As shown in fig. 3, fig. 3 illustrates a terminal defragmentation method provided in an embodiment of the present application, where the method is applied to a terminal having a management device and a flash memory device, where the flash memory device includes a flash memory controller and a storage medium, the storage medium includes Q storage blocks, Q is an integer greater than or equal to 1, and the method includes:

step 101, the management device determines that the system performance of the terminal is less than or equal to a preset threshold.

Illustratively, the management device may include a processor and a storage controller. The management device may be a chip with a memory controller. For example, the management device may be a system on chip (SoC). Step 101 may specifically be performed by a processor.

Specifically, in the actual use process, the management device determines that the terminal system is in the stuck scene, and the management device executes step 101. For example, when the terminal is used for a long time, the application start time on the terminal is longer than the preset time, or the frame drop occurs when the application is switched back and forth or the internal refresh of the application occurs, the management device determines that the terminal system is in a stuck scene.

Optionally, the management device may also determine, according to an operation instruction input by the user, that the system performance of the terminal is less than or equal to the preset threshold. For example, a user may check the storage condition of the flash memory device according to the usage condition of the terminal or according to a preset period, and if the user determines that the storage space of the flash memory device is smaller than expected, an operation instruction for managing that the device needs to perform performance recovery on the terminal to trim the fragmented files in the flash memory device may be input to the terminal.

Step 102, the management device controls the terminal to be in a performance recovery mode.

When the terminal is in the performance recovery mode (restore _ performance), the terminal temporarily disables a read operation, a write operation, or a delete operation with respect to the flash memory device. When the terminal is in the performance recovery mode, the flash memory device is in an idle state. It is to be understood that the flash memory device may defragment the fragmented files in the flash memory device when the terminal is in the performance recovery mode.

Step 103, the management device sends a first operation instruction to the flash memory controller, where the first operation instruction is used to instruct the flash memory controller to organize the storage space of the storage medium.

Specifically, the processor of the management device may send the first operation instruction to the storage controller, so that the storage controller sends the first operation instruction to the flash memory controller.

Step 104, when the terminal is in the performance recovery mode, the flash memory controller receives the first operation instruction sent by the management device.

Step 105, in response to the first operation instruction, the flash memory controller determines a plurality of fragmented files stored in M of the Q storage blocks; q is more than or equal to M and more than or equal to 1, and M is an integer. The corresponding first physical addresses of the plurality of fragmented files in the M memory blocks are not continuous.

In the embodiment of the application, when a plurality of fragmented files are stored in M storage blocks, each fragmented file in the plurality of fragmented files corresponds to a first physical address. The first physical address of any one of the fragmented files is a physical address when the any one of the fragmented files is stored in the M memory blocks.

The sum of the sizes of the fragment files stored in any one of the M storage blocks is smaller than the size of the storage space of the any one storage block. In this embodiment of the present application, one fragmented file may be stored in one storage block, and certainly two or more fragmented files may also be stored in one storage block, when two or more fragmented files are stored in the same storage block, corresponding first physical addresses of the two or more fragmented files in the storage block are not consecutive.

Illustratively, as shown in fig. 4, the size of each of the storage blocks 1 to 4 is 256KB, the size of the fragment file 1 is 4KB, the size of each of the fragment file 2 and the fragment file 3 is 8KB, the size of the fragment file 4 is 16KB, the fragment file 1 is stored in the storage block 1, the fragment file 2 is stored in the storage block 2, the fragment file 3 is stored in the storage block 3, and the fragment file 4 is stored in the storage block 4.

Step 106, the flash memory controller stores the plurality of fragmented files in N storage blocks of the Q storage blocks according to the sizes of the plurality of fragmented files, wherein M is larger than or equal to N and larger than or equal to 1, N is an integer, and corresponding second physical addresses of the plurality of fragmented files in the N storage blocks are continuous.

In this embodiment of the present application, the second physical address of any one of the fragmented files is a physical address when any one of the fragmented files is stored in the N storage blocks.

As a possible implementation manner, step 106 in the embodiment of the present application may be implemented by: the flash memory controller may keep a target fragmented file of the fragmented files still and migrate the remaining fragmented files according to the sizes of the fragmented files, so that the fragmented files are stored in the N storage blocks. At this time, the N storage blocks include the storage block stored in the target fragmented file.

Illustratively, the size of the target fragmented file in the plurality of fragmented files satisfies a preset threshold. For example, the target fragmented file is the fragmented file with the smallest fragmented file size among the plurality of fragmented files, or the target fragmented file is the fragmented file with the largest fragmented file size among the plurality of fragmented files.

For example, as shown in fig. 5, the flash memory controller may keep the fragment file 1 stored in the storage block 1 still, migrate the fragment file 2 from the storage block 2 to the storage block 1, migrate the fragment file 3 from the storage block 3 to the storage block 1, migrate the fragment file 4 from the storage block 4 to the storage block 1, and finally store the fragment files 1 to 4 in the storage block 1.

As another possible implementation manner, step 106 in the embodiment of the present application may be implemented by: the flash memory controller can select N unoccupied memory blocks from the Q memory blocks, and then merge and arrange the plurality of fragmented files to be stored in the N unoccupied memory blocks. I.e. the N memory blocks are unoccupied memory blocks.

It should be understood that if the sum of the sizes of one or more file shards is less than or equal to the size of any of the Q storage blocks, a plurality of shard files may be stored into one storage block a. When N is 1. If the sum of the size of one or more file shards is greater than the size of one storage block, the one or more file shards may be stored in two or more storage blocks. It should be noted that, if the size of one fragmented file a is larger than the remaining storage space of the storage block 1, the fragmented file a may be split into 2 parts, where one part is stored in the remaining storage space of the storage block 1, and the other part is stored in the storage space of the storage block 2.

As still another possible implementation manner, step 106 in the embodiment of the present application may be implemented by: the flash memory controller determines a first target storage block in the M storage blocks, wherein the residual storage space of the first target storage block is the largest of the M storage blocks, and then the flash memory controller enables the file fragments stored in the first target storage block to be stored in the first target storage block continuously, and the fragment files in the rest storage blocks except the first target storage block in the M storage blocks are migrated to the first target storage block and a second target storage block. At this time, the number of the first target memory blocks and the second target memory blocks is N. The second target storage block is a storage block in the M storage blocks or the second target storage block is an unoccupied storage block in the Q storage blocks or a storage block with the largest remaining space in the Q storage blocks.

It should be noted that, the specific steps of causing the flash memory controller to store the file fragments stored in the first target storage block into the first target storage block are: if the file fragment stored in the first target storage block includes a plurality of fragment files having discontinuous addresses, the flash memory controller needs to make the addresses of the plurality of fragment files in the first target storage block continuous.

For example, the M storage blocks include a storage block 1, a storage block 2, and a storage block 3, where the storage block 1 stores a shard file 1-1, a shard file 1-2, the storage block 2 has a shard file 2-1, a shard file 2-2, and the storage block 3 has a shard file 3-1 and a shard file 3-2. If the remaining space of the storage block 1 is the largest, the flash memory controller may determine to keep the fragmented files 1-1 and 1-2 stored in the storage block 1, and store the fragmented files 2-1, 2-2, 3-1, and 3-2 in the remaining space of the storage block 1 as much as possible. When the remaining space of the storage block 1 is not enough to store the fragmented file 2-1, the fragmented file 2-2, the fragmented file 3-1, and the fragmented file 3-2, fragmented files that are not stored in the remaining space of the storage block 1 may be stored in the second target storage block.

It should be noted that, in an actual process, a plurality of fragmented files may be stored in one storage block, but the first physical addresses between the plurality of fragmented files are not consecutive, so that a newly written fragmented file cannot be stored between any two fragmented files. For this case, the flash memory controller may further migrate the plurality of fragmented files with discontinuous first physical addresses stored in the same storage block, so that the first physical addresses of the plurality of fragmented files stored in the same storage block after migration are continuous. As shown in fig. 6: the fragment files 1, 2 and 3 are stored in the storage block 1, but the first physical addresses corresponding to the fragment files 1, 2 and 3 are not consecutive, which also causes the storage space of the storage block 1 to be wasted, so that the flash memory controller may migrate the fragment files 2 and 3 to make the first physical addresses of the fragment files 1, 2 and 3 in the storage block 1 consecutive, and migrate the storage block 3 into the storage block 1.

As a possible implementation manner of the embodiment of the present application, as shown in fig. 7, step 102 in the embodiment of the present application may be specifically implemented by:

step 1021, the management device displays a first prompt message on a display screen of the terminal, wherein the first prompt message is used for prompting whether the user agrees to the performance recovery mode or not.

As shown in fig. 8, in the case where the management apparatus determines that the terminal is in system stuck, the management apparatus prompts the user on the display interface of the display screen of the terminal with the contents in the dialog 18 shown in fig. 8: whether to approve entering a performance recovery mode.

Step 1022, the management device determines that an instruction confirming entering the performance recovery mode is received from the user, and the management device controls the terminal to be in the performance recovery mode.

As shown in fig. 8, in the case where the management apparatus determines that the terminal is in system stuck, the management apparatus prompts the user on the display interface of the display screen of the terminal with the contents in the dialog 18 shown in fig. 8: whether to approve entering a performance recovery mode. If it is determined that the user selection 'yes' indicates that the user agrees to enter the performance recovery mode, the management apparatus may immediately control the terminal to be in the performance recovery mode. If it is determined that the user selection "no" indicates that the user does not agree to enter the performance recovery mode, the management device may suspend performing step 102. If it is determined that the user selects "defer" to indicate that the user agrees to enter the performance recovery mode for a specified period of time, the management device may control the terminal to be in the performance recovery mode when the specified period of time is reached. In the embodiment of the application, if the terminal selects "defer", further, the management device may further display a time period for agreeing to "defer" on the display screen. The time period for granting "defer" may be prestored by the management device, but may also be autonomously input by the user as shown in fig. 9. The embodiments of the present application do not limit this. Fig. 8 and 9 take the example that the user receives the first prompting message when using the terminal. Of course, as shown in fig. 10, the management apparatus may also display the first prompt message on the display screen when the user does not use the terminal. And if the user agrees to enter the performance recovery mode, the management equipment controls the terminal to immediately enter the performance recovery mode according to the received recovery operation instruction from the user.

The terminal is restarted to enter a performance recovery mode, and only a small system part is started, that is, only the most basic functions of the terminal are started, such as initialization operations of a processor (CPU), a Double Data Rate SDRAM (DDR memory), a Liquid Crystal Display (LCD), a touch screen (TP), and other core devices, and all operations are completed in the memory.

It should be noted that, in the embodiment of the present application, the management apparatus may execute step 1021 and step 1022 when the user is in the non-sleep time period. The so-called non-sleep period may be determined in conjunction with the work and rest of the user using the terminal. For example, the early 7: 00-late 23:00 may be taken as a non-sleep period.

It should be noted that, if the management device determines that the system performance of the terminal is less than or equal to the preset threshold, the management device may also autonomously determine to control the terminal to be in the performance recovery mode without user confirmation in the sleep time period of the user. For example, the sleep period may be 1: 00-6 a.m.: 59.

for example, the management apparatus may analyze a sleep time period of the user according to daily work and rest of the user using the terminal. Of course, the terminal may also determine whether the user is in a sleep state in combination with information reflected by an application corresponding to the wearable device installed on the management device. For example, the management device determines if the user is in a sleep state if the application reflects that the user entered a sleep mode.

Please continue to refer to fig. 7, which is another embodiment of the present application, a method provided in the embodiment of the present application further includes:

and 107, the management device displays a second prompt message on a display screen of the terminal, wherein the second prompt message is used for prompting that the user cannot forcibly operate the terminal when the terminal is in the performance recovery mode. For example, to prompt that a power-on cannot be forced.

For example, as shown in fig. 11, in the process that the management device determines that the flash memory controller arranges the storage space, the management device displays a prompt message on the display screen of the terminal: for prompting the user to refrain from other operations during the terminal being in the performance recovery mode.

That is, in the process of arranging the fragmented files by the flash memory controller, the management device may display the second prompt message on the display screen of the terminal.

As a possible implementation manner, as shown in fig. 7, step 105 in the embodiment of the present application may be specifically implemented by the following manner:

in step 1051, the flash memory controller determines the storage location of each fragmented file in the storage block where the fragmented file is located.

As a possible implementation manner, step 1051 in the embodiment of the present application may be specifically implemented by the following processes:

in the process 1, the flash memory controller determines a first Physical Address (PA) corresponding to each fragmented file. The first physical address of each fragmented file is the corresponding physical address of each fragmented file when a plurality of fragmented files are stored in the M memory blocks.

Wherein the physical address corresponding to any one of the fragmented files may be used to determine the specific storage locations where the fragmented file is scattered across the stored memory blocks on the flash memory storage device.

In this embodiment of the present application, the first physical address corresponding to each fragmented file may not be consecutive.

In this embodiment of the present application, a first physical address corresponding to each of a plurality of fragmented files is a physical address corresponding to each of the fragmented files when the plurality of fragmented files are stored in M storage blocks. For example, taking the plurality of fragmentation files including fragmentation file 1 and fragmentation file 2, fragmentation file 1 being 4kB in size and fragmentation file 2 being 8kB in size, fragmentation file 1 being stored in storage block 1 and fragmentation file 2 being stored in storage block 2, if storage block 1 and storage block 2 are 128kB in size, storage block 1 corresponds to an address 0000000000-: 0000000000-0000000011. The first physical address corresponding to the fragmented file 2 may be: 0010000000-0010000111.

As an example, the process 1 in the embodiment of the present application may be implemented by: the flash memory controller determines a Logical Address (LA) corresponding to each fragmented file. And the flash memory controller determines a first physical address corresponding to each fragmented file according to the address mapping table and the logical address corresponding to each fragmented file. The address mapping table at least comprises a mapping relation between a logical address corresponding to each fragmented file and a first physical address of each fragmented file.

In this embodiment, when multiple fragmented files correspond to the same file, the first physical addresses corresponding to the multiple fragmented files may not be consecutive, but the logical addresses of the multiple fragmented files corresponding to the same file may be consecutive or may not be consecutive. For example, fragmentation file 1 corresponds to logical address 1, fragmentation file 2 corresponds to logical address 2, and logical address 1 and logical address 2 are consecutive.

After the fragmented files are stored in the flash memory storage device, the file system may assign a logical address to each fragmented file, and the logical addresses of the fragmented files belonging to the same file may be continuous or discontinuous.

In the embodiment of the application, an address mapping table is stored in the flash memory controller. This address mapping table may also be referred to as: a logical address/physical address mapping translation table.

For another example, in the embodiment of the present application, the process 1 may be specifically implemented in the following manner: the flash memory controller determines a starting physical address corresponding to each fragmented file, and the flash memory controller determines a first physical address corresponding to each fragmented file according to the size of each fragmented file. For example, if the starting physical address of the fragment file 1 is 0000000000 and the size of the fragment file 1 is 4kB, the flash memory controller may determine that the first physical address of the fragment file 1 may be: 0000000000-0000000011.

And 2, determining the storage position of each fragmented file in the storage block where each fragmented file is located according to the respective first physical address of each fragmented file by the flash memory controller.

Step 1052, the flash controller determines a plurality of fragmented files stored in the storage medium according to the storage location of each fragmented file in the respective storage block.

As shown in fig. 7, in order to enable a processor to correctly read a plurality of fragmented files, as another embodiment of the present application, a method provided by an embodiment of the present application further includes:

step 108, the flash controller determines a second physical address of each fragmented file in the N storage blocks.

For example, with reference to fig. 5, after migrating file fragment 2 from storage block 2 to storage block 1 with the physical address corresponding to storage block 1 being 0000000000-.

Step 109, the flash memory controller updates the address mapping table according to the second physical address corresponding to each fragmented file. Wherein, the updated address mapping table at least comprises: and mapping relation between the second physical address corresponding to each fragmented file and the logical address corresponding to each fragmented file.

As another embodiment of the present application, with continuing reference to fig. 7, a method provided by an embodiment of the present application further includes:

step 110, the management device sends an inquiry command to the flash memory controller periodically according to a preset period, where the inquiry command is used to inquire whether the flash memory controller finishes sorting the storage space of the storage medium.

For example, the preset period may be 10 seconds.

Step 111, the flash memory controller receives the query command sent by the management device.

For example, after the flash memory controller receives the first operation instruction, the flash memory controller may start a monitor process for receiving the query command, where the monitor process is in a suspended state. Specifically, the monitoring process receives the query command, returns to the current state if the sorting is not completed, and determines whether the current state is completed, and if the current state is not completed, the monitoring process continues to be in the suspended state, and if the current state is completed, the flash memory device is directly restarted.

Specifically, after receiving the query command, if it is determined that the storage space of the storage medium is not sorted, the flash memory controller may send a query response to the management device, where the query response is used to indicate a progress of sorting the storage space of the storage medium by the flash memory controller. For example, the finishing schedule is 60%, or the finishing schedule is 40%.

In step 112, the flash memory controller determines whether the fragmented files stored in the storage medium are sorted. If the storage space of the storage medium is completely sorted, the flash memory controller executes step 113, and if the storage space of the storage medium is not completely sorted, executes step 114.

Step 113, the flash memory controller sends a query response to the management device. The query response is used to indicate that the storage space of the storage medium has been cleared up.

Step 114, the flash memory controller sends an inquiry response to the management device, where the inquiry response is used to indicate that the storage space of the storage medium is not sorted.

Step 115, the management device receives a query response sent by the flash memory device, where the query response is used to indicate that the storage space of the storage medium has been sorted, or the query response is used to indicate that the storage space of the storage medium has not been sorted.

Step 116, the management device determines that the flash memory controller finishes sorting the fragmented files stored in the storage medium, and the management device controls the terminal to exit the performance recovery mode and controls the terminal to be powered on.

For example, as shown in fig. 12, if the management device determines that the flash memory controller does not sort the storage space of the storage medium, the management device may display, on a display screen of the terminal, according to a query response indicating a progress of the flash memory controller in sorting the storage space of the storage medium: the behavior resumes the typeface of progress. Of course, the performance recovery progress may also be displayed in the form of a progress bar.

As another embodiment of the present application, as shown in fig. 7, the method provided in this embodiment of the present application may further include, after step 106:

step 117, when any one of the fragmented files changes from the first physical address to the second physical address, the flash memory controller erases the data stored in the storage space corresponding to the first physical address.

Illustratively, as shown in fig. 4, after the fragmented files 2 to 4 are migrated into the storage block 1, but the fragmented files 2 to 4 are still stored in the storage blocks 2 to 4, in order to avoid the duplication of fragmented files, the fragmented files stored in the storage blocks 2 to 4 need to be deleted to increase the continuous storage space in the storage medium.

It should be noted that, in the file migration process in this embodiment, taking fig. 5 as an example, if the location of the fragmented file 1 is not changed, if the fragmented files 2, 3, and 4 are to be written into the storage block 1, the fragmented file 1 may be read first, then the fragmented file 1 in the storage block 1 is erased, and then the fragmented file 1 and other files are written into the blank (erased) storage block 1 together.

The above-mentioned scheme of the embodiment of the present application is introduced mainly from the perspective of interaction between network elements. It will be appreciated that various network elements, such as flash memory storage devices, management devices, etc., which implement the above-described functions, include corresponding hardware structures and/or software modules for performing the various functions. Those of skill in the art would readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the flash memory device and the management device may be exemplified according to the above method to divide the functional units, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

The method of the embodiment of the present application is described above with reference to fig. 1 to 7, and a terminal defragmentation apparatus for performing the method provided by the embodiment of the present application is described below. Those skilled in the art will appreciate that the method and apparatus can be combined and referred to, and the terminal defragmentation apparatus provided in the embodiments of the present application can perform the steps performed by the flash memory storage device and the management device in the terminal defragmentation method described above.

In case of an integrated unit, fig. 13 shows a terminal defragmentation device according to the above embodiments, which may comprise: communication unit 102, processing unit 101. Optionally, the terminal defragmentation device may further include a storage unit, where the storage unit is configured to store applications, pictures, and the like of the terminal.

In one example, the terminal defragmentation device is a flash memory storage device, or a chip applied in a flash memory storage device. In this case, the communication unit 102 is configured to support the terminal defragmentation device to perform the step 104 performed by the flash memory storage device in the above-described embodiment. The processing unit 101 is adapted to support the terminal defragmentation device to perform the

steps

105 and 106 as performed by the flash memory storage device in the above described embodiment.

In a possible implementation, the processing unit 101 is configured to enable the terminal defragmentation device to perform the steps 1051, 1052 performed by the flash memory storage device in the above embodiments.

In a possible embodiment, the processing unit 101 is further configured to enable the terminal defragmentation device to perform

steps

109, 112, and 117 as performed by the flash memory storage device in the above-described embodiment. The communication unit 102 is further configured to support the terminal defragmentation device to perform

steps

111, 113, and 114 performed by the flash memory device in the above embodiments.

In another example, the terminal defragmentation device is a management device or a chip applied to the management device. In this case, the communication unit 102 is configured to support the terminal defragmentation device to perform step 103 performed by the management apparatus in the above-described embodiment. Or the processing unit 101, is configured to support the terminal defragmentation device to perform step 101 and step 102, which are performed by the management apparatus in the above embodiments.

In a possible implementation, the processing unit 101 is configured to support the terminal defragmentation apparatus to perform steps 1021, 1022 performed by the management device in the above embodiment.

In a possible embodiment, the processing unit 101 is configured to support the terminal defragmentation device to perform the steps 107, 116 performed by the management apparatus in the above-described embodiment. The communication unit 102 is further configured to support the terminal defragmentation device to perform steps 110 and 115 performed by the management apparatus in the foregoing embodiment.

In case of an integrated unit, fig. 14 shows a schematic diagram of a possible logical structure of the terminal defragmentation device as referred to in the above embodiments. This terminal defragmentation device includes: a processing module 112 and a communication module 113. The processing module 112 is used for controlling and managing the actions of the terminal defragmentation devices, for example, the processing module 112 is used for executing the steps of information/data processing in the terminal defragmentation devices. The communication module 113 is used to support the terminal defragmentation device to perform the steps of information/data transmission or reception.

In a possible embodiment, the terminal defragmenter may further comprise a storage module 111 for storing program code and data available to the terminal defragmenter.

In one example, the terminal defragmentation device is a flash memory storage device, or a chip applied in a flash memory storage device. In this case, the communication module 113 is used to support the terminal defragmenter to perform the step 104 performed by the flash memory storage device in the above embodiment. The processing module 112 is used to support the terminal defragmentation device to perform the

steps

105 and 106 performed by the flash memory storage device in the above embodiments.

In a possible implementation, the processing module 112 is configured to support the terminal defragmenter to perform the steps 1051 and 1052 performed by the flash memory device in the above embodiments.

In a possible embodiment, the processing module 112 is further configured to support the terminal defragmenter to perform

steps

109, 112, and 117 performed by the flash memory storage device in the above embodiment. The communication module 113 is further configured to support the terminal defragmentation device to perform

steps

111, 113, and 114 performed by the flash memory device in the foregoing embodiment.

In another example, the terminal defragmentation device is a management device or a chip applied to the management device. In this case, the communication module 113 is configured to support the terminal defragmentation device to perform step 103 performed by the management apparatus in the above embodiment. Or the processing module 112, is configured to support the terminal defragmentation device to perform step 101 and step 102 performed by the management apparatus in the foregoing embodiments.

In a possible implementation, the processing module 112 is configured to support the terminal defragmentation apparatus to perform steps 1021, 1022 performed by the management device in the above embodiment.

In a possible embodiment, the processing module 112 is configured to support the terminal defragmentation device to perform the steps 107, 116 performed by the management apparatus in the above embodiments. The communication module 113 is further configured to support the terminal defragmentation device to perform step 110 and step 115, which are performed by the management device in the foregoing embodiment.

The processing module 112 may be a processor or controller, such as a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. A processor may also be a combination of computing functions, e.g., a combination of one or more microprocessors, a digital signal processor and a microprocessor, or the like. The communication module 113 may be a communication interface or the like. The storage module 111 may be a memory.

When the processing module 112 is the processor 41 or the processor 45, the communication module 113 is the communication interface 43, and the storage module 111 is the memory 42, the terminal defragmentation device according to the present application may be the communication apparatus shown in fig. 15.

As shown in fig. 15, fig. 15 is a schematic diagram illustrating a hardware structure of a communication device according to an embodiment of the present application. The hardware structure of the flash memory storage device and the management device in the embodiment of the present application may refer to the structure shown in fig. 15. The communication device comprises a processor 41, a communication line 44 and at least one communication interface 43.

The processor 41 may be a general-purpose Central Processing Unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs in accordance with the present disclosure.

The communication link 44 may include a path for transmitting information between the aforementioned components.

The communication interface 43, using any transceiver or like device, is used for communicating with other devices or communication networks.

Optionally, the communication device may also include a memory 42.

The memory 42 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be separate and coupled to the processor via a communication line 44. The memory may also be integral to the processor.

The memory 42 is used for storing computer-executable instructions for executing the present application, and is controlled by the processor 41 to execute. The processor 41 is configured to execute computer-executable instructions stored in the memory 42, so as to implement the terminal defragmentation method provided in the following embodiments of the present application.

Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.

In particular implementations, processor 41 may include one or more CPUs such as CPU0 and CPU1 in fig. 15, for example.

In particular implementations, the communication device may include multiple processors, such as processor 41 and processor 45 in fig. 15, as one embodiment. Each of these processors may be a single core processor or a multi-core processor.

In one example, the communication device is a flash memory storage device, or a chip applied in a flash memory storage device. In this case, the communication interface 43 is used to support the communication device to perform the step 104 performed by the flash memory storage device in the above-described embodiment, and the processor 41 and the processor 45 are used to support the communication device to perform the

steps

105 and 106 performed by the flash memory storage device in the above-described embodiment.

In one possible implementation, the processor 41 and the processor 45 are configured to enable the communication device to perform the steps 1051 and 1052 performed by the flash memory device in the above embodiments.

In one possible embodiment, processor 41 and processor 45 are further configured to enable the communication device to perform

steps

109, 112, and 117 performed by the flash memory storage device in the above-described embodiment. The communication interface 43 is further configured to support the communication device to perform

steps

As another example, the communication device is a management device or a chip applied to the management device. In this case, the communication interface 43 is used to support the communication device to perform the step 103 performed by the management device in the above embodiment. Or processor 41 and processor 45, for enabling the communication device to perform

steps

101 and 102 as performed by the management device in the above embodiments.

In one possible implementation, the processor 41 and the processor 45 are configured to support the communication device to perform the steps 1021, 1022 performed by the management device in the above embodiment.

In a possible embodiment, the processor 41 and the processor 45 are configured to enable the communication device to perform the steps 107, 116 performed by the management device in the above-described embodiment. The communication interface 43 is further configured to support the communication device to perform the steps 110 and 115 performed by the management device in the foregoing embodiment.

Fig. 16 is a schematic structural diagram of a chip 150 according to an embodiment of the present disclosure. Chip 150 includes one or more (including two) processors 1510 and a communication interface 1530.

Optionally, the chip 150 further includes a memory 1540, which may include both read-only memory and random access memory, and provides operating instructions and data to the processor 1510. A portion of memory 1540 may also include non-volatile random access memory (NVRAM).

In some embodiments, memory 1540 stores elements, execution modules, or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present application, by calling an operation instruction stored in the memory 1540 (the operation instruction may be stored in an operating system), a corresponding operation is performed.

One possible implementation is: the flash memory device, the chip used for the management device are similar in structure, and different devices may use different chips to implement their respective functions.

The processor 1510 controls processing operations of any one of the flash memory storage device and the management device, and the processor 1510 may also be referred to as a Central Processing Unit (CPU).

Memory 1540 can include both read-only memory and random-access memory, and provides instructions and data to processor 1510. A portion of memory 1540 may also include NVRAM. For example, in an application where memory 1540, communications interface 1530 and memory 1540 are coupled together by bus system 1520, where bus system 1520 may include a power bus, control bus, status signal bus, etc. in addition to a data bus. For clarity of illustration, however, the various buses are labeled in fig. 16 as bus system 1520.

The method disclosed in the embodiments of the present application may be applied to the processor 1510 or implemented by the processor 1510. The processor 1510 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by instructions in the form of hardware, integrated logic circuits, or software in the processor 1510. The processor 1510 may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 1540, and the processor 1510 reads the information in the memory 1540, and performs the steps of the above method in combination with the hardware thereof.

In one possible implementation, communication interface 1530 is used to perform the steps of receiving and transmitting of flash memory storage devices, management devices in the embodiments shown in FIGS. 1-6. The processor 1510 is used to perform the steps of the processing of the flash memory storage device, the management device, in the embodiment shown in fig. 1-6.

The above communication unit may be a communication interface of the device for receiving signals from other devices. For example, when the device is implemented in the form of a chip, the communication unit is a communication interface for the chip to receive signals from other chips or devices or to transmit signals.

In one aspect, a computer-readable storage medium is provided, in which instructions are stored, and when executed, implement the functions of the flash memory storage device in fig. 3 and 7.

In another aspect, a computer-readable storage medium is provided, in which instructions are stored, and when executed, implement the functions of the management device as in fig. 3 and 7.

In one aspect, a computer program product comprising instructions is provided, the computer program product comprising instructions that, when executed, implement the functionality of a flash memory storage device as in fig. 3 or fig. 7.

In a further aspect, a computer program product comprising instructions is provided, the computer program product comprising instructions that when executed implement the functionality of the management device as in fig. 3, 7.

In one aspect, a chip is provided, the chip is applied in a flash memory device, the chip includes at least one processor and a communication interface, the communication interface is coupled with the at least one processor, and the processor is used for executing instructions to implement the functions of the flash memory device in fig. 3 or fig. 7.

In still another aspect, a chip is provided, where the chip is applied to a management device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled to the at least one processor, and the processor is configured to execute instructions to implement the functions of the management device as in fig. 3 or fig. 7.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and figures are merely exemplary of the present application as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include such modifications and variations.

Claims

1. A terminal defragmentation method is characterized in that the method is applied to a terminal with a flash memory storage device and a management device, wherein the flash memory storage device comprises a flash memory controller and a storage medium, the storage medium comprises Q storage blocks, and Q is an integer greater than or equal to 1; the method comprises the following steps:

when the terminal is in a performance recovery mode, the flash memory controller receives a first operation instruction sent by the management device; the first operation instruction is used for instructing the flash memory controller to arrange a storage space of the storage medium;

in response to the first operating instruction, the flash controller determining a plurality of fragmented files stored in M of the Q memory blocks; q is more than or equal to M and more than or equal to 1, and M is an integer; corresponding first physical addresses of the plurality of fragmented files in the M storage blocks are not continuous;

the flash memory controller stores the plurality of fragmented files in N storage blocks of the Q storage blocks according to the sizes of the plurality of fragmented files; m is larger than or equal to N and larger than or equal to 1, N is an integer, and the corresponding second physical addresses of the plurality of fragment files in the N storage blocks are continuous.

2. The method of claim 1, wherein the flash controller determining a plurality of fragmented files stored in M of the Q memory blocks comprises:

the flash memory controller determines the storage position of each fragmented file in the plurality of fragmented files in the storage block where the fragmented file is located;

and the flash controller determines the plurality of fragmented files stored in the M storage blocks according to the storage positions of the fragmented files in the storage blocks where the fragmented files are respectively located.

3. The method of claim 2, wherein the determining, by the flash controller, a storage location of each of the plurality of fragmented files in the respective storage block comprises:

the flash memory controller determines a first physical address corresponding to each fragment file;

and the flash memory controller determines the storage position of each fragment file in the storage block where the fragment file is located according to the first physical address corresponding to each fragment file.

4. The method of claim 3, wherein the determining, by the flash controller, the first physical address corresponding to each fragmented file comprises:

the flash memory controller determines a logical address corresponding to each fragment file;

the flash memory controller determines a first physical address corresponding to each fragmented file according to an address mapping table and a logical address corresponding to each fragmented file; the address mapping table at least comprises a mapping relation between a logical address corresponding to each fragmented file and a first physical address of each fragmented file.

5. The method of any of claims 1-4, wherein the flash controller stores the plurality of fragmented files in N of the Q memory blocks according to the size of the plurality of fragmented files, and wherein the method further comprises:

the flash memory controller updates an address mapping table according to a second physical address of each fragmented file in the N storage blocks; wherein the updated address mapping table at least comprises: and mapping relation between the second physical address corresponding to each fragmented file and the logical address corresponding to each fragmented file.

6. The method according to any one of claims 1-5, further comprising:

the flash memory controller receives an inquiry command sent by the management device, wherein the inquiry command is used for inquiring whether the flash memory controller finishes arranging the storage space of the storage medium;

and the flash memory controller sends a query response to the management device, wherein the query response is used for indicating the progress of the flash memory controller in sorting the storage space of the storage medium.

7. The method according to any one of claims 1 to 6, wherein when the physical address of any one of the plurality of fragmented files is changed from a first physical address to a second physical address, the method further comprises:

and the flash memory controller erases the fragment file stored in the storage space corresponding to the first physical address.

8. A method for defragmenting a file, applied to a terminal having a flash memory device and a management device, wherein the flash memory device includes a flash memory controller and a storage medium, the storage medium includes Q storage blocks, Q is an integer greater than or equal to 1, and the method includes:

the management equipment determines that the system performance of the terminal is less than or equal to a preset threshold value;

the management equipment controls the terminal to be in a performance recovery mode;

the management equipment sends a first operation instruction to the flash memory controller, wherein the first operation instruction is used for instructing the controller to arrange the storage space of the storage medium.

9. The method of claim 8, wherein the managing device controls the terminal to be in a performance recovery mode, and comprises:

the management equipment displays a first prompt message on a display screen of the terminal, wherein the first prompt message is used for prompting whether a user agrees to enter a performance recovery mode of the terminal;

and the management equipment determines that an instruction for confirming to enter the performance recovery mode is received from the user, and controls the terminal to be in the performance recovery mode.

10. The method according to claim 8 or 9, characterized in that the method further comprises:

and the management equipment displays a second prompt message on a display screen of the terminal, wherein the second prompt message is used for prompting a user that the terminal cannot be operated forcibly when the terminal is in a performance recovery mode.

11. The method according to any one of claims 8-10, further comprising:

the management equipment sends a query command to the flash memory controller according to a preset period, wherein the query command is used for querying whether the flash memory controller finishes arranging the storage space of the storage medium;

and the management equipment receives an inquiry response sent by the flash memory controller, wherein the inquiry response is used for indicating the progress of the flash memory controller in sorting the storage space of the storage medium.

12. The method according to any one of claims 8-11, further comprising:

the management equipment determines that the flash memory controller finishes sorting the storage space of the storage medium;

and the management equipment controls the terminal to exit the performance recovery mode and controls the terminal to be started.

13. A flash memory device is applied to a terminal with a management device, and the flash memory device comprises a flash memory controller and a storage medium, wherein the storage medium comprises Q storage blocks, and Q is an integer greater than or equal to 1; the flash memory controller includes: a processor and a communication interface;

wherein the content of the first and second substances,

the communication interface is used for receiving a first operation instruction sent by the management equipment when the terminal is in a performance recovery mode; the first operation instruction is used for instructing the flash memory controller to arrange a storage space of the storage medium;

in response to the first operational instruction, the processor to determine a plurality of shard files stored in M of the Q memory blocks; q is more than or equal to M and more than or equal to 1, and M is an integer; corresponding first physical addresses of the plurality of fragmented files in the M storage blocks are not continuous;

the processor is further configured to store the plurality of fragmented files in N of the Q storage blocks according to sizes of the plurality of fragmented files; m is larger than or equal to N and larger than or equal to 1, N is an integer, and the corresponding second physical addresses of the plurality of fragment files in the N storage blocks are continuous.

14. The flash memory device of claim 13, wherein the processor is specifically configured to determine a storage location of each of the plurality of fragmented files in the respective storage block, and to determine the plurality of fragmented files stored in the M storage blocks according to the storage location of each of the plurality of fragmented files in the respective storage block.

15. The flash memory device of claim 14, wherein the processor is specifically configured to determine the first physical address corresponding to each fragmented file, and to determine the storage location of each fragmented file in the respective storage block according to the first physical address corresponding to each fragmented file.

16. The flash memory storage device of claim 15, wherein the processor is specifically configured to determine a logical address corresponding to each of the fragmented files; the method comprises the steps of determining a first physical address corresponding to each fragmented file according to an address mapping table and a logic address corresponding to each fragmented file; the address mapping table at least comprises a mapping relation between a logical address corresponding to each fragmented file and a first physical address of each fragmented file.

17. The flash memory storage device of any one of claims 13-16, wherein the processor is further configured to update an address mapping table according to a respective second physical address of each fragmented file in the N memory blocks; wherein the updated address mapping table at least comprises: and mapping relation between the second physical address corresponding to each fragmented file and the logical address corresponding to each fragmented file.

18. The flash memory storage device of any one of claims 13-17, wherein the communication interface is further configured to receive an inquiry command sent by the management device, the inquiry command being used to inquire whether the flash memory controller has finished organizing the storage space of the storage medium;

19. The flash memory device of any of claims 13-18, wherein the processor is further configured to erase the fragmented files stored in the storage space corresponding to the first physical address after the physical address of any of the fragmented files in the plurality of fragmented files is changed from the first physical address to the second physical address.

20. A management device, applied to a terminal having a flash memory storage device including a flash memory controller and a storage medium including Q storage blocks, Q being an integer greater than or equal to 1, the management device comprising:

a processor for determining that a system performance of the terminal is less than or equal to a preset threshold;

the processor is used for controlling the terminal to be in a performance recovery mode;

and the communication interface is used for sending a first operation instruction to the flash memory controller, wherein the first operation instruction is used for indicating the flash memory controller to arrange the storage space of the storage medium.

21. The device of claim 20, wherein the processor is configured to display a first prompt message on a display screen of the terminal, and wherein the first prompt message is configured to prompt a user whether the terminal is approved to enter a performance recovery mode;

the processor is configured to determine that the communication interface receives an instruction confirming entry into the performance recovery mode from the user, and the management device controls the terminal to be in the performance recovery mode.

22. The apparatus of claim 20 or 21, wherein the processor is further configured to display a second prompting message on the display of the terminal, the second prompting message being configured to prompt a user that the terminal cannot be forced to operate during the performance recovery mode of the terminal.

23. The apparatus according to any of claims 20-22, wherein the communication interface is further configured to send a query command to the flash memory controller periodically according to a preset period, the query command being used to query whether the flash memory controller finishes organizing the storage space of the storage medium;

the communication interface is further configured to receive a query response sent by the flash memory controller, where the query response is used to instruct the flash memory controller to sort the progress of the storage space of the storage medium.

24. The apparatus of any of claims 20-23, wherein the processor is further configured to determine that the flash controller is finished organizing the storage space of the storage medium;

the processor is further configured to control the terminal to exit a performance recovery mode, and control the terminal to be powered on.

25. A terminal, characterized in that the terminal comprises a flash memory storage device according to any one of claims 13-19 and a management device according to any one of claims 20-24.

26. A chip comprising a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to execute a computer program or instructions to implement the method of any of claims 8-12.

27. A chip comprising a processor, a memory, and a communication interface, the memory, and the processor being coupled to execute a computer program or instructions to implement the method of any of claims 1-7.