KR20230166991A - Display apparatus - Google Patents

Abstract

The display device includes a base layer, a light emitting device layer disposed on the base layer, first signal lines disposed on the base layer, a conductive layer overlapping the first signal lines, and an encapsulation layer disposed on the light emitting device layer. A display panel including a display panel, an insulating layer disposed on the encapsulation layer, sensing electrodes disposed on the insulating layer, and second signal lines disposed on the insulating layer and electrically connected to the sensing electrodes, A conductive layer is disposed between the first signal lines and the second signal lines, the upper surface of the insulating layer includes a first portion having peaks and valleys and a flat second portion, the sensing electrodes and the Second signal lines may be disposed above the second portion.

Description

DISPLAY APPARATUS}

The present invention relates to a display device, and to a display device that provides uniform touch sensitivity.

Various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation, game consoles, etc. are being developed. Input devices for display devices include a keyboard or mouse. Additionally, recently display devices are equipped with a touch sensing unit as an input device.

The purpose of the present invention is to provide a display device including a touch sensing unit with uniform touch sensitivity.

A display device according to an embodiment of the present invention includes a base layer, a light emitting device layer disposed on the base layer, first signal lines disposed on the base layer, a conductive layer overlapping the first signal lines, and A display panel including an encapsulation layer disposed on a light emitting device layer, an insulating layer disposed on the encapsulation layer, sensing electrodes disposed on the insulating layer, and a second device disposed on the insulating layer and electrically connected to the sensing electrodes. Includes two signal lines, the conductive layer is disposed between the first signal lines and the second signal lines, and the upper surface of the insulating layer includes a first portion having peaks and valleys and a second portion that is flat. And, the sensing electrodes and the second signal lines may be disposed on the second portion.

The upper surface of the encapsulation layer and the lower surface of the insulating layer include curved portions, and the lower surface of the insulating layer and the upper surface of the encapsulating layer may be in direct contact.

The light-emitting device layer includes a first electrode, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer, and the conductive layer may be disposed on the same layer as the second electrode. there is.

The second electrode may extend toward the conductive layer, and the second electrode and the conductive layer may be connected to each other.

The display panel further includes a gate driving circuit, and each of the first signal lines may provide clock signals to the gate driving circuit.

The encapsulation layer may include at least one inorganic layer and at least one organic layer.

A plurality of through holes are defined in the conductive layer, and the plurality of through holes may not overlap with the first signal lines or the second signal lines.

The conductive layer has a first region in which the plurality of through holes are not defined and overlaps at least one of the first signal lines and the second signal lines, and an area exposed by the plurality of through holes. It may include a second area having a first areal density, and a third area where the area exposed by the plurality of through holes has a second areal density lower than the first areal density.

The number of first through holes defined in the second area per first area may be greater than the number of second through holes defined in the third area per first area.

The size of the first through hole defined in the second area may be larger than the size of the second through hole defined in the third area.

It may further include pads each electrically connected to the second signal lines.

The display panel includes a display area and a non-display area adjacent to the display area, and an upper surface of the display panel overlapping the non-display area may include a curved surface.

The insulating layer may be directly disposed on the upper surface of the display panel.

The first signal lines and the second signal lines may be disposed in the non-display area.

At least a portion of the conductive layer may be disposed in the non-display area.

The display panel may further include a first dam disposed in the non-display area and a second dam spaced apart from the first dam.

The peak of the insulating layer may overlap the first dam or the second dam, and the valley of the insulating layer may overlap an area between the first dam and the second dam.

A display device according to an embodiment of the present invention has a display area and a non-display area adjacent to the display area defined, a light emitting element layer disposed in the display area, and a light emitting element layer disposed in the non-display area to control the light emitting element layer. first signal lines providing signals for, a conductive layer disposed in the non-display area and overlapping the first signal lines, a dam disposed in the non-display area, and a layer disposed on the light emitting device layer and the dam. A display panel including an encapsulation layer, an insulating layer disposed on the encapsulation layer and having a peak overlapping with the dam, sensing electrodes disposed on the insulating layer, and disposed on the insulating layer, electrically connected to the sensing electrodes. and second signal lines connected to each other, wherein the conductive layer is disposed between the first signal lines and the second signal lines, and the upper surface of the encapsulation layer and the lower surface of the insulating layer may include curved portions. You can.

The upper surface of the insulating layer includes a first portion having the peak and a valley adjacent to the peak, and a second portion extending from the first portion and being flat, and the sensing electrodes and the second signal lines are connected to the second portion. Can be placed above.

The display panel further includes an additional dam spaced apart from the dam, a valley overlaps an area between the dam and the additional dam, and the height of the additional dam may be different from the height of the dam.

A display device according to an embodiment of the present invention includes a conductive portion that covers an overlapping area where a plurality of clock signal lines and a plurality of touch signal lines overlap. The conductive unit may prevent noise from occurring in the touch signal lines due to a change in the level of a signal applied to the clock signal lines. That is, the conductive part can block the touch sensitivity of the touch sensing unit from changing due to the noise.

Figure 1A is a perspective view of a first operation of a display device according to an embodiment of the present invention.
FIG. 1B is a perspective view of a second operation of a display device according to an embodiment of the present invention.
Figure 1C is a perspective view of a third operation of a display device according to an embodiment of the present invention.
Figure 2 is a cross-sectional view of a display device according to an embodiment of the present invention.
3A and 3B are perspective views of a display device according to an embodiment of the present invention.
Figure 4a is a perspective view of a display device according to an embodiment of the present invention.
Figure 4b is a perspective view of a display device according to an embodiment of the present invention.
Figure 5a is a plan view of an organic light emitting display panel according to an embodiment of the present invention.
Figure 5b is a block diagram of a driving stage of a gate driving circuit according to an embodiment of the present invention.
Figure 5c is a cross-sectional view of a display module according to an embodiment of the present invention.
Figure 6a is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
Figure 6b is a partial cross-sectional view of an organic light emitting display panel according to an embodiment of the present invention.
Figure 6c is a partial cross-sectional view of an organic light emitting display panel according to an embodiment of the present invention.
7A to 7C are cross-sectional views of thin film encapsulation layers according to an embodiment of the present invention.
Figure 8a is a cross-sectional view of a touch sensing unit according to an embodiment of the present invention.
8B to 8E are plan views of a touch sensing unit according to an embodiment of the present invention.
Figure 8f is a partially enlarged view of the BB area of Figure 8e.
FIG. 9A is a partially enlarged view of area AA of FIG. 5C.
Figure 9b is a cross-sectional view briefly showing the WW area of Figure 9a.
FIG. 9C is a partially enlarged view of area AA of FIG. 5C.
Figure 9d is a partial enlarged view of area AA of Figure 5c.
FIG. 10A is a partially enlarged view of area AA of FIG. 5C.
FIG. 10B is a cross-sectional view briefly showing area XX of FIG. 10A.
FIG. 10C is a partially enlarged view of area AA of FIG. 5C.
FIG. 10D is a cross-sectional view briefly showing the YY area of FIG. 10C.
FIG. 11A is a partially enlarged view of area AA of FIG. 5C.
FIG. 11B is a cross-sectional view briefly showing the ZZ region of FIG. 11A.
FIG. 11C is a partially enlarged view of area AA of FIG. 5C.
FIG. 12A is a partially enlarged view of area AA of FIG. 5C.
FIG. 12B is an enlarged plan view of a portion of the configuration shown in FIG. 12A.
FIG. 12C is an enlarged plan view of a portion of the configuration shown in FIG. 12A.
FIG. 13A is a partially enlarged view of area AA of FIG. 5C.
FIG. 13B is an enlarged plan view of a portion of the configuration shown in FIG. 13A.
Figure 14a is a partial enlarged view of area AA of Figure 5c.
FIG. 14B is an enlarged plan view of a portion of the configuration shown in FIG. 14A.

Since the present invention can be subject to various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

In this specification, when a component (or region, layer, part, etc.) is referred to as being “on,” “connected to,” or “coupled to” another component, it is directly connected/connected to another component. This means that they can be combined or a third component can be placed between them.

Like reference numerals refer to like elements. Additionally, in the drawings, the thickness, proportions, and dimensions of components are exaggerated for effective explanation of technical content. “And/or” includes all combinations of one or more that the associated configurations may define.

Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and similarly, the second component may also be named a first component without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

Additionally, terms such as “below,” “on the lower side,” “above,” and “on the upper side” are used to describe the relationship between the components shown in the drawings. The above terms are relative concepts and are explained based on the direction indicated in the drawings.

Terms such as “include” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but do not include one or more other features, numbers, or steps. , it should be understood that it does not exclude in advance the possibility of the existence or addition of operations, components, parts, or combinations thereof.

FIG. 1A is a perspective view of a first operation of the display device DD according to an embodiment of the present invention. FIG. 1B is a perspective view of a second operation of the display device DD according to an embodiment of the present invention. FIG. 1C is a perspective view of a third operation of the display device DD according to an embodiment of the present invention.

As shown in FIG. 1A , in the first operation mode, the display surface IS on which the image IM is displayed is parallel to the surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface IS, that is, the thickness direction of the display device DD, is indicated by the third direction DR3. The front (or upper) and back (or lower) surfaces of each member are separated by the third direction DR3. However, the direction indicated by the first to third directions DR1, DR2, and DR3 is a relative concept and can be converted to another direction. Hereinafter, the first to third directions refer to the same reference numerals as the directions indicated by the first to third directions DR1, DR2, and DR3, respectively.

1A to 1C show a flexible foldable display device as an example of the display device DD. However, the present invention may be a rollable display device or a banded display device and is not particularly limited. Additionally, although a flexible display device is shown in this embodiment, the present invention is not limited thereto. The display device DD according to this embodiment may be a flat rigid display device or a curved rigid display device. The display device (DD) according to the present invention can be used in large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, game consoles, and smart watches.

As shown in FIG. 1A, the display surface IS of the display device DD may include a plurality of areas. The display device DD includes a display area DD-DA where an image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area (DD-NDA) is an area where images are not displayed. Figure 1a shows a vase as an example of an image (IM). As an example, the display area (DD-DA) may have a rectangular shape. The non-display area (DD-NDA) may surround the display area (DD-DA). However, the shape is not limited to this, and the shape of the display area (DD-DA) and the shape of the non-display area (DD-NDA) may be designed relatively.

As shown in FIGS. 1A to 1C, the display device DD may include a plurality of areas defined according to the operation type. The display device DD displays a bending area BA that is bent, a first non-bending area NBA1, and a second non-bending area NBA2 on the basis of the bending axis BX. It can be included.

As shown in FIG. 1B, the display device DD is bent inside so that the display surface IS of the first non-bending area NBA1 and the display surface IS of the second non-bending area NBA2 face each other. -bending) can be done. As shown in FIG. 1C, the display device DD may be outer-bended so that the display surface IS is exposed to the outside.

1A to 1C show only one bending area BA, but the present invention is not limited thereto. For example, in one embodiment of the present invention, the display device DD may include a plurality of bending areas BA.

In one embodiment of the present invention, the display device DD may be configured to repeat only the operation modes shown in FIGS. 1A and 1B. However, it is not limited to this, and the bending area BA may be defined to correspond to the way the user manipulates the display device DD. For example, unlike FIGS. 1B and 1C, the bending area BA may be defined parallel to the first direction DR1 or may be defined diagonally. The area of the bending area (BA) is not fixed and may be determined depending on the radius of curvature.

Figure 2 is a cross-sectional view of the display device DD according to an embodiment of the present invention. FIG. 2 shows a cross section defined by the second direction DR2 and the third direction DR3.

As shown in FIG. 2, the display device DD includes a protective film (PM), a display module (DM), an optical member (LM), a window (WM), a first adhesive member (AM1), and a second adhesive member ( AM2), and a third adhesive member (AM3). The display module (DM) is disposed between the protective film (PM) and the optical member (LM). The optical member LM is disposed between the display module DM and the window WM. The first adhesive member (AM1) combines the display module (DM) and the protective film (PM), the second adhesive member (AM2) combines the display module (DM) and the optical member (LM), and the third adhesive member (AM3) combines the optical member (LM) and the window (WM).

The protective film (PM) protects the display module (DM). The protective film PM provides a first outer surface OS-L exposed to the outside and an adhesive surface adhered to the first adhesive member AM1. The protective film (PM) prevents external moisture from penetrating into the display module (DM) and absorbs external shock.

The protective film (PM) may include a plastic film as a base substrate. Protective films (PM) are polyethersulfone (PES), polyacrylate (polyacrylate), polyetherimide (PEI), polyethylenenaphthalate (PEN), polyethyleneterephthalate (PET), and polyethylene terephthalate (PET). Phenylene sulfide (PPS, polyphenylene sulfide), polyarylate, polyimide (PI, polyimide), polycarbonate (PC, polycarbonate), poly(arylene ethersulfone), and combinations thereof. It may include a plastic film containing any one selected from the group consisting of

Materials constituting the protective film (PM) are not limited to plastic resins and may include organic/inorganic composite materials. The protective film (PM) may include a porous organic layer and an inorganic material filled in the pores of the organic layer. The protective film (PM) may further include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. In one embodiment of the present invention, the protective film (PM) may be omitted.

The window (WM) can protect the display module (DM) from external shock and provide an input surface to the user. The window WM provides a second outer surface OS-U exposed to the outside and an adhesive surface adhered to the second adhesive member AM2. The display surface IS shown in FIGS. 1A to 1C may be the second outer surface OS-U.

The window WM may include a plastic film. A window (WM) may have a multi-layer structure. The window WM may have a multilayer structure selected from glass substrate, plastic film, and plastic substrate. The window (WM) may further include a bezel pattern. The multilayer structure can be formed through a continuous process or an adhesion process using an adhesive layer.

The optical member (LM) reduces external light reflectance. The optical member LM may include at least a polarizing film. The optical member LM may further include a retardation film. In one embodiment of the present invention, the optical member LM may be omitted.

The display module (DM) may include an organic light emitting display panel (DP, or display panel) and a touch sensing unit (TS). The touch sensing unit (TS) is placed directly on the organic light emitting display panel (DP). In this specification, “directly placed” means formed through a continuous process, excluding attachment using a separate adhesive layer.

The organic light emitting display panel (DP) generates an image (IM, see FIG. 1A) corresponding to input image data. The organic light emitting display panel DP provides a first display panel surface BS1-L and a second display panel surface BS1-U facing each other in the thickness direction DR3. Although the organic light emitting display panel (DP) has been described as an example in this embodiment, the display panel is not limited thereto.

The touch detection unit (TS) acquires coordinate information of external input. The touch sensing unit (TS) can detect external input using a capacitance method.

Although not separately shown, the display module (DM) according to an embodiment of the present invention may further include an anti-reflection layer. The anti-reflection layer may include a color filter or a laminate structure of a conductive layer/insulating layer/conductive layer. The anti-reflection layer can reduce external light reflectance by absorbing, destructively interfering with, or polarizing light incident from the outside. The antireflection layer can replace the function of the optical member (LM).

Each of the first adhesive member (AM1), the second adhesive member (AM2), and the third adhesive member (AM3) is made of an optically clear adhesive film (OCA, Optically Clear Adhesive film) or an optically clear adhesive resin (OCR, Optically Clear Resin). Alternatively, it may be an organic adhesive layer such as a pressure sensitive adhesive film (PSA). The organic adhesive layer may include adhesive materials such as polyurethane-based, polyacrylic-based, polyester-based, polyepoxy-based, and polyvinyl acetate-based.

Although not separately shown, the display device DD may further include a frame structure supporting the functional layers to maintain the state shown in FIGS. 1A to 1C. The frame structure may include a joint structure or a hinge structure.

3A and 3B are perspective views of the display device DD-1 according to an embodiment of the present invention. FIG. 3A shows the display device DD-1 in an unfolded state, and FIG. 3B shows the display device DD-1 in a bent state.

The display device DD-1 may include one bending area (BA) and one non-bending area (NBA). The non-display area (DD-NDA) of the display device (DD-1) may be bent. However, in one embodiment of the present invention, the bending area of the display device DD-1 may be changed.

The display device DD-1 according to this embodiment, unlike the display device DD shown in FIGS. 1A to 1C, can be fixed and operated in one form. The display device DD-1 may operate in a bent state as shown in FIG. 3B. The display device DD-1 may be fixed to a frame, etc. in a bent state, and the frame may be coupled to the housing of the electronic device.

The display device DD-1 according to this embodiment may have the same cross-sectional structure as shown in FIG. 2. However, the non-bending area (NBA) and the bending area (BA) may have different stacked structures. The non-bending area NBA may have the same cross-sectional structure as shown in FIG. 2, and the bending area BA may have a different cross-sectional structure from that shown in FIG. 2. The optical member LM and window WM may not be disposed in the bending area BA. That is, the optical member LM and window WM can be placed only in the non-bending area NBA. The second adhesive member (AM2) and the third adhesive member (AM3) may also be not disposed in the bending area (BA).

FIG. 4A is a perspective view of a display device DD-2 according to an embodiment of the present invention.

The display device DD-2 includes a non-bending area (NBA, or flat area) where the main image is displayed on the front and a bending area (BA, or side area) where the sub-image is displayed on the side. Although not separately shown, the sub-image may include an icon that provides certain information. In this embodiment, the terms “non-bending area (NBA) and bending area (BA)” define the display device DD-2 as a plurality of areas divided by shape.

The bending area (BA) bent from the non-bending area (NBA) displays sub-images in the first direction (DR1), the second direction (DR2), and the fourth direction (DR4) that intersects the third direction (DR3). . However, the directions indicated by the first to fourth directions DR1 to DR4 are relative concepts and can be converted to other directions.

Figure 4b is a perspective view of the display device DD-3 according to an embodiment of the present invention.

The display device DD-3 includes a non-bending area NBA where the main image is displayed on the front, a first bending area BA1 and a second bending area BA2 where the sub-image is displayed on the side. The first bending area BA1 and the second bending area BA2 may be bent from both sides of the non-bending area NBA.

Figure 5a is a plan view of an organic light emitting display panel (DP) according to an embodiment of the present invention.

As shown in FIG. 5A, the organic light emitting display panel (DP) includes a display area (DA) and a non-display area (NDA) on a plane. The display area (DA) and non-display area (NDA) of the organic light emitting display panel (DP) are the display area (DD-DA, see Figure 1a) and the non-display area (DD-NDA) of the display device (DD, see Figure 1a). , see Figure 1a), respectively. The display area (DA) and non-display area (NDA) of the organic light emitting display panel (DP) are the display area (DD-DA, see Figure 1a) and the non-display area (DD-NDA) of the display device (DD, see Figure 1a). , see FIG. 1A), and may change depending on the structure/design of the organic light emitting display panel (DP).

The organic light emitting display panel (DP) includes a plurality of pixels (PX). An area where a plurality of pixels (PX) are arranged is defined as a display area (DA). In this embodiment, the non-display area (NDA) may be defined along the border of the display area (DA).

The organic light emitting display panel (DP) includes gate lines (GL), data lines (DL), light emission lines (EL), control signal lines (SL-D), initialization voltage lines (SL-Vint), and voltage lines ( SL-VDD), power supply line (E-VSS), and pad section (PD).

The gate lines GL are each connected to a corresponding pixel PX among the plurality of pixels PX, and the data lines DL are respectively connected to the corresponding pixel PX among the plurality of pixels PX. do. Each of the light emitting lines EL may be arranged in parallel with a corresponding gate line among the gate lines GL. The control signal line (SL-D) can provide control signals to the gate driving circuit (GDC). The initialization voltage line SL-Vint may provide an initialization voltage to the plurality of pixels PX. The voltage line SL-VDD is connected to a plurality of pixels PX and may provide a first voltage to the plurality of pixels PX. The voltage line SL-VDD may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2. The power supply line (E-VSS) may be placed in the non-display area (NDA) surrounding three sides of the display area (DA). A common voltage (eg, a second voltage) may be provided to the plurality of pixels (PX) on the power supply line (E-VSS). The common voltage may be a voltage at a lower level than the first voltage.

A gate driving circuit (GDC) to which gate lines (GL) and emission lines (EL) are connected may be disposed on one side of the non-display area (NDA). Gate lines (GL), data lines (DL), light emission lines (EL), control signal line (SL-D), initialization voltage line (SL-Vint), voltage line (SL-VDD), and power supply line. Some of the (E-VSS) are placed on the same floor, and some are placed on different floors.

The pad portion PD may be connected to the ends of the data lines DL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD.

Figure 5b is a block diagram of the driving stage (GDSi) of the gate driving circuit (GDC) according to an embodiment of the present invention.

FIG. 5B exemplarily shows a driving stage (GDSi) connected to the i-th gate line (GLi) and the i-th emission line (ELi) among the driving stages of the plurality of gate driving circuits (GDC).

The driving stage (GDSi) may include an emission control stage (EC-Ci) and a gate driving stage (GC-Ci). The light emission control stage (EC-Ci) of the driving stage (GDSi) includes a first clock signal line (CL1), a second clock signal line (CL2), a first voltage line (VL1), a second voltage line (VH1), and a second clock signal line (CL2). 1 Emission control signals (CLK1, CLK2, VGL, VGH, EMFLM) may be provided through the start signal line (EF1). The gate driving stage (GC-Ci) includes a third clock signal line (CL3), a fourth clock signal line (CL4), a third voltage line (VL2), a fourth voltage line (VH2), and a second start signal line (EF2). ) Gate control signals (CLK3, CLK4, VGH1, VGL1, FLM) may be provided through.

In this embodiment, the light emission control stage (EC-Ci) and the gate driving stage (GC-Ci) are included in one driving stage (GDSi) as an example, but it is not limited thereto. For example, the emission control stage (EC-Ci) and the gate driving stage (GC-Ci) may be included in different driving stages.

The light emission control stage (EC-Ci) includes a first clock terminal (CK1), a second clock terminal (CK2), a first voltage input terminal (VPL1), a second voltage input terminal (VPH1), an input terminal (IN), and a carry terminal. It may include a terminal (CR) and an output terminal (OUT1).

The first clock terminal (CK1) receives the first clock signal (CLK1), and the second clock terminal (CK2) receives the second clock signal (CLK2). The first clock signal CLK1 and the second clock signal CLK2 may be signals with different phases. The second clock signal CLK2 may be a signal in which the phase of the first clock signal CLK1 is inverted or a signal whose phase is delayed.

The first voltage input terminal (VPL1) receives the first voltage (VGL), and the second voltage input terminal (VPH1) receives the second voltage (VGH). The voltage level of the first voltage (VGL) may be lower than the voltage level of the second voltage (VGH).

The input terminal (IN) may receive the carry signal of the previous emission control stage (e.g., EC-Ci-1 (not shown)), and the carry terminal (CR) may receive the carry signal of the next emission control stage (e.g., EC-Ci-1 (not shown)). A carry signal can be output as -Ci+1 (not shown). The output terminal OUT1 may provide the emission control signal generated from the emission control stage EC-Ci to the emission line ELi.

The start signal EMFLM may be input to the input terminal IN of the first emission control stage (eg, EC-C1 (not shown)) among the emission control stages.

The gate driving stage (GC-Ci) includes a third clock terminal (CK3), a fourth clock terminal (CK4), a third voltage input terminal (VPL2), a fourth voltage input terminal (VPH2), an input terminal (IN), and a carry. It may include a terminal (CR) and an output terminal (OUT2).

The third clock terminal CK3 receives the third clock signal CLK3, and the fourth clock terminal CK4 receives the fourth clock signal CLK4. The third clock signal CLK3 and the fourth clock signal CLK4 may be signals with different phases. The fourth clock signal CLK4 may be a signal in which the phase of the third clock signal CLK3 is inverted or a signal whose phase is delayed.

The third voltage input terminal (VPL2) receives the third voltage (VL), and the fourth voltage input terminal (VPH2) receives the fourth voltage (VGH1). The voltage level of the third voltage VGL1 may be lower than the voltage level of the fourth voltage VGH1.

The input terminal (IN) may receive the carry signal of the previous gate driving stage (e.g., GC-Ci-1 (not shown)), and the carry terminal (CR) may receive the carry signal of the next gate driving stage (e.g., GC-Ci-1). A carry signal can be output as -Ci+1 (not shown). The output terminal OUT2 may provide a gate signal generated from the gate driving stage GC-Ci to the gate line GLi.

The start signal FLM may be input to the input terminal IN of the first gate driving stage (eg, GC-C1 (not shown)) among the gate driving stages.

In one embodiment of the present invention, the first clock terminal (CK1), the second clock terminal (CK2), the first voltage input terminal (VPL1), the second voltage input terminal (VPH1) of the emission control stage (EC-Ci), Any one of the input terminal (IN), carry terminal (CR), and output terminal (OUT1) may be omitted, or other terminals may be further included. For example, the carry terminal (CR) may be omitted.

In one embodiment of the present invention, the third clock terminal (CK3), the fourth clock terminal (CK4), the third voltage input terminal (VPL2), and the fourth voltage input terminal (VPH2) of the gate driving stage (GC-Ci), Any one of the input terminal (IN), carry terminal (CR), and output terminal (OUT2) may be omitted, or other terminals may be further included. For example, the carry terminal (CR) may be omitted.

In addition, in Figure 5b, the input terminal (IN) of the light emission control stage (EC-Ci) and the input terminal (IN) of the gate driving stage (GC-Ci) are illustratively connected to each of the carry terminals of the previous stage. , but is not limited to this. The connections between driving stages can be varied.

Figure 5c is a cross-sectional view of the display module (DM) according to an embodiment of the present invention. FIG. 5C shows a cross section defined by the second direction DR2 and the third direction DR3.

As shown in FIG. 5C, the organic light emitting display panel (DP) includes a base layer (SUB), a circuit layer (DP-CL) disposed on the base layer (SUB), a light emitting device layer (DP-OLED), and a thin film. Includes an encapsulation layer (TFE).

The base layer (SUB) may include at least one plastic film. The base layer (SUB) is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite substrate. The plastic substrate is at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin. may include.

The circuit layer DP-CL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. A plurality of conductive layers of the circuit layer (DP-CL) may form signal lines or a control circuit of a pixel. The circuit layer DP-CL may include a pixel circuit layer DP-PCL disposed in the display area DA and a driving circuit layer DP-DCL disposed in the non-display area NDA. The pixel circuit layer (DP-PCL) includes the gate lines (GL), data lines (DL), emission lines (EL), initialization voltage line (SL-Vint), and voltage line (SL- VDD), and circuits included in the pixels (PX).

The driving circuit layer (DP-DCL) may include the gate driving circuit (GDC) and control signal line (SL-D) previously described in FIG. 5A. The control signal line (SL-D) is the first clock signal line (CL1), the second clock signal line (CL2), the third clock signal line (CL3), and the fourth clock signal line (CL4) shown in FIG. 5B. , first voltage line (VL1), second voltage line (VH1), third voltage line (VL2), fourth voltage line (VH2), first start signal line (EF1), second start signal line (EF2) may include. Of the above configuration, the first clock signal line (CL1), the second clock signal line (CL2), the third clock signal line (CL3), and the fourth clock signal line (CL4) may be collectively referred to as clock signal lines. .

The light emitting device layer (DP-OLED) includes organic light emitting diodes.

The thin film encapsulation layer (TFE) seals the light emitting device layer (DP-OLED). The thin film encapsulation layer (TFE) may include at least two inorganic layers and an organic layer disposed between them. The inorganic layers protect the light emitting device layer (DP-OLED) from moisture and oxygen, and the organic thin film protects the light emitting device layer (DP-OLED) from foreign substances such as dust particles.

The touch sensing unit (TS) is disposed on the thin film encapsulation layer (TFE). The touch sensing unit (TS) may be placed directly on the thin film encapsulation layer (TFE). However, the present invention is not limited to this, and a buffer layer may be disposed on the thin film encapsulation layer (TFE), and a touch sensing unit (TS) may be disposed directly on the buffer layer. The buffer layer may be an inorganic layer or an organic layer. The inorganic layer may include at least one of silicon nitride, silicon oxy nitride, silicon oxide, titanium oxide, or aluminum oxide. The organic layer may include a polymer, for example, an acrylic-based organic layer. However, this is an example and is not limited thereto. Although the buffer layer is described as a separate component, the buffer layer may be included in the thin film encapsulation layer (TFE).

The touch sensing unit (TS) includes a touch sensing unit (TSP) and touch signal lines (TSL). The touch sensing unit (TSP) and the touch signal lines (TSL) may have a single-layer or multi-layer structure. The touch sensor (TSP) and touch signal lines (TSL) are made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowire, and graphene. Can contain pins. The touch sensing unit (TSP) and the touch signal lines (TSL) may include a metal layer, such as molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The touch sensing unit (TSP) and the touch signal lines (TSL) may have the same layer structure or may have different layer structures. Specific details about the touch sensing unit (TS) will be described later.

Figure 6a is an equivalent circuit diagram of a pixel (PX) according to an embodiment of the present invention.

FIG. 6A exemplarily shows the i-th pixel (PXi) connected to the k-th data line (DLk) among the plurality of data lines (DL, see FIG. 5A).

The ith pixel (PXi) includes an organic light emitting diode (OLED) and a pixel driving circuit that controls the organic light emitting diode. The driving circuit may include seven thin film transistors (T1 to T7) and one storage capacitor (Cst).

The driving transistor controls the driving current supplied to the organic light-emitting diode (OLED). The output electrode of the second transistor (T2) is electrically connected to the organic light emitting diode (OLED). The output electrode of the second transistor T2 may be in direct contact with the first electrode of the organic light emitting diode (OLED), or may be connected via another transistor (the sixth transistor T6 in this embodiment).

The control electrode of the control transistor can receive a control signal. The control signal applied to the ith pixel (PXi) is the i-1th gate signal (Si-1), the ith gate signal (Si), the i+1th gate signal (Si+1), the data signal (Dk), and an i-th emission control signal (Ei). In an embodiment of the present invention, the control transistor may include a first transistor T1 and third to seventh transistors T3 to T7.

The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the ith gate line GLi, and an output electrode connected to the output electrode of the second transistor T2. do. The first transistor T1 is turned on by the gate signal (Si, hereinafter referred to as the i-th gate signal) applied to the ith gate line (GLi), and the data signal (Dk) applied to the k-th data line (DLk). is provided to the storage capacitor (Cst).

Figure 6b is a partial cross-sectional view of an organic light emitting display panel according to an embodiment of the present invention. Figure 6c is a partial cross-sectional view of an organic light emitting display panel according to an embodiment of the present invention. Specifically, FIG. 6B shows a cross section of a portion corresponding to the first transistor T1 of the equivalent circuit shown in FIG. 6A. FIG. 6C shows a cross section of a portion corresponding to the second transistor T2, the sixth transistor T6, and the organic light emitting diode (OLED) of the equivalent circuit shown in FIG. 6A.

Referring to FIGS. 6B and 6C, a buffer layer (BFL) may be disposed on the base layer (SUB). The buffer layer (BFL) improves the bonding strength between the base layer (SUB) and the conductive patterns or semiconductor patterns. The buffer layer (BFL) may include an inorganic layer. Although not separately shown, a barrier layer to prevent foreign substances from entering may be further disposed on the upper surface of the base layer (SUB). The buffer layer (BFL) and barrier layer may be selectively disposed or omitted.

On the buffer layer (BFL), a semiconductor pattern (OSP1: hereinafter referred to as a first semiconductor pattern) of the first transistor (T1), a semiconductor pattern (OSP2: hereinafter referred to as a second semiconductor pattern) of the second transistor (T2), and a sixth transistor (T6) are formed on the buffer layer (BFL). A semiconductor pattern (OSP6: hereinafter referred to as the sixth semiconductor pattern) is disposed. The first semiconductor pattern (OSP1), the second semiconductor pattern (OSP2), and the sixth semiconductor pattern (OSP6) may be selected from amorphous silicon, polysilicon, and metal oxide semiconductors.

A first insulating layer 10 may be disposed on the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. 6B and 6C exemplarily show that the first insulating layer 10 is provided in the form of a layer covering the first semiconductor pattern (OSP1), the second semiconductor pattern (OSP2), and the sixth semiconductor pattern (OSP6). However, the first insulating layer 10 may be provided in a pattern arranged to correspond to the first semiconductor pattern (OSP1), the second semiconductor pattern (OSP2), and the sixth semiconductor pattern (OSP6).

The first insulating layer 10 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer, a silicon oxy nitride layer, and a silicon oxide layer.

On the first insulating layer 10, the control electrode (GE1: hereinafter referred to as first control electrode) of the first transistor (T1), the control electrode (GE2 (hereinafter referred to as second control electrode)) of the second transistor (T2), and the sixth The control electrode GE6 (hereinafter referred to as the sixth control electrode) of the transistor T6 is disposed. The first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be manufactured according to the same photolithography process as the gate lines GL (see FIG. 5A).

A second insulating layer 20 covering the first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be disposed on the first insulating layer 10. The second insulating layer 20 may provide a flat top surface. The second insulating layer 20 may include organic materials and/or inorganic materials.

On the second insulating layer 20, the input electrode (SE1: hereinafter referred to as first input electrode) and the output electrode (DE1: first output electrode) of the first transistor (T1), and the input electrode ( SE2: hereinafter referred to as the second input electrode) and output electrode (DE2: second output electrode), input electrode (SE6: hereinafter referred to as the sixth input electrode) and output electrode (DE6: sixth output electrode) of the sixth transistor (T6) ) is placed.

The first input electrode (SE1) and the first output electrode (DE1) have a first through hole (CH1) and a second through hole (CH2) penetrating the first insulating layer 10 and the second insulating layer 20. Each is connected to the first semiconductor pattern OSP1 through. The second input electrode (SE2) and the second output electrode (DE2) have third through holes (CH3) and fourth through holes (CH4) penetrating the first and second insulating layers (10) and (20). Each is connected to the second semiconductor pattern (OSP2) through. The sixth input electrode (SE6) and the sixth output electrode (DE6) have a fifth through hole (CH5) and a sixth through hole (CH6) penetrating the first and second insulating layers (10) and (20). Each is connected to the sixth semiconductor pattern (OSP6) through. Meanwhile, in another embodiment of the present invention, the first transistor T1, the second transistor T2, and the sixth transistor T6 may be modified to have a bottom gate structure.

On the second insulating layer 20, a first input electrode (SE1), a second input electrode (SE2), a sixth input electrode (SE6), a first output electrode (DE1), a second output electrode (DE2), 6 A third insulating layer 30 covering the output electrode DE6 is disposed. The third insulating layer 30 includes an organic layer and/or an inorganic layer. In particular, the third insulating layer 30 may include an organic material to provide a flat surface.

Any one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted depending on the circuit structure of the pixel. Each of the second insulating layer 20 and the third insulating layer 30 may be defined as an interlayer insulating layer (interlayer). The interlayer insulating layer is disposed between the conductive pattern disposed below and the conductive pattern disposed above with respect to the interlayer insulating layer to insulate the conductive patterns.

A pixel defining layer (PDL) and an organic light emitting diode (OLED) are disposed on the third insulating layer 30. The first electrode AE is disposed on the third insulating layer 30. The first electrode (AE) is connected to the sixth output electrode (DE6) through the seventh through hole (CH7) penetrating the third insulating layer (30). An opening (OP) is defined in the pixel definition layer (PDL). The opening OP of the pixel definition layer PDL exposes at least a portion of the first electrode AE.

The pixel PX may be arranged in a pixel area on a plane. The pixel area may include a light-emitting area (PXA) and a non-light-emitting area (NPXA) adjacent to the light-emitting area (PXA). The non-emissive area (NPXA) may surround the luminous area (PXA). In this embodiment, the light emitting area PXA is defined to correspond to a partial area of the first electrode AE exposed by the opening OP.

The hole control layer (HCL) may be commonly disposed in the emission area (PXA) and the non-emission area (NPXA). Although not separately shown, a common layer such as a hole control layer (HCL) may be formed in common across a plurality of pixels (PX, see FIG. 5A).

An organic light emitting layer (EML) is disposed on the hole control layer (HCL). The organic light emitting layer (EML) may be disposed in an area corresponding to the opening OP. That is, the organic light emitting layer (EML) may be formed separately in each of the plurality of pixels (PX). Although the patterned organic light emitting layer (EML) is shown as an example in this embodiment, the organic light emitting layer (EML) may be commonly disposed in a plurality of pixels (PX). At this time, the organic light emitting layer (EML) can generate white light. Additionally, the organic light emitting layer (EML) may have a multilayer structure.

An electronic control layer (ECL) is disposed on the organic light emitting layer (EML). Although not separately shown, the electronic control layer (ECL) may be commonly formed in a plurality of pixels (PX, see FIG. 5A).

A second electrode (CE) is disposed on the electronic control layer (ECL). The second electrode CE is commonly disposed in the plurality of pixels PX.

A thin film encapsulation layer (TFE) is disposed on the second electrode (CE). The thin film encapsulation layer (TFE) is commonly disposed in the plurality of pixels (PX). The thin film encapsulation layer (TFE) includes at least one inorganic layer and at least one organic layer. The thin film encapsulation layer (TFE) may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

In this embodiment, the thin film encapsulation layer (TFE) directly covers the second electrode (CE). In one embodiment of the present invention, a capping layer covering the second electrode (CE) may be further disposed between the thin film encapsulation layer (TFE) and the second electrode (CE). At this time, the thin film encapsulation layer (TFE) can directly cover the capping layer.

7A to 7C are cross-sectional views of thin film encapsulation layers (TFE1, TFE2, and TFE3) according to an embodiment of the present invention. Hereinafter, thin film encapsulation layers (TFE1, TFE2, TFE3) according to embodiments of the present invention will be described with reference to FIGS. 7A to 7C.

As shown in FIG. 7A, the thin film encapsulation layer (TFE1) may include n inorganic thin films (IOL1 to IOLn), including the first inorganic thin film (IOL1) in contact with the second electrode (CE, see FIG. 6C). You can. The first inorganic thin film (IOL1) may be defined as a lower inorganic thin film, and inorganic thin films other than the first inorganic thin film (IOL1) among the n inorganic thin films (IOL1 to IOLn) may be defined as upper inorganic thin films.

The thin film encapsulation layer (TFE1) includes n-1 organic thin films (OL1 to OLn), and the n-1 organic thin films (OL1 to OLn) are arranged alternately with n inorganic thin films (IOL1 to IOLn). It can be. The n-1 organic thin films (OL1 to OLn) may have a greater thickness on average than the n inorganic thin films (IOL1 to IOLn).

Each of the n inorganic thin films (IOL1 to IOLn) may have a single layer containing one material, or may have multiple layers each containing different materials. Each of the n-1 organic thin films (OL1 to OLn) may be formed by depositing or printing organic monomers. For example, each of the n-1 organic thin films (OL1 to OLn) may be formed using an inkjet printing method or may be formed by coating a composition containing an acrylic monomer. In one embodiment of the present invention, the thin film encapsulation layer (TFE1) may further include an nth organic thin film.

As shown in FIGS. 7B and 7C, the inorganic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may be made of the same or different inorganic materials and may have the same or different thickness. The organic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different organic materials and may have the same or different thickness.

As shown in FIG. 7B, the thin film encapsulation layer (TFE2) includes a first inorganic thin film (IOL1), a first organic thin film (OL1), a second inorganic thin film (IOL2), and a second organic thin film (OL2) sequentially stacked. , and a third inorganic thin film (IOL3).

The first inorganic thin film (IOL1) may have a two-layer structure. The first sub-layer (S1) and the second sub-layer (S2) may include different inorganic materials.

As shown in FIG. 7C, the thin film encapsulation layer (TFE3) may include a first inorganic thin film (IOL10), a first organic thin film (OL1), and a second inorganic thin film (IOL20) sequentially stacked. The first inorganic thin film (IOL10) may have a two-layer structure. The first sub-layer (S10) and the second sub-layer (S20) may include different inorganic materials. The second inorganic thin film (IOL20) may have a two-layer structure. The second inorganic thin film (IOL20) may include a first sub-layer (S100) and a second sub-layer (S200) deposited in different deposition environments. The first sub-layer S100 may be deposited under low-power conditions and the second sub-layer S200 may be deposited under high-power conditions. The first sub-layer (S100) and the second sub-layer (S200) may include the same inorganic material.

Figure 8a is a cross-sectional view of a touch sensing unit (TS) according to an embodiment of the present invention.

As shown in FIG. 8A, the touch sensing unit (TS) includes a first conductive layer (TS-CL1), a first insulating layer (TS-IL1, hereinafter referred to as first touch insulating layer), and a second conductive layer (TS-CL2). ), and a second insulating layer (TS-IL2, hereinafter referred to as a second touch insulating layer). The first conductive layer (TS-CL1) is directly disposed on the thin film encapsulation layer (TFE). Without being limited thereto, another buffer layer (eg, an inorganic layer or an organic layer) may be further disposed between the first conductive layer (TS-CL1) and the thin film encapsulation layer (TFE). In another embodiment of the present invention, a plastic film, a glass substrate, or a plastic substrate may be disposed between the first conductive layer (TS-CL1) and the thin film encapsulation layer (TFE).

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The multi-layered conductive layer may include at least two of transparent conductive layers and metal layers. The multi-layered conductive layer may include metal layers containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowire, and graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and alloys thereof.

Each of the first conductive layer (TS-CL1) and the second conductive layer (TS-CL2) includes a plurality of patterns. Hereinafter, the first conductive layer (TS-CL1) will be described as including first conductive patterns, and the second conductive layer (TS-CL2) will be described as including second conductive patterns. Each of the first conductive patterns and second conductive patterns may include touch electrodes and touch signal lines.

Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may have a single-layer or multi-layer structure. Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may have at least one of an inorganic layer and an organic layer.

The first touch insulating layer TS-IL1 is sufficient to insulate the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and its shape is not limited. The shape of the first touch insulating layer TS-IL1 may change depending on the shapes of the first and second conductive patterns. The first touch insulating layer TS-IL1 may entirely cover the thin film encapsulation layer TFE or may include a plurality of insulating patterns. It is sufficient for the plurality of insulating patterns to overlap the first or second connection parts CP1 or CP2, which will be described later.

In this embodiment, a two-layer touch sensing unit is shown as an example, but is not limited thereto. The single-layer touch sensing unit includes a conductive layer and an insulating layer covering the conductive layer. The conductive layer includes touch sensors and touch signal lines connected to the touch sensors. The single-layer touch sensing unit can acquire coordinate information using the self-cap method.

8B to 8E are plan views of a touch sensing unit (TS) according to an embodiment of the present invention.

As shown in FIG. 8B, the touch sensing unit (TS) may include a touch sensing unit (TSP, see FIG. 5C), touch signal lines (TSL, see FIG. 5C), and a pad unit (PDa).

The touch sensing unit (TSP, see FIG. 5C) may include first touch electrodes (TE1-1 to TE1-m) and second touch electrodes (TE2-1 to TE2-n). The touch signal lines (TSL, see FIG. 5C) are first touch signal lines (SL1-1 to SL1-m) connected to the first touch electrodes (TE1-1 to TE1-m), and second touch electrodes. It may include second touch signal lines (SL2-1 to SL2-n) connected to (TE2-1 to TE2-n). The pad portion PDa may be electrically connected to the first touch signal lines SL1-1 to SL1-m and the second touch signal lines SL2-1 to SL2-n.

between the first touch electrodes (TE1-1 to TE1-m) and the first touch signal lines (SL1-1 to SL1-m), and connected to the second touch electrodes (TE2-1 to TE2-n) Connection electrodes (TSD) may be disposed between the two touch signal lines (SL2-1 to SL2-n). The connection electrodes (TSD) may be connected to ends of each of the first touch electrodes (TE1-1 to TE1-m) and the second touch electrodes (TE2-1 to TE2-n) to transmit signals. In another embodiment of the present invention, the connection electrodes (TSD) may be omitted.

Each of the first touch electrodes TE1-1 to TE1-m may have a mesh shape with a plurality of touch openings defined. Each of the first touch electrodes TE1-1 to TE1-m includes a plurality of first touch sensor units SP1 and a plurality of first connection parts CP1. The first touch sensor units SP1 are arranged in the first direction DR1. Each of the first connection parts CP1 connects two adjacent first touch sensor parts SP1. Although not specifically shown, the first touch signal lines SL1-1 to SL1-m may also have a mesh shape.

The second touch electrodes TE2-1 to TE2-n are insulated and intersect the first touch electrodes TE1-1 to TE1-m. Each of the second touch electrodes TE2-1 to TE2-n may have a mesh shape with a plurality of touch openings defined. Each of the second touch electrodes TE2-1 to TE2-n includes a plurality of second touch sensor units SP2 and a plurality of second connection parts CP2. The second touch sensor units SP2 are arranged in the second direction DR2. Each of the second connection parts CP2 connects two adjacent second touch sensor parts SP2. The second touch signal lines SL2-1 to SL2-n may also have a mesh shape.

The first touch electrodes (TE1-1 to TE1-m) and the second touch electrodes (TE2-1 to TE2-n) are electrostatically coupled. As touch detection signals are applied to the first touch electrodes TE1-1 to TE1-m, capacitors are formed between the first touch sensor units SP1 and the second touch sensor units SP2.

A plurality of first touch sensor units (SP1), a plurality of first connection parts (CP1), and first touch signal lines (SL1-1 to SL1-m), a plurality of second touch sensor units (SP2), a plurality of Some of the second connection parts CP2 and the second touch signal lines SL2-1 to SL2-n are formed by patterning the first conductive layer TS-CL1 shown in FIG. 8A, and other parts are formed by patterning the first conductive layer TS-CL1 shown in FIG. 8A. Can be formed by patterning the second conductive layer (TS-CL2) shown in FIG. 8A.

In order to electrically connect conductive patterns disposed on different layers, a contact hole penetrating the first touch insulating layer TS-IL1 shown in FIG. 8A may be formed. Hereinafter, a touch sensing unit (TS) according to an embodiment will be described with reference to FIGS. 8C to 8E.

As shown in FIG. 8C, first conductive patterns are disposed on the thin film encapsulation layer (TFE, see FIG. 8A). The first conductive patterns may include bridge patterns CP2. Bridge patterns CP2 are directly disposed on the thin film encapsulation layer (TFE). A thin film encapsulation layer (TFE) covering the display area (DA) is shown as an example. The bridge patterns CP2 correspond to the second connection parts CP2 shown in FIG. 8B.

As shown in FIG. 8D, the first touch insulating layer TS-IL1 covering the bridge patterns CP2 is disposed on the thin film encapsulation layer TFE. Contact holes CH that partially expose the bridge patterns CP2 are defined in the first touch insulating layer TS-IL1. Contact holes (CH) may be formed through a photolithography process.

As shown in FIG. 8E, second conductive patterns are disposed on the first touch insulating layer TS-IL1. The second conductive patterns include a plurality of first touch sensor units SP1 (see FIG. 8B), a plurality of first connection parts CP1, first touch signal lines SL1-1 to SL1-m, and a plurality of first touch signal lines SL1-1 to SL1-m. It may include two touch sensor units (SP2, see FIG. 8B) and second touch signal lines (SL2-1 to SL2-n). Although not separately shown, a second touch insulating layer (TS-IL2) covering the second conductive patterns is disposed on the first touch insulating layer (TS-IL1).

In one embodiment of the present invention, the first conductive patterns may include first touch electrodes (TE1-1 to TE1-m) and first touch signal lines (SL1-1 to SL1-m). The first conductive patterns may include second touch electrodes (TE2-1 to TE2-n) and second touch signal lines (SL2-1 to SL2-n). At this time, contact holes CH are not defined in the first touch insulating layer TS-IL1.

Additionally, in one embodiment of the present invention, the first conductive patterns and the second conductive patterns may be interchanged. That is, the second conductive patterns may include bridge patterns CP2.

Figure 8f is a partially enlarged view of the BB area of Figure 8e.

As shown in FIG. 8F, the first touch sensor unit SP1 overlaps the non-emission area NPXA. The first touch sensor unit SP1 includes a plurality of first extension parts SP1-A extending in the fifth direction DR5 intersecting the first direction DR1 and the second direction DR2 and a fifth direction ( It includes a plurality of second extension parts SP1-B extending in the sixth direction DR6 intersecting DR5). The plurality of first extension parts SP1-A and the plurality of second extension parts SP1-B may be defined as mesh lines. The line width of the mesh lines may be several microns.

The plurality of first extension parts SP1-A and the plurality of second extension parts SP1-B are connected to each other to form a plurality of touch openings TS-OP. In other words, the first touch sensor unit SP1 has a mesh shape with a plurality of touch openings TS-OP. Although the touch openings TS-OP are shown as having a one-to-one correspondence with the light emitting areas PXA, the present invention is not limited thereto. One touch opening (TS-OP) may correspond to two or more light emitting areas (PXA).

The size of the light emitting areas (PXA) may vary. For example, the sizes of the light emitting areas PXA that provide blue light and those that provide red light among the light emitting areas PXA may be different. Accordingly, the sizes of the touch openings TS-OP may also vary. Although FIG. 10 exemplarily shows that the sizes of the light emitting areas PXA are varied, the size is not limited thereto. The sizes of the light emitting areas PXA may be the same, and the sizes of the touch openings TS-OP may also be the same.

FIG. 9A is a partially enlarged view of area AA of FIG. 5C. Figure 9b is a cross-sectional view briefly showing the WW area of Figure 9a.

Referring to FIGS. 9A and 9B, touch signal lines (TSL) are shown. The touch signal lines TSL may be the second touch signal lines SL1-1 to SL1-m shown in FIG. 8B.

The conductive portion EP may be disposed between the touch signal lines TSL and a plurality of clock signal lines CL1, CL2, CL3, CL4 (CL). The conductive portion EP may be disposed on the same layer as the second electrode CE. For example, the conductive portion (EP) and the second electrode (CE) may be disposed on the pixel defining layer (PDL). The meaning of being disposed on the same layer means the same layer (eg, pixel defining layer (PDL)) and does not mean only a flat plane.

The second electrode (CE) extends toward the conductive portion (EP), and the second electrode (CE) and the conductive portion (EP) may be connected to each other. That is, the second electrode (CE) and the conductive part (EP) may be formed through the same process.

The conductive part (EP) may be electrically connected to the power supply line (E-VSS). The conductive part EP may receive the second voltage ELVSS (see FIG. 6A) from the power supply line E-VSS.

The conductive part EP may cover the overlap area OA where the touch signal lines TSL and the clock signal lines CL overlap on a plane. For example, the conductive portion EP may completely cover the overlapping area OA. The conductive part EP can prevent noise from occurring in the touch signal lines TSL due to the clock signal applied to the clock signal lines CL, and as a result, can prevent changes in touch sensitivity due to noise.

The first dam part DM1 and the second dam part DM2 may be disposed in the non-display area NDA. The first dam portion DM1 and the second dam portion DM2 may be arranged to surround the display area DA in a plane view. When printing an organic monomer to form the organic thin film OL1 of the thin film encapsulation layer TFE, the first dam part DM1 and the second dam part DM2 can prevent the organic monomer from overflowing.

The first dam portion DM1 may be disposed on the power supply line E-VSS. The first dam DM1 may be formed as a single layer, and the first dam DM1 may be formed simultaneously with the pixel defining layer PDL.

The second dam unit DM2 may be disposed outside the first dam unit DM1. For example, the distance between the first dam part DM1 and the display area DA may be greater than the distance between the second dam part DM2 and the display area DA.

The second dam portion DM2 may cover a portion of the power supply line (E-VSS). The second dam portion DM2 may be formed of a plurality of layers, and the second dam portion DM2 may include a first layer DM2-1 and a second layer DM2-2. The first layer (DM2-1) may be formed simultaneously with the third insulating layer 30, and the second layer (DM2-2) may be formed simultaneously with the pixel defining layer (PDL).

In FIG. 9A , the pixel definition layer (PDL) is shown extended so as to overlap all of the clock signal lines CL on a plane, but the pixel definition layer (PDL) is not limited thereto. For example, in another embodiment of the present invention, the pixel definition layer (PDL) may extend only to an area that overlaps the gate driving circuit (GDC) or may extend only to an area that overlaps some of the clock signal lines (CL). there is. For example, the pixel definition layer (PDL) includes a third clock signal line (CL3), a fourth clock signal line (CL4), a third voltage line (VL2), a fourth voltage line (VH2), and a second start signal. It may extend only to the area that overlaps the line (EF2).

FIG. 9C is a partially enlarged view of area AA of FIG. 5C.

Referring to FIG. 9C, the conductive portion EP-1 may be disposed between the touch signal lines TSL and a plurality of clock signal lines CL (see FIG. 9B). The conductive portion EP-1 may be disposed on the same layer as the second electrode CE. For example, the conductive portion EP-1 and the second electrode CE may be disposed on the pixel defining layer PDL.

The conductive portion EP-1 may be spaced apart from the second electrode CE. That is, the conductive portion EP-1 and the second electrode CE may not be physically connected to each other. The conductive part (EP-1) may be electrically connected to the power supply line (E-VSS). The conductive part EP-1 may receive the second voltage ELVSS (see FIG. 6A) from the power supply line E-VSS. However, this is an example, and a constant voltage may be applied to the conductive part EP-1. For example, the first voltage (ELVDD (see FIG. 6A)), a ground voltage, or a separate constant voltage other than those listed above may be applied to the conductive portion EP-1.

The second electrode (CE) may be electrically connected to the power supply line (E-VSS) through a pattern not shown. Accordingly, the second electrode CE may receive the second voltage ELVSS (see FIG. 6A) from the power supply line E-VSS.

The conductive portion EP-1 may block the touch sensitivity of the touch sensing unit from changing due to a signal applied to the clock signal lines CL.

Figure 9d is a partial enlarged view of area AA of Figure 5c.

Referring to FIG. 9D , the conductive portion EP-2 may be disposed between the touch signal lines TSL and a plurality of clock signal lines CL (see FIG. 9B). The conductive portion EP-2 may be disposed on the same layer as the second electrode CE.

A plurality of through holes HL may be defined in the conductive portion EP-2. The plurality of through holes HL may serve to discharge gases that may be generated from layers including an organic material layer. The plurality of through holes HL may not overlap the overlap area OA (see FIG. 9B) where the touch signal lines TSL and the clock signal lines CL overlap. FIG. 9D exemplarily shows that the through holes HL are not defined in the area overlapping with the clock signal lines CL (see FIG. 9B) on the plane. In another embodiment of the present invention, the through holes HL may not be defined in areas that overlap the touch signal lines TSL on a plane.

According to an embodiment of the present invention, since through holes HL are not defined in the overlapping area OA (see FIG. 9B), even if a plurality of through holes HL are provided in the conductive part EP-2, the clock It is possible to easily prevent the touch sensitivity of the touch sensing unit from changing due to signals applied to the signal lines CL.

FIG. 10A is a partially enlarged view of area AA of FIG. 5C. FIG. 10B is a cross-sectional view briefly showing area XX of FIG. 10A.

The conductive portion EP-3 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive portion EP-3 may be disposed on the same layer as the first electrode AE. For example, the conductive portion EP-3 and the first electrode AE may be disposed on the third insulating layer 30. The first electrode (AE) and the conductive portion (EP-3) may be formed through the same process.

The conductive part (EP-3) may be electrically connected to the power supply line (E-VSS). The conductive part EP-3 may receive the second voltage ELVSS (see FIG. 6A) from the power supply line E-VSS. However, this is an example, and a constant voltage may be applied to the conductive part EP-3. For example, the first voltage (ELVDD (see FIG. 6A)), a ground voltage, or a separate constant voltage other than those listed above may be applied to the conductive part EP-1.

A plurality of through holes (HL-1) may be defined in the conductive portion (EP-3). The through holes HL-1 may serve to discharge gases that may be generated from layers containing organic matter. The through holes HL-1 may not overlap the overlap area OA where the touch signal lines TSL and the clock signal lines CL overlap. More specifically, in FIG. 10A, the through holes HL-1 may not be defined in areas that overlap the clock signal lines CL on a plane. Accordingly, the conductive portion EP-3 may completely cover the overlap area OA where the touch signal lines TSL and the clock signal lines CL overlap on a plane. The conductive part EP-3 may block noise from occurring in the touch signal lines TSL due to the clock signal applied to the clock signal lines CL. That is, changes in touch sensitivity can be reduced by the conductive portion EP-3, and a touch sensing unit with uniform touch sensitivity can be provided.

FIG. 10C is a partially enlarged view of area AA of FIG. 5C. FIG. 10D is a cross-sectional view briefly showing the YY area of FIG. 10C.

The conductive portion EP-4 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. A plurality of through holes (HL-2) may be defined in the conductive portion (EP-4).

The through holes HL-2 may not overlap the overlap area OA where the touch signal lines TSL and the clock signal lines CL overlap. More specifically, in FIG. 10C, the through holes HL-2 may not be defined in areas overlapping the touch signal lines TSL on a plane.

The conductive part EP-4 may shield a signal applied to the clock signal lines CL below the touch signal lines TSL. That is, since the through-holes HL-2 are not defined in the area overlapping the touch signal lines TSL, the touch signal lines TSL are affected by signals from each of the clock signal lines CL. Noise may not occur.

FIG. 11A is a partially enlarged view of area AA of FIG. 5C. FIG. 11B is a cross-sectional view briefly showing the ZZ region of FIG. 11A.

The conductive portion EP-5 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive portion EP-5 may include a first conductive layer (EP-L1) and a second conductive layer (EP-L2). The first conductive layer EP-L1 may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 may be disposed on the same layer as the second electrode CE. For example, the first conductive layer (EP-L1) and the first electrode (AE) may be disposed on the third insulating layer 30, and the second conductive layer (EP-L2) and the second electrode (CE) may be disposed on the pixel It may be placed on the defining layer (PDL). The first conductive layer (EP-L1) and the first electrode (AE) may be formed by the same process, and the second conductive layer (EP-L2) and the second electrode (CE) may be formed by the same process. there is.

Each of the first conductive layer (EP-L1) and the second conductive layer (EP-L2) may be electrically connected to the power supply line (E-VSS). Each of the first conductive layer (EP-L1) and the second conductive layer (EP-L2) may receive the second voltage (ELVSS (see FIG. 6A)) from the power supply line (E-VSS). However, this is an example, and a constant voltage may be applied to the second conductive layer (EP-L2). For example, the first voltage (ELVDD, see FIG. 6A) may be applied to the second conductive layer (EP-L2), a ground voltage may be applied, or a separate constant voltage other than those listed above may be applied. .

A plurality of first through holes HL-3 may be defined in the first conductive layer EP-L1. The plurality of first through holes HL-3 may serve to discharge gases that may be generated from layers containing organic materials. Although FIG. 11A exemplarily shows a plurality of first through holes HL-3 arranged at regular intervals, the present invention is not limited thereto.

The second conductive layer EP-L2 may cover all of the plurality of first through holes HL-3 in a plane view. According to this embodiment, the space between the touch signal lines (TSL) and the plurality of clock signal lines (CL) may be double shielded by the first conductive layer (EP-L1) and the second conductive layer (EP-L2). there is. In addition, the area that is not shielded by the plurality of first through holes HL-3 on the plane will be shielded by the second conductive layer EP-L2 covering the plurality of first through holes HL-3. You can. Therefore, even if high and low level voltages are alternately applied to the plurality of clock signal lines CL, the plurality of clock signal lines are connected by the first conductive layer EP-L1 and the second conductive layer EP-L2. Since the signal applied to the fields CL is shielded, noise may not occur in the touch signal lines TSL.

FIG. 11C is a partially enlarged view of area AA of FIG. 5C.

The conductive portion EP-6 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive portion EP-6 may include a first conductive layer EP-L1 and a second conductive layer EP-L2a. The conductive portion EP-6 of FIG. 11C has a different shape of the second conductive layer EP-L2a compared to the conductive portion EP-5 previously described in FIG. 11A.

Previously, in FIG. 11A, the second electrode (CE) extends toward the second conductive layer (EP-L2), and the second electrode (CE) and the second conductive layer (EP-L2) may be physically connected to each other. However, in FIG. 11B, the second conductive layer (EP-L2a) may be spaced apart from the second electrode (CE). That is, the conductive portion EP-1 and the second electrode CE may not be physically connected to each other.

FIG. 12A is a partially enlarged view of area AA of FIG. 5C. FIG. 12B is an enlarged plan view of a portion of the configuration shown in FIG. 12A.

The conductive portion EP-6 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive portion EP-6 may include a first conductive layer (EP-L1a) and a second conductive layer (EP-L2). The first conductive layer (EP-L1a) may be disposed on the same layer as the first electrode (AE), and the second conductive layer (EP-L2) may be disposed on the same layer as the second electrode (CE). For example, the first conductive layer (EP-L1a) and the first electrode (AE) may be disposed on the third insulating layer 30, and the second conductive layer (EP-L2) and the second electrode (CE) may be disposed on the pixel It may be placed on the defining layer (PDL). The first conductive layer (EP-L1a) and the first electrode (AE) may be formed by the same process, and the second conductive layer (EP-L2) and the second electrode (CE) may be formed by the same process. there is.

A plurality of first through holes HL-4 may be defined in the first conductive layer EP-L1a. The plurality of first through holes HL-4 may serve to discharge gases that may be generated from layers containing organic materials. The plurality of first through holes HL-4 may not be defined in an area overlapping the clock signal lines CL on a plane.

In Figure 12b, the third clock signal line (CL3), the fourth clock signal line (CL4), the third voltage line (VL2), the fourth voltage line (VH2), and the second start signal line (EF2) are illustratively shown. Shown. The plurality of first through-holes HL-4 may not be defined in an area overlapping with the third clock signal line CL3 and the fourth clock signal line CL4.

A signal whose level continuously changes while an image of one frame is displayed may be applied to the third clock signal line CL3 and the fourth clock signal line CL4. Therefore, if the upper part of the third clock signal line CL3 and the fourth clock signal line CL4 is not shielded, noise may be generated in the touch signal lines TSL due to the signals. According to an embodiment of the present invention, since the plurality of first through-holes HL-4 are not defined in the upper portions of the third clock signal line CL3 and the fourth clock signal line CL4, the third clock signal line The upper portions of the line CL3 and the fourth clock signal line CL4 are completely shielded. Accordingly, noise may be prevented from occurring in the touch signal lines TSL by signals applied to the third clock signal line CL3 and the fourth clock signal line CL4.

The first conductive layer EP-L1a may include a first area AR1, a second area AR2, and a third area AR3. The first area AR1, the second area AR2, and the third area AR3 are shown in FIG. 12B.

The first area AR1 overlaps the clock signal lines CL and may be an area in which the plurality of first through holes HL-4 are not defined. FIG. 12B shows a first area AR1 that does not overlap the third and fourth clock signal lines CL3 and CL4. The second area AR2 is an area where a plurality of first through holes HL-4 are defined, and the area exposed by the plurality of first through holes HL-4 and HL-4a is the first area. It may be an area with density. The third area AR3 is an area where a plurality of first through holes HL-4 are defined, and the area exposed by the plurality of first through holes HL-4 has a second areal density. It can be. The second areal density may be lower than the first areal density. The exposed area may be the third insulating layer 30. For example, the number of the plurality of first through holes HL-4 defined in the second area AR2 may be two per first area SA1, and the number of the plurality of first through holes HL-4 defined in the second area AR2 may be two, and the number of the plurality of first through holes HL-4 defined in the second area AR2 may be two. The number of the plurality of first through holes HL-4 may be one per first area SA1.

Since the plurality of first through-holes HL-4 are not defined in the first area AR1 overlapping the third clock signal line CL3 and the fourth clock signal line CL4, in order to compensate for this, the plurality of first through-holes HL-4 are not defined. A plurality of first through holes HL-4a may be further defined in the second area AR2.

The shape of the hole HLa is shown by a dotted line in the first area AR1. This is shown for convenience of explanation, and does not mean that the hole HLa is defined in the first area AR1. Assuming that the plurality of first through holes HL-4 are arranged at uniform intervals, there must be a hole HLa in the first area AR1, but the hole is not defined in the first area AR1. . Accordingly, the layer (for example, the third insulating layer 30) below the first conductive layer (EP-L1a) is formed in the first conductive layer (EP-L1a) by the first through holes (HL-4). The design condition that more than a predetermined area must be exposed may not be satisfied, and as a result, gases that may be generated from layers containing organic matter may not be smoothly discharged. To prevent this, first through-holes HL-4a may be additionally defined in the second area AR2 to correspond to the number of holes HLa that are not defined in the first area AR1. Accordingly, the layer (for example, the third insulating layer 30) below the first conductive layer (EP-L1a) is formed by the first through holes (HL-4) of the first conductive layer (EP-L1a). The design condition that more than a certain area must be exposed can be satisfied. To facilitate understanding, arrows are drawn between the virtual hole (HLa) and the first through holes (HL-4a) to show the movement relationship of the holes. The arrows are not elements, but are shown simply to aid understanding.

FIG. 12C is an enlarged plan view of a portion of the configuration shown in FIG. 12A.

In FIG. 12C, there must be a hole HLa in the first area AR1, but since the hole is not defined in the first area AR1, first through holes are arranged in the second area AR2 to compensate for this. As an example, the size of (HL-4b) was expanded.

The expansion of the size of the first through holes HL-4b is equivalent to the expansion of the exposed area of the third insulating layer 30 (see FIG. 12A) disposed below the first through holes HL-4b. has As a result, the design condition that the first through holes HL-4 must have a predetermined area or more on the conductive part EP-6 (see FIG. 12A) can be satisfied.

In FIG. 12C , the first through-holes HL-4b are shown as an example in which only the width in the vertical direction is expanded compared to the first through-hole HL-4, but the present invention is not limited thereto. For example, the width of the first through-holes HL-4b may be expanded in the horizontal direction compared to the first through-hole HL-4, and the width in both the vertical and horizontal directions may be expanded.

FIG. 13A is a partially enlarged view of area AA of FIG. 5C. FIG. 13B is an enlarged plan view of a portion of the configuration shown in FIG. 13A.

The conductive portion EP-7 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive portion EP-7 may include a first conductive layer (EP-L1b) and a second conductive layer (EP-L2). The first conductive layer (EP-L1b) may be disposed on the same layer as the first electrode (AE), and the second conductive layer (EP-L2) may be disposed on the same layer as the second electrode (CE). For example, the first conductive layer (EP-L1b) and the first electrode (AE) may be disposed on the third insulating layer 30, and the second conductive layer (EP-L2) and the second electrode (CE) may be disposed on the pixel It may be placed on the defining layer (PDL). The first conductive layer (EP-L1b) and the first electrode (AE) may be formed by the same process, and the second conductive layer (EP-L2) and the second electrode (CE) may be formed by the same process. there is.

A plurality of first through holes HL-5 may be defined in the first conductive layer EP-L1b. The plurality of first through holes HL-5 may serve to discharge gases that may be generated from layers containing organic materials. The plurality of first through holes HL-5 may not be defined in an area overlapping the touch signal lines TSL on a plane.

FIG. 13B illustrates some touch signal lines (TSL) as an example. The plurality of first through holes HL-5 may not be defined in an area overlapping the touch signal lines TSL.

That is, since the plurality of first through-holes HL-5 are not defined below the touch signal lines TSL, the influence of the AC signal applied to the clock signal lines CL can be reduced. Accordingly, the probability of noise occurring in the touch signal lines (TSL) is reduced, and changes in touch sensitivity due to noise can be prevented.

The first conductive layer EP-L1b may include a first area AR1, a second area AR2, and a third area AR3. The first area AR1, the second area AR2, and the third area AR3 are shown in FIG. 13B.

The first area AR1 overlaps the touch signal lines TSL and may be an area in which the plurality of first through holes HL-5 are not defined. The second area AR2 is an area defined by a plurality of first through holes HL-5 and HL-5a, and is an area exposed by the plurality of first through holes HL-5 and HL-5a. This may be an area having the first areal density. The third area AR3 is an area where a plurality of first through holes HL-5 are defined, and the area exposed by the plurality of first through holes HL-5 has a second areal density. It can be. The second areal density may be lower than the first areal density. The exposed area may be the third insulating layer 30. For example, the number of the plurality of first through holes HL-5 defined in the second area AR2 may be two per first area SA1, and the number of the plurality of first through holes HL-5 defined in the second area AR2 may be two, and the number of the plurality of first through holes HL-5 defined in the second area AR2 may be two. The number of the plurality of first through holes HL-5 may be one per first area SA1.

Since the plurality of first through holes HL-5 are not defined in the first area AR1 overlapping the touch signal lines TSL, a plurality of first through holes HL-5 are formed in the second area AR2 to compensate for this. Through holes HL-5a may be further defined. For example, the shape of the hole HLa is shown as a dotted line in the first area AR1. This is shown for convenience of explanation, and does not mean that the hole HLa is defined in the first area AR1. Assuming that the plurality of first through holes HL-5 are arranged at uniform intervals, there must be a hole HLa in the first area AR1, but the hole is not defined in the first area AR1. . Accordingly, the layer (for example, the third insulating layer 30) below the first conductive layer (EP-L1b) is formed in the first conductive layer (EP-L1b) by the first through holes (HL-5). The design condition that more than a predetermined area must be exposed may not be satisfied, and as a result, gases that may be generated from layers containing organic matter may not be smoothly discharged. To prevent this, first through-holes HL-5a may be additionally defined in the second area AR2 corresponding to the number of holes HLa that are not defined in the first area AR1. Accordingly, the layer (for example, the third insulating layer 30) below the first conductive layer (EP-L1b) is formed by the first through holes (HL-5) of the first conductive layer (EP-L1b). The design condition that more than a certain area must be exposed can be satisfied.

Although not shown in FIG. 13B, the size of the first through holes HL-5 disposed in the second area AR2 is expanded to compensate for the fact that the hole is not defined in the first area AR1 as shown in FIG. 12C. You can also do it.

Figure 14a is a partial enlarged view of area AA of Figure 5c. FIG. 14B is an enlarged plan view of a portion of the configuration shown in FIG. 14A.

The conductive portion EP-8 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive portion EP-8 may include a first conductive layer EP-L1c and a second conductive layer EP-L2b. The first conductive layer (EP-L1c) may be disposed on the same layer as the first electrode (AE), and the second conductive layer (EP-L2b) may be disposed on the same layer as the second electrode (CE).

A plurality of first through holes HL-6 may be defined in the first conductive layer EP-L1c. The plurality of first through holes HL-6 may serve to discharge gases that may be generated from layers containing organic materials. A plurality of second through holes HL-7 may be defined in the second conductive layer EP-L2b. The plurality of second through holes HL-7 may serve to discharge gases that may be generated from layers containing organic materials.

On a plane, the first through holes HL-6 and the second through holes HL-7 may not overlap each other. Accordingly, the area where the first through holes HL-6 are formed is covered by the second conductive layer EP-L2b, and the area where the second through holes HL-7 are formed is covered with the first conductive layer EP-L2b. -L1c). Accordingly, the overlapping area between the touch signal lines TSL and the plurality of clock signal lines CL is shielded by at least one of the first conductive layer EP-L1c and the second conductive layer EP-L2b. It can be. That is, the conductive part EP-8 can reduce changes in touch sensitivity caused by noise generated from signals of the clock signal lines CL.

In FIG. 14B, each of the plurality of first through holes HL-6 and the plurality of second through holes HL-7 is arranged in the second direction DR1 and alternately along the first direction DR1. The arrangement is shown as an example, but is not limited thereto. The plurality of first through holes HL-6 and the plurality of second through holes HL-7 do not overlap on a plane and may have various arrangements. For example, a plurality of first through holes HL-6 and a plurality of second through holes HL-7 may be alternately arranged in the first direction DR1 and the second direction DR2. there is.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or have ordinary knowledge in the relevant technical field should not deviate from the spirit and technical scope of the present invention as set forth in the claims to be described later. It will be understood that the present invention can be modified and changed in various ways within the scope of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

DD: Display device DM: Display module
DP: Organic light emitting display panel TS: Touch sensing unit
SUB: Base layer DP-CL: Circuit layer
DP-OLED: Light emitting element layer TFE: Thin film encapsulation layer
DA: Display area NDA: Non-display area

Claims (20)

Comprising a base layer, a light emitting device layer disposed on the base layer, first signal lines disposed on the base layer, a conductive layer overlapping the first signal lines, and an encapsulation layer disposed on the light emitting device layer. display panel;
an insulating layer disposed on the encapsulation layer;
Sensing electrodes disposed on the insulating layer; and
disposed on the insulating layer and comprising second signal lines electrically connected to the sensing electrodes,
The conductive layer is disposed between the first signal lines and the second signal lines,
A display device wherein the upper surface of the insulating layer includes a first portion having peaks and valleys and a flat second portion, and the sensing electrodes and the second signal lines are disposed on the second portion. According to claim 1,
The upper surface of the encapsulation layer and the lower surface of the insulating layer include curved portions,
A display device in which the lower surface of the insulating layer and the upper surface of the encapsulation layer are in direct contact. According to claim 1,
The light-emitting device layer includes a first electrode, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer, and the conductive layer is disposed on the same layer as the second electrode. Device. According to clause 3,
The second electrode extends toward the conductive layer, and the second electrode and the conductive layer are connected to each other. According to claim 1,
The display panel further includes a gate driving circuit, and each of the first signal lines provides clock signals to the gate driving circuit. According to claim 1,
The display device wherein the encapsulation layer includes at least one inorganic layer and at least one organic layer. According to claim 1,
A display device in which a plurality of through holes are defined in the conductive layer, and the plurality of through holes do not overlap with the first signal lines or the second signal lines. According to clause 7,
The conductive layer is,
a first region in which the plurality of through holes are not defined and overlaps at least one of the first signal lines and the second signal lines;
a second area where the area exposed by the plurality of through holes has a first areal density; and
A display device wherein an area exposed by the plurality of through holes includes a third area having a second areal density lower than the first areal density. According to clause 8,
The display device wherein the first number of first through-holes defined in the second area is greater than the first number of second through-holes defined in the third area. According to clause 8,
The display device wherein the size of the first through hole defined in the second area is larger than the size of the second through hole defined in the third area. According to claim 1,
A display device further comprising pads electrically connected to the second signal lines. According to claim 1,
The display panel includes a display area and a non-display area adjacent to the display area, and a top surface of the display panel overlapping the non-display area includes a curved surface. According to claim 12,
The display device wherein the insulating layer is directly disposed on the upper surface of the display panel. According to claim 12,
The first signal lines and the second signal lines are disposed in the non-display area. According to claim 12,
At least a portion of the conductive layer is disposed in the non-display area. According to claim 12,
The display panel further includes a first dam disposed in the non-display area and a second dam spaced apart from the first dam. According to claim 16,
The peak of the insulating layer overlaps the first dam or the second dam, and the valley of the insulating layer overlaps an area between the first dam and the second dam. A display area and a non-display area adjacent to the display area are defined, a light emitting element layer disposed in the display area, first signal lines disposed in the non-display area and providing a signal for controlling the light emitting element layer, a display panel including a conductive layer disposed in the non-display area and overlapping the first signal lines, a dam disposed in the non-display area, and an encapsulation layer disposed on the light emitting device layer and the dam;
an insulating layer disposed on the encapsulation layer and having a peak overlapping with the dam;
Sensing electrodes disposed on the insulating layer; and
disposed on the insulating layer and comprising second signal lines electrically connected to the sensing electrodes,
The conductive layer is disposed between the first signal lines and the second signal lines,
A display device wherein the upper surface of the encapsulation layer and the lower surface of the insulating layer include curved portions. According to clause 18,
The upper surface of the insulating layer includes a first portion having the peak and a valley adjacent to the peak, and a second portion extending from the first portion and being flat, and the sensing electrodes and the second signal lines are connected to the second portion. Display device placed above. According to clause 19,
The display panel further includes an additional dam spaced apart from the dam, a valley overlaps an area between the dam and the additional dam, and the height of the additional dam is different from the height of the dam.

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