KR20220150850A - Display apparatus - Google Patents

Abstract

A display device defines a display area and a non-display area adjacent to the display area and comprises: a display panel including a light emitting layer disposed in the display area, first signal lines disposed in the non-display area and providing signals for controlling the light emitting element layer, a conductive part disposed in the non-display area and overlapping the first signal lines, and an encapsulation layer for sealing the light emitting element layer; an insulating layer disposed directly on the encapsulation layer; sensing electrodes disposed on the insulating layer; and second signal lines disposed on the insulating layer and electrically connected to the sensing electrodes. The conductive part is disposed between the first signal lines and the second signal lines. A portion of the upper surface of the encapsulation layer disposed in the non-display area includes a curved portion. The insulating layer may be curved along the curved portion of the upper surface of the encapsulation layer. Accordingly, the conductive part may prevent noise from being generated in touch signal lines due to a change in the level of a signal applied to clock signal lines.

Description

Display device {DISPLAY APPARATUS}

The present invention relates to a display device, and relates to a display device providing uniform touch sensitivity.

Various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game machines are being developed. Input devices of the display devices include a keyboard or a mouse. Also, recent display devices include a touch sensing unit as an input device.

An object of the present invention is to provide a display device including a touch sensing unit having uniform touch sensitivity.

A display device according to an exemplary embodiment of the present invention defines a display area and a non-display area adjacent to the display area, a light emitting layer disposed in the display area, and a signal disposed in the non-display area and controlling the light emitting element layer. A display panel including first signal lines providing a , a conductive portion disposed in the non-display area and overlapping the first signal lines, and an encapsulation layer sealing the light emitting element layer, directly on the encapsulation layer. an insulating layer, sensing electrodes disposed on the insulating layer, and second signal lines disposed on the insulating layer and electrically connected to the sensing electrodes, wherein the conductive part comprises the first signal line A portion of the upper surface of the encapsulation layer disposed between the lines and the second signal lines and disposed in the non-display area includes a curved portion, and the insulating layer includes the curved portion of the upper surface of the encapsulation layer. can be bent along

The light emitting element layer may include a first electrode, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer, and the conductive part may be disposed on the same layer as the second electrode. .

The second electrode may extend toward the conductive part, and the second electrode and the conductive part may be connected to each other.

The first signal lines may be clock signal lines to which a clock signal is applied.

The display panel may further include a gate driving circuit, and each of the first signal lines may provide clock signals to the gate driving circuit.

The encapsulation layer may include at least one inorganic layer and at least one organic layer.

A plurality of through holes may be defined in the conductive part, and the plurality of through holes may not overlap the first signal lines or the second signal lines.

In the conductive part, the plurality of through holes are not defined, and a first region overlapping at least one of the first signal lines and the second signal lines and a region exposed by the plurality of through holes are second. A second area having an area density of 1, and an area exposed by the plurality of through holes may include a third area having a second area density lower than the first area density.

The number of first through holes defined in the second area per first area may be greater than the number of second through holes defined in the third area per first area.

A size of the first through hole defined in the second area may be greater than a size of the second through hole defined in the third area.

The display device may further include sensing pads disposed in the non-display area and electrically connected to the second signal lines.

A display device according to an exemplary embodiment of the present invention includes a display panel in which a display area and a non-display area adjacent to the display area are defined, and a portion of an upper surface overlapping the non-display area is curved; an insulating layer, sensing electrodes disposed on the insulating layer, and sensing lines disposed on the insulating layer and electrically connected to the sensing electrodes, wherein the display panel includes a clock signal disposed in the non-display area. A light emitting element layer disposed in the display area, including lines, a first electrode, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer, disposed in the non-display area, It is disposed on the same layer as the second electrode, and includes a conductive portion disposed between the clock signal lines and the sensing lines, and an encapsulation layer disposed on the light emitting element layer and the conductive portion and defining the upper surface; , The insulating layer may be curved along a curved shape of a portion of the upper surface.

The display panel may further include a gate driving circuit, and each of the clock signal lines may provide a clock signal to the gate driving circuit.

A plurality of through holes may be defined in the conductive part, and the plurality of through holes may not overlap the clock signal lines or the sensing lines.

Sensing pads disposed in the non-display area and electrically connected to the sensing lines, respectively, may be further included.

A display device according to an embodiment of the present invention includes a conductive portion covering an overlapping region where a plurality of clock signal lines and a plurality of touch signal lines overlap. The conductive unit may prevent noise from being generated in the touch signal lines due to a change in level of a signal applied to the clock signal lines. That is, the conductive part may block the change in touch sensitivity of the touch sensing unit due to the noise.

1A is a perspective view according to a first operation of a display device according to an exemplary embodiment of the present invention.
1B is a perspective view according to a second operation of a display device according to an exemplary embodiment of the present invention.
1C is a perspective view of a third operation of a display device according to an exemplary embodiment of the present invention.
2 is a cross-sectional view of a display device according to an exemplary embodiment of the present invention.
3A and 3B are perspective views of a display device according to an exemplary embodiment of the present invention.
4A is a perspective view of a display device according to an exemplary embodiment of the present invention.
4B is a perspective view of a display device according to an exemplary embodiment of the present invention.
5A is a plan view of an organic light emitting display panel according to an exemplary embodiment of the present invention.
5B is a block diagram of a driving stage of a gate driving circuit according to an embodiment of the present invention.
5C is a cross-sectional view of a display module according to an embodiment of the present invention.
6A is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
6B is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment.
6C is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment of the present invention.
7A to 7C are cross-sectional views of thin film encapsulation layers according to an embodiment of the present invention.
8A is a cross-sectional view of a touch sensing unit according to an embodiment of the present invention.
8B to 8E are plan views of a touch sensing unit according to an embodiment of the present invention.
FIG. 8F is a partially enlarged view of the BB region of FIG. 8E.
9A is a partially enlarged view of an area AA of FIG. 5C.
FIG. 9B is a cross-sectional view schematically illustrating the WW region of FIG. 9A.
9C is a partially enlarged view of the area AA of FIG. 5C.
9D is a partially enlarged view of the area AA of FIG. 5C.
10A is a partially enlarged view of an area AA of FIG. 5C.
FIG. 10B is a cross-sectional view schematically illustrating an area XX of FIG. 10A.
FIG. 10C is a partially enlarged view of area AA of FIG. 5C.
FIG. 10D is a cross-sectional view schematically illustrating area YY of FIG. 10C.
11A is a partially enlarged view of an area AA of FIG. 5C.
FIG. 11B is a cross-sectional view schematically illustrating the ZZ region of FIG. 11A.
11C is a partially enlarged view of the area AA of FIG. 5C.
12A is a partially enlarged view of an area AA of FIG. 5C.
FIG. 12B is an enlarged plan view of some components shown in FIG. 12A.
FIG. 12c is a plan view showing an enlarged portion of the components shown in FIG. 12a.
FIG. 13A is a partially enlarged view of area AA of FIG. 5C.
FIG. 13B is an enlarged plan view of some components shown in FIG. 13A.
14A is a partially enlarged view of an area AA of FIG. 5C.
FIG. 14B is an enlarged plan view of some components shown in FIG. 14A.

Since the present invention may have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

In this specification, when an element (or region, layer, section, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it is directly connected/connected to the other element. It means that they can be combined or a third component can be placed between them.

Like reference numerals designate like components. Also, in the drawings, the thickness, ratio, and dimensions of components are exaggerated for effective description of technical content. “And/or” includes any combination of one or more that the associated elements may define.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In addition, terms such as "below", "lower side", "above", and "upper side" are used to describe the relationship between components shown in the drawings. The above terms are relative concepts and will be described based on the directions shown in the drawings.

Terms such as "include" or "have" are intended to indicate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but that one or more other features, numbers, or steps are present. However, it should be understood that it does not preclude the possibility of existence or addition of operations, components, parts, or combinations thereof.

1A is a perspective view of a first operation of a display device DD according to an exemplary embodiment of the present invention. 1B is a perspective view according to a second operation of the display device DD according to an embodiment of the present invention. 1C is a perspective view of a third operation of the display device DD according to an exemplary embodiment of the present invention.

As shown in FIG. 1A , in the first operation mode, the display surface IS on which the image IM is displayed is parallel to the plane defined by the first and second directions DR1 and DR2 . The third direction DR3 indicates the normal direction of the display surface IS, that is, the thickness direction of the display device DD. The front (or upper surface) and rear surface (or lower surface) of each member are divided by the third direction DR3. However, the directions indicated by the first to third directions DR1 , DR2 , and DR3 may be converted into other directions as a relative concept. Hereinafter, the same reference numerals refer to directions indicated by the first to third directions DR1 , DR2 , and DR3 , respectively.

1A to 1C illustrate a flexible foldable display device as an example of the display device DD. However, the present invention may be a rollable display device or a banded display device that rolls, and is not particularly limited. In addition, although the flexible display device is shown in this embodiment, the present invention is not limited thereto. The display device DD according to this embodiment may be a flat rigid display device or a curved rigid display device. The display device DD according to the present invention may be used in large-sized electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as mobile phones, tablets, car navigation devices, game consoles, and smart watches.

As shown in FIG. 1A , the display surface IS of the display device DD may include a plurality of areas. The display device DD includes a display area DD-DA where the image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is an area in which an image is not displayed. FIG. 1A shows a vase as an example of the image IM. As an example, the display area DD-DA may have a rectangular shape. The non-display area DD-NDA may surround the display area DD-DA. However, it is not limited thereto, and the shape of the display area DD-DA and the shape of the non-display area DD-NDA can be designed relatively.

As shown in FIGS. 1A to 1C , the display device DD may include a plurality of regions defined according to an operation type. The display device DD includes a bending area BA that is bent, a first non-bending area NBA1 that is non-bending, and a second non-bending area NBA2 that is bent on the basis of the bending axis BX. can include

As shown in FIG. 1B , the display device DD is inner bent so that the display surface IS of the first non-bending area NBA1 and the display surface IS of the second non-bending area NBA2 face each other. -bending). As shown in FIG. 1C , the display device DD may be outer-bended so that the display surface IS is exposed to the outside.

Although only one bending area BA is illustrated in FIGS. 1A to 1C , the present invention is not limited thereto. For example, in one embodiment of the present invention, the display device DD may include a plurality of bending areas BA.

In one embodiment of the present invention, the display device DD may be configured to repeat only the operation modes shown in FIGS. 1A and 1B. However, the present invention is not limited thereto, and the bending area BA may be defined to correspond to a shape in which the user manipulates the display device DD. For example, unlike FIGS. 1B and 1C , the bending area BA may be defined parallel to the first direction DR1 or may be defined in a diagonal direction. The area of the bending area BA is not fixed and may be determined according to the radius of curvature.

2 is a cross-sectional view of a display device DD according to an exemplary embodiment. 2 illustrates a cross section defined by the second and third directions DR2 and DR3.

As shown in FIG. 2, the display device DD includes a protective film PM, a display module DM, an optical member LM, a window WM, a first adhesive member AM1, and a second adhesive member ( AM2), and a third adhesive member AM3. The display module DM is disposed between the protective film PM and the optical member LM. The optical member LM is disposed between the display module DM and the window WM. The first adhesive member AM1 couples the display module DM and the protective film PM, the second adhesive member AM2 couples the display module DM and the optical member LM, and the third adhesive member AM2 couples the display module DM and the optical member LM. (AM3) couples the optical member (LM) and the window (WM).

The protective film PM protects the display module DM. The protective film PM provides the first outer surface OS-L exposed to the outside and provides an adhesive surface adhered to the first adhesive member AM1. The protective film PM prevents external moisture from penetrating into the display module DM and absorbs external impact.

The protective film PM may include a plastic film as a base substrate. The protective film (PM) is polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylenenaphthalate (PEN), polyethyleneterephthalate (PET), polyetherimide (PEI), phenylene sulfide (PPS, polyphenylene sulfide), polyarylate, polyimide (PI, polyimide), polycarbonate (PC, polycarbonate), poly(arylene ethersulfone), and combinations thereof. It may include a plastic film containing any one selected from the group consisting of

Materials constituting the protective film PM are not limited to plastic resins and may include organic/inorganic composite materials. The protective film PM may include a porous organic layer and an inorganic material filled in pores of the organic layer. The protective film PM may further include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. In one embodiment of the present invention, the protective film (PM) may be omitted.

The window WM may protect the display module DM from external impact and provide an input surface to the user. The window WM provides a second outer surface OS-U exposed to the outside and provides an adhesive surface adhered to the second adhesive member AM2. The display surface IS shown in FIGS. 1A to 1C may be the second outer surface OS-U.

The window WM may include a plastic film. The window WM may have a multi-layered structure. The window WM may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WM may further include a bezel pattern. The multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer.

The optical member LM reduces reflectance of external light. The optical member LM may include at least a polarizing film. The optical member LM may further include a retardation film. In one embodiment of the present invention, the optical member LM may be omitted.

The display module DM may include an organic light emitting display panel (DP, or display panel) and a touch sensing unit TS. The touch sensing unit TS is directly disposed on the organic light emitting display panel DP. In this specification, "directly disposed" means formed by a continuous process, excluding attachment using a separate adhesive layer.

The organic light emitting display panel DP generates an image (IM, see FIG. 1A) corresponding to the input image data. The organic light emitting display panel DP provides a first display panel surface BS1 -L and a second display panel surface BS1 -U facing each other in the thickness direction DR3 . Although the organic light emitting display panel DP has been described as an example in this embodiment, the display panel is not limited thereto.

The touch sensing unit TS acquires coordinate information of an external input. The touch sensing unit TS may sense an external input in a capacitive manner.

Although not separately shown, the display module DM according to an embodiment of the present invention may further include an antireflection layer. The antireflection layer may include a color filter or a multilayer structure of a conductive layer/insulation layer/conductive layer. The anti-reflection layer may reduce external light reflectance by absorbing, destructively interfering with, or polarizing light incident from the outside. The antireflection layer may replace the function of the optical member LM.

Each of the first adhesive member (AM1), the second adhesive member (AM2), and the third adhesive member (AM3) is an optically clear adhesive film (OCA) or an optically clear adhesive resin (OCR). Alternatively, it may be an organic adhesive layer such as a pressure sensitive adhesive film (PSA). The organic adhesive layer may include an adhesive material such as polyurethane-based, polyacrylic-based, polyester-based, polyepoxy-based, or polyvinyl acetate-based.

Although not separately shown, the display device DD may further include a frame structure supporting the functional layers to maintain the state shown in FIGS. 1A to 1C . The frame structure may include a joint structure or a hinge structure.

3A and 3B are perspective views of a display device DD-1 according to an embodiment of the present invention. FIG. 3A shows the display device DD-1 in an unfolded state, and FIG. 3B shows the display device DD-1 in a bent state.

The display device DD- 1 may include one bending area BA and one non-bending area NBA. The non-display area DD-NDA of the display device DD-1 may be bent. However, in one embodiment of the present invention, the bending area of the display device DD-1 may be changed.

Unlike the display device DD shown in FIGS. 1A to 1C , the display device DD- 1 according to the present embodiment may be fixed and operated in one form. The display device DD-1 may operate in a bent state as shown in FIG. 3B. The display device DD-1 may be fixed to a frame in a bent state, and the frame may be coupled to a housing of an electronic device.

The display device DD- 1 according to this embodiment may have the same cross-sectional structure as that shown in FIG. 2 . However, the non-bending area NBA and the bending area BA may have a different stacked structure. The non-bending area NBA may have the same cross-sectional structure as that shown in FIG. 2 , and the bending area BA may have a cross-sectional structure different from that shown in FIG. 2 . The optical member LM and the window WM may not be disposed in the bending area BA. That is, the optical member LM and the window WM may be disposed only in the non-bending area NBA. The second adhesive member AM2 and the third adhesive member AM3 may also not be disposed in the bending area BA.

4A is a perspective view of a display device DD-2 according to an embodiment of the present invention.

The display device DD-2 includes a non-bending area (NBA, or flat area) in which the main image is displayed on the front side and a bending area (BA, or side area) in which the sub image is displayed on the side. Although not separately shown, the sub image may include an icon providing predetermined information. In this embodiment, the term "non-bending area NBA and bending area BA" defines the display device DD-2 as a plurality of areas divided into shapes.

The bending area BA bent from the non-bending area NBA displays a sub image in a fourth direction DR4 crossing the first direction DR1 , the second direction DR2 , and the third direction DR3 . . However, directions indicated by the first to fourth directions DR1 to DR4 may be converted to other directions as a relative concept.

4B is a perspective view of a display device DD-3 according to an embodiment of the present invention.

The display device DD-3 includes a non-bending area NBA where the main image is displayed on the front side, and a first bending area BA1 and a second bending area BA2 where the sub image is displayed on the side. The first bending area BA1 and the second bending area BA2 may be bent from both sides of the non-bending area NBA.

5A is a plan view of an organic light emitting display panel DP according to an exemplary embodiment of the present invention.

As shown in FIG. 5A , the organic light emitting display panel DP includes a display area DA and a non-display area NDA on a plane. The display area DA and the non-display area NDA of the organic light emitting display panel DP are the display area DD-DA (see FIG. 1A) and the non-display area DD-NDA of the display device DD (see FIG. 1A). , see Fig. 1a) respectively. The display area DA and the non-display area NDA of the organic light emitting display panel DP are the display area DD-DA (see FIG. 1A) and the non-display area DD-NDA of the display device DD (see FIG. 1A). , see FIG. 1A) and may be changed according to the structure/design of the organic light emitting display panel DP.

The organic light emitting display panel DP includes a plurality of pixels PX. An area where the plurality of pixels PX is disposed is defined as a display area DA. In this embodiment, the non-display area NDA may be defined along the edge of the display area DA.

The organic light emitting display panel DP includes gate lines GL, data lines DL, emission lines EL, a control signal line SL-D, an initialization voltage line SL-Vint, and a voltage line ( SL-VDD), a power supply line (E-VSS), and a pad part (PD).

The gate lines GL are respectively connected to corresponding pixels PX among the plurality of pixels PX, and the data lines DL are respectively connected to corresponding pixels PX among the plurality of pixels PX. do. Each of the light emitting lines EL may be arranged parallel to a corresponding one of the gate lines GL. The control signal line SL-D may provide control signals to the gate driving circuit GDC. The initialization voltage line SL-Vint may provide an initialization voltage to the plurality of pixels PX. The voltage line SL-VDD is connected to the plurality of pixels PX and may provide a first voltage to the plurality of pixels PX. The voltage line SL-VDD may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2 . The power supply line E-VSS may be disposed in the non-display area NDA while surrounding three side surfaces of the display area DA. A common voltage (eg, a second voltage) may be provided to the plurality of pixels PX of the power supply line E-VSS. The common voltage may be a voltage lower than the first voltage.

A gate driving circuit GDC to which gate lines GL and emission lines EL are connected may be disposed on one side of the non-display area NDA. Gate lines GL, data lines DL, emission lines EL, control signal line SL-D, initialization voltage line SL-Vint, voltage line SL-VDD, and power supply line Some of the (E-VSS) are placed on the same floor, and some are placed on different floors.

The pad part PD may be connected to ends of the data lines DL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD.

5B is a block diagram of a driving stage GDSi of a gate driving circuit GDC according to an embodiment of the present invention.

5B illustrates a driving stage GDSi connected to the i-th gate line GLi and the i-th emission line ELi among the driving stages of the plurality of gate driving circuits GDC.

The driving stage GDSi may include an emission control stage EC-Ci and a gate driving stage GC-Ci. The emission control stage EC-Ci of the driving stage GDSi includes a first clock signal line CL1, a second clock signal line CL2, a first voltage line VL1, a second voltage line VH1, Emission control signals CLK1, CLK2, VGL, VGH, and EMFLM may be provided through one start signal line EF1. The gate driving stage GC-Ci includes a third clock signal line CL3, a fourth clock signal line CL4, a third voltage line VL2, a fourth voltage line VH2, and a second start signal line EF2. ), the gate control signals CLK3, CLK4, VGH1, VGL1, and FLM may be provided.

In this embodiment, it is illustrated that the emission control stage EC-Ci and the gate driving stage GC-Ci are included in one driving stage GDSi, but is not limited thereto. For example, the emission control stage EC-Ci and the gate driving stage GC-Ci may be included in different driving stages.

The emission control stage EC-Ci includes a first clock terminal CK1, a second clock terminal CK2, a first voltage input terminal VPL1, a second voltage input terminal VPH1, an input terminal IN, and a carry A terminal CR and an output terminal OUT1 may be included.

The first clock terminal CK1 receives the first clock signal CLK1, and the second clock terminal CK2 receives the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may have different phases. The second clock signal CLK2 may be a signal obtained by inverting a phase of the first clock signal CLK1 or a delayed signal.

The first voltage input terminal VPL1 receives the first voltage VGL, and the second voltage input terminal VPH1 receives the second voltage VGH. The voltage level of the first voltage VGL may be lower than that of the second voltage VGH.

The input terminal IN may receive a carry signal from a previous light emission control stage (eg EC-Ci-1 (not shown)), and the carry terminal CR may receive a carry signal of a next light emission control stage (eg EC-Ci-1 (not shown)). A carry signal may be output as -Ci+1 (not shown). The output terminal OUT1 may provide the emission control signal generated from the emission control stage EC-Ci to the emission line ELi.

The start signal EMFLM may be input to an input terminal IN of a first light emission control stage (eg, EC-C1 (not shown)) among light emission control stages.

The gate driving stage GC-Ci includes a third clock terminal CK3, a fourth clock terminal CK4, a third voltage input terminal VPL2, a fourth voltage input terminal VPH2, an input terminal IN, and a carry A terminal CR and an output terminal OUT2 may be included.

The third clock terminal CK3 receives the third clock signal CLK3, and the fourth clock terminal CK4 receives the fourth clock signal CLK4. The third clock signal CLK3 and the fourth clock signal CLK4 may have different phases. The fourth clock signal CLK4 may be a signal obtained by inverting a phase of the third clock signal CLK3 or a delayed signal.

The third voltage input terminal VPL2 receives the third voltage VL, and the fourth voltage input terminal VPH2 receives the fourth voltage VGH1. The voltage level of the third voltage VGL1 may be lower than that of the fourth voltage VGH1.

The input terminal (IN) may receive a carry signal of a previous gate driving stage (eg, GC-Ci-1 (not shown)), and the carry terminal (CR) may receive a carry signal of a next gate driving stage (eg, GC-Ci-1 (not shown)). A carry signal may be output as -Ci+1 (not shown). The output terminal OUT2 may provide a gate signal generated from the gate driving stage GC-Ci to the gate line GLi.

The start signal FLM may be input to an input terminal IN of a first gate driving stage (eg, GC-C1 (not shown)) among gate driving stages.

In one embodiment of the present invention, the first clock terminal CK1, the second clock terminal CK2, the first voltage input terminal VPL1, the second voltage input terminal VPH1 of the emission control stage EC-Ci, Any one of the input terminal IN, the carry terminal CR, and the output terminal OUT1 may be omitted or other terminals may be further included. For example, the carry terminal CR may be omitted.

In an embodiment of the present invention, the third clock terminal CK3, the fourth clock terminal CK4, the third voltage input terminal VPL2, the fourth voltage input terminal VPH2 of the gate driving stage GC-Ci, Any one of the input terminal IN, the carry terminal CR, and the output terminal OUT2 may be omitted or other terminals may be further included. For example, the carry terminal CR may be omitted.

In addition, in FIG. 5B, the input terminal (IN) of the emission control stage (EC-Ci) and the input terminal (IN) of the gate driving stage (GC-Ci) are connected to the carry terminals of the previous stage. , but is not limited thereto. Connections between driving stages may be variously changed.

5C is a cross-sectional view of a display module DM according to an embodiment of the present invention. 5C illustrates a cross section defined by the second and third directions DR2 and DR3.

As shown in FIG. 5C , the organic light emitting display panel DP includes a base layer SUB, a circuit layer DP-CL disposed on the base layer SUB, a light emitting element layer DP-OLED, and a thin film. It includes an encapsulation layer (TFE).

The base layer SUB may include at least one plastic film. The base layer SUB is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite material substrate. The plastic substrate may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin. can include

The circuit layer DP-CL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit layer DP-CL may configure signal lines or control circuits of pixels. The circuit layer DP-CL may include a pixel circuit layer DP-PCL disposed in the display area DA and a driving circuit layer DP-DCL disposed in the non-display area NDA. The pixel circuit layer DP-PCL includes the gate lines GL, data lines DL, emission lines EL, initialization voltage line SL-Vint, and voltage line SL- as described above with reference to FIG. 5A. VDD), and circuits included in the pixels PX.

The driving circuit layer DP-DCL may include the gate driving circuit GDC and the control signal line SL-D described above with reference to FIG. 5A. The control signal lines SL-D include the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4 shown in FIG. 5B. , the first voltage line (VL1), the second voltage line (VH1), the third voltage line (VL2), the fourth voltage line (VH2), the first start signal line (EF1), the second start signal line (EF2) can include In the above configuration, the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4 may collectively be referred to as clock signal lines. .

The light emitting element layer DP-OLED includes organic light emitting diodes.

The thin film encapsulation layer (TFE) encapsulates the light emitting element layer (DP-OLED). The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer interposed therebetween. The inorganic layers protect the light emitting device layer DP-OLED from moisture and oxygen, and the organic thin film protects the light emitting device layer DP-OLED from foreign substances such as dust particles.

The touch sensing unit TS is disposed on the thin film encapsulation layer TFE. The touch sensing unit TS may be directly disposed on the thin film encapsulation layer TFE. However, it is not limited thereto, and a buffer layer may be disposed on the thin film encapsulation layer TFE, and the touch sensing unit TS may be directly disposed on the buffer layer. The buffer layer may be an inorganic layer or an organic layer. The inorganic layer may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer may include a polymer, for example, an acryl-based organic layer. However, this is illustrative and not limited thereto. Although the buffer layer has been described as a separate component, the buffer layer may be included in the thin film encapsulation layer (TFE).

The touch sensing unit TS includes a touch sensing unit TSP and touch signal lines TSL. The touch sensing unit TSP and the touch signal lines TSL may have a single-layer or multi-layer structure. The touch sensing unit (TSP) and the touch signal lines (TSL) are indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphite. May contain pins. The touch sensing unit TSP and the touch signal lines TSL may include a metal layer, for example, molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The touch sensing unit TSP and the touch signal lines TSL may have the same layer structure or different layer structures. Details of the touch sensing unit TS will be described later.

6A is an equivalent circuit diagram of a pixel PX according to an embodiment of the present invention.

FIG. 6A illustrates an i-th pixel PXi connected to a k-th data line DLk among a plurality of data lines DL (see FIG. 5A ).

The i-th pixel PXi includes an organic light emitting diode (OLED) and a pixel driving circuit that controls the organic light emitting diode. The driving circuit may include seven thin film transistors T1 to T7 and one storage capacitor Cst.

The driving transistor controls driving current supplied to the organic light emitting diode (OLED). An output electrode of the second transistor T2 is electrically connected to the organic light emitting diode OLED. The output electrode of the second transistor T2 may directly contact the first electrode of the organic light emitting diode OLED, or may be connected via another transistor (the sixth transistor T6 in this embodiment).

A control electrode of the control transistor may receive a control signal. Control signals applied to the i-th pixel PXi include the i-1-th gate signal Si-1, the i-th gate signal Si, the i+1-th gate signal Si+1, the data signal Dk, and an i-th emission control signal Ei. In an embodiment of the present invention, the control transistor may include a first transistor T1 and third to seventh transistors T3 to T7.

The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the ith gate line GLi, and an output electrode connected to the output electrode of the second transistor T2. do. The first transistor T1 is turned on by the gate signal Si (hereinafter referred to as the i-th gate signal) applied to the i-th gate line GLi, and the data signal Dk applied to the k-th data line DLk. is provided to the storage capacitor Cst.

6B is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment. 6C is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment of the present invention. Specifically, FIG. 6B shows a cross-section of a portion corresponding to the first transistor T1 of the equivalent circuit shown in FIG. 6A. FIG. 6C is a cross-sectional view of portions corresponding to the second transistor T2, the sixth transistor T6 and the organic light emitting diode (OLED) of the equivalent circuit shown in FIG. 6A.

Referring to FIGS. 6B and 6C , a buffer layer BFL may be disposed on the base layer SUB. The buffer layer BFL improves bonding strength between the base layer SUB and conductive patterns or semiconductor patterns. The buffer layer BFL may include an inorganic layer. Although not separately shown, a barrier layer that prevents foreign substances from entering may be further disposed on the upper surface of the base layer SUB. The buffer layer (BFL) and the barrier layer may be selectively disposed or omitted.

On the buffer layer BFL, a semiconductor pattern (OSP1: hereinafter referred to as first semiconductor pattern) of the first transistor T1, a semiconductor pattern (OSP2: hereinafter referred to as second semiconductor pattern) of the second transistor T2, and a sixth transistor T6 are formed on the buffer layer BFL. A semiconductor pattern (OSP6: hereinafter referred to as a sixth semiconductor pattern) is disposed. The first semiconductor pattern OSP1 , the second semiconductor pattern OSP2 , and the sixth semiconductor pattern OSP6 may be selected from amorphous silicon, polysilicon, or a metal oxide semiconductor.

A first insulating layer 10 may be disposed on the first semiconductor pattern OSP1 , the second semiconductor pattern OSP2 , and the sixth semiconductor pattern OSP6 . 6B and 6C exemplarily show that the first insulating layer 10 is provided in a layer form covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. However, the first insulating layer 10 may be provided in a pattern disposed corresponding to the first semiconductor pattern OSP1 , the second semiconductor pattern OSP2 , and the sixth semiconductor pattern OSP6 .

The first insulating layer 10 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer, a silicon oxy nitride layer, and a silicon oxide layer.

On the first insulating layer 10, the control electrode GE1 of the first transistor T1 (hereinafter referred to as the first control electrode), the control electrode GE2 of the second transistor T2 (hereinafter referred to as the second control electrode), and the sixth A control electrode GE6 (hereinafter referred to as a sixth control electrode) of the transistor T6 is disposed. The first control electrode GE1 , the second control electrode GE2 , and the sixth control electrode GE6 may be manufactured according to the same photolithography process as the gate lines GL (see FIG. 5A ).

A second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first control electrode GE1 , the second control electrode GE2 , and the sixth control electrode GE6 . The second insulating layer 20 may provide a flat upper surface. The second insulating layer 20 may include an organic material and/or an inorganic material.

On the second insulating layer 20, the input electrode (SE1: hereinafter referred to as the first input electrode) and the output electrode (DE1: first output electrode) of the first transistor T1, the input electrode of the second transistor T2 ( SE2: hereinafter, second input electrode) and output electrode (DE2: second output electrode), input electrode (SE6: hereinafter, hereinafter, sixth input electrode) and output electrode (DE6: sixth output electrode) of the sixth transistor T6 ) is placed.

The first input electrode SE1 and the first output electrode DE1 have a first through hole CH1 and a second through hole CH2 penetrating the first insulating layer 10 and the second insulating layer 20 . are respectively connected to the first semiconductor pattern OSP1 through The second input electrode SE2 and the second output electrode DE2 include a third through hole CH3 and a fourth through hole CH4 penetrating the first insulating layer 10 and the second insulating layer 20 . are respectively connected to the second semiconductor pattern OSP2 through The sixth input electrode SE6 and the sixth output electrode DE6 include a fifth through hole CH5 and a sixth through hole CH6 penetrating the first insulating layer 10 and the second insulating layer 20 . are respectively connected to the sixth semiconductor pattern OSP6 through Meanwhile, in another embodiment of the present invention, the first transistor T1 , the second transistor T2 , and the sixth transistor T6 may be modified into a bottom gate structure.

On the second insulating layer 20, the first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, A third insulating layer 30 covering the six output electrodes DE6 is disposed. The third insulating layer 30 includes an organic layer and/or an inorganic layer. In particular, the third insulating layer 30 may include an organic material to provide a flat surface.

Any one of the first insulating layer 10 , the second insulating layer 20 , and the third insulating layer 30 may be omitted depending on the circuit structure of the pixel. Each of the second insulating layer 20 and the third insulating layer 30 may be defined as an interlayer. The interlayer insulating layer is disposed between the conductive pattern disposed below and the conductive pattern disposed above the interlayer insulating layer to insulate the conductive patterns.

A pixel defining layer (PDL) and an organic light emitting diode (OLED) are disposed on the third insulating layer 30 . A first electrode AE is disposed on the third insulating layer 30 . The first electrode AE is connected to the sixth output electrode DE6 through the seventh through hole CH7 penetrating the third insulating layer 30 . An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

The pixel PX may be disposed in a pixel area on a plane. The pixel area may include an emission area PXA and a non-emission area NPXA adjacent to the emission area PXA. The non-emission area NPXA may surround the emission area PXA. In this embodiment, the light emitting area PXA is defined to correspond to a partial area of the first electrode AE exposed through the opening OP.

The hole control layer HCL may be disposed in common in the emission area PXA and the non-emission area NPXA. Although not separately shown, a common layer such as a hole control layer (HCL) may be commonly formed in a plurality of pixels (PX, see FIG. 5A).

An organic light emitting layer (EML) is disposed on the hole control layer (HCL). The organic light emitting layer EML may be disposed in an area corresponding to the opening OP. That is, the organic light emitting layer EML may be separately formed in each of the plurality of pixels PX. Although the patterned organic light emitting layer EML is illustrated as an example in this embodiment, the organic light emitting layer EML may be commonly disposed in a plurality of pixels PX. In this case, the organic light emitting layer EML may generate white light. Also, the organic light emitting layer EML may have a multilayer structure.

An electronic control layer (ECL) is disposed on the organic light emitting layer (EML). Although not separately shown, the electronic control layer ECL may be formed in common with a plurality of pixels PX (see FIG. 5A ).

A second electrode CE is disposed on the electronic control layer ECL. The second electrode CE is commonly disposed in the plurality of pixels PX.

A thin film encapsulation layer TFE is disposed on the second electrode CE. The thin film encapsulation layer TFE is commonly disposed in the plurality of pixels PX. The thin film encapsulation layer TFE includes at least one inorganic layer and at least one organic layer. The thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers that are alternately stacked.

In this embodiment, the thin film encapsulation layer TFE directly covers the second electrode CE. In one embodiment of the present invention, a capping layer covering the second electrode CE may be further disposed between the thin film encapsulation layer TFE and the second electrode CE. In this case, the thin film encapsulation layer (TFE) may directly cover the capping layer.

7A to 7C are cross-sectional views of thin film encapsulation layers TFE1 , TFE2 , and TFE3 according to an embodiment of the present invention. Hereinafter, thin film encapsulation layers TFE1 , TFE2 , and TFE3 according to exemplary embodiments of the present invention will be described with reference to FIGS. 7A to 7C .

As shown in FIG. 7A , the thin film encapsulation layer TFE1 may include n inorganic thin films IOL1 to IOLn including the first inorganic thin film IOL1 contacting the second electrode CE (see FIG. 6C ). can The first inorganic thin film IOL1 may be defined as a lower inorganic thin film, and inorganic thin films other than the first inorganic thin film IOL1 among n inorganic thin films IOL1 to IOLn may be defined as upper inorganic thin films.

The thin film encapsulation layer TFE1 includes n-1 organic thin films OL1 to OLn, and the n-1 organic thin films OL1 to OLn are alternately disposed with n inorganic thin films IOL1 to IOLn. It can be. The n−1 organic thin films OL1 to OLn may have an average thickness greater than that of the n inorganic thin films IOL1 to IOLn.

Each of the n inorganic thin films IOL1 to IOLn may have a single layer including one material or multiple layers each including a different material. Each of n−1 organic thin films OL1 to OLn may be formed by depositing or printing organic monomers. For example, each of the n−1 organic thin films OL1 to OLn may be formed using an inkjet printing method or may be formed by coating a composition including an acrylic monomer. In an embodiment of the present invention, the thin film encapsulation layer TFE1 may further include an nth organic thin film.

As shown in FIGS. 7B and 7C , the inorganic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different inorganic materials and may have the same or different thicknesses. The organic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different organic materials and may have the same or different thicknesses.

As shown in FIG. 7B, the thin film encapsulation layer TFE2 includes a first inorganic thin film IOL1, a first organic thin film OL1, a second inorganic thin film IOL2, and a second organic thin film OL2 sequentially stacked. , and a third inorganic thin film IOL3.

The first inorganic thin film IOL1 may have a two-layer structure. The first sub-layer S1 and the second sub-layer S2 may include different inorganic materials.

As shown in FIG. 7C , the thin film encapsulation layer TFE3 may include a first inorganic thin film IOL10, a first organic thin film OL1, and a second inorganic thin film IOL20 sequentially stacked. The first inorganic thin film IOL10 may have a two-layer structure. The first sub-layer S10 and the second sub-layer S20 may include different inorganic materials. The second inorganic thin film IOL20 may have a two-layer structure. The second inorganic thin film IOL20 may include a first sub-layer S100 and a second sub-layer S200 deposited in different deposition environments. The first sub-layer S100 may be deposited under a low power condition and the second sub-layer S200 may be deposited under a high power condition. The first sub-layer S100 and the second sub-layer S200 may include the same inorganic material.

8A is a cross-sectional view of a touch sensing unit TS according to an embodiment of the present invention.

As shown in FIG. 8A , the touch sensing unit TS includes a first conductive layer TS-CL1, a first insulating layer TS-IL1 (hereinafter referred to as a first touch insulating layer), and a second conductive layer TS-CL2. ), and a second insulating layer (TS-IL2, hereinafter referred to as a second touch insulating layer). The first conductive layer TS-CL1 is directly disposed on the thin film encapsulation layer TFE. Without being limited thereto, another buffer layer (eg, an inorganic layer or an organic layer) may be further disposed between the first conductive layer TS-CL1 and the thin film encapsulation layer TFE. In another embodiment of the present invention, a plastic film, a glass substrate, or a plastic substrate may be disposed between the first conductive layer TS-CL1 and the thin film encapsulation layer TFE.

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The conductive layer of the multilayer structure may include at least two or more layers of transparent conductive layers and metal layers. The multi-layered conductive layer may include metal layers containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and alloys thereof.

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 includes a plurality of patterns. Hereinafter, it will be described that the first conductive layer TS-CL1 includes first conductive patterns and the second conductive layer TS-CL2 includes second conductive patterns. Each of the first conductive patterns and the second conductive patterns may include touch electrodes and touch signal lines.

Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may have a single-layer or multi-layer structure. Each of the first touch insulating layer TS-IL1 and the second touch insulating layer TS-IL2 may include at least one of an inorganic layer and an organic layer.

The first touch insulating layer TS-IL1 is sufficient to insulate the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and the shape is not limited. The shape of the first touch insulating layer TS-IL1 may be changed according to the shapes of the first conductive patterns and the second conductive patterns. The first touch insulating layer TS-IL1 may entirely cover the thin film encapsulation layer TFE or may include a plurality of insulating patterns. It is sufficient if the plurality of insulating patterns overlap the first connection parts CP1 or the second connection parts CP2 to be described later.

In this embodiment, the two-layered touch sensing unit is shown as an example, but is not limited thereto. The single-layer touch sensing unit includes a conductive layer and an insulating layer covering the conductive layer. The conductive layer includes touch sensors and touch signal lines connected to the touch sensors. The single-layered touch sensing unit may acquire coordinate information in a self-cap method.

8B to 8E are plan views of a touch sensing unit (TS) according to an embodiment of the present invention.

As shown in FIG. 8B , the touch sensing unit TS may include a touch sensing unit (TSP, see FIG. 5C), touch signal lines (TSL, see FIG. 5C), and a pad part PDa.

The touch sensing unit TSP (see FIG. 5C ) may include first touch electrodes TE1-1 to TE1-m and second touch electrodes TE2-1 to TE2-n. The touch signal lines (TSL, see FIG. 5C) include first touch signal lines SL1-1 to SL1-m connected to first touch electrodes TE1-1 to TE1-m, and second touch electrodes. Second touch signal lines SL2-1 to SL2-n connected to (TE2-1 to TE2-n) may be included. The pad part PDa may be electrically connected to the first touch signal lines SL1-1 to SL1-m and the second touch signal lines SL2-1 to SL2-n.

between the first touch electrodes TE1-1 to TE1-m and the first touch signal lines SL1-1 to SL1-m and connected to the second touch electrodes TE2-1 to TE2-n; Connection electrodes TSD may be disposed between the two touch signal lines SL2-1 to SL2-n. The connection electrodes TSD may be connected to ends of the first touch electrodes TE1-1 to TE1-m and the second touch electrodes TE2-1 to TE2-n, respectively, to transmit signals. In another embodiment of the present invention, the connection electrodes TSD may be omitted.

Each of the first touch electrodes TE1-1 to TE1-m may have a mesh shape in which a plurality of touch openings are defined. Each of the first touch electrodes TE1-1 to TE1-m includes a plurality of first touch sensor parts SP1 and a plurality of first connection parts CP1. The first touch sensor parts SP1 are aligned in the first direction DR1. Each of the first connection parts CP1 connects two adjacent first touch sensor parts SP1 among the first touch sensor parts SP1. Although not specifically illustrated, the first touch signal lines SL1-1 to SL1-m may also have a mesh shape.

The second touch electrodes TE2-1 to TE2-n insulate and cross the first touch electrodes TE1-1 to TE1-m. Each of the second touch electrodes TE2 - 1 to TE2 - n may have a mesh shape in which a plurality of touch openings are defined. Each of the second touch electrodes TE2-1 to TE2-n includes a plurality of second touch sensor parts SP2 and a plurality of second connection parts CP2. The second touch sensor parts SP2 are aligned in the second direction DR2. Each of the second connection parts CP2 connects two adjacent second touch sensor parts SP2 among the second touch sensor parts SP2. The second touch signal lines SL2-1 to SL2-n may also have a mesh shape.

The first touch electrodes TE1-1 to TE1-m and the second touch electrodes TE2-1 to TE2-n are electrostatically coupled. As the touch sensing signals are applied to the first touch electrodes TE1-1 to TE1-m, capacitors are formed between the first touch sensor parts SP1 and the second touch sensor parts SP2.

A plurality of first touch sensor parts SP1, a plurality of first connection parts CP1, and first touch signal lines SL1-1 to SL1-m, a plurality of second touch sensor parts SP2, a plurality of Some of the two second connection parts CP2 and the second touch signal lines SL2-1 to SL2-n are formed by patterning the first conductive layer TS-CL1 shown in FIG. may be formed by patterning the second conductive layer TS-CL2 shown in FIG. 8A.

In order to electrically connect conductive patterns disposed on other layers, a contact hole may be formed penetrating the first touch insulating layer TS-IL1 shown in FIG. 8A. Hereinafter, the touch sensing unit TS according to an exemplary embodiment will be described with reference to FIGS. 8C to 8E.

As shown in FIG. 8C, first conductive patterns are disposed on the thin film encapsulation layer (TFE, see FIG. 8A). The first conductive patterns may include bridge patterns CP2. Bridge patterns CP2 are directly disposed on the thin film encapsulation layer TFE. The thin film encapsulation layer TFE covering the display area DA is illustrated as an example. The bridge patterns CP2 correspond to the second connection parts CP2 shown in FIG. 8B.

As shown in FIG. 8D , a first touch insulating layer TS-IL1 covering the bridge patterns CP2 is disposed on the thin film encapsulation layer TFE. Contact holes CH partially exposing the bridge patterns CP2 are defined in the first touch insulating layer TS-IL1. Contact holes CH may be formed by a photolithography process.

As shown in FIG. 8E , second conductive patterns are disposed on the first touch insulating layer TS-IL1. The second conductive patterns include a plurality of first touch sensor parts SP1 (see FIG. 8B), a plurality of first connection parts CP1, first touch signal lines SL1-1 to SL1-m, and a plurality of first touch signal lines SL1-1 to SL1-m. It may include two touch sensor units SP2 (see FIG. 8B) and second touch signal lines SL2-1 to SL2-n. Although not separately illustrated, a second touch insulating layer TS-IL2 covering the second conductive patterns is disposed on the first touch insulating layer TS-IL1.

In one embodiment of the present invention, the first conductive patterns may include first touch electrodes TE1-1 to TE1-m and first touch signal lines SL1-1 to SL1-m. The first conductive patterns may include second touch electrodes TE2-1 to TE2-n and second touch signal lines SL2-1 to SL2-n. In this case, contact holes CH are not defined in the first touch insulating layer TS-IL1.

Also, in one embodiment of the present invention, the first conductive patterns and the second conductive patterns may be interchanged. That is, the second conductive patterns may include bridge patterns CP2.

FIG. 8F is a partially enlarged view of the BB region of FIG. 8E.

As shown in FIG. 8F , the first touch sensor unit SP1 overlaps the non-emission area NPXA. The first touch sensor unit SP1 includes a plurality of first extension parts SP1-A extending in a fifth direction DR5 intersecting the first and second directions DR1 and DR2, and a fifth direction ( DR5) and a plurality of second extension parts SP1-B extending in the sixth direction DR6 crossing. The plurality of first extension parts SP1 -A and the plurality of second extension parts SP1 -B may be defined as mesh lines. The line width of the mesh line may be several microns.

The plurality of first extension parts SP1 -A and the plurality of second extension parts SP1 -B are connected to each other to form a plurality of touch openings TS-OP. In other words, the first touch sensor unit SP1 has a mesh shape having a plurality of touch openings TS-OP. Although it is illustrated that the touch openings TS-OP correspond to the light emitting areas PXA one-to-one, it is not limited thereto. One touch opening TS-OP may correspond to two or more light emitting areas PXA.

The light emitting areas PXA may have various sizes. For example, among the light emitting areas PXA, the light emitting areas PXA providing blue light and the light emitting areas PXA providing red light may have different sizes. Accordingly, the sizes of the touch openings TS-OP may also vary. In FIG. 10 , various sizes of the light emitting regions PXA are illustrated as an example, but are not limited thereto. The light emitting regions PXA may have the same size, and the touch openings TS-OP may also have the same size.

9A is a partially enlarged view of an area AA of FIG. 5C. FIG. 9B is a cross-sectional view schematically illustrating the WW region of FIG. 9A.

Referring to FIGS. 9A and 9B , touch signal lines TSL are illustrated. The touch signal lines TSL may be the second touch signal lines SL1-1 to SL1-m shown in FIG. 8B.

The conductive part EP may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL1 , CL2 , CL3 , CL4 (hereinafter referred to as CL). The conductive part EP may be disposed on the same layer as the second electrode CE. For example, the conductive part EP and the second electrode CE may be disposed on the pixel defining layer PDL. The meaning of being disposed on the same layer means the same layer (eg, the pixel defining layer (PDL)), and does not mean only a flat plane.

The second electrode CE extends toward the conductive portion EP, and the second electrode CE and the conductive portion EP may be connected to each other. That is, the second electrode CE and the conductive portion EP may be formed through the same process.

The conductive part EP may be electrically connected to the power supply line E-VSS. The conductive part EP may receive the second voltage ELVSS (see FIG. 6A ) from the power supply line E-VSS.

The conductive part EP may cover an overlapping area OA where the touch signal lines TSL and the clock signal lines CL overlap on a plane. For example, the conductive portion EP may completely cover the overlapping area OA. The conductive part EP may prevent noise from being generated in the touch signal lines TSL due to the clock signal applied to the clock signal lines CL, and as a result, a change in touch sensitivity due to the noise may be prevented.

A first dam part DM1 and a second dam part DM2 may be disposed in the non-display area NDA. The first dam part DM1 and the second dam part DM2 may be disposed while enclosing the display area DA on a plane. When the organic monomer is printed to form the organic thin film OL1 of the thin film encapsulation layer TFE, the first dam portion DM1 and the second dam portion DM2 may prevent the organic monomer from overflowing.

The first dam part DM1 may be disposed on the power supply line E-VSS. The first dam portion DM1 may be formed as a single layer, and the first dam portion DM1 may be formed simultaneously with the pixel defining layer PDL.

The second dam part DM2 may be disposed outside the first dam part DM1. For example, the distance between the first dam part DM1 and the display area DA may be greater than the distance between the second dam part DM2 and the display area DA.

The second dam part DM2 may cover part of the power supply line E-VSS. The second dam part DM2 may be formed of a plurality of layers, and the second dam part DM2 may include a first layer DM2 - 1 and a second layer DM2 - 2 . The first layer DM2 - 1 may be formed simultaneously with the third insulating layer 30 , and the second layer DM2 - 2 may be formed simultaneously with the pixel defining layer PDL.

In FIG. 9A , the pixel-defining layer PDL is extended to overlap all clock signal lines CL on a plane, but is not limited thereto. For example, in another embodiment of the present invention, the pixel defining layer PDL may extend only to an area overlapping the gate driving circuit GDC or may extend only to an area overlapping some of the clock signal lines CL. have. For example, the pixel definition layer PDL includes a third clock signal line CL3 , a fourth clock signal line CL4 , a third voltage line VL2 , a fourth voltage line VH2 , and a second start signal. It may be extended only to an area overlapping the line EF2.

9C is a partially enlarged view of the area AA of FIG. 5C.

Referring to FIG. 9C , the conductive part EP- 1 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL (see FIG. 9B ). The conductive part EP-1 may be disposed on the same layer as the second electrode CE. For example, the conductive part EP- 1 and the second electrode CE may be disposed on the pixel defining layer PDL.

The conductive part EP-1 may be spaced apart from the second electrode CE. That is, the conductive part EP-1 and the second electrode CE may not be physically connected to each other. The conductive part EP-1 may be electrically connected to the power supply line E-VSS. The conductive part EP-1 may receive the second voltage ELVSS (see FIG. 6A) from the power supply line E-VSS. However, this is exemplary, and a constant voltage may be applied to the conductive part EP-1. For example, a first voltage ELVDD (see FIG. 6A ) may be applied to the conductive part EP- 1 , a ground voltage may be applied, or a separate constant voltage other than those listed above may be applied.

The second electrode CE may be electrically connected to the power supply line E-VSS through a pattern not shown. Accordingly, the second electrode CE may receive the second voltage ELVSS (see FIG. 6A ) from the power supply line E-VSS.

The conductive part EP- 1 may block the touch sensitivity of the touch sensing unit from being changed by signals applied to the clock signal lines CL.

9D is a partially enlarged view of the area AA of FIG. 5C.

Referring to FIG. 9D , the conductive part EP- 2 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL (see FIG. 9B ). The conductive part EP-2 may be disposed on the same layer as the second electrode CE.

A plurality of through holes HL may be defined in the conductive portion EP- 2 . The plurality of through holes HL may serve to discharge gases that may be generated from the layers including the organic material layer. The plurality of through holes HL may not overlap the overlapping area OA (refer to FIG. 9B ) where the touch signal lines TSL and the clock signal lines CL overlap. In FIG. 9D , it is illustratively illustrated that the through holes HL are not defined in an area overlapping the clock signal lines CL (see FIG. 9B ) on a plane. In another embodiment of the present invention, the through holes HL may not be defined in an area overlapping the touch signal lines TSL on a plane.

According to the embodiment of the present invention, since the through-holes HL are not defined in the overlapping area OA (see FIG. 9B), even if a plurality of through-holes HL are provided in the conductive portion EP-2, the clock Changes in the touch sensitivity of the touch sensing unit due to signals applied to the signal lines CL may be easily blocked.

10A is a partially enlarged view of an area AA of FIG. 5C. FIG. 10B is a cross-sectional view schematically illustrating an area XX of FIG. 10A.

The conductive part EP- 3 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive part EP-3 may be disposed on the same layer as the first electrode AE. For example, the conductive portion EP- 3 and the first electrode AE may be disposed on the third insulating layer 30 . The first electrode AE and the conductive portion EP-3 may be formed through the same process.

The conductive part EP-3 may be electrically connected to the power supply line E-VSS. The conductive part EP-3 may receive the second voltage ELVSS (see FIG. 6A) from the power supply line E-VSS. However, this is exemplary, and a constant voltage may be applied to the conductive part EP-3. For example, a first voltage ELVDD (see FIG. 6A ) may be applied to the conductive part EP- 1 , a ground voltage may be applied, or a separate constant voltage other than those listed above may be applied.

A plurality of through holes HL-1 may be defined in the conductive part EP-3. The through-holes HL-1 may serve to discharge gases that may be generated from the layers including the organic material. The through holes HL- 1 may not overlap the overlapping area OA where the touch signal lines TSL and clock signal lines CL overlap. More specifically, in FIG. 10A , the through holes HL-1 may not be defined in an area overlapping the clock signal lines CL on a plane. Accordingly, the conductive part EP- 3 may completely cover the overlapping area OA where the touch signal lines TSL and the clock signal lines CL overlap on a plane. The conductive part EP- 3 may block noise from being generated in the touch signal lines TSL by the clock signal applied to the clock signal lines CL. That is, a change in touch sensitivity can be reduced by the conductive part EP-3, and a touch sensing unit having a uniform touch sensitivity can be provided.

FIG. 10C is a partially enlarged view of area AA of FIG. 5C. FIG. 10D is a cross-sectional view schematically illustrating area YY of FIG. 10C.

The conductive part EP- 4 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. A plurality of through holes HL-2 may be defined in the conductive part EP-4.

The through holes HL- 2 may not overlap the overlapping area OA where the touch signal lines TSL and clock signal lines CL overlap. More specifically, in FIG. 10C , the through holes HL- 2 may not be defined in an area overlapping the touch signal lines TSL on a plane.

The conductive part EP- 4 may shield signals applied to the clock signal lines CL under the touch signal lines TSL. That is, since the through-holes HL-2 are not defined in an area overlapping the touch signal lines TSL, the touch signal lines TSL are affected by signals of each of the clock signal lines CL. The generated noise may not occur.

11A is a partially enlarged view of an area AA of FIG. 5C. FIG. 11B is a cross-sectional view schematically illustrating the ZZ region of FIG. 11A.

The conductive part EP-5 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive part EP-5 may include a first conductive layer EP-L1 and a second conductive layer EP-L2. The first conductive layer EP-L1 may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 may be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1 and the first electrode AE may be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE may be a pixel. It may be disposed on the definition layer PDL. The first conductive layer EP-L1 and the first electrode AE may be formed through the same process, and the second conductive layer EP-L2 and the second electrode CE may be formed through the same process. have.

Each of the first conductive layer EP-L1 and the second conductive layer EP-L2 may be electrically connected to the power supply line E-VSS. Each of the first conductive layer EP-L1 and the second conductive layer EP-L2 may receive the second voltage ELVSS (refer to FIG. 6A ) from the power supply line E-VSS. However, this is exemplary, and a constant voltage may be applied to the second conductive layer EP-L2. For example, a first voltage (ELVDD, see FIG. 6A) may be applied to the second conductive layer EP-L2, a ground voltage may be applied, or a separate constant voltage other than those listed above may be applied. .

A plurality of first through holes HL-3 may be defined in the first conductive layer EP-L1. The plurality of first through-holes HL- 3 may serve to discharge gases that may be generated from layers including organic materials. In FIG. 11A , the plurality of first through-holes HL-3 are spaced apart at regular intervals and arranged as an example, but it is not limited thereto.

The second conductive layer EP-L2 may cover all of the plurality of first through holes HL-3 on a plane. According to the present embodiment, between the touch signal lines TSL and the plurality of clock signal lines CL may be double-shielded by the first conductive layer EP-L1 and the second conductive layer EP-L2. have. In addition, a region not covered by the plurality of first through-holes HL-3 on a plane is covered by the second conductive layer EP-L2 by covering the plurality of first through-holes HL-3. can Therefore, even when high and low level voltages are alternately applied to the plurality of clock signal lines CL, the plurality of clock signal lines are generated by the first conductive layer EP-L1 and the second conductive layer EP-L2. Noise may not be generated in the touch signal lines TSL because signals applied to the fields CL are shielded.

11C is a partially enlarged view of the area AA of FIG. 5C.

The conductive part EP-6 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive part EP-6 may include a first conductive layer EP-L1 and a second conductive layer EP-L2a. The conductive portion EP-6 of FIG. 11C has a difference in shape of the second conductive layer EP-L2a when compared to the conductive portion EP-5 described above with reference to FIG. 11A.

11A, the second electrode CE extends toward the second conductive layer EP-L2, and the second electrode CE and the second conductive layer EP-L2 may be physically connected to each other. However, in FIG. 11B , the second conductive layer EP-L2a may be spaced apart from the second electrode CE. That is, the conductive part EP-1 and the second electrode CE may not be physically connected to each other.

12A is a partially enlarged view of an area AA of FIG. 5C. FIG. 12B is an enlarged plan view of some components shown in FIG. 12A.

The conductive part EP-6 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive part EP-6 may include a first conductive layer EP-L1a and a second conductive layer EP-L2. The first conductive layer EP-L1a may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 may be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1a and the first electrode AE may be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE may be a pixel. It may be disposed on the definition layer PDL. The first conductive layer EP-L1a and the first electrode AE may be formed through the same process, and the second conductive layer EP-L2 and the second electrode CE may be formed through the same process. have.

A plurality of first through holes HL-4 may be defined in the first conductive layer EP-L1a. The plurality of first through-holes HL- 4 may serve to discharge gases that may be generated from layers including organic materials. The plurality of first through holes HL- 4 may not be defined in an area overlapping the clock signal lines CL on a plane.

12B illustrates the third clock signal line CL3, the fourth clock signal line CL4, the third voltage line VL2, the fourth voltage line VH2, and the second start signal line EF2. shown The plurality of first through holes HL-4 may not be defined in an area overlapping the third and fourth clock signal lines CL3 and CL4.

The third clock signal line CL3 and the fourth clock signal line CL4 may be applied with signals whose levels continuously change while an image of one frame is displayed. Accordingly, if upper portions of the third and fourth clock signal lines CL3 and CL4 are not shielded, noise may be generated in the touch signal lines TSL due to the signals. According to an embodiment of the present invention, since the plurality of first through-holes HL-4 are not defined above the third clock signal line CL3 and the fourth clock signal line CL4, the third clock signal line HL-4 is not defined. Upper portions of the line CL3 and the fourth clock signal line CL4 are completely shielded. Therefore, it is possible to prevent noise from being generated in the touch signal lines TSL by signals applied to the third clock signal line CL3 and the fourth clock signal line CL4 .

The first conductive layer EP-L1a may include a first area AR1, a second area AR2, and a third area AR3. The first area AR1, the second area AR2, and the third area AR3 are illustrated in FIG. 12B.

The first area AR1 overlaps the clock signal lines CL and may be an area in which the plurality of first through holes HL-4 are not defined. 12B illustrates a first area AR1 that does not overlap the third and fourth clock signal lines CL3 and CL4. The second area AR2 is an area in which the plurality of first through holes HL-4 are defined, and the area exposed by the plurality of first through holes HL-4 and HL-4a is the first area It may be a region with density. The third area AR3 is an area in which the plurality of first through holes HL-4 are defined, and the area exposed by the plurality of first through holes HL-4 has a second area density. can be The second areal density may be lower than the first areal density. The exposed region may be the third insulating layer 30 . For example, the number of the plurality of first through holes HL-4 defined in the second area AR2 per first area SA1 may be two, and the number of first through holes HL-4 defined in the third area AR3 may be two. The number of the plurality of first through holes HL-4 per first area SA1 may be one.

Since the plurality of first through holes HL-4 are not defined in the first region AR1 overlapping the third clock signal line CL3 and the fourth clock signal line CL4, in order to compensate for this, A plurality of first through holes HL-4a may be further defined in the second area AR2.

The shape of the hole HLa is indicated by a dotted line in the first area AR1. This is illustrated for convenience of description, but does not mean that the hole HLa is defined in the first area AR1. Assuming that the plurality of first through-holes HL-4 are arranged at regular intervals, there should be holes HLa in the first area AR1, but no holes are defined in the first area AR1. . Accordingly, a layer (eg, the third insulating layer 30) under the first conductive layer EP-L1a is formed by the first through-holes HL-4 in the first conductive layer EP-L1a. A design condition that more than a predetermined area should be exposed may not be satisfied, and as a result, gases that may be generated from layers containing organic materials may not be smoothly discharged. To prevent this, first through-holes HL-4a may be additionally defined in the second area AR2 to correspond to the number of holes HLa not defined in the first area AR1. Therefore, a layer (eg, the third insulating layer 30) under the first conductive layer EP-L1a is formed by the first through-holes HL-4 of the first conductive layer EP-L1a. A design condition that a predetermined area or more should be exposed may be satisfied. For convenience of understanding, arrows are shown between the imaginary hole HLa and the first through holes HL-4a to show the movement relationship of the holes. Arrows are not elements, but are simply shown for ease of understanding.

FIG. 12c is a plan view showing an enlarged portion of the components shown in FIG. 12a.

In FIG. 12C , the first area AR1 should have the hole HLa, but since the hole is not defined in the first area AR1, the first through holes disposed in the second area AR2 to compensate for this. (HL-4b) was expanded in size as an example.

The expansion of the size of the first through holes HL-4b means the same as the expansion of the exposed area of the third insulating layer 30 (see FIG. 12A) disposed under the first through holes HL-4b. have As a result, it is possible to satisfy the design condition that the first through holes HL-4 have a predetermined area or more on the conductive portion EP-6 (see FIG. 12A).

In FIG. 12C , it is exemplified that only the width of the first through holes HL-4b is increased in the vertical direction compared to the first through hole HL-4, but is not limited thereto. For example, the widths of the first through holes HL-4b in the horizontal direction may be larger than those of the first through holes HL-4, or the widths of the first through holes HL-4b may be increased in both the vertical and horizontal directions.

FIG. 13A is a partially enlarged view of area AA of FIG. 5C. FIG. 13B is an enlarged plan view of some components shown in FIG. 13A.

The conductive part EP-7 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive part EP-7 may include a first conductive layer EP-L1b and a second conductive layer EP-L2. The first conductive layer EP-L1b may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2 may be disposed on the same layer as the second electrode CE. For example, the first conductive layer EP-L1b and the first electrode AE may be disposed on the third insulating layer 30, and the second conductive layer EP-L2 and the second electrode CE may be a pixel. It may be disposed on the definition layer PDL. The first conductive layer EP-L1b and the first electrode AE may be formed through the same process, and the second conductive layer EP-L2 and the second electrode CE may be formed through the same process. have.

A plurality of first through holes HL-5 may be defined in the first conductive layer EP-L1b. The plurality of first through-holes HL-5 may serve to discharge gases that may be generated from layers including organic materials. The plurality of first through holes HL- 5 may not be defined in an area overlapping the touch signal lines TSL on a plane.

13B shows some touch signal lines TSL as an example. The plurality of first through holes HL- 5 may not be defined in an area overlapping the touch signal lines TSL.

That is, since the plurality of first through-holes HL-5 are not defined under the touch signal lines TSL, the influence of AC signals applied to the clock signal lines CL can be reduced. Therefore, the probability of generating noise in the touch signal lines TSL is reduced, and a change in touch sensitivity due to noise can be prevented.

The first conductive layer EP-L1b may include a first area AR1, a second area AR2, and a third area AR3. The first area AR1, the second area AR2, and the third area AR3 are illustrated in FIG. 13B.

The first area AR1 may overlap the touch signal lines TSL and may be an area in which the plurality of first through holes HL-5 are not defined. The second area AR2 is an area in which the plurality of first through holes HL-5 and HL-5a are defined, and is exposed by the plurality of first through holes HL-5 and HL-5a. It may be a region having this first areal density. The third area AR3 is an area in which the plurality of first through holes HL-5 are defined, and the area exposed by the plurality of first through holes HL-5 has a second area density. can be The second areal density may be lower than the first areal density. The exposed region may be the third insulating layer 30 . For example, the number of the plurality of first through-holes HL-5 defined in the second area AR2 per first area SA1 may be two, and the number defined in the third area AR3 The number of the plurality of first through holes HL-5 per first area SA1 may be one.

Since the plurality of first through holes HL-5 are not defined in the first area AR1 overlapping the touch signal lines TSL, the plurality of first through holes HL-5 are formed in the second area AR2 to compensate for this. Through holes HL-5a may be further defined. For example, the shape of the hole HLa is illustrated by a dotted line in the first area AR1. This is illustrated for convenience of description, but does not mean that the hole HLa is defined in the first area AR1. Assuming that the plurality of first through-holes HL-5 are arranged at uniform intervals, there should be holes HLa in the first area AR1, but no holes are defined in the first area AR1. . Accordingly, a layer (eg, the third insulating layer 30) under the first conductive layer EP-L1b is formed by the first through-holes HL-5 in the first conductive layer EP-L1b. A design condition that more than a predetermined area should be exposed may not be satisfied, and as a result, gases that may be generated from layers containing organic materials may not be smoothly discharged. To prevent this, first through-holes HL-5a may be additionally defined in the second area AR2 to correspond to the number of holes HLa not defined in the first area AR1. Therefore, a layer (eg, the third insulating layer 30) under the first conductive layer EP-L1b is formed by the first through-holes HL-5 of the first conductive layer EP-L1b. It is possible to satisfy a design condition that a predetermined area or more should be exposed.

Although not shown in FIG. 13B, the size of the first through-holes HL-5 disposed in the second area AR2 is increased to compensate for the fact that no hole is defined in the first area AR1 as shown in FIG. 12C. You can do it.

14A is a partially enlarged view of an area AA of FIG. 5C. FIG. 14B is an enlarged plan view of some components shown in FIG. 14A.

The conductive part EP- 8 may be disposed between the touch signal lines TSL and the plurality of clock signal lines CL. The conductive part EP-8 may include a first conductive layer EP-L1c and a second conductive layer EP-L2b. The first conductive layer EP-L1c may be disposed on the same layer as the first electrode AE, and the second conductive layer EP-L2b may be disposed on the same layer as the second electrode CE.

A plurality of first through holes HL-6 may be defined in the first conductive layer EP-L1c. The plurality of first through-holes HL-6 may serve to discharge gases that may be generated from layers including organic materials. A plurality of second through holes HL-7 may be defined in the second conductive layer EP-L2b. The plurality of second through-holes HL-7 may serve to discharge gases that may be generated from layers including organic materials.

On a plane, the first through holes HL-6 and the second through holes HL-7 may not overlap each other. Therefore, the area where the first through holes HL-6 are formed is covered by the second conductive layer EP-L2b, and the area where the second through holes HL-7 are formed is covered by the first conductive layer EP. -L1c). Therefore, an overlapping region between the touch signal lines TSL and the plurality of clock signal lines CL is shielded by at least one of the first conductive layer EP-L1c and the second conductive layer EP-L2b. It can be. That is, the conductive part EP-8 may reduce a change in touch sensitivity due to noise generated from signals of the clock signal lines CL.

In FIG. 14B , each of the plurality of first through holes HL-6 and the plurality of second through holes HL-7 is arranged in the second direction DR1 and alternately along the first direction DR1. Although the arrangement has been shown as an example, it is not limited thereto. The plurality of first through holes HL-6 and the plurality of second through holes HL-7 do not overlap on a plane and may have various arrangements. For example, the plurality of first through holes HL-6 and the plurality of second through holes HL-7 may be alternately disposed in the first direction DR1 and the second direction DR2. have.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art do not deviate from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that the present invention can be variously modified and changed within the scope not specified. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

DD: display device DM: display module
DP: organic light emitting display panel TS: touch sensing unit
SUB: base layer DP-CL: circuit layer
DP-OLED: light emitting element layer TFE: thin film encapsulation layer
DA: display area NDA: non-display area

Claims (15)

A display area and a non-display area adjacent to the display area are defined, a light emitting layer disposed in the display area, first signal lines disposed in the non-display area and providing signals for controlling the light emitting element layer, the ratio a display panel disposed in a display area and including a conductive portion overlapping the first signal lines, and an encapsulation layer sealing the light emitting element layer;
an insulating layer disposed directly on the encapsulation layer;
sensing electrodes disposed on the insulating layer; and
It is disposed on the insulating layer and includes second signal lines electrically connected to the sensing electrodes, respectively,
The conductive part is disposed between the first signal lines and the second signal lines,
A portion of the upper surface of the encapsulation layer disposed in the non-display area includes a curved portion,
The insulating layer is curved along the curved portion of the upper surface of the encapsulation layer. According to claim 1,
The light emitting element layer includes a first electrode, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer, and the conductive part is disposed on the same layer as the second electrode. . According to claim 2,
The second electrode extends toward the conductive part, and the second electrode and the conductive part are connected to each other. According to claim 1,
The first signal lines are clock signal lines to which a clock signal is applied. According to claim 1,
The display device of claim 1 , wherein the display panel further includes a gate driving circuit, and each of the first signal lines provides clock signals to the gate driving circuit. According to claim 1,
The encapsulation layer includes at least one inorganic layer and at least one organic layer. According to claim 1,
A plurality of through holes are defined in the conductive part, and the plurality of through holes do not overlap the first signal lines or the second signal lines. According to claim 7,
The conductive part,
a first region in which the plurality of through holes are not defined and overlaps at least one of the first signal lines and the second signal lines;
a second region in which an area exposed by the plurality of through holes has a first areal density; and
The display device of claim 1 , wherein an area exposed by the plurality of through holes includes a third area having a second area density lower than the first area density. According to claim 8,
The number of first through holes defined in the second area per first area is greater than the number of second through holes defined in the third area per first area. According to claim 8,
The size of the first through hole defined in the second area is greater than the size of the second through hole defined in the third area. According to claim 1,
and sensing pads disposed in the non-display area and electrically connected to the second signal lines, respectively. a display panel in which a display area and a non-display area adjacent to the display area are defined, and a portion of an upper surface overlapping the non-display area is curved;
an insulating layer disposed directly on the upper surface of the display panel;
sensing electrodes disposed on the insulating layer; and
It is disposed on the insulating layer and includes sensing lines electrically connected to the sensing electrodes, respectively,
The display panel,
clock signal lines arranged in the non-display area;
a light emitting element layer disposed in the display area and including a first electrode, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer;
a conductive part disposed in the non-display area, disposed on the same layer as the second electrode, and disposed between the clock signal lines and the sensing lines; and
An encapsulation layer disposed on the light emitting element layer and the conductive portion and defining the upper surface,
The insulating layer is curved along a curved shape of a portion of the upper surface. According to claim 12,
The display device of claim 1 , wherein the display panel further includes a gate driving circuit, and each of the clock signal lines provides a clock signal to the gate driving circuit. According to claim 12,
A plurality of through holes are defined in the conductive part, and the plurality of through holes do not overlap the clock signal lines or the sensing lines. According to claim 12,
and sensing pads disposed in the non-display area and electrically connected to the sensing lines, respectively.

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