KR20230160681A - Display apparatus - Google Patents

Abstract

One embodiment of the present invention includes a pixel unit including a first data line and a second data line; a data driving circuit that outputs data signals through output lines; A first switch connecting a first output line among the output lines to the first data line by a first control signal, and a second switch connecting the first output line to the second data line by a second control signal. A data distribution circuit including; and a control circuit that alternately outputs the first control signal and the second control signal for each frame of line time.

Description

Display apparatus {Display apparatus}

Embodiments of the present invention relate to display devices.

The display device is provided with a plurality of gate lines, a plurality of data lines, and a plurality of pixels located at the intersection of these lines. In order to apply a data signal to each of a plurality of data lines, the data driver must be provided with a number of output lines corresponding to the number of data lines, and as a number of integrated circuits are required, there is a problem in that the manufacturing cost increases.

Embodiments of the present invention provide a display device and a method of driving the same that can reduce the number of output lines of the data driver. Additionally, embodiments of the present invention provide a display device and a method of driving the same that can reduce image quality degradation due to external noise entering a data line. However, these tasks are illustrative and do not limit the scope of the present invention.

A display device according to an embodiment of the present invention includes a pixel unit including a first data line and a second data line; a data driving circuit that outputs data signals through output lines; A first switch connecting a first output line among the output lines to the first data line by a first control signal, and a second switch connecting the first output line to the second data line by a second control signal. A data distribution circuit including; and a control circuit that alternately outputs the first control signal and the second control signal for each line time of one frame, wherein the line time is a first line time and a second line following the first line time. It includes a time, and the control circuit continuously outputs the first control signal during the second line time of the previous line time and the first line time of the current line time, and outputs the second control signal during the second line time of the current line time. It is output continuously during the first line time of the second line time and the next line time.

In one embodiment, the data driving circuit may output a data signal in synchronization with the output timing of the first control signal and the second control signal for each line time.

In one embodiment, the second data line may be spaced apart from the first data line by one column.

In one embodiment, the pixel unit includes first pixels emitting a first color and second pixels emitting a second color connected to the first data line, alternating in the column direction, and repeating in the column direction. It may include third pixels connected to the second data line and emitting light in a third color.

In one embodiment, the data driving circuit alternately outputs first color data and second color data to the first output line in synchronization with the output timing of the first control signal for each line time, and controls the second control signal. Third color data can be output to the first output line in synchronization with the signal output timing.

In one embodiment, the second data line may be spaced two columns apart from the first data line.

In one embodiment, the pixel unit includes a third data line between the first data line and the second data line; and first pixels emitting a first color and second pixels emitting a second color connected to the first data line and the second data line, alternating in the column direction, and the third pixels alternating in the column direction. It includes third pixels that emit light in a third color connected to a data line, and the data distribution circuit includes a third switch that connects a second output line among the output lines to the third data line by the first control signal. More may be included.

In one embodiment, the data driving circuit alternately outputs first color data and second color data to the first output line in synchronization with the output timing of the first control signal for each line time, and controls the second control signal. Third color data can be output to the second output line in synchronization with the signal output timing.

In one embodiment, the second data line may be spaced three columns apart from the first data line.

In one embodiment, the pixel unit includes a third data line between the first data line and the second data line; a fourth data line between the third data line and the second data line; and first pixels repeating in the column direction and emitting light in a first color connected to the first data line, second pixels repeating in the column direction and emitting light in a second color connected to the third data line, and and third pixels emitting light in a third color repeatedly in a column direction and connected to the fourth data line, wherein the data distribution circuit divides a second output line among the output lines into the third color by the first control signal. It may further include a third switch connected to the data line, and a fourth switch connected to the fourth data line among the output lines by the first control signal.

In one embodiment, the data driving circuit outputs first color data to the first output line in synchronization with the output timing of the first control signal for each line time, and outputs second color data to the first output line. output, third color data can be output to the first output line, and the first color data can be output to the second output line in synchronization with the output timing of the second control signal.

In one embodiment, the pixel unit further includes a plurality of gate lines arranged in each row, and a gate signal supplied to each of the gate lines may overlap a portion of the first control signal and a portion of the second control signal. there is.

A display device according to an embodiment of the present invention includes first pixels emitting a first color and second pixels emitting a second color alternately in a column direction and connected to a first data line, and a pixel unit including third pixels repeatedly connected to a second data line and emitting light in a third color; a data driving circuit that outputs data signals through output lines; a data distribution circuit connecting the output lines to the first data line and the second data line according to a control signal; and a control circuit for outputting the control signal, wherein first data lines and second data lines are alternately arranged in the row direction, and the data distribution circuit connects each of the output lines to corresponding output lines for each line time of one frame. a plurality of demultiplexers selectively connected to a pair of first data lines and a second data line, wherein the line time includes a first line time and a second line time following the first line time, The control circuit alternately outputs a first control signal and a second control signal to each of the demultiplexers. The first control signal is continuously output during the second line time of the previous line time and the first line time of the current line time, and the second control signal is output continuously during the second line time of the current line time and the first line time of the next line time. It is output continuously during line time.

In one embodiment, the data driving circuit alternately outputs first color data and second color data to each of the output lines in synchronization with the output timing of the first control signal for each line time, and outputs the first color data and second color data to each of the output lines for each line time. Third color data can be output to each of the output lines in synchronization with the output timing of .

In one embodiment, each of the demultiplexers includes a first switch connecting a corresponding output line among the output lines to the first data line, and connecting the corresponding output line to the second data line by a second control signal. It may include a second switch connected to .

In one embodiment, the pixel unit further includes a plurality of gate lines arranged in each row, and a gate signal supplied to each of the gate lines may overlap a portion of the first control signal and a portion of the second control signal. there is.

A display device according to an embodiment of the present invention includes first pixels emitting a first color and second pixels emitting a second color alternately in a column direction and connected to a first data line, and a pixel unit including third pixels repeatedly connected to a second data line and emitting light in a third color; a data driving circuit that outputs data signals through output lines; a data distribution circuit connecting the output lines to the first data line and the second data line according to a control signal; and a control circuit for outputting the control signal, wherein first data lines and second data lines are alternately arranged in the row direction, and the data distribution circuit outputs a first output line among the output lines for each line time of one frame. A first demultiplexer for selectively connecting a line to a pair of first data lines, and a second demultiplexer for selectively connecting a second output line among the output lines to a pair of second data lines, wherein the line time includes a first line time and a second line time following the first line time, and the control circuit alternately outputs a first control signal and a second control signal to the first demultiplexer and the second demultiplexer, respectively. do. The first control signal is continuously output during the second line time of the previous line time and the first line time of the current line time, and the second control signal is output continuously during the second line time of the current line time and the first line time of the next line time. It is output continuously during line time.

In one embodiment, the data driving circuit alternately transmits first color data and second color data to each of the first output lines in synchronization with the output timing of the first control signal and the second control signal for each line time. and output third color data to each of the second output lines in synchronization with the output timing of the first control signal and the second control signal.

In one embodiment, the first demultiplexer includes a pair of switches connecting the first output line to each of the pair of first data lines, and the second demultiplexer connects the second output line to the pair of first data lines. It may include a pair of switches connected to each of the second data lines.

In one embodiment, the pixel unit further includes a plurality of gate lines arranged in each row, and a gate signal supplied to each of the gate lines may overlap a portion of the first control signal and a portion of the second control signal. there is.

According to embodiments of the present invention, the number of output lines of the data driver can be reduced, thereby reducing the manufacturing cost of the display device. Additionally, according to embodiments of the present invention, deterioration in image quality of the display device due to external noise flowing into the data line can be reduced. Of course, the scope of the present invention is not limited by this effect.

1 is a perspective view schematically showing a display device according to an embodiment of the present invention.
Figure 2 is a plan view schematically showing a display device according to an embodiment.
Figures 3A to 3C are circuit diagrams showing pixels according to one embodiment.
Figure 4 is a diagram explaining a demultiplexer according to an embodiment.
Figure 5 is a diagram explaining a demultiplexer according to an embodiment.
FIG. 6 is a timing diagram explaining the operation of the demultiplexer shown in FIG. 5.
Figure 7 is a diagram explaining a demultiplexer according to an embodiment.
Figure 8 is a diagram explaining a demultiplexer according to an embodiment.
FIG. 9 is a timing diagram explaining the operation of the demultiplexer shown in FIG. 8.
Figure 10 is a diagram explaining a demultiplexer according to an embodiment.
Figure 11 is a diagram explaining a demultiplexer according to an embodiment.
FIG. 12 is a timing diagram explaining the operation of the demultiplexer shown in FIG. 11.

Since the present invention can be modified in various ways and can have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

In the following embodiments, terms such as first and second are used not in a limiting sense but for the purpose of distinguishing one component from another component.

In the following examples, singular terms include plural terms unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have mean that the features or components described in the specification exist, and do not exclude in advance the possibility of adding one or more other features or components.

In the following embodiments, when a part of a film, region, component, etc. is said to be on or on another part, it is not only the case where it is directly on top of the other part, but also when another film, region, component, etc. is interposed between them. Also includes cases where there are.

In the drawings, the sizes of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to what is shown.

In this specification, “A and/or B” refers to A, B, or A and B. Additionally, in this specification, “at least one of A and B” refers to the case of A, B, or A and B.

In the following embodiments, the meaning of "extending in the first direction or the second direction" includes not only extending in a straight line, but also extending in a zigzag or curved line along the first or second direction. .

In the following embodiments, “on a plane” means when the target part is viewed from above, and “on a cross-section” means when a cross section of the target part is cut vertically and viewed from the side. In the following embodiments, “overlapping” a first component with a second component means that the first component is located above or below the second component.

In the following embodiments, when X and Y are connected, this may include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. You can. Here, X and Y may be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the drawings or detailed description, and may also include connection relationships other than those shown in the drawings or detailed description.

When X and Y are electrically connected, for example, an element that enables electrical connection between It may include one or more connections between X and Y.

In the following embodiments, “ON” used in connection with the device state may refer to an activated state of the device, and “OFF” may refer to a deactivated state of the device. “On,” as used in connection with a signal received by a device, may refer to a signal that activates the device, and “off” may refer to a signal that deactivates the device. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor is activated by a low-level voltage, and an N-channel transistor is activated by a high-level voltage. Therefore, it should be understood that the "on" voltages for a P-channel transistor (P-type transistor) and an N-channel transistor (N-type transistor) are opposite (low vs. high) voltage levels.

1 is a perspective view schematically showing a display device according to an embodiment of the present invention. Referring to FIG. 1 , the display device 10 may include a display area DA where an image is displayed and a peripheral area PA disposed around the display area DA. The display device 10 may provide a predetermined image using light emitted from a plurality of pixels arranged in the display area DA. The peripheral area (PA) is an area arranged around the display area (DA) and may be a type of non-display area in which pixels are not arranged. The display area DA may be entirely surrounded by the peripheral area PA. In the peripheral area (PA), various wires that transmit electrical signals to be applied to the display area (DA) and pads to which a printed circuit board or driver IC chip are attached may be located.

Figure 2 is a plan view schematically showing a display device according to an embodiment. Referring to FIG. 2 , the display device 10 may include a pixel unit 110, a gate driver 130, a data driver 150, a data distribution unit 170, and a control unit 190.

The display area DA may be provided with a pixel unit 110 in which a plurality of pixels P are arranged. The peripheral area (PA) may be provided with a gate driver 130, a data driver 150, a data distribution unit 170, and a control unit 190.

Each of the plurality of pixels P may be connected to a corresponding gate line among the plurality of gate lines GL1 to GLn and a corresponding data line among the plurality of data lines DL1 to DLm. Each of the plurality of gate lines GL1 to GLn may extend in a first direction (eg, x direction, row direction) and be connected to pixels P located in the same row. The gate lines GL1 to GLn can each transmit a gate signal to the pixels P in the same row. The plurality of data lines DL1 to DLm may each extend in a second direction (eg, y direction, column direction) and be connected to pixels P located in the same column.

The gate driver 130 is connected to a plurality of gate lines GL1 to GLn, generates a gate signal in response to the gate drive control signal GCS from the control unit 190, and transmits the gate signal to the gate lines GL1 to GLn. Can be supplied sequentially. When gate signals are sequentially supplied to the gate lines GL1 to GLn, pixels P can be selected row by row. The data lines DL1 to DLm may transmit data signals DATA to pixels P in each selected row. The gate line may be connected to the gate of the transistor included in the pixel (P). The gate signal may be a gate control signal that controls the turn-on and turn-off of the transistor connected to the gate line. The gate signal may be a square wave signal in which an on voltage at which the transistor can be turned on and an off voltage at which the transistor can be turned off are repeated.

The data driver 150 is connected to a plurality of output lines (OL1 to OLm/i), and the plurality of output lines (OL1 to OLm/i) are connected to a plurality of data lines (DL1 to DLm) through the data distribution unit 170. can be connected to The data driving unit 150 can convert an image signal into a data signal in the form of voltage or current according to the data driving control signal (DCS) input from the control unit 190. The data driver 150 may supply data signals to the data distribution unit 170 through output lines OL1 to OLm/i.

The data distribution unit 170 may be connected between a plurality of output lines (OL1 to OLm/i) and a plurality of data lines (DL1 to DLm). The data distribution unit 170 may include m/i (i is a natural number equal to or greater than 2) demultiplexers (DMXs) including a plurality of switches. That is, the data distribution unit 170 may be equipped with the same number of demultiplexers (DMX) as the number of output lines. One end of the demultiplexer (DMX) may be connected to one corresponding output line among the plurality of output lines (OL1 to OLm/i). And the other end of the demultiplexer (DMX) can be connected to i data lines. The demultiplexer (DMX) can supply the data signal supplied from the corresponding output line to i data lines. By using a demultiplexer (DMX), fewer output lines are required than the number of data lines, so the number of output lines connected to the data driver 150 is reduced, thereby reducing manufacturing costs. The demultiplexer (DMX) may include a plurality of switches connected to each of the corresponding output lines and i data lines.

The control unit 190 may generate a data drive control signal (DCS) and a gate drive control signal (GCS) in response to synchronization signals supplied from the outside. The control unit 190 may output a data driving control signal (DCS) to the data driving unit 150 and a gate driving control signal (GCS) to the gate driving unit 130. The control unit 190 outputs a distribution control signal (CCS) to the data distribution unit 170, and the data distribution unit 170 outputs the output lines (OL1 to OLm/i) and data lines in response to the distribution control signal (CCS). (DL1 to DLm) can be selectively connected. The control unit 190 may output i distribution control signals (CCS) to each demultiplexer (DMX) so that i data signals supplied to one output line are time-divided and supplied to i data lines. The i distribution control signals may be output sequentially so as not to overlap each other.

The gate driver 130, data distribution unit 170, and control unit 190 may be formed directly on the substrate. The data driver 150 may be placed on a flexible printed circuit board (FPCB) electrically connected to a pad disposed on one side of the board. In another embodiment, the data driver 150 may be placed directly on the substrate using a chip on glass (COG) or chip on plastic (COP) method.

When the display device 10 is an organic light emitting display device, the first power voltage ELVDD and the second power voltage ELVSS may be supplied to the pixels P of the display device 10. The first power voltage ELVDD may be a high-level voltage provided to the first electrode (pixel electrode or anode electrode) of the display element (light-emitting element) included in each pixel (P). The second power voltage ELVSS may be a low-level voltage provided to the second electrode (opposite electrode or cathode electrode) of the display element included in each pixel P. The first power voltage ELVDD and the second power voltage ELVSS may be driving voltages for causing the plurality of pixels P to emit light.

Hereinafter, the display device 10 according to an embodiment of the present invention will be described by taking an organic light emitting display device as an example, but the display device of the present invention is not limited thereto. As another embodiment, the display device 10 of the present invention may be a display device such as an inorganic light emitting display (Inorganic Light Emitting Display) or a quantum dot light emitting display (Quantum dot Light Emitting Display).

Figures 3A to 3C are circuit diagrams showing pixels according to one embodiment.

Referring to FIG. 3A, the pixel circuit (PC) is connected to a light emitting element to emit light from the pixel (P). The light emitting device may be an organic light emitting diode (OLED). The pixel circuit (PC) may include a first transistor (T1) as a driving transistor, a second transistor (T2) as a switching transistor, and a capacitor (Cst). The second transistor (T2) is connected to the gate line (GL) and the data line (DL), and receives the data signal (DATA) input through the data line (DL) according to the gate signal input through the gate line (GL). It can be transmitted to the first transistor (T1).

The capacitor (Cst) is connected to the second transistor (T2) and the driving voltage line (PL), and corresponds to the difference between the voltage received from the switching transistor (T2) and the first power voltage (ELVDD) supplied to the driving voltage line (PL). The voltage can be stored.

The first transistor (T1) is connected to the driving voltage line (PL) and the capacitor (Cst), and controls the driving current flowing from the driving voltage line (PL) to the organic light-emitting diode (OLED) in response to the voltage value stored in the capacitor (Cst). can do. Organic light-emitting diodes (OLEDs) can emit light with a predetermined brightness by driving current.

Although FIG. 3A illustrates the case where the pixel circuit (PC) includes two thin film transistors and one capacitor, the present invention is not limited to this.

Referring to FIG. 3B, the pixel circuit (PC) includes first to seventh transistors (T1 to T7), and depending on the type (p-type or n-type) of the transistor and/or operating conditions, the first to seventh transistors (T1 to T7). The first terminal of each of the through seventh transistors T1 to T7 may be a source or a drain, and the second terminal may be a terminal different from the first terminal. For example, if the first terminal is the source, the second terminal may be the drain. The first transistor (T1) is a driving transistor whose size of source-drain current is determined according to the gate-source voltage (Vgs), and the second to seventh transistors (T2 to T7) are gate-source voltages, essentially gate voltages. It may be a switching transistor that turns on/off depending on .

The pixel circuit (PC) includes a first gate line (GWL) that transmits the first gate signal (GW), a second gate line (GIL) that transmits the second gate signal (GI), and a third gate signal (GB). A third gate line (GBL) transmitting the emission control signal (EM), a data line (DL) transmitting the data signal (DATA), and a driving voltage line transmitting the driving voltage (ELVDD). (PL), can be connected to the initialization voltage line (VL) that transmits the initialization voltage (Vint).

The first transistor T1 may include a gate connected to the second node N2, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The first transistor (T1) receives the data signal (DATA) according to the switching operation of the second transistor (T2) and supplies driving current to the light emitting device. The light emitting device may be an organic light emitting diode (OLED).

The second transistor T2 (data writing transistor) may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. . The second transistor (T2) is turned on according to the first gate signal (GW) received through the first gate line (GWL) and transmits the data signal (DATA) transmitted through the data line (DL) to the first node (N1). A switching operation can be performed.

The third transistor T3 (compensation transistor) may include a gate connected to the first gate line GWL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. . The third transistor T3 may be turned on according to the first gate signal GW received through the first gate line GWL to diode-connect the first transistor T1.

The fourth transistor T4 (first initialization transistor) may include a gate connected to the second gate line GIL, a first terminal connected to the initialization voltage line VL, and a second terminal connected to the second node N2. there is. The fourth transistor (T4) is turned on according to the second gate signal (GI) received through the second gate line (GIL) and transfers the initialization voltage (Vint) to the gate of the first transistor (T1), thereby turning the first transistor (T1) on. The gate voltage of T1) can be initialized.

The fifth transistor T5 (first emission control transistor) may include a gate connected to the emission control line EL, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first node N1. there is. The sixth transistor (T6) (second light emission control transistor) has a gate terminal connected to the light emission control line (EL), a first terminal connected to the third node (N3), and a second terminal connected to the pixel electrode of the organic light emitting diode (OLED). It may include terminals. The fifth transistor (T5) and sixth transistor (T6) are simultaneously turned on according to the emission control signal (EM) received through the emission control line (EL), allowing a driving current to flow to the organic light emitting diode (OLED).

The seventh transistor (T7) (second initialization transistor) has a gate connected to the third gate line (GBL), a second terminal of the sixth transistor (T6), and a first terminal connected to the pixel electrode of the organic light emitting diode (OLED), It may include a second terminal connected to the initialization voltage line (VL). The seventh transistor (T7) is turned on according to the third scan signal (GB) received through the third gate line (GBL) and transfers the initialization voltage (Vint) to the pixel electrode of the organic light emitting diode (OLED). (OLED) pixel electrodes can be initialized. The seventh transistor T7 may be omitted.

The capacitor Cst may include a first electrode connected to the second node N2 and a second electrode connected to the driving voltage line PL.

An organic light emitting diode (OLED) includes a pixel electrode and a common electrode facing the pixel electrode, and the common electrode can receive a second power voltage (ELVSS). An organic light emitting diode (OLED) can display an image by receiving a driving current from the first transistor (T1) and emitting light in a predetermined color.

In FIGS. 3A and 3B, the transistors of the pixel circuit show P-type transistors, but the embodiment of the present invention is not limited thereto. For example, the transistors of the pixel circuit may be N-type transistors, or, as shown in FIG. 3C, some may be P-type transistors and others may be N-type transistors. In one embodiment, in the pixel circuit of FIG. 3C, the third transistor T3 and the fourth transistor T4 may be N-type transistors, and the remainder may be P-type transistors. The pixel circuits in FIGS. 3A to 3C are exemplary, and the pixel circuit of the pixel P of the present invention may be of various types.

Figure 4 is a diagram explaining a demultiplexer according to an embodiment. Figure 4 is an example of a demultiplexer (DMX) that selectively connects the kth output line (OLk) to a pair of adjacent ith data lines (DLi) and i+1th data lines (DLi+1). The demultiplexer (DMX) may include a first switch (SW1) and a second switch (SW2).

The first switch (SW1) may be provided between the k-th output line (OLk) and the i-th data line (DLi). The first switch (SW1) connects the k-th output line (OLk) and the i-th data line (DLi) by the first control signal (CLA), and the data signal (DATA) applied to the k-th output line (OLk) can be applied to the ith data line (DLi).

The second switch (SW2) may be provided between the kth output line (OLk) and the i+1th data line (DLi+1). The second switch (SW2) connects the kth output line (OLk) and the i+1th data line (DLi+1) by the second control signal (CLB), and transmits data to the kth output line (OLk). The signal (DATA) can be applied to the i+1th data line (DLi+1).

The distribution control signal (CCS) may include a first control signal (CLA) and a second control signal (CLB). The first control signal CLA and the second control signal CLB may be applied alternately at different timings without overlapping.

The pixels (P) may include a first pixel (PR), a second pixel (PB), and a third pixel (PG) that emit light of different colors. In one embodiment, the first pixel PR and the second pixel PB are alternately arranged in the column M1 where the ith data line DLi is arranged and may be connected to the ith data line DLi. The third pixel PG is repeatedly arranged in the column M2 where the i+1th data line DLi+1 is placed and may be connected to the i+1th data line DLi+1. One of the ith data line (DLi) and the i+1th data line (DLi+1) may be an odd data line (DLo) and the other may be an even data line (DLe). Figure 4 is an example in which the i-th data line (DLi) is an odd data line (DLo) and the i+1-th data line (DLi+1) is an even data line (DLe). A pair of data lines connected to the demultiplexer (DMX) may be a pair of odd and even data lines spaced apart by one column. The first pixel (PR) is a red pixel that emits red light, the second pixel (PB) is a blue pixel that emits blue light, and the third pixel (PG) is a green pixel that emits green light. You can.

Figure 4 shows pixels P connected to the n-1th gate line (GLn-1) arranged in the n-1 row and the nth gate line (GLn) arranged in the n-th row. The gate lines GLn-1 and GLn shown in FIG. 4 may be the gate line GL shown in FIG. 3A or the first gate line GWL shown in FIGS. 3B and 3C.

Figure 5 is a diagram explaining a demultiplexer according to an embodiment. FIG. 6 is a timing diagram explaining the operation of the demultiplexer shown in FIG. 5. The demultiplexer in FIG. 5 is an example of the demultiplexer in FIG. 4 being applied.

Referring to FIG. 5, the data distribution unit 170A may include a plurality of demultiplexers 172A, and the pixel unit 110 may include a plurality of pixels (P).

In the pixel unit 110, columns in which the first pixels (PR) and second pixels (PB) are alternately arranged and columns in which the third pixels (PG) are alternately arranged may be alternately repeated in the row direction. A plurality of gate lines and a plurality of data lines may be arranged in the pixel unit 110. In one embodiment, the gate lines may be the gate line GL shown in FIG. 3A or the first gate line GWL shown in FIGS. 3B and 3C. In FIG. 5 , for convenience of explanation, gate lines GLn-3 to GLn in rows n-3 to n and data lines DL1 to DL8 in first to eighth columns are shown. The data lines may include odd data lines (eg, DL1, DL3, DL5, DL7, ...) and even data lines (eg, DL2, DL4, DL6, DL8, ...). A pair of data lines connected to the demultiplexer 172A may be a pair of odd data lines and a pair of even data lines. Hereinafter, the demultiplexer 172A connected to the first output line OL1 will be described as an example, and this can be equally applied to the demultiplexers 172A connected to the remaining output lines.

The demultiplexer 172A may include a first switch (SW1) and a second switch (SW2).

The first switch SW1 may be provided between the first output line OL1 and the first data line DL1. The first switch SW1 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the first output line OL1, and a second terminal connected to the first data line DL1. . The first switch (SW1) is turned on by the first control signal (CLA) applied from the first control line (CL1), connects the first output line (OL1) to the first data line (DL1), and connects the first output line (OL1) to the first data line (DL1). The data signal DATA applied to the line OL1 may be applied to the first data line DL1.

The second switch SW2 may be provided between the first output line OL1 and the second data line DL2. The second switch SW2 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the first output line OL1, and a second terminal connected to the second data line DL2. . The second switch (SW2) is turned on by the second control signal (CLB) applied from the second control line (CL2), connects the first output line (OL1) to the second data line (DL2), and connects the first output line (OL1) to the second data line (DL2). The data signal DATA applied to the line OL1 can be applied to the second data line DL2.

The data signal (DATA) includes the first data signal (R) applied to the first pixel (PR), the second data signal (B) applied to the second pixel (PB), and the third data signal (B) applied to the third pixel (PG). It may include 3 data signals (G).

Figure 6 shows the order of data signals applied by the data driver to the pixels through the output line. Hereinafter, supplying an arbitrary signal may mean that the on voltage of the signal is supplied.

Referring to FIG. 6, the first control signal (CLA) and the second control signal (CLB) are transmitted from the control unit 190 (FIG. 2) through the first control line (CL1) and the second control line (CL2) to the demultiplexer (172A). ) can be supplied. The first control signal CLA and the second control signal CLB may be gate control signals that control turn-on and turn-off of the first switch SW1 and the second switch SW2 of the demultiplexer 172A. The first control signal (CLA) and the second control signal (CLB) are an on voltage at which the first switch (SW1) and the second switch (SW2) can be turned on, and the first switch (SW1) and the second switch (SW2) It may be a square wave signal with a repeating off voltage that can be turned off. In one embodiment, the on voltage of the first control signal CLA and the second control signal CLB may be a low level voltage (first level voltage), and the off voltage may be a high level voltage (second level voltage). .

The first control signal CLA and the second control signal CLB may have the same waveform and may be phase-shifted signals. For example, the second control signal CLB has the same waveform as the first control signal CLA and may be applied with a phase shift (phase delay) at predetermined intervals (e.g., 1 horizontal period (1H)). there is. The timing at which the voltage levels of the first control signal CLA and the second control signal CLB are inverted may be the same. The period during which the on voltage of the first control signal CLA is maintained (hereinafter referred to as 'on voltage period') and the period during which the off voltage is maintained (hereinafter referred to as 'off voltage period') are respectively controlled by the second control signal ( CLB) can overlap with the off-voltage period and on-voltage period. The on-voltage period of the first control signal CLA and the second control signal CLB may be approximately 1H.

During one frame, gate signals (..., Gn-3, Gn-2, Gn-1, Gn) are transmitted from the gate driver 130 (FIG. 2) to gate lines (..., GLn-3, GLn-2, It can be supplied sequentially through GLn-1, GLn). The gate signals (..., Gn-3, Gn-2, Gn-1, Gn) may be gate control signals that control the turn-on and turn-off of the data writing transistor (e.g., the second transistor (T2)). there is. Gate signals (..., Gn-3, Gn-2, Gn-1, Gn) can be supplied with an on voltage at which the data write transistor can be turned on and an off voltage at which the data write transistor can be turned off. In one embodiment, the on voltage of the gate signals (..., Gn-3, Gn-2, Gn-1, Gn) is a low level voltage (first level voltage), and the off voltage is a high level voltage (first level voltage). 2 level voltage).

The on-voltage period of the gate signals (..., Gn-3, Gn-2, Gn-1, Gn) can be referred to as line time (LT, Line Time). The line time (LT) may be the time required to write a data signal (DATA) to the pixels (P) of one row (line 1) in the display device 10. In one embodiment, line time (LT) may be approximately 1H. The line time (LT) may include a first line time (LT1) and a second line time (LT2) that follows the first line time (LT1). The first control signal (CLA) and the second control signal (CLB) may be supplied alternately every line time (LT).

The first control signal (CLA) or the second control signal (CLB) is supplied during the first line time (LT1) of the line time (hereinafter referred to as 'current line time') of the row to which the gate signal is supplied, and the second control signal (CLA) is supplied. The second control signal CLB or the first control signal CLA may be supplied during the line time LT2. For example, the line time when the n-1th gate signal (Gn-1) is supplied is called the current line time, and the line time when the n-2th gate signal (Gn-2) is supplied is called the previous line time. When the line time through which the nth gate signal (Gn) is supplied is called the next line time, the first control signal (CLA) is supplied continuously during the second line time of the previous line time and the first line time of the current line time. , the second control signal CLB may be continuously supplied during the second line time of the current line time and the first line time of the next line time.

The data driver 150 (FIG. 2) can supply a data signal (DATA) to each output line in synchronization with the gate signal.

For example, when the n-3rd gate signal (Gn-3) is supplied to the n-3th gate line (GLn-3) during the line time (LT), Connected pixels (PR11, PG11, PB12, PG12, PR13, PG13, PB14, PG14, ...) are selected, and the data driver 150 is output lines (OL1, OL2, OL3, OL4, ...). Data signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the first control signal CLA is supplied to the first switches SW1 of the demultiplexers 172A during the first line time LT1, and the second control signal CLB is supplied to the demultiplexers during the second line time LT2. It can be supplied to the second switches (SW2) of (172A). Accordingly, during the first line time (LT1), the first of the pixels (PR11, PG11, PB12, PG12, PR13, PG13, PB14, PG14, ...) connected to the n-3th gate line (GLn-3) 1Data signals (R11, B12, R13, B14) are transmitted to the pixels (PR11, PB12, PR13, PB14, ...) connected to the data lines (DL1, DL3, DL5, DL7, ...) to which the switch (SW1) is connected. , ...) can be supplied. And, during the second line time (LT2), the second of the pixels (PR11, PG11, PB12, PG12, PR13, PG13, PB14, PG14, ...) connected to the n-3th gate line (GLn-3) Data signals (G11, G12, G13, G14, ...) can be supplied.

Next, when the n-2th gate signal (Gn-2) is supplied to the n-2th gate line (GLn-2) during the line time (LT), the Pixels (PB21, PG21, PR22, PG22, PB23, PG23, PR24, PG24, ...) are selected, and the data driver 150 transmits data to the output lines (OL1, OL2, OL3, OL4, ...). Signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the second control signal CLB is supplied to the second switches SW2 of the demultiplexers 172A during the first line time LT1, and the first control signal CLA is supplied to the demultiplexer during the second line time LT2. It can be supplied to the first switches (SW1) of (172A). Accordingly, during the first line time (LT1), the first of the pixels (PB21, PG21, PR22, PG22, PB23, PG23, PR24, PG24, ...) connected to the n-2th gate line (GLn-2) 2Data signals (G21, G22, G23, G24) are transmitted to the pixels (PG21, PG22, PG23, PG24, ...) connected to the data lines (DL2, DL4, DL6, DL8, ...) to which the switch (SW2) is connected. , ...) can be supplied. And, during the second line time (LT2), the first of the pixels (PB21, PG21, PR22, PG22, PB23, PG23, PR24, PG24, ...) connected to the n-2th gate line (GLn-2) Data signals (B21, R22, B23, R24, ...) can be supplied.

Next, when the n-1th gate signal (Gn-1) is supplied to the n-1th gate line (GLn-1) during the line time (LT), the Pixels (PR31, PG31, PB32, PG32, PR33, PG33, PB34, PG34, ...) are selected, and the data driver 150 transmits data to the output lines (OL1, OL2, OL3, OL4, ...). Signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the first control signal CLA is supplied to the first switches SW1 of the demultiplexers 172A during the first line time LT1, and the second control signal CLB is supplied to the demultiplexers during the second line time LT2. It can be supplied to the second switches (SW2) of (172A). Accordingly, during the first line time (LT1), the first of the pixels (PR31, PG31, PB32, PG32, PR33, PG33, PB34, PG34, ...) connected to the n-1th gate line (GLn-1) 1Data signals (R31, B32, R33, B34) are transmitted to the pixels (PR31, PB32, PR33, PB34, ...) connected to the data lines (DL1, DL3, DL5, DL7, ...) to which the switch (SW1) is connected. , ...) can be supplied. And, during the second line time (LT2), the second of the pixels (PR31, PG31, PB32, PG32, PR33, PG33, PB34, PG34, ...) connected to the n-1th gate line (GLn-2) Data signals (G31, G32, G33, G34, ...) can be supplied.

Next, when the nth gate signal (Gn) is supplied to the nth gate line (GLn) for the line time (LT), the pixels (PB41, PG41, PR42, PG42, PB43) connected to the nth gate line (GLn) , PG43, PR44, PG44, ...) are selected, and the data driver 150 sends data signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the second control signal CLB is supplied to the second switches SW2 of the demultiplexers 172A during the first line time LT1, and the first control signal CLA is supplied to the demultiplexer during the second line time LT2. It can be supplied to the first switches (SW1) of (172A). Accordingly, during the first line time (LT1), the second switch (SW2) among the pixels (PB41, PG41, PR42, PG42, PB43, PG43, PR44, PG44, ...) connected to the nth gate line (GLn) ) are connected to the pixels (PG41, PG42, PG43, PG44, ...) connected to the data lines (DL2, DL4, DL6, DL8, ...), which transmit data signals (G41, G42, G43, G44, ...). ) can be supplied. And, during the second line time (LT2), the first switch (SW1) among the pixels (PB41, PG41, PR42, PG42, PB43, PG43, PR44, PG44, ...) connected to the nth gate line (GLn) Data signals (B41, R42, B43, R44, ...) are transmitted to pixels (PB41, PR42, PB43, PR44, ...) connected to data lines (DL1, DL3, DL5, DL7, ...). can be supplied.

By the above-described method, the data signal (DATA[1]) supplied by the data driver 150 to the first output line OL1 is R11, G11, G21, B21, R31, G31, G41, B41, ... The order is, and the data signal (DATA[2]) supplied to the second output line (OL2) may be in the order of B12, G12, G22, R22, B32, G32, G42, R42, .... That is, the data driver 150 transmits a data signal (R) of the first pixel (PR) and a data signal (B) of the second pixel (PB) to one of the two output lines in units of two output lines. can be output continuously, and the data signal (G) of the third pixel (PG) can be output twice continuously on the remaining output lines.

Figure 7 is a diagram explaining a demultiplexer according to an embodiment. Hereinafter, detailed description of content that overlaps with the embodiment shown in FIG. 4 will be omitted.

Referring to FIG. 7, the data distribution unit 170 according to one embodiment may include a plurality of demultiplexers (DMX). Demultiplexers (DMXs) may include first demultiplexers (DMX1) and second demultiplexers (DMX2). The first demultiplexer (DMX1) can selectively connect the kth output line (OLk) to the ith data line (DLi) and the i+2th data line (DLi+2). The second demultiplexer (DMX2) can selectively connect the k+1th output line (OLk+1) to the i+1th data line (DLi+1) and the i+3th data line (DLi+3).

The first demultiplexer (DMX1) may include a first switch (SW11) and a second switch (SW12).

The first switch (SW11) may be provided between the k-th output line (OLk) and the i-th data line (DLi). The first switch (SW11) connects the k-th output line (OLk) and the i-th data line (DLi) by the first control signal (CLA), and the data signal (DATA) applied to the k-th output line (OLk) can be applied to the ith data line (DLi).

The second switch (SW12) may be provided between the k-th output line (OLk) and the i+2-th data line (DLi+2). The second switch (SW12) connects the kth output line (OLk) and the i+2th data line (DLi+2) by the second control signal (CLB), and transmits data to the kth output line (OLk). The signal (DATA) can be applied to the i+2th data line (DLi+2).

The second demultiplexer (DMX2) may include a first switch (SW21) and a second switch (SW22).

The first switch (SW21) may be provided between the k+1th output line (OLk+1) and the i+1th data line (DLi+1). The first switch (SW21) connects the k+1th output line (OLk+1) and the i+1th data line (DLi+1) by the first control signal (CLA), and the k+1th output line ( The data signal (DATA) applied to OLk+1) can be applied to the i+1th data line (DLi).

The second switch (SW22) may be provided between the k+1th output line (OLk+1) and the i+3th data line (DLi+3). The second switch (SW22) connects the k+1th output line (OLk+1) and the i+3th data line (DLi+3) by the second control signal (CLB), and the kth output line (OLk) The data signal (DATA) applied to can be applied to the i+3th data line (DLi+3).

7 shows that the i-th data line (DLi) and the i+2-th data line (DLi+2) are odd data lines (DLo), and the i+1-th data line (DLi+1) and the i+3-th data line ( DLi+2) is an example of an even data line (DLe). A pair of data lines connected to the first demultiplexer (DMX1) are a pair of odd data lines spaced apart by two columns, and a pair of data lines connected to the second demultiplexer (DMX2) are a pair of odd data lines spaced apart by two columns. It may be a pair of even data lines.

Figure 8 is a diagram explaining a demultiplexer according to an embodiment. FIG. 9 is a timing diagram explaining the operation of the demultiplexer shown in FIG. 8. The demultiplexer in FIG. 8 is an example of the demultiplexer in FIG. 7 being applied. Hereinafter, detailed description of content that overlaps with the embodiment shown in FIGS. 5 and 6 will be omitted.

Referring to FIG. 8, the data distribution unit 170B includes a plurality of first demultiplexers 172B1 and a plurality of second demultiplexers 172B2, and the pixel unit 110 includes a plurality of pixels P. You can. In one embodiment, a pair of data lines connected to the first demultiplexer 172A may be a pair of odd data lines. A pair of data lines connected to the second demultiplexer 172B may be a pair of even-numbered data lines. Hereinafter, the first demultiplexer 172B1 connected to the first output line OL1 and the second demultiplexer 172B2 connected to the second output line OL2 will be described as an example, which means that the first demultiplexer 172B1 connected to the remaining output lines ) and the second demultiplexers 172B2.

The first demultiplexer 172B1 may include a first switch (SW11) and a second switch (SW12).

The first switch SW11 may be provided between the first output line OL1 and the first data line DL1. The first switch SW11 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the first output line OL1, and a second terminal connected to the first data line DL1. . The first switch (SW11) is turned on by the first control signal (CLA) applied from the first control line (CL1), connects the first output line (OL1) to the first data line (DL1), and turns on the first output line (CL1). The data signal DATA applied to the line OL1 may be applied to the first data line DL1.

The second switch SW12 may be provided between the first output line OL1 and the third data line DL3. The second switch SW12 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the first output line OL1, and a second terminal connected to the third data line DL3. . The second switch (SW12) is turned on by the second control signal (CLB) applied from the second control line (CL2), connects the first output line (OL1) to the third data line (DL3), and connects the first output line (OL1) to the third data line (DL3). The data signal (DATA) applied to the line (OL1) can be applied to the third data line (DL3).

The second demultiplexer 172B2 may include a first switch (SW21) and a second switch (SW22).

The first switch SW21 may be provided between the second output line OL2 and the second data line DL2. The first switch SW21 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the second output line OL2, and a second terminal connected to the second data line DL2. . The first switch (SW21) is turned on by the first control signal (CLA) applied from the first control line (CL1), connects the second output line (OL2) to the second data line (DL2), and connects the second output line (OL2) to the second data line (DL2). The data signal DATA applied to the line OL2 may be applied to the second data line DL2.

The second switch SW22 may be provided between the second output line OL2 and the fourth data line DL4. The second switch SW22 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the second output line OL2, and a second terminal connected to the fourth data line DL4. . The second switch (SW22) is turned on by the second control signal (CLB) applied from the second control line (CL2), connects the second output line (OL2) to the fourth data line (DL4), and connects the second output line (OL2) to the fourth data line (DL4). The data signal DATA applied to the line OL2 can be applied to the fourth data line DL4.

Referring to FIG. 9, when the n-3rd gate signal (Gn-3) is supplied to the n-3th gate line (GLn-3) during the line time (LT), the n-3th gate line (GLn-3) ) are selected, and the data driver 150 is connected to the output lines (OL1, OL2, OL3, OL4, ...). ) can output data signals (DATA[1], DATA[2], DATA[3], DATA[4], ...). At this time, the first control signal CLA is supplied to the first switches SW11 and SW21 of the first demultiplexers 172B1 and the second demultiplexers 172B2 during the first line time LT1, and the second control signal ( CLB) may be supplied to the second switches SW12 and SW22 of the first and second demultiplexers 172B1 and 172B2 during the second line time LT2. Accordingly, during the first line time (LT1), the first of the pixels (PR11, PG11, PB12, PG12, PR13, PG13, PB14, PG14, ...) connected to the n-3th gate line (GLn-3) 1Switches (SW11, SW21) are connected to data lines (DL1, DL2, DL5, DL6, ...) and data signals (R11, G11, R13, G13, ...) can be supplied. And, during the second line time (LT2), the second of the pixels (PR11, PG11, PB12, PG12, PR13, PG13, PB14, PG14, ...) connected to the n-3th gate line (GLn-3) Data signals (B12, G12, B14) are transmitted to the pixels (PB12, PG12, PB14, PG14, ...) connected to the data lines (DL3, DL4, DL7, DL8, ...) to which the switches (SW12, SW22) are connected. , G14, ...) can be supplied.

Next, when the n-2th gate signal (Gn-2) is supplied to the n-2th gate line (GLn-2) during the line time (LT), the Pixels (PB21, PG21, PR22, PG22, PB23, PG23, PR24, PG24, ...) are selected, and the data driver 150 transmits data to the output lines (OL1, OL2, OL3, OL4, ...). Signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the second control signal (CLB) is supplied to the second switches (SW12, SW22) of the first demultiplexers (172B1) and the second demultiplexers (172B2) during the first line time (LT1), and the first control signal ( CLA) may be supplied to the first switches (SW11, SW21) of the first demultiplexers (172B1) and the second demultiplexers (172B2) during the second line time (LT2). Accordingly, during the first line time (LT1), the first of the pixels (PB21, PG21, PR22, PG22, PB23, PG23, PR24, PG24, ...) connected to the n-2th gate line (GLn-2) 2Data signals (R22, G22, R24, G24, ...) can be supplied. And, during the second line time (LT2), the first of the pixels (PB21, PG21, PR22, PG22, PB23, PG23, PR24, PG24, ...) connected to the n-2th gate line (GLn-2) Data signals (B21, G21, B23) are transmitted to the pixels (PB21, PG21, PB23, PG23, ...) connected to the data lines (DL1, DL2, DL5, DL6, ...) to which the switches (SW11, SW21) are connected. , G23, ...) can be supplied.

Next, when the n-1th gate signal (Gn-1) is supplied to the n-1th gate line (GLn-1) during the line time (LT), the Pixels (PR31, PG31, PB32, PG32, PR33, PG33, PB34, PG34, ...) are selected, and the data driver 150 transmits data to the output lines (OL1, OL2, OL3, OL4, ...). Signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the first control signal CLA is supplied to the first switches SW11 and SW21 of the first demultiplexers 172B1 and the second demultiplexers 172B2 during the first line time LT1, and the second control signal ( CLB) may be supplied to the second switches SW12 and SW22 of the first and second demultiplexers 172B1 and 172B2 during the second line time LT2. Accordingly, during the first line time (LT1), the first of the pixels (PR31, PG31, PB32, PG32, PR33, PG33, PB34, PG34, ...) connected to the n-1th gate line (GLn-1) 1Switches (SW11, SW21) are connected to data lines (DL1, DL2, DL5, DL6, ...) and data signals (R31, G31, R33, G33, ...) can be supplied. And, during the second line time (LT2), the second of the pixels (PR31, PG31, PB32, PG32, PR33, PG33, PB34, PG34, ...) connected to the n-1th gate line (GLn-1) Data signals (B32, G32, B34) are transmitted to the pixels (PB32, PG32, PB34, PG34, ...) connected to the data lines (DL3, DL4, DL7, DL8, ...) to which the switches (SW12, SW22) are connected. , G34, ...) can be supplied.

Next, when the nth gate signal (Gn) is supplied to the nth gate line (GLn) for the line time (LT), the pixels (PB41, PG41, PR42, PG42, PB43) connected to the nth gate line (GLn) , PG43, PR44, PG44, ...) are selected, and the data driver 150 sends data signals (DATA[1], DATA[2], DATA[3], DATA[4], ...) can be output. At this time, the second control signal (CLB) is supplied to the second switches (SW12, SW22) of the first demultiplexers (172B1) and the second demultiplexers (172B2) during the first line time (LT1), and the first control signal ( CLA) may be supplied to the first switches (SW11, SW21) of the first demultiplexers (172B1) and the second demultiplexers (172B2) during the second line time (LT2). Accordingly, during the first line time LT1, the second switches ( Data signals (R42, G42, R44, G44, ...) can be supplied. And, during the second line time (LT2), the first switches (SW11) among the pixels (PB41, PG41, PR42, PG42, PB43, PG43, PR44, PG44, ...) connected to the n-th gate line (GLn) , SW21) are connected to the data lines (DL1, DL2, DL5, DL6, ...) and the data signals (B41, G41, B43, RG43, . ..) can be supplied.

By the above-described method, the data signal (DATA[1]) supplied by the data driver 150 to the first output line OL1 is R11, B12, R22, B21, R31, B32, R42, B41, ... The order is, and the data signal (DATA[2]) supplied to the second output line (OL2) may be in the order of G11, G12, G22, G21, G31, G32, G42, G41, .... That is, the data driver 150 outputs the data signal (R) of the first pixel (PR) and the data signal (B) of the second pixel (PB) to the odd output lines (OL1, OL3, ...), The data signal (G) of the third pixel (PG) can be output through the even output lines (OL2, OL4, ...).

Figure 10 is a diagram explaining a demultiplexer according to an embodiment. Hereinafter, detailed description of content that overlaps with the embodiment shown in FIG. 4 will be omitted.

Referring to FIG. 10, the data distribution unit 170 according to one embodiment may include a plurality of demultiplexers (DMX). The demultiplexers (DMX) may include first demultiplexers (DMX1), second demultiplexers (DMX2), and third demultiplexers (DMX3). The first demultiplexer (DMX1) can selectively connect the kth output line (OLk) to the ith data line (DLi) and the i+3th data line (DLi+3). The second demultiplexer (DMX2) can selectively connect the k+1th output line (OLk+1) to the i+1th data line (DLi+1) and the i+4th data line (DLi+4). The third demultiplexer (DMX3) can selectively connect the k+2th output line (OLk+2) to the i+2th data line (DLi+2) and the i+5th data line (DLi+5).

The first demultiplexer (DMX1) may include a first switch (SW11) and a second switch (SW12).

The first switch (SW11) may be provided between the k-th output line (OLk) and the i-th data line (DLi). The first switch (SW11) connects the k-th output line (OLk) and the i-th data line (DLi) by the first control signal (CLA), and the data signal (DATA) applied to the k-th output line (OLk) can be applied to the ith data line (DLi).

The second switch (SW12) may be provided between the kth output line (OLk) and the i+3th data line (DLi+3). The second switch (SW12) connects the kth output line (OLk) and the i+3th data line (DLi+3) by the second control signal (CLB), and transmits data to the kth output line (OLk). The signal (DATA) can be applied to the i+3th data line (DLi+3).

The second demultiplexer (DMX2) may include a first switch (SW21) and a second switch (SW22).

The first switch (SW21) may be provided between the k+1th output line (OLk+1) and the i+1th data line (DLi+1). The first switch (SW21) connects the k+1th output line (OLk+1) and the i+1th data line (DLi+1) by the first control signal (CLA), and the k+1th output line ( The data signal (DATA) applied to OLk+1) can be applied to the i+1th data line (DLi+1).

The second switch (SW22) may be provided between the k+1th output line (OLk+1) and the i+4th data line (DLi+4). The second switch (SW22) connects the k+1th output line (OLk+1) and the i+4th data line (DLi+4) by the second control signal (CLB), and the k+1th output line ( The data signal (DATA) applied to OLk+1) can be applied to the i+4th data line (DLi+4).

The third demultiplexer (DMX3) may include a first switch (SW31) and a second switch (SW32).

The first switch (SW31) may be provided between the k+2th output line (OLk+2) and the i+2th data line (DLi+2). The first switch (SW31) connects the k+2th output line (OLk+2) and the i+2th data line (DLi+2) by the first control signal (CLA), and the k+2th output line ( The data signal (DATA) applied to OLk+2) can be applied to the i+2th data line (DLi+2).

The second switch (SW32) may be provided between the k+2th output line (OLk+2) and the i+5th data line (DLi+5). The second switch (SW32) connects the k+2th output line (OLk+2) and the i+5th data line (DLi+5) by the second control signal (CLB), and the k+2th output line ( The data signal (DATA) applied to OLk+2) can be applied to the i+5th data line (DLi+5).

The pixels (P) may include a first pixel (PR), a second pixel (PB), and a third pixel (PG) that emit light of different colors. In one embodiment, the first pixels PR are repeatedly arranged in the column M1' where the i-th data line DLi is disposed and may be connected to the i-th data line DLi. The third pixel PG is repeatedly arranged in the column M2' where the i+1th data line DLi+1 is placed and may be connected to the i+1th data line DLi+1. The second pixels PB are repeatedly arranged in the column M3' where the i+2th data line DLi+2 is placed and may be connected to the i+2th data line DLi+2. 10 shows that the i-th data line (DLi), the i+2-th data line (DLi+2), and the i+4-th data line (DLi+4) are odd data lines (DLo), and the i+1-th data line ( DLi+1), i+3th data line (DLi+2), and i+5th data line (DLi+5) are examples of even data lines (DLe). A pair of data lines connected to the first demultiplexer (DMX1) are data lines connected to first pixels (PR) spaced apart by three columns, and a pair of data lines connected to the second demultiplexer (DMX2) are spaced apart by three columns. The third pixels (PG) spaced apart from each other are data lines connected, and a pair of data lines connected to the third demultiplexer (DMX3) may be data lines connected to the second pixels (PB) spaced apart at three column intervals. .

Figure 11 is a diagram explaining a demultiplexer according to an embodiment. FIG. 12 is a timing diagram explaining the operation of the demultiplexer shown in FIG. 11. The demultiplexer in FIG. 11 is an example of the demultiplexer in FIG. 10 being applied. Hereinafter, detailed description of content that overlaps with the embodiment shown in FIGS. 5 and 6 will be omitted.

Referring to FIG. 11, the data distribution unit 170C may include a plurality of first demultiplexers 172C1, a plurality of second demultiplexers 172C2, and a plurality of third demultiplexers 172C3.

In the pixel unit 110, a column in which the first pixels (PR) are repeatedly arranged, a column in which the third pixels (PG) are alternately arranged, and a column in which the second pixels (PB) are alternately arranged are alternately repeated in the row direction. You can. A plurality of gate lines and a plurality of data lines may be arranged in the pixel unit 110. In one embodiment, a pair of data lines connected to the first demultiplexer 172C1 may be data lines spaced at three-column intervals in which the first pixels PR are arranged in repeating columns. A pair of data lines connected to the second demultiplexer 172C2 may be data lines spaced in three columns in which the third pixels PG are arranged in repeating columns. A pair of data lines connected to the third demultiplexer 172C3 may be data lines spaced in three columns in which the second pixels PB are arranged in repeating columns. Hereinafter, the first demultiplexer 172C1 connected to the first output line OL1, the second demultiplexer 172C2 connected to the second output line OL2, and the third demultiplexer 172C3 connected to the third output line OL3. This is explained as an example, and can be equally applied to the first demultiplexers 172C1, second demultiplexers 172C2, and third demultiplexers 172C3 connected to the remaining output lines.

The first demultiplexer 172C1 may include a first switch (SW11) and a second switch (SW12).

The first switch SW11 may be provided between the first output line OL1 and the first data line DL1. The first switch SW11 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the first output line OL1, and a second terminal connected to the first data line DL1. . The first switch (SW11) is turned on by the first control signal (CLA) applied from the first control line (CL1), connects the first output line (OL1) to the first data line (DL1), and turns on the first output line (CL1). The data signal DATA applied to the line OL1 may be applied to the first data line DL1.

The second switch SW12 may be provided between the first output line OL1 and the fourth data line DL4. The second switch SW12 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the first output line OL1, and a second terminal connected to the fourth data line DL4. . The second switch (SW12) is turned on by the second control signal (CLB) applied from the second control line (CL2), connects the first output line (OL1) to the fourth data line (DL4), and connects the first output line (OL1) to the fourth data line (DL4). The data signal DATA applied to the line OL1 can be applied to the fourth data line DL4.

The second demultiplexer 172C2 may include a first switch (SW21) and a second switch (SW22).

The first switch SW21 may be provided between the second output line OL2 and the second data line DL2. The first switch SW21 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the second output line OL2, and a second terminal connected to the second data line DL2. . The first switch (SW21) is turned on by the first control signal (CLA) applied from the first control line (CL1), connects the second output line (OL2) to the second data line (DL2), and connects the second output line (OL2) to the second data line (DL2). The data signal DATA applied to the line OL2 may be applied to the second data line DL2.

The second switch SW22 may be provided between the second output line OL2 and the fifth data line DL5. The second switch SW22 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the second output line OL2, and a second terminal connected to the fifth data line DL5. . The second switch (SW22) is turned on by the second control signal (CLB) applied from the second control line (CL2), connects the second output line (OL2) to the fifth data line (DL5), and connects the second output line (OL2) to the fifth data line (DL5). The data signal DATA applied to the line OL2 can be applied to the fifth data line DL5.

The third demultiplexer 172C3 may include a first switch (SW31) and a second switch (SW32).

The first switch SW31 may be provided between the third output line OL3 and the third data line DL3. The first switch SW31 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the third output line OL3, and a second terminal connected to the third data line DL3. . The first switch (SW31) is turned on by the first control signal (CLA) applied from the first control line (CL1) to connect the third output line (OL3) to the third data line (DL3), and the third output The data signal (DATA) applied to the line (OL3) can be applied to the third data line (DL3).

The second switch SW32 may be provided between the third output line OL3 and the sixth data line DL6. The second switch SW32 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the third output line OL3, and a second terminal connected to the sixth data line DL6. . The second switch (SW32) is turned on by the second control signal (CLB) applied from the second control line (CL2), connects the third output line (OL3) to the sixth data line (DL6), and connects the third output line (OL3) to the sixth data line (DL6). The data signal DATA applied to the line OL3 can be applied to the sixth data line DL6.

Referring to FIG. 12, when the n-2th gate signal (Gn-2) is supplied to the n-2th gate line (GLn-2) during the line time (LT), the n-2th gate line (GLn-2) ) are selected, and the data driver 150 transmits a data signal (DATA) to the output lines (OL1, OL2, OL3, ...). [1], DATA[2], DATA[3], ...) can be output. At this time, the first control signal CLA is applied to the first switches SW11, SW21, and SW31 of the first demultiplexers 172C1, second demultiplexers 172C2, and third demultiplexers 172C3 during the first line time LT1. ), and the second control signal (CLB) is applied to the second switches (SW12) of the first demultiplexers (172C1), second demultiplexers (172C2), and third demultiplexers (172C3) during the second line time (LT2). , SW22, SW32). Accordingly, during the first line time (LT1), the first switches ( Data signals (R11, G11, B11, ...) are transmitted to pixels (PR11, PG11, PB11, ...) connected to data lines (DL1, DL2, DL3, ...) connected to SW11, SW21, SW31. can be supplied. And, during the second line time (LT2), the second switches (SW12) among the pixels (PR11, PG11, PB11, PR12, PG12, PB12, ...) connected to the n-2th gate line (GLn-2) , SW22, SW32) are connected to the data lines (DL4, DL5, DL6, ...) and the data signals (R12, G12, B12, ...) are connected to the pixels (PR12, PG12, PB12, ...). can be supplied.

Next, when the n-1th gate signal (Gn-1) is supplied to the n-1th gate line (GLn-1) during the line time (LT), the Pixels (PR21, PG21, PB21, PR22, PG22, PB22, ...) are selected, and the data driver 150 transmits a data signal (DATA[1]) to the output lines (OL1, OL2, OL3, ...). , DATA[2], DATA[3], ...) can be output. At this time, the second control signal CLB is applied to the second switches SW12, SW22, and SW32 of the first demultiplexers 172C1, second demultiplexers 172C2, and third demultiplexers 172C3 during the first line time LT1. ), and the first control signal (CLA) is applied to the first switches (SW11) of the first demultiplexers (172C1), second demultiplexers (172C2), and third demultiplexers (172C3) during the second line time (LT2). , SW21, SW31). Accordingly, during the first line time (LT1), the second switches ( Data signals (R22, G22, B22, ...) are transmitted to pixels (PR22, PG22, PB22, ...) connected to data lines (DL4, DL5, DL6, ...) connected to SW12, SW22, SW32. can be supplied. And, during the second line time (LT2), the first switches (SW11) among the pixels (PR11, PG11, PB11, PR12, PG12, PB12, ...) connected to the n-1th gate line (GLn-1) , SW21, SW31) are connected to the data lines (DL1, DL2, DL3, ...) and the data signals (R21, G21, B21, ...) are connected to the pixels (PR21, PG21, PB21, ...). can be supplied.

Next, when the nth gate signal (Gn) is supplied to the nth gate line (GLn) for the line time (LT), the pixels (PR31, PG31, PB31, PR32, PG32) connected to the nth gate line (GLn) , PB32, ...) is selected, and the data driver 150 sends data signals (DATA[1], DATA[2], DATA[3], . ..) can be output. At this time, the first control signal CLA is applied to the first switches SW11, SW21, and SW31 of the first demultiplexers 172C1, second demultiplexers 172C2, and third demultiplexers 172C3 during the first line time LT1. ), and the second control signal (CLB) is applied to the second switches (SW12) of the first demultiplexers (172C1), second demultiplexers (172C2), and third demultiplexers (172C3) during the second line time (LT2). , SW22, SW32). Accordingly, during the first line time (LT1), the first switches (SW11, SW21, Data signals (R31, G31, B31, ...) can be supplied to the pixels (PR31, PG31, PB31, ...) connected to the data lines (DL1, DL2, DL3, ...) to which SW31) is connected. there is. And, during the second line time (LT2), the second switches (SW12, SW22, SW32) among the pixels (PR31, PG31, PB31, PR32, PG32, PB32, ...) connected to the n-th gate line (GLn) ) can be supplied to the pixels (PR32, PG32, PB32, ...) connected to the data lines (DL4, DL5, DL6, ...). .

By the above-described method, the data signal (DATA[1]) supplied by the data driver 150 to the first output line OL1 is in the following order: R11, R12, R22, R21, R31, R32, ... The data signal (DATA[2]) supplied to the second output line (OL2) is in the order of G11, G12, G22, G21, G31, G32, ..., and the data signal supplied to the third output line (OL3) (DATA[3]) can be in the following order: B11, B12, B22, B21, B31, B32, ... That is, the data driver 150 outputs the data signal (R) of the first pixel (PR) through one output line among the three output lines, and outputs the data signal (R) of the third pixel through the other output line, in units of three output lines. The data signal (G) of (PG) can be output, and the data signal (B) of the second pixel (PB) can be output through the remaining output line.

The display device according to embodiments of the present invention drives two control signals that control the switches of the demultiplexer with a line time of approximately 1H period, and displays the nth row (line) of the mth column during 1/2H when the control signal is applied. ), and then the data signal can be applied to the pixel in the n+1th row of the mth column for 1/2H. The display device according to embodiments of the present invention performs switching of the control signal once per line time (approximately 1H), thereby reducing the switching frequency to 1/2 compared to the case where the control signal switching is performed every 1/2 line time. It can be reduced to Accordingly, when driving at high frequencies, the problem of image quality deterioration due to external noise that occurs as the switching frequency of the control signal increases is resolved, and power consumption can be reduced.

Display devices according to embodiments of the present invention include smartphones, mobile phones, smart watches, navigation devices, game consoles, TVs, vehicle head units, notebook computers, laptop computers, tablet computers, PMP (Personal Media Player), and PDAs. It can be implemented with electronic devices such as (Personal Digital Assistants). Additionally, the electronic device may be a flexible device.

As such, the present invention has been described with reference to an embodiment shown in the drawings, but this is merely an example, and those skilled in the art will understand that various modifications and variations of the embodiment are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

10: display device
110: Pixel unit
130: Gate driving part
150: Data driving unit
170, 170A, 170B, 170C: Data distribution unit
190: Control unit
DMX, 172A, 172B, 172C: Demultiplexer

Claims (20)

a pixel unit including a first data line and a second data line;
a data driving circuit that outputs data signals through output lines;
A first switch connecting a first output line among the output lines to the first data line by a first control signal, and a second switch connecting the first output line to the second data line by a second control signal. A data distribution circuit including; and
A control circuit that alternately outputs the first control signal and the second control signal for each frame of line time,
The line time includes a first line time and a second line time following the first line time,
The control circuit is,
Outputting the first control signal continuously during the second line time of the previous line time and the first line time of the current line time,
A display device that continuously outputs the second control signal during a second line time of the current line time and a first line time of the next line time. The method of claim 1, wherein the data driving circuit is:
A display device that outputs a data signal in synchronization with the output timing of the first control signal and the second control signal for each line time. According to paragraph 1,
The second data line is spaced apart from the first data line by one column. The method of claim 3, wherein the pixel unit,
First pixels that alternate in the column direction and emit light in a first color and are connected to the first data line, and second pixels that emit light in a second color, and third pixels that alternate in the column direction and are connected to the second data line. A display device comprising third pixels that emit color. The method of claim 4, wherein the data driving circuit is:
At each line time, first color data and second color data are alternately output to the first output line in synchronization with the output timing of the first control signal, and third color data are output in synchronization with the output timing of the second control signal. A display device that outputs to the first output line. According to paragraph 1,
The second data line is spaced apart from the first data line by two columns. According to clause 6,
The pixel unit,
a third data line between the first data line and the second data line; and
First pixels emitting light in a first color and second pixels emitting light in a second color alternately in the column direction and connected to the first data line and the second data line, and the third data lines alternately in the column direction. Includes third pixels connected to a line and emitting light in a third color,
The data distribution circuit further includes a third switch connecting a second output line among the output lines to the third data line by the first control signal. The method of claim 7, wherein the data driving circuit is:
At each line time, first color data and second color data are alternately output to the first output line in synchronization with the output timing of the first control signal, and third color data are output in synchronization with the output timing of the second control signal. A display device that outputs to the second output line. According to paragraph 1,
The second data line is spaced three columns apart from the first data line. According to clause 9,
The pixel unit,
a third data line between the first data line and the second data line;
a fourth data line between the third data line and the second data line; and
First pixels that repeat in the column direction and emit light in a first color connected to the first data line, second pixels that repeat in the column direction and emit light in a second color connected to the third data line, and the column It repeats in one direction and includes third pixels emitting light in a third color connected to the fourth data line,
The data distribution circuit includes a third switch connecting a second output line among the output lines to the third data line by the first control signal, and a third output line among the output lines by the first control signal. A display device further comprising a fourth switch connected to the fourth data line. The method of claim 10, wherein the data driving circuit is:
At each line time, in synchronization with the output timing of the first control signal, first color data is output to the first output line, second color data is output to the first output line, and third color data is output to the first output line. A display device that outputs the first color data to the second output line in synchronization with the output timing of the second control signal. According to paragraph 1,
The pixel unit further includes a plurality of gate lines arranged in each row,
A display device wherein a gate signal supplied to each of the gate lines overlaps a portion of the first control signal and a portion of the second control signal. First pixels that alternate in the column direction and emit light in the first color connected to the first data line, second pixels that emit light in the second color, and alternately in the column direction and emit light in the third color connected to the second data line. a pixel unit including third pixels that emit light;
a data driving circuit that outputs data signals through output lines;
a data distribution circuit connecting the output lines to the first data line and the second data line according to a control signal; and
It includes a control circuit that outputs the control signal,
The first data line and the second data line are arranged alternately in the row direction,
The data distribution circuit is,
A plurality of demultiplexers for selectively connecting each of the output lines to a corresponding pair of first and second data lines for each line time of one frame,
The line time includes a first line time and a second line time following the first line time,
The control circuit alternately outputs a first control signal and a second control signal to each of the demultiplexers.
The first control signal is continuously output during the second line time of the previous line time and the first line time of the current line time,
The second control signal is continuously output during the second line time of the current line time and the first line time of the next line time. The method of claim 13, wherein the data driving circuit is:
At each line time, first color data and second color data are alternately output to each of the output lines in synchronization with the output timing of the first control signal, and third color data is output in synchronization with the output timing of the second control signal. A display device that outputs output through each of the output lines. The method of claim 13, wherein each of the demultiplexers:
A display comprising a first switch connecting a corresponding output line among the output lines to the first data line, and a second switch connecting the corresponding output line to the second data line by a second control signal. Device. According to clause 13,
The pixel unit further includes a plurality of gate lines arranged in each row,
A display device wherein a gate signal supplied to each of the gate lines overlaps a portion of the first control signal and a portion of the second control signal. First pixels that alternate in the column direction and emit light in the first color connected to the first data line, second pixels that emit light in the second color, and alternately in the column direction and emit light in the third color connected to the second data line. a pixel unit including third pixels that emit light;
a data driving circuit that outputs data signals through output lines;
a data distribution circuit connecting the output lines to the first data line and the second data line according to a control signal; and
It includes a control circuit that outputs the control signal,
The first data line and the second data line are arranged alternately in the row direction,
The data distribution circuit is,
A first demultiplexer that selectively connects a first output line among the output lines to a pair of first data lines for each line time of one frame, and selectively connects a second output line among the output lines to a pair of second data lines. It includes a second demultiplexer connected to,
The line time includes a first line time and a second line time following the first line time,
The control circuit alternately outputs a first control signal and a second control signal to the first demultiplexer and the second demultiplexer, respectively.
The first control signal is continuously output during the second line time of the previous line time and the first line time of the current line time,
The second control signal is continuously output during the second line time of the current line time and the first line time of the next line time. The method of claim 17, wherein the data driving circuit is:
At each line time, first color data and second color data are alternately output to each of the first output lines in synchronization with the output timing of the first control signal and the second control signal, and the first control signal and the second control signal are output alternately to each of the first output lines. A display device that outputs third color data to each of the second output lines in synchronization with the output timing of the second control signal. According to clause 17,
The first demultiplexer includes a pair of switches connecting the first output line to each of the pair of first data lines,
The second demultiplexer includes a pair of switches connecting the second output line to each of the pair of second data lines. According to clause 17,
The pixel unit further includes a plurality of gate lines arranged in each row,
A display device wherein a gate signal supplied to each of the gate lines overlaps a portion of the first control signal and a portion of the second control signal.

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