KR20230113125A - Image sensor and electronic device comprising thereof - Google Patents

Abstract

An image sensor according to an embodiment of the present disclosure includes a first pixel and a second pixel connected to the same column line, and the first pixel includes 2N subpixels sharing a first floating diffusion node (N is 2 above positive integers), wherein the second pixel includes 2N sub-pixels sharing a second floating diffusion node, provided in the first pixel and the second pixel according to an exposure time setting value and a timing generator that changes the reset order and read order of the 4N subpixels and outputs row addresses according to the changed order, and a row driver that drives the pixel array based on the row addresses.

Description

Image sensor and electronic device including the same

The technical idea of the present disclosure relates to an image sensor, and more particularly, to an image sensor with an extended dynamic range and an operating method thereof.

An image sensor is a device that captures a two-dimensional or three-dimensional image of an object. An image sensor generates an image of an object using a photoelectric conversion element that reacts according to the intensity of light reflected from the object. As CMOS (Complementary Metal-Oxide Semiconductor) technology develops, CMOS image sensors using CMOS are widely used. Recently, as the resolution of an image sensor increases, an image sensor having a reduced pixel size and an increased dynamic range is required.

An object of the present disclosure is to provide a method for reading a pixel array capable of minimizing an exposure time of a pixel array having a shared pixel structure.

An image sensor according to an exemplary embodiment of the present disclosure includes a first pixel and a second pixel connected to the same column line, and the first pixel includes N subpixels (N is a positive integer greater than or equal to 2), and the second pixel includes N subpixels sharing a second floating diffusion node, the first pixel and the second pixel according to an exposure time setting value It may include a timing generator that changes the reset order and read order of 2N subpixels included in , and outputs a row address according to the changed order, and a row driver that drives the pixel array based on the row address.

An image sensor according to an exemplary embodiment of the present disclosure includes a plurality of pixels arranged in rows and columns, and each of the plurality of pixels includes N subpixels (N is an integer greater than or equal to 2) sharing a floating diffusion node. 2N subpixels provided in a pixel array, a first pixel and a second pixel adjacent in a column direction are sequentially read, wherein the first subpixel of the first pixel is read in a first horizontal period and the second pixel is read out sequentially. The reset order and read order of the 2N subpixels such that the second subpixel of the 2N subpixel is reset, the second subpixel of the second pixel is read, and the third subpixel of the first pixel is reset in the second horizontal period. and a row driver for driving the pixel array according to a reset order and a read order of the 2N subpixels based on a row address provided from the timing generator and a timing generator for setting ? according to an exposure time setting value.

An electronic device according to an exemplary embodiment of the present disclosure includes an image sensor including a pixel array including a plurality of pixels and generating image data based on an optical signal received by the pixel array, and illumination information indicating ambient illumination. and an application processor generating an exposure time setting value based on and transmitting the exposure time setting value to the image sensor, wherein the plurality of pixels include a first pixel and a second pixel connected to the same column line. wherein each of the first pixel and the second pixel includes subpixels sharing a floating diffusion node, and a reset order and a read order of a plurality of subpixels of the first pixel and the second pixel are the exposure time setting value may change according to

According to the image sensor and the method of operating the image sensor according to the technical idea of the present disclosure, two pixels alternately reset and read sub-pixels according to an exposure time set value in a pixel array having a shared pixel structure. A reset order and a read order of a plurality of subpixels included in may be changed. Accordingly, the limitation of exposure time can be overcome and the minimum exposure time can be set, so that the dynamic range of the image sensor can be increased even in an ultra-high luminance environment.

1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure.
2A is a plan view illustrating an example of a pixel array according to an exemplary embodiment of the present disclosure, and FIG. 2B is a vertical cross-sectional view of the pixel array according to an exemplary embodiment of the present disclosure.
3A and 3B illustratively show a color pattern of a pixel array according to embodiments of the present disclosure.
4 is a timing diagram illustrating an operation according to a rolling shutter of a pixel array according to an embodiment of the present disclosure.
5 is a circuit diagram illustrating a pixel and a pixel array according to an exemplary embodiment of the present disclosure.
6 is a timing diagram of control signals provided to a pixel array according to an embodiment of the present disclosure.
7 is a timing diagram of control signals provided to a pixel array according to a comparative example.
8A to 8D illustrate reset and read sequences according to setting an exposure time of a pixel array according to an embodiment of the present disclosure.
9A to 9H show a reading order of subpixels included in a pixel array according to an embodiment of the present disclosure.
10 illustrates conversion of image data stored in line buffers into image data according to a color pattern in an image sensor according to an embodiment of the present disclosure.
11 is a schematic block diagram of a timing generator according to an embodiment of the present disclosure.
12A to 12C illustrate an address calculation method of a timing generator according to an embodiment of the present disclosure.
13 is a timing diagram illustrating resetting and reading according to a change in an exposure time set value in an image sensor according to an exemplary embodiment of the present disclosure.
14 is a block diagram schematically illustrating an electronic device including an image sensor according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure.

The image sensor 100 may be mounted in an electronic device having an image or light sensing function. For example, the image sensor 100 may be a camera, a smart phone, a wearable device, the Internet of Things (IoT), a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (portable multimedia player), It can be mounted on an electronic device such as a navigation device. In addition, the image sensor 100 may be mounted on electronic devices provided as parts, such as vehicles, furniture, manufacturing facilities, doors, and various measuring devices.

The image sensor 100 includes a pixel array 110, a row driver 120, an analog-to-digital conversion circuit 130 (hereinafter referred to as an ADC circuit), a timing controller 140, and an image conversion circuit 150. , may include a memory 160. The image sensor 100 may further include an image signal processor 170 .

The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in rows and columns. ).

The pixel PX may sense light using a photoelectric conversion element and output an image signal that is an electrical signal according to the detected light. The photoelectric conversion element may be a light-sensing element composed of an organic material or an inorganic material, such as an inorganic photo diode, an organic photo diode, a perovskite photo diode, a photo transistor, a photo gate, or a pinned photo diode. can

In the pixel array 110 according to an embodiment of the present disclosure, the pixels PX may have a shared pixel structure. The pixel PX may include a plurality of sub-pixels sharing a floating diffusion node. The sub-pixel may include a photoelectric conversion element and a transfer transistor that transfers charges generated by the photoelectric conversion element to the floating diffusion node. As an example, the pixel PX may include four sub-pixels (SPX11, SPX12, SPX21, and SPX22 in FIG. 3) arranged in a 2×2 matrix as shown in FIG. 3A. However, it is not limited thereto, and the pixel PX may include M×N sub-pixels (N is a positive integer equal to or greater than 2 and M is a positive integer) arranged in an M×N matrix or an N×M matrix. .

Accordingly, the pixel array 110 may include a plurality of sub-pixel rows, and each sub-pixel row may include a plurality of sub-pixels contiguous in a row direction or each sub-pixel row may include a plurality of sub-pixels contiguous in a row direction. Sub-pixels may be arranged. Hereinafter, in the present disclosure, a 'row' means a sub-pixel row, and a row composed of pixels (or a row in which pixels are arranged) will be referred to as a pixel row.

In the embodiment, two pixels PX (for example, PX1 and PX2 and PX3 and PX4 in FIG. 3A ) adjacent in the column direction (column direction) may be connected to the same column line CL, and the exposure time setting value (again In other words, a reset order (or referred to as a shutter order) and a readout order of a plurality of subpixels included in the two pixels PX may be changed according to the set exposure time. The two pixels PX may alternately output pixel signals generated in each sub-pixel. Here, the reset of the sub-pixel means the reset of the photoelectric conversion element included in the sub-pixel. Before the exposure time, the sub-pixel may be reset by turning on a transfer transistor connected to the photoelectric conversion element (eg, a photodiode) provided in the sub-pixel to remove charges generated from the photoelectric conversion element. When the transfer transistor is turned on, charges generated in the photoelectric conversion device are transferred to the floating diffusion node, and then (or simultaneously) a reset voltage is applied to the floating diffusion node to remove the charges. The reading of the sub-pixel may be performed by turning on the photoelectric conversion transfer transistor to transfer electric charges generated by the photoelectric conversion element included in the sub-pixel to the floating diffusion node during the exposure time. A pixel voltage generated corresponding to the charge transferred to the floating diffusion node may be output to the ADC circuit 130 through a column line connected to the pixel. The exposure time (or referred to as integration time) is the period from when the transfer transistor is turned on and off to reset the subpixel and then turned on again to read the subpixel. can mean a period of time.

A subpixel of another pixel PX, for example, a second pixel, may be reset during a horizontal period in which a subpixel of one of the two pixels PX, for example, a first pixel, is read, for example, during the first horizontal period. there is. In the first horizontal period, other sub-pixels of the first pixel are reset or no pixel signals are read. Also, in a second horizontal period after the first horizontal period, a pixel signal may be read from a subpixel of a second pixel, and another subpixel of the first pixel may be reset.

The row driver 120 may drive the pixel array 110 . The row driver 120 decodes a row control signal (eg, a row address) received from the timing controller 140 and generates a plurality of row lines RL connected to the pixel array 110 in response to the decoded row control signal. ), at least one row line RL may be selected. Here, the row control signal may select at least one row among a plurality of rows included in the pixel array 110 .

In an exemplary embodiment, the row driver 120 may drive the pixel array 110 in units of two pixel rows. For example, the row driver 1120 transmits a row control signal (eg, a row address) indicating to select a plurality of subpixels provided in a first pixel and a second pixel disposed adjacently in a column direction in a set order to a timing controller ( 140), and at least one row line among a plurality of row lines connected to the pixel array 110 may be selected based on the row control signal.

The row driver 120 may generate pixel control signals, such as a selection signal, a reset signal, and a transmission control signal, provided to each pixel based on the row control signal. A plurality of subpixels may be reset and read based on the selection signal, the reset signal, and the transmission control signals.

The pixel array 110 outputs a pixel signal, for example, a pixel voltage, from each of the pixels PX included in at least one pixel row selected by a selection signal provided from the row driver 120 . The pixel signal may include a reset signal indicating a voltage level in a state in which a floating diffusion node included in a pixel is reset, and an image signal indicating a voltage level according to an optical signal received in at least one subpixel.

The row driver 120 may transmit control signals for outputting pixel signals to the pixel array 110 , and the pixels PX may operate in response to the control signals to output pixel signals.

The ADC circuit 130 may convert pixel signals output from the pixel array 110 into pixel values that are digital signals. The ADC circuit 130 includes a plurality of analog-to-digital converters (ADCs), and each of the plurality of ADCs may convert a pixel signal into a pixel value using a correlated double sampling (CDS) method. A pixel signal received through each of the plurality of column lines CL may be converted into a pixel value by a corresponding ADC among the plurality of ADCs.

The memory 160 may include a plurality of line buffers, and a plurality of pixel values generated by the ADC circuit 130 may be stored in the plurality of line buffers in units of rows.

The image conversion circuit 150 converts first image data including a plurality of pixel values output from the ADC circuit 130 and stored in the memory 160 into a color pattern of the pixel array 110 (for example, the pixel array 110). It can be converted into second image data having the same color pattern as the pattern of the color filter array on the image). For example, the pixel array 110 may have a Bayer pattern, but as described above, the readout order of a plurality of subpixels provided in two pixels PX in units of two pixels PX is As it is changed, the first image data output from the ADC circuit 130 does not have a Bayer pattern. The image conversion circuit 150 may access the memory 160 to convert first image data into second image data of a Bayer pattern.

The timing controller 140 outputs a control signal to each of the row driver 120, the ADC circuit 130, and the image conversion circuit 150, and the row driver 120, the ADC circuit 130, and the image conversion circuit ( 150) operation and operation timing can be controlled.

In an embodiment, the timing controller 140 changes (or adjusts) a reset order and a read order of a plurality of subpixels included in two adjacent pixels PX in a column direction according to the set exposure time value, and the changed order A row address according to can be generated. The timing controller 140 may set an exposure time between resetting and reading a subpixel according to an exposure time setting value. In this case, the timing controller 140 is configured to prevent pixel signals from being read from other subpixels included in the same pixel or resetting other subpixels in the horizontal period during which pixel signals are read from one subpixel included in one pixel. The reset order and read order of subpixels of can be changed. The timing controller 140 may change the reset order of the plurality of subpixels and the reading order so that the subpixel of the second pixel is reset during the horizontal period in which the subpixel of the first pixel is read out of the two pixels PX. The timing controller 140 may change the reset order and the read order of the plurality of subpixels included in the two pixels PX so that the resetting and reading of the subpixels are alternately performed in the two pixels PX. there is. As described above, the change of the reset order and the read order of a plurality of subpixels according to the exposure time setting value will be described in detail with reference to FIGS. 5 to 12C.

The image signal processor 170 may perform various signal processing on image data provided from the image data conversion circuit 150, for example, second image data. For example, the image signal processor 170 may perform signal processing such as picture quality compensation, binning, and downsizing on received image data. Picture quality compensation may be, for example, black level compensation, lens shading compensation, It may include signal processing such as crosstalk compensation and bad pixel correction.

Image data output from the image signal processor 170 may be transmitted to an external processor. For example, the external processor may be a host processor of an electronic device on which the image sensor 100 is mounted. For example, the external processor may be an application processor of a mobile terminal. The image sensor 100 may transmit image data to an external processor according to a data communication method based on a set interface, for example, MIPI (Mobile Industry Processor Interface).

As described above, in the image sensor 100 according to an embodiment of the present disclosure, the pixel array 110 has a shared pixel structure, and is divided into two pixels PX units according to an exposure time setting value, and in two pixels PX units according to an exposure time setting value. The reset order (or shuttering order) and the readout order of the plurality of subpixels included in the two pixels PX may be changed so that subpixel resetting and subpixel reading are alternately performed. As described above, as subpixel resetting and subpixel reading are alternately performed in the two pixels PX, the settable exposure time range is increased and the minimum exposure time can be set. Accordingly, the limitation of exposure time setting according to the shared pixel structure is overcome, and the dynamic range of the image sensor 100 can be increased even in a super high light environment.

2A is a plan view illustrating an example of a pixel array according to an exemplary embodiment of the present disclosure, and FIG. 2B is a vertical cross-sectional view of the pixel array according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2A , the pixel array 110 may include a plurality of pixels arranged in rows and columns, for example, first to fourth pixels PX1 , PX2 , PX3 , and PX4 . Although four pixels are shown for convenience of explanation, the pixel array 110 may include a larger number of pixels, and the number of pixels may be determined according to the resolution of the pixel array 110 .

The first pixel PX1 includes first to fourth subpixels SPX11, SPX12, SPX21, and SPX22 sharing the floating diffusion node FD, and the first to fourth subpixels SPX11, SPX12, SPX21, Each SPX22 may include a photoelectric conversion element, for example, a photodiode PD and a transfer gate TG. The transfer gate (TG) is the gate of the transfer transistor. The second to fourth pixels PX2 , PX3 , and PX4 may have the same structure as the first pixel PX1 .

16 subpixels included in the first to fourth pixels PX1 , PX2 , PX3 , and PX4 may be arranged in a 4×4 matrix, and as shown, the subpixels are arranged in the first to fourth rows Row1, Row2, Row3, Row4).

As described with reference to FIG. 1, two pixels adjacent to each other in the second direction (or column direction), for example, the Y-axis direction, for example, the first pixel PX1 and the second pixel PX2, and the third pixel ( PX3 ) and the fourth pixel PX4 may be connected to the same column line (CL in FIG. 1 ). The reset order and the read order of eight subpixels included in two pixels, for example, the first pixel PX1 and the second pixel PX2 , may be changed according to the exposure time setting value. Accordingly, the two pixels can alternately output pixel signals generated from sub-pixels.

A vertical cross-section along line A-A' is shown in FIG. 2B. Referring to FIG. 2B , the pixel array 110 includes a semiconductor substrate 111 (hereinafter referred to as a substrate) having a first surface 111B and a second surface 111F facing each other, and a first surface of the substrate 111 It may include an incident layer 112 disposed on 111B and a wiring layer 113 (or referred to as a wiring structure) disposed on the second surface 111F of the substrate 111 .

A first deep trench isolation (DTI) (DTI1) and a second DTI (DTI2) may be disposed on the substrate 111 . The first DTI (DTI1) may pass through the substrate 111 and reach from the first surface 111B to the second surface 111F. The second DTI (DTI2) extends from the first surface 111B toward the second surface 111F, but may be spaced apart from the second surface 111F. The first DTI1 (DTI1) and the second DTI (DTI2) may prevent cross-talk between pixels and sub-pixels.

A first photoelectric conversion element PD11 is disposed in the first area AR11 of the first subpixel SPX1, and a second photoelectric conversion element PD12 is disposed in the second area AR12 of the second subpixel SPX2. can be placed.

The first surface 111B of the substrate 111 may be a light incident surface, and light may be incident through the incident layer 112 and the first surface 111B. The incident layer 112 may include a micro lens ML and a color filter CF. In an embodiment, an antireflection layer AF may be disposed between the first surface 111B of the substrate 111 and the color filter CF.

The color filter CF may transmit light of a specific frequency band, that is, light of a specific color. A plurality of color filters CF may constitute a color filter array. In an embodiment, the color filter array may have a Bayer pattern. The plurality of color filters may include a red filter, a blue filter, and two green filters, and the red filter, blue filter, and two green filters are arranged in a 2 × 2 row and column, wherein the two green filters are diagonally can be placed as In an embodiment, the plurality of color filters CF may include a red filter, a blue filter, a green filter, and a white filter arranged in a 2×2 configuration. In an embodiment, the plurality of color filters CF may include a red filter, two yellow filters, and a blue filter disposed in a 2×2 pattern, and the two yellow filters may be disposed diagonally. However, it is not limited thereto, and the plurality of color filters may include filters combined with different colors. For example, the plurality of color filters may include a yellow filter, a cyan filter, and a green filter.

A first color filter CF1 may be disposed on the first sub-pixel SPX11 , and a second color filter CF2 may be disposed on the second sub-pixel SPX12 . The first color filter CF1 and the second color filter CF2 may transmit light of the same color or different colors. A color that can be sensed by a corresponding sub-pixel (first sub-pixel SPX11 or second sub-pixel SPX12) may be determined according to the color of light transmitted through the color filter CF.

The floating diffusion node FD may be formed adjacent to the second surface 111F of the substrate 111 and is located at the center of subpixels, for example, the first subpixel SPX11 and the second subpixel SPX12. can do. The floating diffusion node FD may be a region doped with impurities of the second conductivity type.

Transistor gates, for example, a first transfer gate TG11 and a second transfer gate TG12 may be formed adjacent to the second surface 111F of the substrate 111 in the wiring layer 113 . A well region (not shown) may be formed around the first transfer gate TG11 and the second transfer gate TG12 . A well region may be formed adjacent to the second surface 111F within the substrate 111 . The well region can act as the drain and source of the transistor. The first transfer gate TG11 and the second transfer gate TG12 may be formed adjacent to the floating diffusion node FD. As shown, the first transfer gate TG11 and the second transfer gate TG12 may share a floating diffusion node FD.

3A and 3B illustratively show a color pattern of a pixel array according to embodiments of the present disclosure.

Referring to FIG. 3A , a pixel array ( 110 in FIG. 1 ) may have a Bayer pattern. The Bayer pattern may refer to a pattern in which green is 50% and red and blue are 25% respectively according to human visual characteristics. A plurality of pixels included in the pixel array 110, for example, the first to fourth pixels PX1, PX2, PX3, and PX4 are first to fourth sub-pixels SPX11, SPX12, and SPX21 arranged in a 2 × 2 matrix. , SPX22). Each of the first to fourth pixels PX1 , PX2 , PX3 , and PX4 includes a first green sub-pixel Gr, a red sub-pixel R, a blue sub-pixel B, and a second green sub-pixel Gb. It can be. As described with reference to FIG. 2B , the color of a subpixel may be determined based on the color of light transmitted by a color filter disposed on each subpixel (eg, a frequency band of an optical signal transmitted by the color filter).

Referring to FIG. 3B , the pixel array 110 may have a tetra pattern. Each of the first to fourth pixels PX1 , PX2 , PX3 , and PX4 arranged in a 2×2 matrix may include first to fourth sub-pixels SPX11 , SPX12 , SPX21 , and SPX22 having the same color. The first pixel PX1 includes four first green sub-pixels Gr, the second pixel PX2 includes four blue sub-pixels B, and the third pixel PX3 includes 4 red sub-pixels R, and the fourth pixel PX4 may include four second green sub-pixels Gb.

4 is a timing diagram illustrating an operation according to a rolling shutter of a pixel array according to an embodiment of the present disclosure.

Referring to FIG. 4 , the pixel array ( 110 in FIG. 1 ) may operate according to a rolling shutter method. The pixel array 110 may include a plurality of rows, for example, first to fourth m rows (R0 to R4m-1) (m is a positive integer), and each of the plurality of rows may include a plurality of subpixels. there is. The first to fourth m rows R0 to R4m−1 may be sequentially disposed within the pixel array 110 . For example, the first row R0 is disposed at the top (or bottom) of the pixel array 110 and the 4m row R4m-1 is disposed within the pixel array 110. It can be placed at the bottom (or top).

A plurality of subpixels provided in a plurality of rows may be sequentially reset in units of at least one row, rather than being reset (shuttered) simultaneously.

Non-integration time (NIT), reset time (RST), exposure time (IT) (or referred to as integration time), and readout time (RO) for each of a plurality of rows during one frame (FRM) can be assigned A time point from when the read time RO starts to when the next read time RO starts may be defined as one frame FRM. An initial non-integration time (NIT), a reset time (RST), and an exposure time (IT) may be referred to as a shutter frame.

A subpixel may be reset at the reset time RST. Charges may be removed by turning on the transfer transistor included in the sub-pixel and transferring charges generated by the photodiode to the floating diffusion node during the non-integration time (NIT). In an embodiment, since the transfer transistor of the subpixel is turned on while the reset voltage is applied to the floating diffusion node, the floating diffusion node and the subpixel may be reset together. Charges according to the light signal may be generated and accumulated in the photodiode provided in the sub-pixel during the exposure time IT. A subpixel may be read at the read time RO. In other words, the transfer transistor included in the sub-pixel is turned on at the read time RO, and the charge accumulated in the photodiode during the exposure time IT is transferred to the floating diffusion node, and the pixel voltage corresponding to the transferred charge is It can be output through a column line (CL in FIG. 1).

As described with reference to FIGS. 3A and 3B , two pixels adjacent in a column direction may be arranged in four rows. In other words, 2 pixel rows may include 4 rows (ie, 4 sub-pixel rows). Sub-pixel resetting and reading may be alternately performed for two pixels. Accordingly, as shown in FIG. 4 , reset according to the order arranged in the pixel array 110 in units of four adjacent rows for a plurality of rows, for example, the first to fourth m rows (R0 to R4m-1) Each of the time RST, exposure time IT, readout time RO, and non-integration time NIT may be sequentially started. The order in which each of the reset time (RST), exposure time (IT), readout time (RO), and non-integration time (NIT) of each row within the four rows starts does not follow the order in which the four rows are arranged, It can be changed according to the exposure time setting value.

Meanwhile, in FIG. 4, two pixels are arranged in four rows as an example, but the technical idea of the present disclosure is not limited thereto, and when a pixel includes subpixels arranged in an N×N matrix, Two pixels may be arranged in 2N rows, and within the 2N rows, each of the reset time (RST), exposure time (IT), readout time (RO), and non-integration time (NIT) of each row starts The order in which it is performed may be changed according to the setting value of the exposure time.

5 is a circuit diagram illustrating a pixel and a pixel array according to an exemplary embodiment of the present disclosure. For convenience of description, the first pixel PX1 and the second pixel PX2 connected to the same column line CL are illustrated.

Referring to FIG. 5 , the first pixel PX1 includes first to fourth photoelectric conversion devices PD11, PD12, PD21, and PD22 and first to fourth transfer transistors TX11, TX12, TX21, and TX22 respectively connected thereto. ), a reset transistor RX1, a driving transistor DX1, and a selection transistor SX1. One photoelectric conversion element and one transfer transistor may constitute one sub-pixel. Accordingly, the first pixel PX1 may include four sub-pixels. The four subpixels may share a floating diffusion node FD1 , a reset transistor RX1 , a driving transistor DX1 , and a selection transistor SX1 .

Pixel control signals received through the row lines RL are applied to gates of the first to fourth transfer transistors TX11, TX12, TX21, and TX22, the reset transistor RX1, and the select transistor SX1. to fourth transmission control signals TS11, TS12, TS21, and TS22, a reset signal RS1, and a selection signal SEL1 may be applied.

The reset transistor RX1 may be turned on in response to the reset signal RX1 and may reset the floating diffusion node FD1 by applying the power supply voltage VDDP to the floating diffusion node FD1 as a reset voltage. In other words, the reset transistor RX1 is turned on to remove the charge accumulated in the floating diffusion node FD1.

The driving transistor DX1 may generate a pixel signal (eg, a pixel voltage) corresponding to the potential of the floating diffusion node FD1. The selection transistor SX1 may be turned on in response to the selection signal SEL1 during the read time of the first pixel PX1 to transfer the pixel signal to the column line CL. In detail, the selection transistor SX1 is turned on at the read time of each of the four sub-pixels included in the first pixel PX1 to determine the reset level of the floating diffusion node FD1 in the reset state and the corresponding sub-pixel. Image signals corresponding to charges may be output as pixel signals to the column line CL. The pixel signal corresponding to the reset level of the floating diffusion node FD1 is output to the column line CL before the transfer transistor of the corresponding sub-pixel is turned on during read time, and the pixel signal corresponding to the image signal is turned on by the transfer transistor. After being turned on and then turned off, it can be output as a pixel signal. The first to fourth transfer transistors TX11, TX12, TX21, and TX22 respond to each of the first to fourth transfer control signals TS11, TS12, TS21, and TS22 having an active level (eg, logic high) before the exposure time. The first to fourth transmission control signals TS11, TS12, TS21, and TS22 that are turned on to reset the first to fourth photoelectric conversion elements PD11, PD12, PD21, and PD22 and have an active level after an exposure time It is turned on in response to each of the photoelectric conversion devices, and during the exposure time, charges generated by the first to fourth photoelectric conversion devices PD11, PD12, PD21, and PD22 may be transferred to the floating diffusion node FD1. Here, the time at which the first to fourth transfer control signals TS11, TS12, TS21, and TS22 have an active level, that is, the time at which the first to fourth transfer transistors TX11, TX12, TX21, and TX22 are turned on may be different from each other.

The second pixel PX2 includes first to fourth photoelectric conversion devices PD31 , PD32 , PD41 , and PD42 , fifth to eighth transfer transistors TX31 , TX32 , TX41 , and TX42 respectively connected thereto, and a reset transistor RX2 . ), a driving transistor DX2 and a selection transistor SX2. Gates of the fifth to eighth transfer transistors TX31 , TX32 , TX41 , and TX42 , the reset transistor RX2 , and the select transistor SX2 receive control signals received through the row lines RL, for example, An eighth transmission control signal TS31 , TS32 , TS41 , and TS42 , a reset signal RS1 , and a selection signal SEL1 may be applied. Since the configuration and operation of the second pixel PX2 are the same as those of the first pixel PX1 , overlapping descriptions will be omitted.

The first pixel PX1 and the second pixel PX2 have a shared pixel structure in which a plurality of subpixels share floating diffusion nodes FD1 and FD2. When the rolling shutter method is applied to the pixel array 110 having a shared pixel structure as described above, another subpixel cannot be reset or read out to another subpixel in a horizontal period in which one subpixel is read out in the same pixel. Accordingly, restrictions may occur in setting the minimum exposure time of the pixel array 110 .

However, in the image sensor ( 100 in FIG. 1 ) according to an embodiment of the present disclosure, two pixels, for example, a first pixel PX1 and a second pixel PX2 connected to one column line CL, form one read unit. , and the first pixel PX1 and the second pixel PX2 can alternately perform sub-pixel resetting and sub-pixel reading operations according to the exposure time set value. Also, the reset order and the read order of the eight sub-pixels included in the second pixel PX2 may be changed. Accordingly, it is possible to set the minimum exposure time. This will be described in detail with reference to FIGS. 6 to 8D.

6 is a timing diagram of control signals provided to a pixel array according to an embodiment of the present disclosure.

An exposure time setting value, for example, CIT (Coarse Integration Time) is set to 2, and accordingly, a time corresponding to approximately two horizontal periods may be set as the exposure time. Here, the horizontal period is a period in which a pixel signal output from the pixel array (110 in FIG. 1) is converted into a pixel value, which is a digital signal, and can be distinguished by a horizontal synchronization signal HD. For example, a rising edge following the rising edge of the horizontal synchronization signal HD may be defined as one horizontal period. For example, the horizontal synchronizing signal HD may be generated by the timing controller ( 140 of FIG. 1 ) and provided to the ADC circuit ( 130 of FIG. 1 ) and the row driver 120 .

5 and 6, in the first horizontal period 1H and the second horizontal period 2H, the first selection signal SEL1 and the second selection signal SEL2 have an inactive level (eg, logic low), , the first reset signal RS1 and the second reset signal RS2 may have an active level (eg, logic high). Accordingly, the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 may be turned off, and the reset transistors RX1 and RX2 may be turned on.

In the first horizontal period 1H, a pulse signal is applied as a first transfer control signal TS11 to the first transfer transistor TX11, and accordingly, the first sub-pixel of the first pixel PX1, specifically the first photoelectric cell. The conversion element PD11 may be reset. The pulse signal may be referred to as a reset control signal.

In the second horizontal period 2H, a pulse signal (that is, a reset control signal) is applied as the second transfer control signal TS12 to the second transfer transistor TX12, and thus the second sub-pixel PX1 of the first pixel PX1 is applied. A pixel, specifically, the second photoelectric conversion element PD12 may be reset.

In the third horizontal period 3H and the fourth horizontal period 4H, the second reset signal RS2 may have an inactive level, and accordingly, the reset transistor RX1 of the first pixel PX1 is turned off. can The first selection signal SEL1 having an active level is applied to the selection transistor SX1 of the first pixel PX1, and the selection transistor SX1 is turned on so that the pixel signal from the first pixel PX1 is applied to the column line (CL).

In the third horizontal period 3H, the first sub-pixel of the first pixel PX1 may be read. The pulse signal may be applied to the first transfer transistor TX11 as the first transfer control signal TS11 to turn on the first transfer transistor TX11. The pulse signal may be referred to as a read control signal. After the first transfer transistor TX11 is turned off in the first horizontal period 1H and turned on in the third horizontal period 3H, the first photoelectric conversion element PD11 generates and The accumulated charge is provided to the floating diffusion node FD1, and a pixel signal corresponding to the potential of the floating diffusion node FD1, that is, a pixel signal (eg, an image signal) from the first sub-pixel is transmitted to the column line CL. can be output. Although not shown, the reset level of the floating diffusion node FD1 may be output as a pixel signal to the column line CL before the first transfer transistor TX11 is turned on, and corresponding to reading of other subpixels. Before the transfer transistor is turned on, the reset level of the floating diffusion node to which the subpixel is connected may be output as a pixel signal to the column line CL.

As shown in FIG. 6 , at the end of the third horizontal period 3H and/or the beginning of the fourth horizontal period 4H, the active level pulse signal is applied as the first reset signal RS1 to the first pixel PX1. The floating diffusion node FD1 of the first pixel PX1 may be reset. Thereafter, the second sub-pixel of the first pixel PX1 may be read in the fourth horizontal period 4H. When the pulse signal is applied as the second transfer control signal TS12 to the second transfer transistor TX12 to turn on the second transfer transistor TX12, the pixel signal of the second sub-pixel may be read. During the exposure time from when the second transfer transistor TX12 is turned off in the second horizontal period 2H to being turned on in the fourth horizontal period 4H, the second photoelectric conversion element PD12 generates and The accumulated charge is provided to the floating diffusion node FD1, and a pixel signal corresponding to the potential of the floating diffusion node FD1, that is, a pixel signal from the second sub-pixel may be output to the column line CL.

Hereinafter, the description of resetting and reading the first subpixel of the first pixel PX1 and the second subpixel of the first pixel PX2 described above in relation to resetting and reading other subpixels may be applied. The exposure time of each sub-pixel may be the time from when the corresponding transfer transistor is turned on to reset the sub-pixel and then turned off and then turned on again to read the sub-pixel. The exposure times of the pixels are substantially the same.

Meanwhile, in the third horizontal period 3H, the pulse signal is applied as the fifth transfer control signal TS31 to the fifth transfer transistor TX31, and accordingly, the fifth sub-pixel of the second pixel PX2, specifically the 5th transfer transistor TX31. 5 The photoelectric conversion element PD31 may be reset. In addition, in the fourth horizontal period 4H, a pulse signal is applied as a sixth transfer control signal TS32 to the sixth transfer transistor TX32, and accordingly, the sixth sub-pixel of the second pixel PX2, specifically the th 6 The photoelectric conversion element PD32 may be reset.

In the fifth horizontal period 5H and the sixth horizontal period 6H, the first selection signal SEL1 and the second reset signal RS2 have an inactive level, and the second selection signal SEL2 and the first reset signal ( RS1) may have an active level. Accordingly, the selection transistor SX2 of the second pixel PX2 is turned on, and a pixel signal from the second pixel PX2 is provided to the column line CL. During the fifth horizontal period 5H, a pulse signal is applied as a fifth transfer control signal TS31 to the fifth transfer transistor TX31 so that a fifth sub-pixel of the second pixel PX2 may be read.

At the end of the fifth horizontal period 5H and/or the beginning of the sixth horizontal period 4H, a pulse signal having an active level is provided as the second reset signal RS2 to the reset transistor RX2 of the second pixel PX2. , the floating diffusion node FD2 of the second pixel PX2 may be reset. Thereafter, in the sixth horizontal period 6H, the pulse signal is applied as the sixth transfer control signal TS32 to the sixth transfer transistor TX32 of the second pixel PX2 to read the sixth sub-pixel. During the fifth horizontal period 5H, the pulse signal is applied as the third transfer control signal TS21 to the third transfer transistor TX21, and accordingly, the third sub-pixel of the first pixel PX1, specifically the third photoelectric conversion. Device PD21 may be reset. In addition, in the sixth horizontal period 6H, a pulse signal is applied as a fourth transfer control signal TS22 to the fourth transfer transistor TX22, and accordingly, the fourth sub-pixel of the first pixel PX1, in detail, the fourth transfer transistor TX22. 4 The photoelectric conversion element PD22 may be reset.

In the seventh horizontal period 7H and the eighth horizontal period 8H, the first selection signal SEL1 and the second reset signal RS2 have active levels, and the second selection signal SEL2 and the first reset signal ( RS1) may have an inactive level. Accordingly, the selection signal SEL1 of the active level of the first pixel PX1 is applied again to the selection transistor SX1 of the first pixel PX1, and the selection transistor SX1 is turned on to turn on the first pixel PX1. ) may be provided to the column line CL. In the seventh horizontal period 7H, a pulse signal is applied as a third transfer control signal TS21 to the third transfer transistor TX21 so that the third subpixel can be read.

At the end of the seventh horizontal period 7H and/or the beginning of the eighth horizontal period 8H, the active level pulse signal is provided as the first reset signal RS1 to the reset transistor RX21 of the first pixel PX1, thereby , the floating diffusion node FD1 of the first pixel PX1 may be reset. Thereafter, in the eighth horizontal period 8H, the pulse signal is applied as the fourth transfer control signal TS22 to the fourth transfer transistor TX22 so that the fourth sub-pixel of the first pixel PX1 can be read.

In the seventh horizontal period 7H, the pulse signal is applied as the seventh transfer control signal TS41 to the seventh transfer transistor TX41, and accordingly, the seventh sub-pixel of the second pixel PX2, specifically the seventh photoelectric cell. The conversion element PD41 may be reset. Also, in the eighth horizontal period 8H, the pulse signal is applied as the eighth transfer control signal TS42 to the eighth transfer transistor TX42, and accordingly, the eighth sub-pixel of the second pixel PX2, specifically the th 8 The photoelectric conversion element PD42 may be reset.

In the ninth horizontal period 9H and the tenth horizontal period 10H, the first selection signal SEL1 and the second reset signal RS2 have an inactive level, and the second selection signal SEL2 and the first reset signal ( RS1) may have an active level. Accordingly, the selection transistor SX2 of the second pixel PX2 is turned on, and a pixel signal from the second pixel PX2 is provided to the column line CL. In the ninth horizontal period 9H, a pulse signal is applied as a seventh transfer control signal TS41 to the seventh transfer transistor TX41 to read a seventh sub-pixel of the second pixel PX2 .

At the end of the ninth horizontal period 9H and/or the beginning of the tenth horizontal period 10H, the active level pulse signal is provided as the second reset signal RS2 to the reset transistor RX2 of the second pixel PX2, thereby , the floating diffusion node FD2 of the second pixel PX2 may be reset. Then, in the tenth horizontal period 10H, the pulse signal is applied as the eighth transfer control signal TS42 to the eighth transfer transistor TX42 so that the eighth sub-pixel of the second pixel PX2 can be read.

Meanwhile, in the embodiment of FIG. 6 , when a sub-pixel is reset, that is, when a transfer transistor included in the sub-pixel is turned on based on an active level transfer control signal, the selection signal has an inactive level, and the reset signal has an inactive level. The signal is shown as having an active level. For example, when the first transmission control signal TS11 is at an active level in the first horizontal period 1H, the first selection signal SEL1 maintains an inactive level and the first reset signal RS1 maintains an active level. has been shown to be

However, the present invention is not limited thereto, and in an embodiment, when a subpixel is reset, a reset signal of an inactive level may be applied to a reset transistor of a pixel included in the subpixel to turn off the reset transistor. Charges generated in the photoelectric conversion element of the sub-pixel may be transferred to the floating diffusion node, and the photoelectric conversion element may be reset. Then, after the transfer control signal transitions to an inactive level to turn off the transfer transistor, the reset signal transitions to an active level to turn on the reset transistor. Accordingly, the floating diffusion node may be reset by applying a reset voltage to the floating diffusion node.

As described above, the horizontal period during which the first pixel PX1 and the second pixel PX2 alternately perform subpixel resetting and subpixel reading operations, and the subpixels of the first pixel PX1 are read. (For example, in the third horizontal period 3H, the fourth horizontal period 4H, the seventh horizontal period 7H, and the eighth horizontal period 8H), the sub-pixels of the second pixel PX2 are reset, and In the horizontal period (eg, the fifth horizontal period 5H, the sixth horizontal period 6H, the ninth horizontal period 9H, and the tenth horizontal period 9H) in which the sub-pixels of the 2-pixel PX2 are read, A sub-pixel of one pixel PX1 may be reset.

7 is a timing diagram of control signals provided to a pixel array according to a comparative example.

An exposure time setting value, for example, CIT (Coarse Integration Time) is set to 2, and accordingly, a time corresponding to approximately two horizontal periods may be set as the exposure time.

Referring to FIG. 7 , subpixels of the first pixel PX1 and the second pixel PX2 may be sequentially reset and the subpixels may be sequentially read. At this time, the first transfer transistor TX11 is turned on in response to a pulse signal (eg, a read control signal) of the first transfer control signal TS11 in the third horizontal period 3H, and the A first sub-pixel may be read. Also, the third sub-pixel of the first pixel PX1 may be reset in response to a pulse signal (eg, a reset control signal) of the third transmission control signal TS21. Since the first subpixel and the second subpixel share the floating diffusion node FD1, when the third subpixel is reset, the potential of the floating diffusion node FD1 is changed, and accordingly, when the first subpixel is read, the potential of the floating diffusion node FD1 is changed. , noise may be added to the pixel signal from the first sub-pixel output to the column line CL. Accordingly, other subpixels within the same pixel can be inhibited from being reset in a horizontal period in which a subpixel is read, that is, in a horizontal period in which a pixel signal from the subpixel is output.

Since other subpixels are prohibited from being read or reset during the horizontal period in which subpixels in the same pixel are read, as shown in FIG. 7 , the subpixels of the first pixel PX1 and the second pixel PX2 are sequentially When reset to , and sub-pixels are sequentially read, an exposure time setting value, for example, CIT (Coarse Integration Time), cannot be set to 3 or less, and exposure time setting is restricted. For example, since a time corresponding to approximately three horizontal periods or less cannot be set as the exposure time, restrictions arise in setting the minimum exposure period.

However, as described with reference to FIG. 6 , in the image sensor 100 according to an embodiment of the present disclosure, the first pixel PX1 and the second pixel PX2 alternately reset subpixels and read subpixels. The reset order of eight subpixels included in the first pixel PX1 and the second pixel PX2 and the read order of the subpixels may be changed according to the exposure time setting value so as to perform Therefore, the limitation in setting the exposure time is overcome, and by setting one horizontal period as the exposure time, it is possible to set the minimum exposure time. Therefore, since the minimum exposure time can be set in an ultra-high luminance environment, the dynamic range of an image generated by the image sensor 100 can be expanded.

8A to 8D illustrate reset and read sequences according to setting an exposure time of a pixel array according to an embodiment of the present disclosure.

As described with reference to FIG. 3A , it is assumed that a first pixel and a second pixel including subpixels of a 2×2 matrix having a Bayer pattern are disposed in first to fourth rows. Subpixels of the first pixel are disposed in the first row and the second row, the first green subpixel Gr1 is disposed in the even column of the first row, and the odd column in the first row Red sub-pixels R1 may be disposed, blue sub-pixels B1 may be disposed in even-numbered columns of the second row, and second green sub-pixels Gb1 may be disposed in odd-numbered columns of the second row. Subpixels of the second pixel are disposed in the third row and the fourth row, the first green subpixel Gr2 is disposed in the even column of the third row, and the odd column in the third row. Red sub-pixels R2 may be disposed, blue sub-pixels B2 may be disposed in even-numbered columns of the fourth row, and second green sub-pixels Gb2 may be disposed in odd-numbered columns of the fourth row.

Referring to FIG. 8A , when the CIT for setting the exposure time is set to 1, after the subpixel is reset, the subpixel can be read in the next horizontal period. Here, that a sub-pixel is read means that a pixel signal from the sub-pixel is output to a column line. As described with reference to FIG. 6 , the exposure time of the subpixel is from the time when the transfer transistor is turned off after the transfer transistor of the subpixel is turned on and the photoelectric conversion element is reset, and the transfer transistor is used to read the subpixel. It may be up to the time of turning on again, and the exposure time of a plurality of subpixels may be the same.

In the fourth horizontal period 4H, the first green sub-pixel Gr1 of the first pixel may be reset. In the fifth horizontal period 5H, the first green subpixel Gr1 of the first pixel may be read, and the first green subpixel Gr2 of the second pixel may be reset. In the sixth horizontal period 6H, the first green sub-pixel Gr2 of the second pixel may be read, and the red sub-pixel R1 of the first pixel may be reset.

In this way, the subpixels can be read in the next horizontal period after being reset, and in the horizontal period in which the subpixels of the first pixel are read, the subpixels of the second pixel are reset, and the subpixels of the first pixel are reset. During the period, sub-pixels of the second pixel may be read.

Referring to FIG. 8B , when CIT is set to 2, a subpixel is reset, and a subpixel can be read in a horizontal period after one horizontal period.

In the third horizontal period 3H, the first green subpixel Gr1 of the first pixel may be reset, and in the fourth horizontal period 4H, the red subpixel R1 of the first pixel may be reset. In the fifth horizontal period 5H, the first green subpixel Gr1 of the first pixel may be read and the first green subpixel Gr2 of the second pixel may be reset. In the sixth horizontal period 6H, the red sub-pixel R1 of the first pixel may be read, and the red sub-pixel R2 of the second pixel may be reset. In the seventh horizontal period 7H, the first green subpixel Gr2 of the second pixel may be read, and the blue subpixel B1 of the first pixel may be reset. During the eighth horizontal period 8H, the red subpixel R2 of the second pixel may be read, and the second green subpixel Gb2 of the first pixel may be reset.

In this way, two sub-pixels included in one pixel may be sequentially reset and then sequentially read. A subpixel of a second pixel may be reset during a horizontal period in which a subpixel of a first pixel is read, and a subpixel of a second pixel may be read during a horizontal period during which a subpixel of the first pixel is reset.

Referring to FIG. 8C , when CIT is set to 3, the subpixel is reset and the subpixel can be read in the horizontal period after two horizontal periods.

The first green sub-pixel Gr1 of the first pixel is reset in the second horizontal period 2H, the first green sub-pixel Gr2 of the second pixel is reset in the third horizontal period 3H, and the fourth In the horizontal period 4H, the red sub-pixel R1 of the first pixel may be reset. In the fifth horizontal period 5H, the first green subpixel Gr1 of the first pixel may be read and the red subpixel R2 of the second pixel may be reset. In the sixth horizontal period 6H, the first green subpixel Gr2 of the second pixel may be read and the blue subpixel B1 of the first pixel may be reset. In the seventh horizontal period 7H, the red sub-pixel R1 of the first pixel may be read and the blue sub-pixel B2 of the second pixel may be reset.

In this way, the sub-pixels can be reset and read out in a horizontal period after two horizontal periods. A subpixel of a second pixel may be reset during a horizontal period in which a subpixel of a first pixel is read, and a subpixel of a second pixel may be read during a horizontal period during which a subpixel of the first pixel is reset.

Referring to FIG. 8D , when CIT is set to 4, the subpixel is reset, and the subpixel can be read in the horizontal period after three horizontal periods.

In the first to fourth horizontal periods 1H, 2H, 3H, and 4H, a first green subpixel Gr1, a red subpixel R1, a blue subpixel B1, and a second green subpixel ( Gb1) is sequentially reset, and in the fifth to eighth horizontal periods 5H, 6H, 7H, and 8H, the first green sub-pixel Gr1, the red sub-pixel R1, the blue sub-pixel B1 and The second green sub-pixel Gb1 may be sequentially read. In addition, in the fifth to eighth horizontal periods 5H, 6H, 7H, and 8H, the first green sub-pixel Gr2, the red sub-pixel R2, the blue sub-pixel B2 and the second green sub-pixel Gr2 of the second pixel The pixel Gb12 is sequentially reset, and in the ninth to twelfth horizontal periods 9H, 10H, 11H, and 12H, the first green sub-pixel Gr2, red sub-pixel R2, and blue sub-pixel of the second pixel ( B2) and the second green sub-pixel Gb2 may be sequentially read.

When the CIT is set to 4 or more, subpixels of the first pixel and the second pixel may be sequentially reset and read in this way.

As described with reference to FIGS. 8A to 8D , the exposure time may be changed according to the CIT. When the CIT is 1, the shortest exposure time is set, and the exposure time may increase as the CIT increases.

9A to 9H exemplarily illustrate a reading order of subpixels included in a pixel array according to an embodiment of the present disclosure.

Referring to FIGS. 9A to 9H , sub-pixels of the first pixel PX1 and the fifth pixel PX5 are disposed in a first row Row1 and a second row Row2, and the second pixel PX2 and Subpixels of the sixth pixel PX6 are disposed in the third row Row3 and the fourth row Row4, and the subpixels of the third pixel PX3 and the seventh pixel PX7 are disposed in the fifth row Row5. and the sixth row Row6 , and the sub-pixels of the fourth pixel PX4 and the eighth pixel PX8 may be disposed in the seventh row Row7 and the eighth row 8 .

In this embodiment, subpixels arranged in two rows can be simultaneously read in one horizontal period for fast reading, and for this, some of the pixels arranged in the same column, for example, the first pixel PX1 and the second The pixel PX2 may be connected to the first column line CL1 , and other portions, for example, the third pixel PX3 and the fourth pixel PX4 may be connected to the second column line CL2 . Pixel signals output from the first and second pixels PX1 and PX2 are provided to the first ADC ADC1, and pixel signals output from the third and fourth pixels PX3 and PX4 are supplied to the second ADC. It can be provided as an ADC (ADC2). The fifth pixel PX5 and the sixth pixel PX6 are connected to the third column line CL3 , and the pixel signals output from the fifth pixel PX5 and the sixth pixel PX6 are transmitted to the third ADC ADC3 . can be provided as The seventh pixel PX7 and the eighth pixel PX8 are connected to the fourth column line CL4, and the pixel signals output from the seventh pixel PX7 and the eighth pixel PX8 are connected to the fourth ADC ADC4. can be provided as However, the technical concept of the present disclosure is not limited thereto, and subpixels arranged in one row can be read in one horizontal period, and for this, pixels arranged in the same column can be connected to the same column line.

9A and 9B show the reading order of subpixels when CIT is set to 1. Since CIT is set to 1, subpixels read out in each horizontal period can be reset in the previous horizontal period.

Referring to FIG. 9A , the first green sub-pixel Gr of the first pixel PX1 , the third pixel PX3 , the fifth pixel PX5 , and the seventh pixel PX7 in the first horizontal period 1H is read out The pixel signals output through the first to fourth column lines CL1 , CL2 , CL3 , and CL4 are converted into pixel values in the first to fourth ADCs ADC1 , ADC2 , ADC3 , and ADC4 , respectively, and stored in a memory (see FIG. 1 ). 160) may be stored in the line buffer.

Afterwards, as shown in FIG. 9B , the first green sub-pixels of the second pixel PX2 , the fourth pixel PX4 , the sixth pixel PX6 , and the eighth pixel PX8 in the second horizontal period 2H. A pixel can be read from (Gr).

Referring to FIG. 9C , the red sub-pixels R of the first pixel PX1 , the third pixel PX3 , the fifth pixel PX5 , and the seventh pixel PX7 are read in the third horizontal period 3H. It can be.

Referring to FIG. 9D , in the fourth horizontal period 4H, the red sub-pixels R of the second pixel PX2 , the fourth pixel PX4 , the sixth pixel PX6 , and the eighth pixel PX8 are read out. It can be.

Referring to FIG. 9E , pixels from the blue sub-pixel B of the first pixel PX1 , the third pixel PX3 , the fifth pixel PX5 , and the seventh pixel PX7 in the fifth horizontal period 3H. can be read out.

Referring to FIG. 9F , the blue sub-pixels B of the second pixel PX2 , the fourth pixel PX4 , the sixth pixel PX6 , and the eighth pixel PX8 are read in the sixth horizontal period 6H. It can be.

Referring to FIG. 9G , the second green sub-pixels Gb of the first pixel PX1 , the third pixel PX3 , the fifth pixel PX5 , and the seventh pixel PX7 in the seventh horizontal period 7H can be read out.

Referring to FIG. 9H , in the eighth horizontal period 8H, second green sub-pixels Gb of the second pixel PX2 , the fourth pixel PX4 , the sixth pixel PX6 , and the eighth pixel PX8 can be read out.

Pixel values generated by converting pixel signals output in the same horizontal period into digital signals may be stored in the same line buffer of the memory 160 .

10 illustrates conversion of image data stored in line buffers into image data according to a color pattern in an image sensor according to an embodiment of the present disclosure. Image data conversion of FIG. 10 may be performed by the image conversion circuit 150 of FIG. 1 .

As described with reference to FIGS. 9A to 9H , pixel values corresponding to pixel signals output from a plurality of subpixels included in the pixels in a plurality of horizontal periods (1H to 8H) are stored in a memory (160 in FIG. 1 ). ) may be stored as the first image data IDT1 in the line buffers LB1 to LB7. For example, first pixel values P_Gr generated in the first horizontal period 1H and the second horizontal period 2H are stored in the first line buffer LB1 and the second line buffer LB2, and Second pixel values P_R generated in the third and fourth horizontal periods 3H and 4H are stored in the three-line buffer LB3 and the fourth line buffer LB4, and the fifth line buffer LB5 ) and the sixth line buffer LB6 store the third pixel values P_B generated in the fifth horizontal period 5H and the sixth horizontal period 6H, and the seventh line buffer LB7 and the eighth line The buffer LB8 may store the fourth pixel values P_GB in the seventh horizontal period 7H and the eighth horizontal period 8H. Here, the first pixel value P_Gr is a pixel value corresponding to the first green sub-pixel (Gr in FIG. 9A ), and the second pixel value P_R is a pixel value corresponding to the red sub-pixel (R in FIG. 9A ). , The third pixel value P_B may be a pixel value corresponding to the blue sub-pixel (B in FIG. 9A), and the fourth pixel value P_Gb may be a pixel value corresponding to the second green sub-pixel (Gb in FIG. 9A). there is.

The image signal processor ( 170 in FIG. 1 ) may perform signal processing on image data of a specific color pattern, for example, a Bayer pattern. Accordingly, the image conversion circuit 150 may access the memory 160 to convert the first image data IDT1 into second image data IDT2 having a Bayer pattern.

11 is a schematic block diagram of a timing generator according to an embodiment of the present disclosure.

Referring to FIG. 11 , the timing generator 140 includes a register bank 141, a buffer 142, a first address generation circuit 143, a second address generation circuit 144, and a first address recalculation circuit 145. , a second address recalculation circuit 146 and an address output circuit 147. The first address generation circuit 143, the second address generation circuit 144, the first address recalculation circuit 145, the second address recalculation circuit 146, and the address output circuit 147 are implemented in hardware, or Alternatively, it may be implemented as a combination of hardware and software.

The register bank 141 may store an exposure time setting value (eg, CIT) and a set of tuning values corresponding to the plurality of exposure time setting values. The exposure time setting value may be stored in the register bank 141 . A set of a plurality of tuning values may be predetermined and stored in the register bank 141 corresponding to each exposure time setting value.

The exposure time setting value may be provided from an external processor that communicates with the image sensor (100 in FIG. 1 ), for example, an application processor, and changes in ambient illumination every frame or according to the ambient illumination of the image sensor (100 in FIG. 1 ). It can be changed whenever it exceeds a certain range. The application processor may receive illuminance information (eg, an illuminance value) from the illuminance sensor, and determine a change in an exposure time setting value, for example, CIT. For example, the application processor can change the CIT whenever the illuminance value exceeds a certain range, increase the exposure time by setting the CIT large when the illuminance becomes dark, and shorten the exposure time by setting the CIT small when the illuminance becomes bright. can reduce

An exposure time setting value and a set of tuning values corresponding to the exposure time setting value may be provided to the buffer 142 . At this time, the exposure time setting value may be changed according to the ambient illumination, and the changed exposure time setting value and the set of tuning values corresponding to the changed exposure time setting value are applied to the frame starting after the change. Buffer 142 can be implemented as a double buffer.

The buffer 142 may provide an exposure time setting value, for example, CIT, to the first address generating circuit 143 and the second address generating circuit 144 in synchronization with an update timing pulse indicating an update time of a frame. In this case, CITs provided to the first address generating circuit 143 and the second address generating circuit 144 may be different. The buffer 142 may provide a set of tuning values corresponding to the CIT to the second address recalculation circuit 145 and the second address recalculation circuit 146 in synchronization with the update timing pulse.

For example, a first CIT (CIT1) may be set for the Kth frame (K is a positive integer), and a second CIT (CIT2) may be set for the K+1th frame. The first CIT (CIT1) is provided to the first address generation circuit 143 before the K-th frame (eg, the K-1-th frame), and a first tuning value set (TVS1) corresponding to the first CIT (CIT1) This first address recalculation circuit 145 may be provided.

The first address generation circuit 143 may generate an input row address IR_ADD (or referred to as a reference address). As shown in FIGS. 12A to 12C , the value of the input row address IR_ADD may sequentially increase and may sequentially indicate a plurality of rows of the pixel array ( 110 in FIG. 1 ).

The first address generation circuit 143 may generate a read timing signal and a reset timing signal based on the read timing signal and the first CIT (CIT1). The read timing signal may indicate a time point at which reading of a subpixel starts (eg, a horizontal period), and a reset timing signal may indicate a time point at which a reset of a subpixel starts (eg, a horizontal period). In an embodiment, the read timing signal may be fixed to a specific horizontal period (eg, the fifth horizontal period 5H of FIGS. 8A to 8C), and reset in units of one horizontal period based on the first CIT (CIT1). The timing point can be adjusted.

For example, if the first CIT (CIT1) is 2, the first address generation circuit 143, as described with reference to FIG. 8B, from the horizontal period in which sub-pixels are read (eg, the fifth horizontal period 5H) A reset timing signal indicating that the sub-pixel is to be reset in a horizontal period two previous years (eg, the third horizontal period 3H) may be generated. If the first CIT (CIT1) is 3, the first address generation circuit 143, as described with reference to FIG. 8C , the horizontal period (for example, the fifth horizontal period 5H) in which the sub-pixel is read out three times earlier. A reset timing signal indicating that the sub-pixel is to be reset in the horizontal period (eg, the second horizontal period 2H) may be generated.

The first address recalculation circuit 145 recalculates the row based on the input row address IR_ADD provided from the first address generator circuit 143 and the first tuning value set TVS1 provided from the buffer 142. You can create a recalculated row address. In an embodiment, when the image sensor (100 in FIG. 1 ) supports fast readout, as described with reference to FIGS. 9A to 9H , subpixels arranged in at least two rows may be simultaneously read. Accordingly, the first address recalculation circuit 145 may generate at least two recalculation row addresses.

The second CIT (CIT2) is provided to the second address generation circuit 144 before the K+1th frame (eg, K frame), and the second tuning value set TVS2 corresponding to the second CIT (CIT2) is It may be provided to the second address recalculation circuit 146 . Operations of the second address generation circuit 144 and the second address recalculation circuit 146 are similar to those of the first address generation circuit 143 and the first address recalculation circuit 143 .

The address output circuit 147 includes a reset timing signal, a read timing signal, a recalculated row address, and a first address generator circuit 143 generated by the first address generator circuit 143 and the first address recalculation circuit 143. The reset timing signal, the read timing signal, and the recalculated row address generated by the first address recalculation circuit 145 may be alternately provided to the row driver 120 for each frame.

For example, the address output circuit 147 provides the reset timing signal generated by the first address generator circuit 143 to the row driver 120 in the K-1th frame, and the first address generator circuit in the Kth frame. 143 and the read timing signal generated by the first address recalculation circuit 145 and the recalculated row address may be provided to the row driver 120 . In addition, the address output circuit 147 provides the reset timing signal generated by the second address generator circuit 144 to the row driver 120 in the Kth frame, and the second address generator circuit 144 in the K+1th frame. ), the read timing signal generated by the second address recalculation circuit 146, and the recalculated row address may be provided to the row driver 120. Accordingly, as shown in FIG. 13 , when the CIT is changed, the changed CIT can be immediately applied to the next frame, thereby preventing a dead frame from occurring.

12A to 12C illustrate an address calculation method of a timing generator according to an embodiment of the present disclosure.

FIG. 12A shows when CIT is 1 or 3, FIG. 12B shows when CIT is 2, and FIG. 12B shows when CIT is 4 or more. A pixel is assumed to contain four sub-pixels arranged in a 2x2 matrix. 12A to 12C illustrate an address calculation method when subpixels disposed in two non-adjacent rows are simultaneously read for fast reading, as described with reference to FIGS. 9A to 9H . A description will be made with reference to FIGS. 9A to 9H .

Referring to FIG. 12A, the input row address IR_ADD generated by the address generating circuit (for example, the first address generating circuit 143 or the second address generating circuit 144 of FIG. 11) has a value increasing by 1 from 0. can have The input row address IR_ADD is a value for sequentially selecting a plurality of rows (for example, a first row (Row1) to an eighth row (Row8) provided in the pixel array (110 of FIGS. 9A to 9H) in every horizontal period. can indicate

When CIT is 1 or 3, the set of tuning values (TVS) may be 0, -1, 2, 1, 3, 2, 5, or 4, as shown. The address recalculation circuit (eg, the first address recalculation circuit 145 or the second address recalculation circuit 146 of FIG. 11 ) first recalculates a value obtained by subtracting the corresponding tuning value from the input row address IR_ADD A value calculated by adding 4 to each of the first recalculated row addresses RR_ADD_0 may be generated as the second recalculated row address RR_ADD_1. The first recalculated row address RR_ADD_0 is 0, 2, 0, 2, 1, 3, 1, 3, and the second recalculated row address RR_ADD_1 is 4, 6, 4, 6, 5, 7 , 5 or 7. If the first recalculated row address RR_ADD_0 is '0', it indicates the first row Row1 in the pixel array 110, and if the second recalculated row address RR_ADD_1 is '4', the pixel array 110 Indicates the fifth row (Row5).

In the E_O phase, among subpixels provided in rows indicated by the first recalculated row address RR_ADD_0 and the second recalculated row address RR_ADD_1, subpixels arranged in odd columns or subpixels arranged in even columns represent them If the E_O phase is an even number (E), subpixels arranged in even columns may be read, and if the E_O phase is an odd number (O), subpixels arranged in odd columns may be read.

For example, if the input address IR_ADD is '0', the first recalculated row address RR_ADD_0 is '0' and the second recalculated row address RR_ADD_1 is '4',

The E_O phase is an even number (E). Accordingly, in the first horizontal period, the first green sub-pixels Gr1 and Gr3 of the first pixel PX1 and the third pixel PX3 disposed in the even columns of the first row and the fifth row are simultaneously read. can

If the input address IR_ADD is '1', the first recalculated row address RR_ADD_0 is '2', the second recalculated row address RR_ADD_1 is '6', and the E_O phase is an even number (E )am. Accordingly, in the second horizontal period, the first green sub-pixels Gr2 and Gr4 of the second pixel PX2 and the fourth pixel PX4 disposed in even columns of the third row and the seventh row are simultaneously read. can

If the input address IR_ADD is '2', the first recalculated row address RR_ADD_0 is '0', the second recalculated row address RR_ADD_1 is '4', and the E_O phase is an odd number (0 )am. Accordingly, in the third horizontal period, the red sub-pixels R1 and R3 of the first pixel PX1 and the third pixel PX3 disposed in odd-numbered columns of the first row and the fifth row may be simultaneously read. .

If the input address IR_ADD is '3', the first recalculated row address RR_ADD_0 is '2', the second recalculated row address RR_ADD_1 is '6', and the E_O phase is an odd number (0 )am. Accordingly, in the fourth horizontal period, the red sub-pixels R2 and R4 of the second pixel PX2 and the fourth pixel PX4 disposed in odd-numbered columns of the third row and the seventh row may be simultaneously read. .

In the fifth horizontal period, the blue sub-pixels B1 and B3 of the first pixel PX1 and the third pixel PX3 disposed in even columns of the second row and the sixth row are simultaneously read, and the sixth horizontal During the period, the blue sub-pixels B2 and B4 of the second pixel PX2 and the fourth pixel PX4 disposed in the even columns of the fourth row and the eighth row are simultaneously read, and in the seventh horizontal period, the second The second green sub-pixels Gb1 and Gb3 of the first pixel PX1 and the third pixel PX3 disposed in the odd-numbered columns of the row and the sixth row are simultaneously read, and in the eighth horizontal period, the fourth row and the second green sub-pixels Gb3 are read. The second green sub-pixels Gb2 and Gb4 of the second and fourth pixels PX2 and PX4 disposed in odd-numbered columns of the eighth row may be simultaneously read.

As described above, when CIT is set to 1 or 3, two adjacent pixels (for example, the first pixel PX1 and the second pixel PX2, or the third pixel ( Sub-pixels may be alternately read from PX3) and the fourth pixel PX4).

Referring to FIG. 12B, the input row address IR_ADD may have a value that increases by one. When CIT is 2, the set of tuning values may be 0, 1, 0, 1, 3, 4, 3, 4 as shown. The value obtained by subtracting the tuning value from the input row address (IR_ADD) is generated as the first recalculated row address (RR_ADD_0), and the value obtained by adding 4 to the first recalculated row address (RR_ADD_0) is the second recalculated row. It can be created as an address (RR_ADD_1).

As shown, the first recalculated row address RR_ADD_0 is 0, 0, 2, 2, 1, 1, 3, 3, and the second recalculated row address RR_ADD_1 is 4, 4, 6, 6, 5, 5, 7, 7, and the E_O phase can be changed every horizontal period. Accordingly, the first green sub-pixels Gr1 and Gr3 of the first pixel and the third pixel disposed in the even columns of the first row and the fifth row are read in the first horizontal period, and in the second horizontal period Red sub-pixels R1 and R3 of the first pixel and the third pixel disposed in odd columns of row 1 and row 5 are read, and are disposed in even columns of row 3 and row 7 in the third horizontal period. The first green sub-pixels Gr2 and Gr4 of the second and fourth pixels are read, and the second and fourth pixels disposed in odd columns of the third row and the seventh row in the fourth horizontal period Red sub-pixels R2 and R4 may be read. In addition, in the fifth horizontal period, the blue sub-pixels B1 and B3 of the first pixel and the third pixel disposed in the even columns of the second row and the sixth row are read, and in the sixth horizontal period, the blue sub-pixels B1 and B3 are read. The second green sub-pixels Gb1 and Gb3 of the first pixel and the third pixel disposed in the odd columns of the sixth row are read, and are disposed in the even columns of the fourth row and the eighth row in the seventh horizontal period. Blue sub-pixels B2 and B4 of the second and fourth pixels are read, and second green of the second and fourth pixels disposed in odd-numbered columns of the fourth row and the eighth row in the eighth horizontal period Sub-pixels Gb2 and Gb4 may be read.

When the CIT is set to 2, two adjacent pixels (eg, the first pixel PX1 and the second pixel PX2, or the third pixel PX3 and the fourth pixel (for example, the first pixel PX1 and the fourth pixel) are connected to the same column line every two horizontal periods. Sub-pixels can be read alternately in PX4)). Referring to FIG. 12C , the input row address IR_ADD may have a value that increases by one. When CIT is 4 or more, the set of tuning values may be 0, 1, 1, 2, 2, 3, 3, 4, as shown. A value obtained by subtracting the tuning value from the input row address (IR_ADD) is generated as the first recalculated row address (RR_ADD_0), and a value obtained by adding 4 to the first recalculated row address (RR_ADD_0) is a second recalculated row. It can be created as an address (RR_ADD_1).

As shown, the first recalculated row address RR_ADD_0 is 0, 0, 1, 1, 2, 2, 3, 3, and the second recalculated row address RR_ADD_1 is 4, 4, 5, 5, 6, 6, 7, 7, and the E_O phase can be changed every horizontal period. Accordingly, the first green sub-pixels Gr1 and Gr3 of the first pixel and the third pixel disposed in the even columns of the first row and the fifth row are read in the first horizontal period, and in the second horizontal period The red sub-pixels R1 and R3 of the first pixel and the third pixel disposed in odd-numbered columns of row 1 and row 5 are read, and are disposed in even-numbered columns of row 2 and row 3 in the third horizontal period. The blue sub-pixels B1 and B3 of the first pixel and the third pixel are read, and the second row of the first pixel and the third pixel disposed in the odd-numbered columns of the second row and the sixth row in the fourth horizontal period. Green sub-pixels Gb1 and Gb3 may be read. Also, in the fifth horizontal period, the first green sub-pixels Gr2 and Gr4 of the second pixel and the fourth pixel disposed in the even columns of the third row and the seventh row are read, and in the sixth horizontal period, the first green subpixels Gr2 and Gr4 are read. Red sub-pixels R2 and R4 of the second pixel and the fourth pixel disposed in odd columns of row 3 and row 7 are read, and are disposed in even columns of row 4 and row 8 in the seventh horizontal period. The blue sub-pixels B2 and B4 of the second and fourth pixels are read, and the second and fourth pixels of the second and fourth pixels are arranged in odd columns of the fourth and eighth rows in the eighth horizontal period. Green sub-pixels Gb2 and Gb4 may be read.

When the CIT is set to 4 or more, among two adjacent pixels (eg, the first pixel PX1 and the second pixel PX2 , or the third pixel PX3 and the fourth pixel PX4 ) connected to the same column line. Four sub-pixels may be sequentially read from one pixel, and then four sub-pixels may be sequentially read from another pixel.

13 is a timing diagram illustrating resetting and reading according to a change in an exposure time set value in an image sensor according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13 , CIT may be set to 8 for the first frame period. A first reset may be sequentially performed on a plurality of rows of the pixel array ( 110 in FIG. 1 ) from the shutter frame period, and a first read may be sequentially performed on a plurality of rows during the first frame period. Here, the first reset and the first read means reset and read of subpixels performed based on the recalculated row address generated by the first address recalculation circuit ( 145 in FIG. 11 ). In the first frame, subpixels may be read according to the third pattern as described with reference to FIG. 8D.

CIT may be changed to 1, and accordingly, a second reset may be performed from the first frame period, and a second read may be performed in the second frame period. Here, the second reset and the second read refer to reset and read of subpixels performed based on the recalculated row address generated by the second address recalculation circuit ( 146 in FIG. 11 ). In the second frame, subpixels may be read according to the first pattern as described with reference to FIG. 8A .

CIT may be changed to 2, and accordingly, a first reset may be performed from the second frame period, and a first read may be performed from the third frame period. In the third frame period, as described with reference to FIG. 8B , subpixels may be read according to the second pattern.

When CIT is changed to 12, a second reset may be performed from the third frame period and a second read may be performed from the fourth frame period. Subpixels may be read according to the third pattern in the fourth frame period.

The timing generator (140 in FIG. 1) includes two sets of address generation circuits (e.g., a first address generation circuit (143 in FIG. 11) and a second address recalculation circuit (145 in FIG. 11) and a second address generation circuit. (144 in FIG. 11) and a second address recalculation circuit (146 in FIG. 11), and when the CIT is changed, by using two sets of address generation circuits alternately, the changed CIT is immediately applied to the next frame. can Accordingly, even if the CIT is changed, it is possible to prevent a dead frame from occurring.

14 is a block diagram schematically illustrating an electronic device including an image sensor according to an exemplary embodiment of the present disclosure.

Referring to FIG. 14 , the electronic device 1000 may include an image sensor 1100, an application processor (AP) 1200, and an illuminance sensor 1300.

The application processor 1200 may provide control signals for controlling the operation of the image sensor 1100 to the image sensor 1100 . Transmission of control signals may be performed based on an interface based on, for example, I2C. The control signals may include an exposure time setting value, eg CIT. The control signals may further include configuration data of the image sensor 1100 such as a lens shading correction value, a crosstalk coefficient, a gain, and the like.

The image sensor 1100 may generate image data IDT by capturing an image of the object based on the received control signals. The image data IDT may include still images and moving images. The image sensor 1100 may perform signal processing such as image quality compensation, binning, downsizing, etc. on the image data IDT, and image quality compensation may include, for example, black level compensation, lens shading compensation, crosstalk compensation, and bad signal processing. It may include signal processing such as pixel correction.

The image sensor 1100 may transmit image data IDT or signal-processed image data to the application processor 1200 . Transmission of the image data IDT may be performed using, for example, a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but embodiments are not limited thereto.

The application processor 1200 performs bad pixel correction, 3A adjustment (auto-focus correction, auto-white balance, auto-exposure), noise reduction, and sharpening on the received image data (IDT). Image processing such as sharpening, gamma control, remosaic, demosaic, resolution scaling (video/preview), and high dynamic range (HDR) processing can be performed.

The illuminance sensor 1300 may sense ambient illuminance of the electronic device 1000 and generate illuminance information IF_L. The illuminance information IF_L may include an illuminance value.

According to an exemplary embodiment of the present disclosure, the application processor 1200 receives illumination information IF_L on ambient illumination of the electronic device 1000 from an external illumination sensor, and sets an exposure time based on the illumination information IF_L. Values such as CIT can be adjusted. For example, the application processor may change the CIT for each frame based on the illuminance information IF_L. As another example, the application processor may change the CIT whenever the illuminance value included in the illuminance information IF_L changes beyond a certain range, and if the illuminance is dark, the CIT is set large to increase the exposure time, and the illuminance is bright. By setting the ground CIT small, the exposure time can be reduced.

The application processor 1200 transmits an exposure time setting value, for example, CIT, to the image sensor 1100 as a control signal, and the exposure time setting value may be stored in the register bank 141 .

As described with reference to FIGS. 11 to 12C , the exposure time setting value is a reset timing signal from the timing controller 140 and a recalculated row address (eg, a first recalculated row address RR_ADD_0 and a second recalculated row address). It can be used to generate a row address (RR_ADD_1). The exposure time of the plurality of rows of the pixel array (110 in FIG. 1) may be set according to the exposure time setting value, the reset order and read order of the plurality of rows of the pixel array 110, and the reset time and read timing can be determined.

The image sensor 100 described with reference to FIGS. 1 to 13 may be applied to the image sensor 1100 . The pixel array has a shared pixel structure, and the reset and read order of a plurality of subpixels of two adjacent pixels in the column direction can be changed (adjusted) according to the exposure time setting value, and the subpixel of the first pixel is read. A subpixel of the second pixel may be reset during the horizontal period, and another subpixel of the first pixel may be reset during the horizontal period during which the subpixel of the second pixel is read. By alternately resetting subpixels and reading subpixels in at least one horizontal period between the first pixel and the second pixel, restrictions on exposure time setting are eliminated and minimum exposure time setting is possible. Accordingly, a dynamic range of the image sensor 1100 may be increased even in an ultra-high luminance environment.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

100: image sensor 110: pixel array
120: low decoder 130: analog-to-digital conversion circuit
140: timing controller 150: image conversion circuit
160: memory 170: image signal processor

Claims (20)

A first pixel and a second pixel connected to the same column line, wherein the first pixel includes N subpixels (N is a positive integer greater than or equal to 2) sharing a first floating diffusion node; a pixel array, wherein 2 pixels include N sub-pixels sharing a second floating diffusion node;
a timing generator for changing a reset order and a read order of 2N subpixels included in the first pixel and the second pixel according to an exposure time set value, and outputting a row address according to the changed order; and
and a row driver driving the pixel array based on the row address. The method of claim 1, wherein the timing generator,
In a first horizontal period, a first sub-pixel of the first pixel is read and a second sub-pixel of the second pixel is reset;
In a second horizontal period, the reset order and the read order of the 2N subpixels are changed such that the second subpixel of the second pixel is read and the third subpixel of the first pixel is reset. , an image sensor. According to claim 1,
The first pixel is
a first reset transistor providing a reset voltage to the first floating diffusion node in response to a first reset signal having an active level;
a first driving transistor configured to generate a first pixel signal corresponding to a potential of the first floating diffusion node; and
a first selection transistor configured to output the first pixel signal to the column line in response to a first selection signal having an active level;
When a sub-pixel of the first pixel is reset, the first select transistor is turned off in response to the first select signal at an inactive level. According to claim 3,
When the sub-pixel of the first pixel is read, the first select transistor is turned on in response to the first select signal at an active level, and the first reset transistor is turned on in response to the first reset signal at an inactive level. An image sensor, characterized in that it is turned off in response. According to claim 1,
In a first horizontal period, a first sub-pixel of the first pixel is read and a first sub-pixel of the second pixel is reset;
In a second horizontal period, the second sub-pixel of the second pixel is read and the third sub-pixel of the first pixel is reset. 6. The method of claim 5, after the second sub-pixel of the second pixel is reset and before the second sub-pixel of the second pixel is read, the fourth to second pixels provided in the first pixel and the second pixel are read. An image sensor, characterized in that a maximum of two sub-pixels among the fifth sub-pixels are reset. According to claim 5,
When the exposure time setting value has a first value, the second horizontal period is continuous with the first horizontal period. According to claim 5,
When the exposure time setting value has a second value, in a third horizontal period between the first horizontal period and the second horizontal period, a fourth sub-pixel of the first pixel is read, and Characterized in that the fifth sub-pixel is reset, the image sensor. According to claim 5,
When the exposure time setting value has a third value, in a third horizontal period following the first horizontal period, the fourth sub-pixel of the first pixel is reset and the fifth sub-pixel of the second pixel is read. and in a fourth horizontal period following the third horizontal period, a sixth sub-pixel of the first pixel is read and a seventh sub-pixel of the second pixel is reset;
The image sensor according to claim 1 , wherein the second horizontal period is consecutive to the fourth horizontal period. The method of claim 1, wherein the timing generator,
a register for storing the exposure time setting value and a set of tuning values corresponding to the plurality of exposure time setting values; and
A recalculated row according to a reset order and a read order of the 2N subpixels changed by generating a reference address based on the exposure time setting value and applying a set of tuning values corresponding to the exposure time setting value to the reference address An image sensor comprising an address generating circuit for generating an address. 11. The method of claim 10, wherein the timing generator,
receiving from the register a set of first exposure time setting values and first tuning values corresponding to a first frame and a set of second exposure time setting values and second tuning values corresponding to a second frame, and an update timing signal In response to, further comprising a double buffer for transmitting the set of the first exposure time setting value and the first tuning value or the set of the second exposure time setting value and the second tuning value to the address generation circuit. characterized by an image sensor. According to claim 1,
and an image data conversion circuit configured to store image data generated according to pixel signals output from the pixel array in a line buffer and convert the image data into Bayer pattern image data. According to claim 1,
The N sub-pixels are arranged in a 2×2 matrix. According to claim 13,
Two sub-pixels arranged in a first diagonal direction convert optical signals of different frequency bands into electrical signals;
The image sensor, characterized in that the other two sub-pixels disposed in the second diagonal direction convert optical signals of the same frequency band into electrical signals. a pixel array including a plurality of pixels arranged in rows and columns, wherein each of the plurality of pixels includes N sub-pixels (N is an integer greater than or equal to 2) sharing a floating diffusion node;
2N subpixels provided in a first pixel and a second pixel adjacent in a column direction are sequentially read, and in a first horizontal period, a first subpixel of the first pixel is read and a second subpixel of the second pixel is read. Set the reset order and read order of the 2N subpixels to the exposure time so that a pixel is reset, the second subpixel of the second pixel is read out, and the third subpixel of the first pixel is reset in a second horizontal period. a timing generator that sets according to values; and
and a row driver configured to drive the pixel array according to a reset order and a read order of the 2N subpixels based on the row address provided from the timing generator. The method of claim 15, when the exposure time setting value is set to a first value,
The image sensor, characterized in that the second horizontal period is continuous with the first horizontal period. The method of claim 15, when the exposure time setting value is set to a second value,
In a third horizontal period between the first horizontal period and the second horizontal period, a fourth subpixel of the first pixel is read and a fifth subpixel of the second pixel is reset. sensor. an image sensor including a pixel array including a plurality of pixels and generating image data based on an optical signal received by the pixel array; and
An application processor configured to generate an exposure time setting value based on illumination information indicating ambient illumination and transmit the exposure time setting value to the image sensor;
The plurality of pixels include a first pixel and a second pixel connected to the same column line, and each of the first pixel and the second pixel includes subpixels sharing a floating diffusion node;
The electronic device characterized in that the reset order and the read order of the plurality of sub-pixels of the first pixel and the second pixel are changed according to the exposure time setting value. According to claim 18,
The image sensor,
a register bank for storing the exposure time setting value, and further comprising a timing generator for determining a reset and read order of the plurality of subpixels of the first pixel and the second pixel based on the exposure time setting value. , electronic devices. The method of claim 18, wherein the image sensor,
In a first period, a first sub-pixel of the first pixel is read and a second sub-pixel of the second pixel is reset;
and determining a reset and read order of the plurality of subpixels such that the second subpixel of the second pixel and the third subpixel of the first pixel are reset during a second period. .