CN116489523A

CN116489523A - Image sensor and electronic device including the same

Info

Publication number: CN116489523A
Application number: CN202310080228.5A
Authority: CN
Inventors: 稻田贵彦; 元东昱; 全贤真; 白在钦
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-01-21
Filing date: 2023-01-18
Publication date: 2023-07-25

Abstract

An image sensor and an electronic device including the image sensor are provided. The image sensor includes: a pixel array including a first pixel and a second pixel connected to the same column line, the first pixel including N sub-pixels sharing a first floating diffusion node, and the second pixel including N sub-pixels sharing a second floating diffusion node, wherein N is a positive integer greater than or equal to two; a timing generator configured to change a reset order and a readout order of 2N sub-pixels included in the first pixel and the second pixel according to the exposure time setting value, and output a row address according to the changed order; and a row driver configured to drive the pixel array based on the row address.

Description

Image sensor and electronic device including the same

The present application is based on and claims priority of korean patent application No. 10-2022-0009234, which was filed on 1 month 21 of 2022, and korean patent application No. 10-2022-0107159, which was filed on 25 months 2022, which is incorporated herein by reference in its entirety.

Technical Field

The inventive concept relates to an image sensor, and more particularly, to an image sensor having an extended dynamic range and a method of operating the same.

Background

An image sensor is a device that captures a two-dimensional or three-dimensional image of an object. The image sensor generates an image of an object by using a photoelectric conversion element that reacts according to the intensity of light reflected by the object. As progress has been made in Complementary Metal Oxide Semiconductor (CMOS) technology, CMOS image sensors using CMOS are widely used. Further, as the resolution of image sensors has recently increased, image sensors having both reduced pixel size and increased dynamic range are required.

Disclosure of Invention

The inventive concept provides a method of reading a pixel array, whereby an exposure time of a pixel array having a shared pixel structure can be reduced.

According to some aspects of the inventive concept, there is provided an image sensor including: a pixel array including a first pixel and a second pixel connected to the same column line, the first pixel including N sub-pixels sharing a first floating diffusion node, and the second pixel including N sub-pixels sharing a second floating diffusion node, wherein N is a positive integer greater than or equal to two; a timing generator configured to change a reset order and a readout order of 2N sub-pixels included in the first pixel and the second pixel according to the exposure time setting value, and output a row address according to the changed order; and a row driver configured to drive the pixel array based on the row address.

According to another aspect of the inventive concept, there is provided an image sensor including: a pixel array including a plurality of pixels arranged in a matrix, each of the plurality of pixels including N sub-pixels sharing a floating diffusion node, wherein N is an integer greater than or equal to 2; a timing generator configured to set a reset order and a readout order of the 2N sub-pixels according to the exposure time setting value such that: while 2N sub-pixels disposed in the first and second pixels adjacent in the column direction are sequentially read out, in the first horizontal period, the first sub-pixel of the first pixel is read out and the second sub-pixel of the second pixel is reset, and in the second horizontal period, the second sub-pixel of the second pixel is read out and the third sub-pixel of the first pixel is reset; and a row driver configured to drive the pixel array based on the row address supplied from the timing generator according to the reset order and the readout order of the 2N sub-pixels.

According to some aspects of the inventive concept, there is provided an electronic device including: an image sensor including a pixel array including a plurality of pixels, and configured to generate image data based on optical signals received by the pixel array; and an application processor configured to generate an exposure time setting value based on illuminance information indicating ambient illuminance and to transmit the exposure time setting value to the image sensor, wherein the plurality of pixels includes a first pixel and a second pixel connected to the same column line, and the first pixel and the second pixel each include a plurality of sub-pixels sharing a floating diffusion node, and a reset order and a readout order of the plurality of sub-pixels of the first pixel and the second pixel are changed according to the exposure time setting value.

Drawings

Example embodiments will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating an image sensor according to some example embodiments;

fig. 2A is a plan view illustrating an example of a pixel array according to some example embodiments, and fig. 2B is a vertical cross-sectional view of a pixel array according to some example embodiments;

fig. 3A and 3B illustrate examples of color patterns of pixel arrays according to some example embodiments;

FIG. 4 is a timing diagram illustrating operation of a rolling shutter of a pixel array according to some example embodiments;

FIG. 5 is a circuit diagram illustrating a pixel and a pixel array according to some example embodiments;

FIG. 6 is a timing diagram of control signals provided to a pixel array according to some example embodiments;

fig. 7 is a timing chart of control signals supplied to the pixel array according to a comparative example;

fig. 8A to 8D illustrate a reset sequence and a readout sequence according to exposure time settings of a pixel array according to some example embodiments;

fig. 9A to 9H illustrate readout sequences of subpixels disposed in a pixel array according to some example embodiments;

FIG. 10 illustrates conversion of image data stored in a line buffer to image data according to a color pattern in an image sensor, according to some example embodiments;

FIG. 11 is a block diagram illustrating a timing generator according to some example embodiments;

fig. 12A to 12C illustrate an address calculation method of a timing generator according to some example embodiments;

fig. 13 is a timing diagram for describing reset and readout according to a change in an exposure time setting value in an image sensor according to some example embodiments; and

fig. 14 is a schematic block diagram of an electronic device including an image sensor, according to some example embodiments.

Detailed Description

Hereinafter, example embodiments of the inventive concepts will be described more fully with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating an image sensor 100 according to some example embodiments.

The image sensor 100 may be installed in an electronic device having an image or light sensing function. For example, the image sensor 100 may be installed in an electronic device, such as a camera, a smart phone, a wearable device, an internet of things (IoT), a tablet Personal Computer (PC), a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a navigation device, and so forth. Further, the image sensor 100 may be mounted in an electronic device provided as a component of a vehicle, furniture, manufacturing equipment, a door, various measuring devices, or the like.

The image sensor 100 may include a pixel array 110, a row driver 120, an analog-to-digital conversion circuit 130 (hereinafter referred to as an "ADC circuit"), a timing controller 140, an image conversion circuit 150, and a memory 160. The image sensor 100 may further include an image signal processor 170.

The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix.

The pixel PX may sense light by using a photoelectric conversion element, and may output an image signal as an electrical signal according to the sensed light. The photoelectric conversion element may include an optical sensor element (such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode) including an organic material or an inorganic material.

In the pixel array 110 according to some example embodiments, the pixels PX may have a shared pixel structure. The pixels PX may each include a plurality of sub-pixels sharing a floating diffusion node. The sub-pixel may include a photoelectric conversion element and a transfer transistor transferring charges generated in the photoelectric conversion element to a floating diffusion node. As an example, as shown in fig. 3A, the pixels PX may each include four sub-pixels (SPX 11, SPX12, SPX21, and SPX22 of fig. 3) arranged in a 2×2 matrix. However, the inventive concept is not limited thereto, and the pixel PX may include m×n sub-pixels arranged in an m×n matrix or an n×m matrix, where N is a positive integer greater than or equal to 2, and M is a positive integer.

Accordingly, the pixel array 110 may include a plurality of sub-pixel rows, each of which may include a plurality of sub-pixels arranged consecutively in the row direction, or each of which may include a plurality of sub-pixel rows arranged consecutively in the row direction. Hereinafter, in the inventive concept, "row" means a sub-pixel row, and a row composed of pixels (or a row in which pixels are arranged) will be referred to as a "pixel row".

In some example embodiments, two adjacent pixels PX (e.g., PX1 and PX2 and PX3 and PX4 in fig. 3A) in the column direction may be connected to the same column line CL, and a reset order (or referred to as a shutter order) and a readout order of a plurality of sub-pixels included in the two pixels PX may be changed according to an exposure time setting value (i.e., a set exposure time). The two pixels PX may alternately output the pixel signals generated in each sub-pixel. Here, reset (or referred to as reset) of the sub-pixel means reset of the photoelectric conversion element provided in the sub-pixel. Before the exposure time, in order to remove charges generated in a photoelectric conversion element (e.g., photodiode) provided in the subpixel, a transfer transistor connected to the photoelectric conversion element may be turned on to reset the subpixel. When the transfer transistor is turned on, the charge generated in the photoelectric conversion element is transferred to the floating diffusion node, and then (or simultaneously) a reset voltage may be applied to the floating diffusion node to remove the charge. Readout of the sub-pixel may be performed by turning on a transfer transistor during an exposure time to transfer charges generated in a photoelectric conversion element provided in the sub-pixel to a floating diffusion node. The pixel voltage generated in response to the charge transferred to the floating diffusion node may be output to the ADC circuit 130 through a column line connected to the pixel. The exposure time (or referred to as "integration time") may represent a period of time from when the transfer transistor is turned off after the transfer transistor is turned on to reset the sub-pixel to when the transfer transistor is turned on again to read out the sub-pixel.

In a horizontal period in which one pixel PX (e.g., a sub-pixel of a first pixel) among the two pixels PX is read out (e.g., in the first horizontal period), the other pixel PX (e.g., a sub-pixel of a second pixel) may be reset. In the first horizontal period, other sub-pixels of the first pixel are reset or no pixel signal is read out. Further, in a second horizontal period subsequent to the first horizontal period, the pixel signal may be read from a sub-pixel of the second pixel, and another sub-pixel of the first pixel may be reset.

The row driver 120 may drive the pixel array 110. The row driver 120 may decode a row control signal (e.g., a row address) received from the timing controller 140 and select at least one row line RL from among a plurality of row lines RL connected to the pixel array 110 in response to the decoded row control signal. Here, the row control signal may select at least one row among a plurality of rows included in the pixel array 110.

In some example embodiments, the row driver 120 may drive the pixel array 110 in units of two pixel rows. For example, the row driver 120 may receive a row control signal (e.g., a row address) indicating that a plurality of sub-pixels disposed in the first pixel and the second pixel disposed adjacent to each other in the column direction are selected according to a setting order from the timing controller 140, and may select at least one row line from among a plurality of row lines connected to the pixel array 110 based on the row control signal.

The row driver 120 may generate pixel control signals (e.g., a selection signal, a reset signal, and a transfer control signal) provided to each pixel based on the row control signals. The plurality of sub-pixels may be reset and read based on the selection signal, the reset signal, and the transfer control signal.

The pixel array 110 outputs a pixel signal (e.g., a pixel voltage) from each pixel PX included in at least one pixel row selected by a selection signal supplied from the row driver 120. The pixel signal may include a reset signal indicating a voltage level in a state where a floating diffusion node provided in the pixel is reset, and an image signal indicating a voltage level according to an optical signal received by at least one sub-pixel.

The row driver 120 may transmit a control signal for outputting a pixel signal to the pixel array 110, and the pixels PX may operate to output the pixel signal in response to the control signal.

The ADC circuit 130 may convert the pixel signal output from the pixel array 110 into a pixel value as a digital signal. The ADC circuit 130 includes a plurality of analog-to-digital converters (ADCs), and each of the plurality of ADCs may convert a pixel signal into a pixel value by using a Correlated Double Sampling (CDS) method. The pixel signal received through each of the plurality of column lines CL may be converted into a pixel value by a corresponding ADC among the plurality of ADCs.

The memory 160 may include a plurality of line buffers, and a plurality of pixel values generated by the ADC circuit 130 may be stored in the plurality of line buffers in a line unit.

The image conversion circuit 150 may convert the first image data including the plurality of pixel values output from the ADC circuit 130 and stored in the memory 160 into second image data having the same color pattern as the color pattern of the pixel array 110 (e.g., the pattern of the color filter array on the pixel array 110). For example, the pixel array 110 may have a Bayer pattern (Bayer pattern), but as described above, when the reading order of a plurality of sub-pixels provided in two pixels PX in units of two pixels PX is changed, the first image data output from the ADC circuit 130 does not have a Bayer pattern. The image conversion circuit 150 may access the memory 160 to convert the first image data into second image data of the bayer pattern.

The timing controller 140 outputs control signals to each of the row driver 120, the ADC circuit 130, and the image conversion circuit 150, and may control the operation and operation timing of each of the row driver 120, the ADC circuit 130, and the image conversion circuit 150.

In some example embodiments, the timing controller 140 may change (or adjust) the reset order and the readout order of the plurality of sub-pixels disposed in the two adjacent pixels PX in the column direction according to the exposure time setting value, and generate the row address according to the changed order. The timing controller 140 may set the exposure time between reset and readout of the sub-pixels according to the exposure time setting value. Here, the timing controller 140 may change the reset order and the readout order of the plurality of sub-pixels such that the pixel signal is not read out from another sub-pixel included in one pixel or the other sub-pixel is not reset in a horizontal period in which the pixel signal is read out from one sub-pixel included in the same pixel. The timing controller 140 may change the reset order and the readout order of the plurality of sub-pixels such that the sub-pixel of the second pixel is reset in a horizontal period in which the sub-pixel of the first pixel among the two pixels PX is read out. The timing controller 140 may change the reset order and the readout order of the plurality of sub-pixels included in the two pixels PX such that the reset of the sub-pixels and the readout of the sub-pixels are alternately performed in the two pixels PX. As described above, the change in the reset order and the readout order of the plurality of sub-pixels according to the exposure time setting value will be described in detail with reference to fig. 5 to 12C.

The image signal processor 170 may perform various signal processes on the image data (e.g., second image data) supplied from the image conversion circuit 150. For example, the image signal processor 170 may perform signal processing (such as image quality compensation, merging, and/or scaling) on the received image data, and the image quality compensation may include, for example, black level compensation, lens shading compensation, crosstalk compensation, and/or bad pixel correction.

The image data output from the image signal processor 170 may be transmitted to an external processor. For example, the external processor may include a host processor of an electronic device in which the image sensor 100 is installed. For example, the external processor may include an application processor of the mobile terminal. The image sensor 100 may transmit image data to an external processor according to a data communication method based on a setup interface, such as a Mobile Industrial Processor Interface (MIPI).

As described above, according to the image sensor 100 of some example embodiments, the pixel array 110 has a shared pixel structure, and the reset order (or referred to as a "shutter order") and the readout order of a plurality of sub-pixels included in two pixels PX are changed so that the reset of the sub-pixels and the readout of the sub-pixels are alternately performed in two pixels PX in units of two pixels according to the exposure time setting value. As described above, when the reset of the sub-pixel and the readout of the sub-pixel are alternately performed in the two pixels PX, the range of settable exposure times may be increased, and the minimum exposure time may be set. Accordingly, the limitation of exposure time setting due to the shared pixel structure can be overcome, and the dynamic range of the image sensor 100 can be increased even in an ultra-high light environment.

Fig. 2A is a plan view illustrating an example of a pixel array according to some example embodiments, and fig. 2B is a vertical cross-sectional view of a pixel array according to some example embodiments.

Referring to fig. 2A, the pixel array 110 may include a plurality of pixels (e.g., first to fourth pixels PX1, PX2, PX3, and PX 4) arranged in a matrix. Although four pixels are shown for convenience of description, the pixel array 110 may include a greater number of pixels, and the number of pixels may be determined according to the resolution of the pixel array 110.

The first pixel PX1 may include first to fourth sub-pixels SPX11, SPX12, SPX21, and SPX22 sharing the floating diffusion node FD, and the first to fourth sub-pixels SPX11, SPX12, SPX21, and SPX22 may each include a photoelectric conversion element (e.g., a photodiode PD) and a transfer gate TG. The transfer gate TG is a gate of the transfer transistor. In one example, two sub-pixels arranged in a first diagonal direction convert optical signals of different frequency bands into electrical signals, and the other two sub-pixels arranged in a second diagonal direction convert optical signals of the same frequency band into electrical signals. The second to fourth pixels PX2, PX3 and PX4 may have the same structure as the first pixel PX 1.

Sixteen sub-pixels included in the first to fourth pixels PX1, PX2, PX3, and PX4 may be arranged in a 4×4 matrix, and as shown, the sub-pixels may be arranged in the first to fourth rows Row1, row2, row3, and Row 4.

As described with reference to fig. 1, two adjacent pixels (such as first and second pixels PX1 and PX2 and third and fourth pixels PX3 and PX 4) in a second direction (or referred to as a "column direction") (e.g., a Y-axis direction) may be connected to the same column line (CL of fig. 1). The reset order and the readout order of eight sub-pixels included in two pixels (e.g., the first pixel PX1 and the second pixel PX 2) may be changed according to the exposure time setting value. Accordingly, two pixels may alternately output pixel signals generated in the sub-pixels.

A vertical cross-section taken along line A-A' is shown in fig. 2B. Referring to fig. 2B, the pixel array 110 may include a semiconductor substrate 111 (hereinafter, referred to as a "substrate") having a first surface 111B and a second surface 111F facing each other, an incident layer 112 disposed on the first surface 111B of the substrate 111, and a wiring layer 113 (or referred to as a "wiring structure") disposed on the second surface 111F of the substrate 111.

A first Deep Trench Isolation (DTI) DTI1 and a second DTI2 may be disposed in the substrate 111. The first DTI1 may pass through the substrate 111 from the first surface 111B to the second surface 111F. The second dtidi 2 may extend from the first surface 111B toward the second surface 111F, but may be spaced apart from the second surface 111F. The first DTI1 and the second DTI2 can prevent or reduce crosstalk between pixels and between sub-pixels.

The first photoelectric conversion element PD11 may be disposed in the first region AR11 of the first subpixel SPX1, and the second photoelectric conversion element PD12 may be disposed in the second region AR12 of the second subpixel SPX 2.

The first surface 111B of the substrate 111 may be an incident surface of light, and the light may be incident through the incident layer 112 and the first surface 111B. The incident layer 112 may include micro-lenses ML and color filters CF. In some example embodiments, the anti-reflection layer AF may be disposed between the first surface 111B of the substrate 111 and the color filter CF.

The color filter CF may transmit light of a specific frequency band (i.e., light of a specific color). The plurality of color filters CF may configure a color filter array. In some example embodiments, the color filter array may have a bayer pattern. However, the inventive concept is not limited thereto, and the color filter array may have different arrangements. The plurality of color filters may include a red filter, a blue filter, and two green filters, and the red filter, the blue filter, and the two green filters may be arranged in a 2×2 matrix, wherein the two green filters may be diagonally arranged. In some example embodiments, the plurality of color filters CF may include a 2×2 arrangement of red, blue, green, and white filters. In some example embodiments, the plurality of color filters CF may include a 2×2 arrangement of red filters, two yellow filters, and a blue filter, and the two yellow filters may be diagonally arranged. However, the inventive concept is not limited thereto, and the plurality of color filters may include filters combined with different colors. For example, the plurality of color filters may include a yellow filter, a cyan filter, and a green filter.

The first color filter CF1 may be disposed on the first subpixel SPX11, and the second color filter CF2 may be disposed on the second subpixel SPX 12. The first and second color filters CF1 and CF2 may transmit light of the same color or different colors. The color detectable by the corresponding sub-pixel (the first sub-pixel SPX11 or the second sub-pixel SPX 12) may be determined according to the color of the light transmitted by the color filter CF.

The floating diffusion FD may be formed adjacent to the second surface 111F of the substrate 111 and may be located at a center between the sub-pixels (e.g., the first sub-pixel SPX11 and the second sub-pixel SPX 12). The floating diffusion FD may be a region doped with an impurity of the second conductivity type.

Gates of the transistors (e.g., a first transfer gate TG11 and a second transfer gate TG 12) may be formed in the wiring layer 113 adjacent to the second surface 111F of the substrate 111. A well region (not shown) may be formed around the first and second transfer gates TG11 and TG 12. The well region may be formed in the substrate 111 adjacent to the second surface 111F. The well region may serve as the drain and source of the transistor. The first and second transfer gates TG11 and TG12 may be formed adjacent to the floating diffusion FD. As shown, the first and second transfer gates TG11 and TG12 may share the floating diffusion node FD.

Fig. 3A and 3B illustrate examples of color patterns of pixel arrays according to some example embodiments.

Referring to fig. 3A, the pixel array (110 of fig. 1) may have a bayer pattern. The bayer pattern may represent a pattern in which pixels are arranged such that green is 50% and red and blue are each 25% to suit human visual characteristics. The plurality of pixels (e.g., first to fourth pixels PX1, PX2, PX3, and PX 4) included in the pixel array 110 may each include first to fourth sub-pixels SPX11, SPX12, SPX21, and SPX22 arranged in a 2×2 matrix. Each of the first to fourth pixels PX1, PX2, PX3, and PX4 may include a first green sub-pixel Gr, a red sub-pixel R, a blue sub-pixel B, and a second green sub-pixel Gb. As described with reference to fig. 2B, the color of the sub-pixel may be determined by the color of light transmitted by the color filter disposed above each sub-pixel (e.g., by the frequency band of the light signal transmitted by the color filter).

Referring to fig. 3B, the pixel array 110 may have a quad pattern (tetra pattern). Each of the first to fourth pixels PX1, PX2, PX3, and PX4 arranged in a 2×2 matrix may include first to fourth sub-pixels SPX11, SPX12, SPX21, and SPX22 each having the same color. The first pixel PX1 may include four first green sub-pixels Gr, the second pixel PX2 may include four blue sub-pixels B, the third pixel PX3 may include four red sub-pixels R, and the fourth pixel PX4 may include four second green sub-pixels Gb.

Fig. 4 is a timing diagram illustrating operation of a rolling shutter of a pixel array according to some example embodiments.

Referring to fig. 4, the pixel array (110 of fig. 1) may operate according to a rolling shutter method. The pixel array 110 may include a plurality of rows (e.g., a first row R0 to a 4 m-th row R4m-1 (m is a positive integer)), and each of the plurality of rows may include a plurality of sub-pixels. The first to 4 m-th rows R0 to R4m-1 may be sequentially arranged in the pixel array 110. For example, the first row R0 is disposed at a topmost (or bottommost) portion in the pixel array 110, and the 4 m-th row R4m-1 may be disposed at a bottommost (or topmost) portion in the pixel array 110.

In some example embodiments, a plurality of sub-pixels disposed in a plurality of rows may not be simultaneously reset (turned off), but may be sequentially reset in at least one row unit.

For each of the plurality of rows during one frame FRM, a non-integration time NIT, a reset time RST, an exposure time IT (also referred to as an integration time), and a readout time RO may be allocated. The period from the start of the read-out time RO to the start of the next read-out time RO may be defined as one frame FRM. The initial non-integration time NIT, the initial reset time RST, and the initial exposure time IT may be referred to as shutter frames.

The sub-pixel may be reset during the reset time RST. The transfer transistor provided in the subpixel may be turned on to transfer the charge generated in the photodiode to the floating diffusion node during the non-integration time NIT, thereby removing the charge. In some example embodiments, when the transfer transistor of the sub-pixel is turned on while the reset voltage is applied to the floating diffusion node, the floating diffusion node and the sub-pixel may be reset together. During the exposure time IT, charges according to the optical signal may be generated and accumulated in photodiodes provided in the sub-pixels. The sub-pixels may be read out during a read out time RO. In other words, the transfer transistor provided in the subpixel may be turned on during the readout time RO such that the charge accumulated in the photodiode during the exposure time IT is transferred to the floating diffusion node, and the pixel voltage corresponding to the transferred charge is output through the column line (CL in fig. 1).

As described with reference to fig. 3A and 3B, two adjacent pixels in the column direction may also be arranged in four rows. In other words, the two pixel rows may include four rows (e.g., four sub-pixel rows). The resetting and readout of the sub-pixels may be performed alternately with respect to the two pixels. Accordingly, as shown in fig. 4, the reset time RST, the exposure time IT, the readout time RO, and the non-integration time NIT may sequentially start in four adjacent row units, respectively, according to an arrangement order in which a plurality of rows (e.g., the first row R0 to the 4 th m row R4 m-1) are arranged in the pixel array 110. The order in which the reset time (RST), the exposure time (IT), the readout time (RO), and the non-integration time (NIT) of each row are respectively stated in the four rows is not in accordance with the order in which the four rows are arranged, but may be changed according to the exposure time setting value.

Although an example in which two pixels are arranged in four rows is described with reference to fig. 4, the inventive concept is not limited thereto, and when the pixels include sub-pixels arranged in an n×n matrix, the two pixels may be arranged in 2N rows, and the order in which the reset time RST, the exposure time IT, the readout time RO, and the non-integration time NIT of each row starts within 2N rows may be changed according to the exposure time setting value.

FIG. 5 is a circuit diagram illustrating a pixel and a pixel array according to some example embodiments; for convenience of description, the first pixel PX1 and the second pixel PX2 connected to the same column line CL are shown.

Referring to fig. 5, the first pixel PX1 may include first to fourth photoelectric conversion elements PD11, PD12, PD21, and PD22, first to fourth transfer transistors TX11, TX12, TX21, and TX22 connected to the first to fourth photoelectric conversion elements PD11, PD12, PD21, and PD22, respectively, a reset transistor RX1, a driving transistor DX1, and a selection transistor SX1. One photoelectric conversion element and one transfer transistor may constitute one sub-pixel. Accordingly, the first pixel PX1 may include four sub-pixels. The four sub-pixels may share the floating diffusion node FD1, the reset transistor RX1, the driving transistor DX1, and the selection transistor SX1.

The pixel control signals (e.g., first to fourth transfer control signals TS11, TS12, TS21 and TS22, a reset signal RS1 and a selection signal SEL 1) received through the row line RL may be applied to gates of the first to fourth transfer transistors TX11, TX12, TX21 and TX22, the reset transistor RX1 and the selection transistor SX1, respectively.

The reset transistor RX1 may be turned on in response to the reset signal RS1 to apply the power supply voltage VDDP as a reset voltage to the floating diffusion node FD1, thereby resetting the floating diffusion node FD1. In other words, the reset transistor RX1 may be turned on to remove the charge accumulated in the floating diffusion node FD1.

The driving transistor DX1 may generate a pixel signal (e.g., a pixel voltage) corresponding to the potential of the floating diffusion node FD1. During the readout time of the first pixel PX1, the selection transistor SX1 may be turned on in response to the selection signal SEL1 to transmit the pixel signal to the column line CL. In detail, the selection transistor SX1 may be turned on during a readout time of each of the four sub-pixels included in the first pixel PX1 to output an image signal corresponding to the reset level of the floating diffusion FD1 in the reset state and the charge generated in the corresponding sub-pixel as a pixel signal to the column line CL. The pixel signal corresponding to the reset level of the floating diffusion FD1 may be output to the column line CL before the transfer transistor of the corresponding sub-pixel is turned on during the readout time, and the pixel signal corresponding to the image signal may be output as the pixel signal when the transfer transistor is turned on and then turned off. The first to fourth transfer transistors TX11, TX12, TX21 and TX22 may be turned on to reset the first to fourth photoelectric conversion elements PD11, PD12, PD21 and PD22, respectively, in response to the first to fourth transfer control signals TS11, TS12, TS21 and TS22 having an active level (e.g., logic high) before the exposure time, and may be turned on to transmit charges generated in the first to fourth photoelectric conversion elements PD11, PD12, PD21 and PD22 to the floating diffusion node FD1 during the exposure time in response to the first to fourth transfer control signals TS11, TS12, TS21 and TS22 having an active level after the exposure time. Here, the times when the first to fourth transfer control signals TS11, TS12, TS21, and TS22 have the active levels (i.e., the times when the first to fourth transfer transistors TX11, TX12, TX21, and TX22 are turned on) may be different from each other.

The second pixel PX2 may include first to fourth photoelectric conversion elements PD31, PD32, PD33, and PD34, fifth to eighth transfer transistors TX31, TX32, TX41, and TX42 connected to the first to fourth photoelectric conversion elements PD31, PD32, PD33, and PD34, respectively, a reset transistor RX2, a driving transistor DX2, and a selection transistor SX2. Control signals (e.g., fifth to eighth transfer control signals TS31, TS32, TS41, and TS42, a reset signal RS2, and a selection signal SEL 2) for driving the pixels received through the row line RL may be applied to gates of the fifth to eighth transfer transistors TX31, TX32, TX41, and TX42, the reset transistor RX2, and the selection transistor SX2. Since the configuration and operation of the second pixel PX2 are the same as those of the first pixel PX1, the repeated description will be omitted.

The first pixel PX1 and the second pixel PX2 have a shared pixel structure in which a plurality of sub-pixels share the floating diffusion node FD1 or the floating diffusion node FD 2. When the rolling shutter method is applied to the pixel array 110 having the shared pixel structure as described above, during a horizontal period in which one sub-pixel is read from within the same pixel, other sub-pixels cannot be reset or read into the other sub-pixels. Accordingly, there may be a limit to the setting of the minimum exposure time of the pixel array 110.

However, in the image sensor (100 of fig. 1) according to some example embodiments, two pixels (e.g., a first pixel PX1 and a second pixel PX 2) connected to one column line CL may operate as one readout unit, and in order for the first pixel PX1 and the second pixel PX2 to alternately perform a reset operation of the sub-pixels and a readout operation of the sub-pixels, a reset order and a readout order of eight sub-pixels included in the first pixel PX1 and the second pixel PX2 may be changed according to an exposure time set value. Thus, the minimum exposure time may be set (or, alternatively, the minimum exposure time may be determined or desired with respect to the above method). This will be described in detail with reference to fig. 6 to 8D.

Fig. 6 is a timing diagram of control signals provided to a pixel array according to some example embodiments.

The exposure time setting value (e.g., coarse Integration Time (CIT)) is set to 2, and thus, a time corresponding to about two horizontal periods may be set as the exposure time. Here, the horizontal period is a period in which a pixel signal output from the pixel array (110 of fig. 1) is converted into a pixel value as a digital signal, and can be distinguished by the horizontal synchronization signal HD. For example, a period from a rising edge of the horizontal synchronization signal HD to a next rising edge of the horizontal synchronization signal HD may be defined as one horizontal period. For example, the horizontal synchronization signal HD may be generated by a timing controller (140 of fig. 1) and provided to the ADC circuit (130 of fig. 1) and the row driver 120.

Referring to fig. 5 and 6, in the first and second horizontal periods 1H and 2H, the first and second selection signals SEL1 and SEL2 have an inactive level (e.g., logic low), and the first and second reset signals RS1 and RS2 may have an active level (e.g., logic high). Accordingly, the selection transistors SX1 and SX2 of the first and second pixels PX1 and PX2 may be turned off, and the reset transistors RX1 and RX2 may be turned on.

In the first horizontal period 1H, the pulse signal may be applied to the first transfer transistor TX11 as the first transfer control signal TS11, and thus, the first subpixel (specifically, the first photoelectric conversion element PD 11) of the first pixel PX1 may be reset. The pulse signal may be referred to as a reset control signal.

In the second horizontal period 2H, a pulse signal (i.e., a reset control signal) may be applied to the second transfer transistor TX12 as the second transfer control signal TS12, and thus, the second sub-pixel of the first pixel PX (specifically, the second photoelectric conversion element PD 12) may be reset.

In the third horizontal period 3H and the fourth horizontal period 4H, the second reset signal RS2 may have an inactive level, and thus, the reset transistor RX1 of the first pixel PX1 may be turned off. The first selection signal SEL1 of an active level may be applied to the selection transistor SX1 of the first pixel PX1, and a pixel signal from the first pixel PX1 may be supplied to the column line CL when the selection transistor SX1 is turned on.

In the third horizontal period 3H, the first sub-pixel of the first pixel PX1 may be read out. The pulse signal may be applied to the first transfer transistor TX11 as the first transfer control signal TS11 to turn on the first transfer transistor TX11. The pulse signal may be referred to as a read control signal. The electric charges generated and accumulated in the first photoelectric conversion element PD11 may be supplied to the floating diffusion node FD1 after being turned off in the first horizontal period 1H from the first transfer transistor TX11 and until an exposure time in which the first transfer transistor TX11 is turned on again in the third horizontal period 3H, and a pixel signal corresponding to the electric potential of the floating diffusion node FD1, that is, a pixel signal (e.g., an image signal) from the first sub-pixel may be output to the column line CL. Although not shown, the reset level of the floating diffusion FD1 may be output as a pixel signal to the column line CL before the first transfer transistor TX11 is turned on, and also when other sub-pixels are read out, the reset level of the floating diffusion connected to the sub-pixel may be output as a pixel signal to the column line CL before the corresponding transfer transistor is turned on.

As shown in fig. 6, when the pulse signal having the active level may be supplied as the first reset signal RS1 to the reset transistor RX11 of the first pixel PX1 at the end of the third horizontal period 3H and/or at the beginning of the fourth horizontal period 4H, the floating diffusion node FD1 of the first pixel PX1 may be reset. Thereafter, the second sub-pixel of the first pixel PX1 may be read out in the fourth horizontal period 4H. When the pulse signal is applied to the second transfer transistor TX12 as the second transfer control signal TS12 to turn on the second transfer transistor TX12, the pixel signal of the second sub-pixel may be read out. The charges generated and accumulated in the second photoelectric conversion element PD12 may be supplied to the floating diffusion node FD1 after being turned off in the second horizontal period 2H from the second transfer transistor TX12 and until an exposure time in which the second transfer transistor TX12 is turned on again in the fourth horizontal period 4H, and a pixel signal corresponding to the potential of the floating diffusion node FD1 (i.e., a pixel signal from the second sub-pixel) may be output to the column line CL.

Hereinafter, the description of the reset and readout of the first subpixel of the first pixel PX1 and the second subpixel of the first pixel PX1 provided above may be applied to the reset and readout of other subpixels. The exposure time of each sub-pixel may be a period from when the corresponding transfer transistor is turned on to reset the sub-pixel and then turned off to when the transfer transistor is turned on again to read out the sub-pixel, and the exposure times of the plurality of sub-pixels are substantially equal.

Meanwhile, in the third horizontal period 3H, the pulse signal may be applied to the fifth transfer transistor TX31 as the fifth transfer control signal TS31, and thus, the fifth subpixel (specifically, the fifth photoelectric conversion element PD 31) of the second pixel PX2 may be reset. Further, in the fourth horizontal period 4H, the pulse signal may be applied to the sixth transfer transistor TX32 as the sixth transfer control signal TS32, and thus, the sixth subpixel (specifically, the sixth photoelectric conversion element PD 32) of the second pixel PX2 may be reset.

In the fifth and sixth horizontal periods 5H and 6H, the first and second selection signals SEL1 and RS2 may have an inactive level, and the second selection signals SEL2 and RS1 may have an active level. Accordingly, the selection transistor SX2 of the second pixel PX2 may be turned on, and the pixel signal from the second pixel PX2 may be supplied to the column line CL. In the fifth horizontal period 5H, the pulse signal may be applied to the fifth transfer transistor TX31 as the fifth transfer control signal TS31, and the fifth subpixel of the second pixel PX2 may be read out.

The floating diffusion node FD2 of the second pixel PX2 may be reset when the pulse signal of the active level is supplied as the second reset signal RS2 to the reset transistor RX2 of the second pixel PX2 at the end of the fifth horizontal period 5H and/or at the beginning of the sixth horizontal period 4H. Next, in the sixth horizontal period 6H, the pulse signal may be applied to the sixth transfer transistor TX32 of the second pixel PX2 as the sixth transfer control signal TS32, and the sixth sub-pixel may be read out. In the fifth horizontal period 5H, the pulse signal may be applied to the third transfer transistor TX21 as the third transfer control signal TS21, and thus, the third sub-pixel of the first pixel PX1 (specifically, the third photoelectric conversion element PD 21) may be reset. Further, in the sixth horizontal period 6H, the pulse signal may be applied to the fourth transfer transistor TX22 as the fourth transfer control signal TS22, and thus, the fourth sub-pixel of the first pixel PX1 (specifically, the fourth photoelectric conversion element PD 22) may be reset.

In the seventh horizontal period 7H and the eighth horizontal period 8H, the first selection signal SEL1 and the second reset signal RS2 may have active levels, and the second selection signal SEL2 and the first reset signal RS1 may have inactive levels. Accordingly, the selection signal SEL1 of the active level of the first pixel PX1 may be applied to the selection transistor SX1 of the first pixel PX1 again, and the pixel signal from the first pixel PX1 may be supplied to the column line CL when the selection transistor SX1 is turned on. In the seventh horizontal period 7H, the pulse signal may be applied to the third transfer transistor TX21 as the third transfer control signal TS21, and the third subpixel may be read out.

The floating diffusion node FD1 of the first pixel PX1 may be reset when the pulse signal of the active level is supplied as the first reset signal RS1 to the reset transistor RX21 of the first pixel PX1 at the end of the seventh horizontal period 7H and/or at the beginning of the eighth horizontal period 8H. Thereafter, in the eighth horizontal period 8H, the pulse signal may be applied to the fourth transfer transistor TX22 as the fourth transfer control signal TS22, and the fourth sub-pixel of the first pixel PX1 may be read out.

In the seventh horizontal period 7H, the pulse signal may be applied to the seventh transfer transistor TX41 as the seventh transfer control signal TS41, and thus, the seventh subpixel (specifically, the seventh photoelectric conversion element PD 33) of the second pixel PX2 may be reset. Further, in the eighth horizontal period 8H, the pulse signal may be applied to the eighth transfer transistor TX42 as the eighth transfer control signal TS42, and thus, the eighth subpixel (specifically, the eighth photoelectric conversion element PD 34) of the second pixel PX2 may be reset.

In the ninth horizontal period 9H and the tenth horizontal period 10H, the first selection signal SEL1 and the second reset signal RS2 may have inactive levels, and the second selection signal SEL2 and the first reset signal RS1 may have active levels. Accordingly, the selection transistor SX2 of the second pixel PX2 may be turned on, and the pixel signal from the second pixel PX2 may be supplied to the column line CL. In the ninth horizontal period 9H, the pulse signal may be applied to the seventh transfer transistor TX41 as the seventh transfer control signal TS41, and the seventh subpixel of the second pixel PX2 may be read out.

The floating diffusion node FD2 of the second pixel PX2 may be reset when the pulse signal of the active level may be supplied as the second reset signal RS2 to the reset transistor RX2 of the second pixel PX2 at the end of the ninth horizontal period 9H and/or at the beginning of the tenth horizontal period 10H. Thereafter, in the tenth horizontal period 10H, the pulse signal may be applied to the eighth transfer transistor TX42 as the eighth transfer control signal TS42, and the eighth subpixel of the second pixel PX2 may be read out.

Meanwhile, in some example embodiments of fig. 6, when the sub-pixel is reset, that is, when the transfer transistor provided in the sub-pixel is turned on based on the transfer control signal of the active level, the selection signal having the inactive level and the reset signal having the active level are illustrated. For example, in the first horizontal period 1H, when the first transfer control signal TS11 is at an active level, the first selection signal SEL1 is shown to maintain an inactive level, and the first reset signal RS1 is shown to maintain an active level.

However, the inventive concept is not limited thereto, and in some example embodiments, when a subpixel is reset, a reset signal of an inactive level may be applied to a reset transistor of a pixel disposed in the subpixel to turn off the reset transistor. The charges generated in the photoelectric conversion element of the sub-pixel may be transferred to the floating diffusion node, and the photoelectric conversion element may be reset. Thereafter, after the transfer control signal is transitioned to an inactive level to turn off the transfer transistor, the reset signal may be transitioned to an active level to turn on the reset transistor. Accordingly, a reset voltage may be applied to the floating diffusion node to reset the floating diffusion node.

As described above, the first pixel PX1 and the second pixel PX2 may alternately reset the sub-pixels and read out the sub-pixels, and in the horizontal period (e.g., the third horizontal period 3H, the fourth horizontal period 4H, the seventh horizontal period 7H, and the eighth horizontal period 8H) in which the sub-pixels of the first pixel PX1 are read out, the sub-pixels of the second pixel PX2 may be reset, and in the horizontal period (e.g., the fifth horizontal period 5H, the sixth horizontal period 6H, the ninth horizontal period 9H, and the tenth horizontal period 10H) in which the sub-pixels of the second pixel PX2 are read out, the sub-pixels of the first pixel PX1 may be reset.

Fig. 7 is a timing chart of control signals supplied to the pixel array according to a comparative example.

The exposure time setting value (e.g., CIT) is set to 2, and thus, a time corresponding to about two horizontal periods may be set as the exposure time.

Referring to fig. 7, the sub-pixels of the first pixel PX1 and the second pixel PX2 may be sequentially reset, and the sub-pixels may be sequentially read out. Here, in the third horizontal period 3H, the first transfer transistor TX11 may be turned on in response to a pulse signal (e.g., a readout control signal) of the first transfer control signal TS11, and the first sub-pixel of the first pixel PX1 may be read out. Further, the third sub-pixel of the first pixel PX1 may be reset in response to the pulse signal (e.g., the reset control signal) of the third transfer control signal TS 21. Since the first and second sub-pixels share the floating diffusion node FD1, when the third sub-pixel is reset, the potential of the floating diffusion node FD1 is changed, and thus, when the first sub-pixel is read out, noise may be added to the pixel signal output from the first sub-pixel to the column line CL. Accordingly, the reset of other sub-pixels in the same pixel in the horizontal period in which the sub-pixel is read out (i.e., in the horizontal period in which the pixel signal from the sub-pixel is output) can be inhibited.

As shown in fig. 7, since readout or reset of other sub-pixels is prohibited in a horizontal period in which the sub-pixels are read from the same pixel, when the sub-pixels of the first pixel PX1 and the second pixel PX2 are sequentially reset and the sub-pixels are sequentially read out, the exposure time setting value (e.g., CIT) cannot be set to 3 or less, resulting in limitation of the setting of the exposure time. For example, a time corresponding to about three horizontal periods or less cannot be set as the exposure time, and thus the setting of the minimum exposure period is limited.

However, as described with reference to fig. 6, in the image sensor 100 according to some example embodiments, in order that the first pixel PX1 and the second pixel PX2 may alternately perform a reset operation of the sub-pixels and a readout operation of the sub-pixels, a reset order of eight sub-pixels and a readout order of eight sub-pixels included in the first pixel PX1 and the second pixel PX2 may be changed according to the exposure time setting value. Accordingly, the limitation on setting the exposure time can be overcome, and by setting one horizontal period as the exposure time, the minimum exposure time can be set. Accordingly, the minimum exposure time may be set in the ultra-high light environment, and thus, the dynamic range of the image generated by the image sensor 100 may be extended.

Fig. 8A to 8D illustrate a reset sequence and a readout sequence according to exposure time settings of a pixel array according to some example embodiments.

As described with reference to fig. 3A, it is assumed that the first pixels and the second pixels each including the sub-pixels of the 2×2 matrix having the bayer pattern are arranged in the first to fourth rows. The subpixels of the first pixel may be arranged in a first row and a second row, the first green subpixel Gr1 may be arranged in an even-numbered column of the first row, the red subpixel R1 may be arranged in an odd-numbered column of the first row, the blue subpixel B1 may be arranged in an even-numbered column of the second row, and the second green subpixel Gb1 may be arranged in an odd-numbered column of the second row. The subpixels of the second pixel may be arranged in the third and fourth rows, the first green subpixel Gr2 may be arranged in the even-numbered columns of the third row, the red subpixel R2 may be arranged in the odd-numbered columns of the third row, the blue subpixel B2 may be arranged in the even-numbered columns of the fourth row, and the second green subpixel Gb2 may be arranged in the odd-numbered columns of the fourth row.

Referring to fig. 8A, when CIT for setting an exposure time is set to 1, after a subpixel is reset, the subpixel may be read out in the next horizontal period. Here, readout of a subpixel means outputting a pixel signal from the subpixel to a column line. As described with reference to fig. 6, the exposure time of the sub-pixel may be from a point of time when the transfer transistor is turned off after the transfer transistor of the sub-pixel is turned on to reset the photoelectric conversion element to a point of time when the transfer transistor is turned on again to read out the sub-pixel, and the exposure times of the plurality of sub-pixels may be the same.

In the fourth horizontal period 4H, the first green subpixel Gr1 of the first pixel may be reset. In the fifth horizontal period 5H, the first green subpixel Gr1 of the first pixel may be read out, and the first green subpixel Gr2 of the second pixel may be reset. In the sixth horizontal period 6H, the first green subpixel Gr2 of the second pixel may be read out, and the red subpixel R1 of the first pixel may be reset.

As described above, after being reset, the sub-pixel may be read out in the next horizontal period, and the sub-pixel of the second pixel may be reset in the horizontal period in which the sub-pixel of the first pixel is read out, and the sub-pixel of the second pixel may be read out in the horizontal period in which the sub-pixel of the first pixel is reset.

Referring to fig. 8B, when CIT is set to 2, the sub-pixel may be reset, and the sub-pixel may be read out in a horizontal period after one horizontal period.

The first green subpixel Gr1 of the first pixel may be reset in the third horizontal period 3H, and the red subpixel R1 of the first pixel may be reset in the fourth horizontal period 4H. In the fifth horizontal period 5H, the first green subpixel Gr1 of the first pixel may be read, and the first green subpixel Gr2 of the second pixel may be reset. In the sixth horizontal period 6H, the red subpixel R1 of the first pixel may be read, and the red subpixel R2 of the second pixel may be reset. In the seventh horizontal period 7H, the first green subpixel Gr2 of the second pixel may be read, and the blue subpixel B1 of the first pixel may be reset. In the eighth horizontal period 8H, the red sub-pixel R2 of the second pixel may be read, and the second green sub-pixel Gb2 of the first pixel may be reset.

As described above, after two sub-pixels included in one pixel are sequentially reset, they can be sequentially read out. The sub-pixels of the second pixel may be reset in a horizontal period in which the sub-pixels of the first pixel are read out, and the sub-pixels of the second pixel may be read out in a horizontal period in which the sub-pixels of the first pixel are reset.

Referring to fig. 8C, when CIT is set to 3, the sub-pixel may be reset, and the sub-pixel may be read out in a horizontal period after two horizontal periods.

In the second horizontal period 2H, the first green sub-pixel Gr1 of the first pixel may be reset, and in the third horizontal period 3H, the first green sub-pixel Gr2 of the second pixel may be reset, and in the fourth horizontal period 4H, the red sub-pixel R1 of the first pixel may be reset. In the fifth horizontal period 5H, the first green subpixel Gr1 of the first pixel may be read out, and the red subpixel R2 of the second pixel may be reset. In the sixth horizontal period 6H, the first green subpixel Gr2 of the second pixel may be read out, and the blue subpixel B1 of the first pixel may be reset. In the seventh horizontal period 7H, the red subpixel R1 of the first pixel may be read, and the blue subpixel B2 of the second pixel may be reset.

As described above, the sub-pixel may be reset and read in a horizontal period subsequent to the two horizontal periods. The sub-pixel of the second pixel may be reset in a horizontal period in which the sub-pixel of the first pixel is read out, and the sub-pixel of the second pixel may be read in a horizontal period in which the sub-pixel of the first pixel is reset.

Referring to fig. 8D, when CIT is set to 4, the sub-pixel may be reset, and the sub-pixel may be read out in a horizontal period after three horizontal periods.

In the first to fourth horizontal periods 1H, 2H, 3H and 4H, the first green sub-pixel Gr1, the red sub-pixel R1, the blue sub-pixel B1 and the second green sub-pixel Gb1 of the first pixel may be sequentially reset, and in the fifth to eighth horizontal periods 5H, 6H, 7H and 8H, the first green sub-pixel Gr1, the red sub-pixel R1, the blue sub-pixel B1 and the second green sub-pixel Gb1 of the first pixel may be sequentially read out. In addition, in the fifth to eighth horizontal periods 5H, 6H, 7H and 8H, the first green sub-pixel Gr2, the red sub-pixel R2, the blue sub-pixel B2 and the second green sub-pixel Gb2 of the second pixel may be sequentially reset, and in the ninth to twelfth horizontal periods 9H, 10H, 11H and 12H, the first green sub-pixel Gr2, the red sub-pixel R2, the blue sub-pixel B2 and the second green sub-pixel Gb2 of the second pixel may be sequentially read out.

As described above, when CIT is set to 4 or more, the sub-pixels of the first pixel and the second pixel may be sequentially reset and read.

As described with reference to fig. 8A to 8D, the exposure time may be changed according to CIT, and when CIT is 1, the shortest exposure time may be set, and the exposure time may increase as CIT increases.

Fig. 9A to 9H illustrate readout sequences of subpixels disposed in a pixel array according to some example embodiments.

Referring to fig. 9A to 9H, the sub-pixels of the first and fifth pixels PX1 and PX5 may be arranged in the first and second ROWs Row1 and Row2, and the sub-pixels of the second and sixth pixels PX2 and PX6 may be arranged in the third and fourth ROWs Row3 and Row4, and the sub-pixels of the third and seventh pixels PX3 and PX7 may be arranged in the fifth and sixth ROWs Row5 and Row6, and the sub-pixels of the fourth and eighth pixels PX4 and PX8 may be arranged in the seventh and eighth ROWs Row7 and Row 8.

In some example embodiments, for quick readout, the sub-pixels arranged in two rows may be simultaneously read in one horizontal period, and for this, some pixels (e.g., first pixel PX1 and second pixel PX 2) arranged in the same column may be connected to the first column line CL1, and other pixels (e.g., third pixel PX3 and fourth pixel PX 4) may be connected to the second column line CL2. The pixel signals output from the first pixel PX1 and the second pixel PX2 may be provided to the first ADC1, and the pixel signals output from the third pixel PX3 and the fourth pixel PX4 may be provided to the second ADC2. The fifth pixel PX5 and the sixth pixel PX6 may be connected to the third column line CL3, and the pixel signals output from the fifth pixel PX5 and the sixth pixel PX6 may be provided to the third ADC3. The seventh pixel PX7 and the eighth pixel PX8 may be connected to the fourth column line CL4, and the pixel signals output from the seventh pixel PX7 and the eighth pixel PX8 may be provided to the fourth ADC4. However, the inventive concept is not limited thereto, and the subpixels disposed in one row may be read in one horizontal period, and for this reason, the pixels disposed in the same column may be connected to the same column line.

Fig. 9A to 9B show the readout order of the sub-pixels when CIT is set to 1. Since CIT is set to 1, the sub-pixel read out in each horizontal period may be reset in the previous horizontal period.

Referring to fig. 9A, in the first horizontal period 1H, the first green sub-pixels Gr of the first, third, fifth, and seventh pixels PX1, PX3, PX5, and PX7 are read out. The pixel signals output to the first to fourth column lines CL1, CL2, CL3 and CL4 may be converted into pixel values by the first to fourth ADCs ADC1, ADC2, ADC3 and ADC4, respectively, and stored in a line buffer of a memory (160 of fig. 1).

Subsequently, as shown in fig. 9B, in the second horizontal period 2H, the first green sub-pixels Gr of the second, fourth, sixth, and eighth pixels PX2, PX4, PX6, and PX8 may be read out.

Referring to fig. 9C, in the third horizontal period 3H, the red sub-pixels R of the first, third, fifth and seventh pixels PX1, PX3, PX5 and PX7 may be read.

Referring to fig. 9D, in the fourth horizontal period 4H, the red sub-pixels R of the second, fourth, sixth and eighth pixels PX2, PX4, PX6 and PX8 may be read.

Referring to fig. 9E, in the fifth horizontal period 5H, the blue sub-pixels B of the first, third, fifth and seventh pixels PX1, PX3, PX5 and PX7 may be read.

Referring to fig. 9F, in the sixth horizontal period 6H, the blue sub-pixels B of the second, fourth, sixth and eighth pixels PX2, PX4, PX6 and PX8 may be read.

Referring to fig. 9G, in the seventh horizontal period 7H, the second green sub-pixels Gb of the first, third, fifth and seventh pixels PX1, PX3, PX5 and PX7 may be read out.

Referring to fig. 9H, in the eighth horizontal period 8H, the second green sub-pixels Gb of the second, fourth, sixth and eighth pixels PX2, PX4, PX6 and PX8 may be read out.

Pixel values generated from pixel signals output during the same horizontal period and converted into digital signals may be stored in the same line buffer of the memory 160.

Fig. 10 illustrates conversion of image data stored in a line buffer to image data according to a color pattern in an image sensor according to some example embodiments. For example, the conversion of the image data of fig. 10 may be performed by the image conversion circuit 150 of fig. 1.

As described with reference to fig. 9A to 9H, pixel values corresponding to pixel signals output in a plurality of horizontal periods 1H to 8H from a plurality of sub-pixels provided in a pixel may be stored as first image data IDT1 in line buffers LB1 to LB7 in a memory (160 of fig. 1). For example, the first pixel value p_gr generated in the first and second horizontal periods 1H and 2H may be stored in the first and second line buffers LB1 and LB2, the second pixel value p_r generated in the third and fourth horizontal periods 3H and 4H may be stored in the third and fourth line buffers LB3 and LB4, the third pixel value p_b generated in the fifth and sixth horizontal periods 5H and 6H may be stored in the fifth and sixth line buffers LB5 and LB6, and the fourth pixel value p_gb generated in the seventh and eighth horizontal periods 7H and 8H may be stored in the seventh and eighth line buffers LB7 and LB 8. Here, the first pixel value p_gr may be a pixel value corresponding to a first green sub-pixel (Gr in fig. 9A), the second pixel value p_r may be a pixel value corresponding to a red sub-pixel (R in fig. 9A), the third pixel value p_b may be a pixel value corresponding to a blue sub-pixel (B in fig. 9A), and the fourth pixel value p_gb may be a pixel value corresponding to a second green sub-pixel (Gb in fig. 9A).

The image signal processor (170 of fig. 1) may perform signal processing on image data of a specific color pattern (e.g., bayer pattern). Accordingly, the image conversion circuit 150 can access the memory 160 to convert the first image data IDT1 into the second image data IDT2 having the bayer pattern.

Fig. 11 is a block diagram illustrating a timing generator according to some example embodiments.

Referring to fig. 11, the timing controller 140 may include a register bank 141, a buffer 142, a first address generation circuit (or address generation circuit 1) 143, a second address generation circuit (or address generation circuit 2) 144, a first address recalculation circuit (address recalculation circuit 1) 145, a second address recalculation circuit (address recalculation circuit 2) 146, and an address output circuit 147. The first address generating circuit 143, the second address generating circuit 144, the first address recalculating circuit 145, the second address recalculating circuit 146, and the address outputting circuit 147 may be implemented in hardware or a combination of hardware and software.

The register bank 141 may store a set of exposure time setting values (e.g., CIT) and a plurality of adjustment values corresponding to the plurality of exposure time setting values. The exposure time setting value may be stored in the register bank 141. The set of the plurality of adjustment values may be preset to correspond to the respective exposure time setting values and stored in the register bank 141.

The exposure time setting value may be provided from an external processor (e.g., an application processor) in communication with the image sensor (100 in fig. 1), and may be changed in each frame according to the ambient illuminance of the image sensor 100, or each time the ambient illuminance changes beyond a certain range. The application processor may receive illumination information (e.g., illumination values) from the illumination sensor and determine a change in exposure time setting (e.g., CIT). For example, the application processor may change the CIT whenever the illuminance value exceeds a particular range. When the illuminance becomes low, the exposure time may be increased by setting a relatively large CIT, and when the illuminance is increased, the exposure time may be decreased by setting a relatively small CIT.

The set of exposure time setting values and adjustment values corresponding to the exposure time setting values may be provided to the buffer 142. Here, the exposure time setting value may be changed according to the ambient illuminance, and in order that the set of the changed exposure time setting value and the adjustment value corresponding to the changed exposure time setting value may be applied to the frame starting after the change, the buffer 142 may be implemented as a double buffer.

The buffer 142 may supply an exposure time setting value (e.g., CIT) to the first address generation circuit 143 and the second address generation circuit 144 in synchronization with an update timing pulse indicating an update timing of a frame. Here, CITs supplied to the first address generating circuit 143 and the second address generating circuit 144 may be different from each other. The buffer 142 may provide the set of adjustment values corresponding to the CIT to the first address recalculation circuit 145 and the second address recalculation circuit 146 in synchronization with the update timing pulse.

For example, a first CIT1 may be set for a kth frame (K is a positive integer), and a second CIT2 may be set for a k+1th frame. The first CIT1 may be provided to the first address generation circuit 143 before a kth frame (e.g., a kth-1 frame), and the set TVS1 of first adjustment values corresponding to the first CIT1 may be provided to the first address recalculation circuit 145.

The first address generating circuit 143 may generate an input row address ir_add (or referred to as a reference address). As shown in fig. 12A to 12C, the value of the input row address ir_add may sequentially increase, and may sequentially indicate a plurality of rows of the pixel array (110 of fig. 1).

The first address generation circuit 143 may generate a read timing signal and generate a reset timing signal based on the read timing signal and the first CIT 1. The readout timing signal may indicate a point in time (e.g., a horizontal period) at which readout of the sub-pixel starts, and the reset timing signal may indicate a point in time (e.g., a horizontal period) at which reset of the sub-pixel starts. In some example embodiments, the readout timing signal may be fixed to a specific horizontal period (e.g., the fifth horizontal period 5H of fig. 8A to 8C), and the reset timing point may be adjusted in units of one horizontal period based on the first CIT 1.

For example, when the first CIT1 is 2, as described with reference to fig. 8B, the first address generation circuit 143 may generate a reset timing signal indicating that the sub-pixel is to be reset in a horizontal period (e.g., the third horizontal period 3H) preceding two horizontal periods from a horizontal period (e.g., the fifth horizontal period 5H) in which the sub-pixel is read out. For example, when the first CIT1 is 3, as described with reference to fig. 8C, the first address generation circuit 143 may generate a reset timing signal indicating that the sub-pixel is to be reset in a horizontal period (e.g., the second horizontal period 2H) preceding three horizontal periods from a horizontal period (e.g., the fifth horizontal period 5H) in which the sub-pixel is read out.

The first address recalculation circuit 145 may generate a recalculated row address based on the input row address ir_add supplied from the first address generation circuit 143 and the set TVS1 of the first adjustment values supplied from the buffer 142. In some example embodiments, when the image sensor (100 of fig. 1) supports fast readout as described with reference to fig. 9A to 9H, the sub-pixels arranged in at least two rows may be read out simultaneously. Thus, the first address recalculation circuit 145 may generate at least two recalculated row addresses.

The second CIT2 may be provided to the second address generation circuitry 144 prior to the k+1st frame (e.g., the K-th frame), and the set of second adjustment values TVS2 corresponding to the second CIT2 may be provided to the second address recalculation circuitry 146. The operations of the second address generation circuit 144 and the second address recalculation circuit 146 are similar to those of the first address generation circuit 143 and the first address recalculation circuit 145, respectively.

The address output circuit 147 may alternately supply the reset timing signal, the readout timing signal, and the recalculated row address generated by the first address generating circuit 143 and the first address recalculating circuit 145, and the reset timing signal, the readout timing signal, and the recalculated row address generated by the second address generating circuit 144 and the second address recalculating circuit 146 to the row driver 120 in each frame.

For example, the address output circuit 147 may supply the reset timing signal generated by the first address generation circuit 143 to the row driver 120 in the K-1 th frame, and supply the readout timing signal generated by the first address generation circuit 143 and the first address recalculation circuit 145 and the recalculated row address to the row driver 120 in the K-1 th frame. In addition, the address output circuit 147 may supply the reset timing signal generated by the second address generation circuit 144 to the row driver 120 in the K-th frame, and supply the readout timing signal generated by the second address generation circuit 144 and the second address recalculation circuit 146 and the recalculated row address to the row driver 120 in the k+1-th frame. Accordingly, as shown in fig. 13, when the CIT is changed, the changed CIT may be immediately applied to the next frame, thereby preventing or reducing the occurrence of a dead frame.

Fig. 12A to 12C illustrate an address calculation method of a timing generator according to some example embodiments.

Fig. 12A shows a case when CIT is 1 or 3, fig. 12B shows a case when CIT is 2, and fig. 12C shows a case when CIT is 4 or more. The pixel is assumed to include four sub-pixels arranged in a 2 x 2 matrix. Fig. 12A to 12C illustrate an address calculation method performed when subpixels arranged in two non-adjacent rows are simultaneously read out with quick readout as described with reference to fig. 9A to 9H. The address calculation method will be described together with reference to fig. 9A to 9H.

Referring to fig. 12A, the input row address ir_add generated by the address generating circuit (e.g., the first address generating circuit 143 or the second address generating circuit 144 of fig. 11) may have a value that increases from 0 one by one. The input Row address ir_add may indicate a value for sequentially selecting a plurality of rows (e.g., first to eighth rows Row1 to Row 8) provided in the pixel array (110 in fig. 9A to 9H) in each horizontal period.

When CIT is 1 or 3, the set of adjustment values TVS may be 0, -1,2,1,3,2,5,4 as shown. The address recalculation circuit (e.g., the first address recalculation circuit 145 or the second address recalculation circuit 146 of fig. 11) may generate a value obtained by subtracting the corresponding adjustment value from the input row address ir_add as the first recalculated row address rr_add_0 and a value calculated by adding 4 to the first recalculated row address rr_add_0 as the second recalculated row address rr_add_1. The first recalculated row address rr_add_0 may be 0,2,0,2,1,3,1,3 and the second recalculated row address rr_add_1 may be 4,6,4,6,5,7,5,7. When the first recalculated Row address rr_add_0 is "0", the first Row1 in the pixel array 110 is indicated, and when the second recalculated Row address rr_add_1 is "4", the fifth Row5 in the pixel array 110 is indicated.

The e_o phase indicates a subpixel arranged in an odd-numbered column or a subpixel arranged in an even-numbered column among subpixels arranged in a row indicated by the first recalculated row address rr_add_0 and the second recalculated row address rr_add_1. When the e_o phase is even (E), the sub-pixels arranged in the even-numbered columns may be read, and when the e_o phase is odd (O), the sub-pixels arranged in the odd-numbered columns may be read.

For example, when the input address ir_add is "0", the first recalculated row address rr_add_0 is "0", and the second recalculated row address rr_add_1 is "4", and the e_o phase is an even number (E). Accordingly, in the first horizontal period, the first green sub-pixels Gr1 and Gr3 of the first and third pixels PX1 and PX3 arranged in the even-numbered columns of the first and fifth rows may be simultaneously read.

When the input address ir_add is "1", the first recalculated row address rr_add_0 is "2", the second recalculated row address rr_add_1 is "6", and the e_o phase is an even number (E). Accordingly, in the second horizontal period, the first green sub-pixels Gr2 and Gr4 of the second pixel PX2 and the fourth pixel PX4 arranged in the even-numbered columns of the third and seventh rows may be simultaneously read.

When the input address ir_add is "2", the first recalculated row address rr_add_0 is "0", and the second recalculated row address rr_add_1 is "4", and the e_o phase is an odd number (O). Accordingly, in the third horizontal period, the red sub-pixels R1 and R3 of the first and third pixels PX1 and PX3 arranged in the odd-numbered columns of the first and fifth rows may be simultaneously read.

When the input address ir_add is "3", the first recalculated row address rr_add_0 is "2", the second recalculated row address rr_add_1 is "6", and the e_o phase is an odd number (O). Accordingly, in the fourth horizontal period, the red sub-pixels R2 and R4 of the second pixel PX2 and the fourth pixel PX4 arranged in the odd-numbered columns of the third and seventh rows may be simultaneously read.

In the fifth horizontal period, the blue sub-pixels B1 and B3 of the first and third pixels PX1 and PX3 arranged in the even-numbered columns of the second and sixth rows may be simultaneously read; in the sixth horizontal period, the blue sub-pixels B2 and B4 of the second pixel PX2 and the fourth pixel PX4 arranged in the even-numbered columns of the fourth and eighth rows may be simultaneously read; in the seventh horizontal period, the second green sub-pixels Gb1 and Gb3 of the first and third pixels PX1 and PX3 arranged in the odd-numbered columns of the second and sixth rows may be simultaneously read; and in the eighth horizontal period, the second green sub-pixels Gb2 and Gb4 of the second pixel PX2 and the fourth pixel PX4 arranged in the odd-numbered columns of the fourth and eighth rows may be simultaneously read.

As described above, when CIT is set to 1 or 3, the sub-pixels may be alternately read from two adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2 or the third pixel PX3 and the fourth pixel PX 4) connected to the same column line in each horizontal period.

Referring to fig. 12B, the input row address ir_add may have a value that increases one by one. When CIT is 2, the set of adjustment values may be 0,1,0,1,3,4,3,4 as shown. A value obtained by subtracting the adjustment value from the input row address ir_add may be generated as the first recalculated row address rr_add_0, and a value obtained by adding 4 to the first recalculated row address rr_add_0 may be generated as the second recalculated row address rr_add_1.

As shown, the first recalculated row address rr_add_0 is 0,0,2,2,1,1,3,3 and the second recalculated row address rr_add_1 is 4,4,6,6,5,5,7,7 and the e_o phase can be changed in each horizontal period. Accordingly, in the first horizontal period, the first green sub-pixels Gr1 and Gr3 of the first and third pixels arranged in the even-numbered columns of the first and fifth rows may be read out; in the second horizontal period, the red subpixels R1 and R3 arranged in the odd-numbered columns of the first and fifth rows may be read; in the third horizontal period, the first green sub-pixels Gr2 and Gr4 of the second and fourth pixels arranged in the even-numbered columns of the third and seventh rows may be read out; and in the fourth horizontal period, the red sub-pixels R2 and R4 of the second and fourth pixels arranged in the odd-numbered columns of the third and seventh rows may be read out. In addition, in the fifth horizontal period, the blue sub-pixels B1 and B3 of the first and third pixels arranged in the even-numbered columns of the second and sixth rows may be read out; in the sixth horizontal period, the second green sub-pixels Gb1 and Gb3 of the first and third pixels arranged in the odd-numbered columns of the second and sixth rows may be read out; in the seventh horizontal period, the blue sub-pixels B2 and B4 of the second and fourth pixels arranged in the even-numbered columns of the fourth and eighth rows may be read out; and in the eighth horizontal period, the second green sub-pixels Gb2 and Gb4 of the second and fourth pixels arranged in the odd-numbered columns of the fourth and eighth rows may be read out.

When CIT is set to 2, the sub-pixels may be alternately read out from two adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2 or the third pixel PX3 and the fourth pixel PX 4) connected to the same column line every two horizontal periods. Referring to fig. 12C, the input row address ir_add may have a value that increases one by one. When CIT is greater than or equal to 4, the set of adjustment values may be 0,1,1,2,2,3,3,4 as shown. A value obtained by subtracting the adjustment value from the input row address ir_add may be generated as the first recalculated row address rr_add_0, and a value obtained by adding 4 to the first recalculated row address rr_add_0 may be generated as the second recalculated row address rr_add_1.

As shown, the first recalculated row address rr_add_0 is 0,0,1,1,2,2,3,3, the second recalculated row address rr_add_1 is 4,4,5,5,6,6,7,7, and the e_o phase can change in each horizontal period. Accordingly, in the first horizontal period, the first green sub-pixels Gr1 and Gr3 of the first and third pixels arranged in the even-numbered columns of the first and fifth rows may be read out; in the second horizontal period, the red sub-pixels R1 and R3 of the first and third pixels arranged in the odd-numbered columns of the first and fifth rows may be read out; in the third horizontal period, the blue sub-pixels B1 and B3 of the first and third pixels arranged in the even-numbered columns of the second and sixth rows may be read out; and in the fourth horizontal period, the second green sub-pixels Gb1 and Gb3 of the first and third pixels arranged in the odd-numbered columns of the second and sixth rows may be read out. In addition, in the fifth horizontal period, the first green sub-pixels Gr2 and Gr4 of the second and fourth pixels arranged in the even-numbered columns of the third and seventh rows may be read out; in the sixth horizontal period, the red sub-pixels R2 and R4 of the third and seventh pixels arranged in the odd-numbered columns of the third and seventh rows may be read out; in the seventh horizontal period, the blue sub-pixels B2 and B4 of the second and fourth pixels arranged in the even-numbered columns of the fourth and eighth rows may be read out; and in the eighth horizontal period, the second green sub-pixels Gb2 and Gb4 of the second and fourth pixels arranged in the odd-numbered columns of the fourth and eighth rows may be read out.

When CIT is set to 4 or more, four sub-pixels may be sequentially read from one pixel among two adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2 or the third pixel PX3 and the fourth pixel PX 4) connected to the same column line, and then the other four sub-pixels may be sequentially read from the other pixel.

Fig. 13 is a timing diagram for describing reset and readout according to a change in an exposure time setting value in an image sensor according to some example embodiments.

Referring to fig. 13, the cit may be set to 8 during the first frame period. The first reset may be sequentially performed on a plurality of rows of the pixel array (110 of fig. 1) from the shutter frame period, and the first readout may be sequentially performed on the plurality of rows in the first frame period. Here, the first reset (reset 1) and the first read (read 1) represent reset and read of the sub-pixels performed based on the recalculated row address generated by the first address recalculation circuit (145 of fig. 11). In the first frame (frame 1), the sub-pixels may be read out according to the third mode (mode 3) as described with reference to fig. 8D.

The CIT may be changed to 1, and thus, a second reset (reset 2) may be performed from the first frame period, and a second readout (read 2) may be performed during the second frame (frame 2) period. Here, the second reset and the second readout represent reset and readout of the sub-pixels performed based on the recalculated row address generated by the second address recalculation circuit (146 of fig. 11). In the second frame, the sub-pixels may be read out according to the first mode (mode 1) as described with reference to fig. 8A.

The CIT may be changed to 2, and thus, the first reset may be performed from the second frame period, and the first readout may be performed during the third frame (frame 3) period. In the third frame period, the sub-pixels may be read out according to the second mode (mode 2) as described with reference to fig. 8B.

When CIT is changed to 12, a second reset may be performed from the third frame period, and a second readout may be performed during the fourth frame (frame 4) period. In the fourth frame period, the sub-pixels may be read out according to the third mode.

The timing generator (140 in fig. 1) includes two sets of address generating circuits (e.g., a first address generating circuit 143 of fig. 11 and a first address recalculating circuit 145 of fig. 11 and a second address generating circuit 144 of fig. 11 and a second address recalculating circuit 146 of fig. 11), and the CIT is changed by alternately using the two sets of address generating circuits, and the changed CIT can be immediately applied to the next frame. Thus, the occurrence of dead frames can be prevented or reduced despite CIT changes.

Fig. 14 is a schematic block diagram of an electronic device 1000 including an image sensor, according to some example embodiments.

Referring to fig. 14, an electronic device 1000 may include an image sensor 1100, an Application Processor (AP) 1200, and an illuminance sensor 1300.

The AP 1200 may provide a control signal to control the operation of the image sensor 1100 to the image sensor 1100. For example, the transmission of control signals may be performed based on an I2C-based interface. The control signal may include an exposure time setting (e.g., CIT). The control signals may also include configuration data (such as lens shading correction values, crosstalk coefficients, and/or gains) for the image sensor 1100.

The image sensor 1100 may generate image data IDT by capturing an image of an object based on a received control signal. The image data IDT may include a still image and a moving image. The image sensor 1100 can perform signal processing (such as image quality compensation, merging, and/or scaling) on the image data IDT, and the image quality compensation can include, for example, black level compensation, lens shading compensation, crosstalk compensation, and/or bad pixel correction.

The image sensor 1100 may transmit the image data IDT or the signal-processed image data to the application processor 1200. The image data IDT may be transmitted using, for example, a Mobile Industrial Processor Interface (MIPI) -based Camera Serial Interface (CSI), but some example embodiments are not limited thereto.

The application processor 1200 may perform bad pixel correction, 3A adjustment (auto focus correction, auto white balance, auto exposure), noise reduction, sharpening, gamma control, restoration mosaic, demosaicing, resolution scaling (video/preview), high Dynamic Range (HDR) processing, and the like on the received image data IDT.

The illuminance sensor 1300 may sense ambient illuminance of the electronic device 1000 and generate illuminance information if_l. The illuminance information if_l may include an illuminance value.

According to some example embodiments, the application processor 1200 may receive illuminance information if_l regarding ambient illuminance of the electronic device 1000 from an external illuminance sensor and adjust an exposure time setting (e.g., CIT) based on the illuminance information if_l. For example, the application processor 1200 may change the CIT per frame based on the illuminance information if_l. As another example, the application processor 1200 may change the CIT whenever the illuminance value included in the illuminance information if_l changes beyond a certain range; when the illuminance is reduced, the application processor 1200 may increase the exposure time by setting a relatively large CIT, and when the illuminance is increased, the application processor 1200 may decrease the exposure time by setting a relatively small CIT.

The application processor 1200 transmits an exposure time setting value (e.g., CIT) as a control signal to the image sensor 1100, and the exposure time setting value may be stored in the register bank 141.

As described with reference to fig. 11 to 12C, the exposure time setting value may be used to generate a reset timing signal and a recalculated row address (e.g., a first recalculated row address rr_add_0 and a second recalculated row address rr_add_1) in the timing controller 140. The exposure time of the plurality of rows of the pixel array (110 of fig. 1) may be set according to the exposure time setting value, and the reset order and the readout order of the plurality of rows of the pixel array 110 and their reset time and readout time may be determined according to the exposure time setting value.

The image sensor 100 described with reference to fig. 1 to 13 may be applied to the image sensor 1100. The pixel array has a shared pixel structure, and the reset and readout order of the plurality of sub-pixels of two adjacent pixels in the column direction may be changed (adjusted) according to the exposure time setting value, and the sub-pixel of the second pixel may be reset in a horizontal period in which the sub-pixel of the first pixel is read out, and the other sub-pixel of the first pixel may be reset in a horizontal period in which the sub-pixel of the second pixel is read out. When the first pixel and the second pixel alternately perform the reset of the sub-pixel and the readout of the sub-pixel every at least one horizontal period, the limitation on the exposure time setting may be eliminated or reduced, and the minimum exposure time may be set as needed. Accordingly, even in an ultra-high light environment, the dynamic range of the image sensor 1100 can be increased.

The image sensor 100 (or other circuitry discussed herein, such as the row driver 120, ADC circuit 130, timing controller 140, image conversion circuit 150, memory 160, register bank 141, buffer 142, first address generation circuit 143, second address generation circuit 144, first address recalculation circuit 145, second address recalculation circuit 146, address output circuit 147, electronic device 1000, AP 1200, and illuminance sensor 1300) may include hardware including logic circuitry, hardware/software combinations (such as a processor executing software), or combinations thereof. For example, processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. An image sensor, comprising:

a pixel array including a first pixel and a second pixel connected to the same column line, the first pixel including N sub-pixels sharing a first floating diffusion node, and the second pixel including N sub-pixels sharing a second floating diffusion node, wherein N is a positive integer greater than or equal to two;

a timing generator configured to change a reset order and a readout order of 2N sub-pixels included in the first pixel and the second pixel according to the exposure time setting value, and output a row address according to the changed reset order and readout order; and

a row driver configured to drive the pixel array based on the row address.

2. The image sensor of claim 1, wherein the timing generator is configured to change the reset order and the readout order of the 2N sub-pixels such that: in the first horizontal period, a first subpixel of the first pixel is read out and a second subpixel of the second pixel is reset; and, in the second horizontal period, the second sub-pixel of the second pixel is read out and the third sub-pixel of the first pixel is reset.

3. The image sensor of claim 1, wherein the first pixel further comprises:

a first reset transistor configured to provide a reset voltage to the first floating diffusion node in response to a first reset signal of an active level;

a first driving transistor configured to generate a first pixel signal corresponding to a potential of the first floating diffusion node; and

a first selection transistor configured to output a first pixel signal to the column line in response to a first selection signal of an active level,

wherein the first selection transistor is turned off in response to the first selection signal of the inactive level based on the sub-pixel of the first pixel being reset.

4. The image sensor of claim 3, wherein the first selection transistor is turned on in response to the first selection signal of the active level and the first reset transistor is turned off in response to the first reset signal of the inactive level based on the sub-pixel of the first pixel being read out.

5. The image sensor of claim 1, wherein,

in the first horizontal period, the first subpixel of the first pixel is read out and the second subpixel of the second pixel is reset, and

in the second horizontal period, the second subpixel of the second pixel is read out, and the third subpixel of the first pixel is reset.

6. The image sensor of claim 5, wherein the fourth subpixel of the second pixel and the fifth subpixel of the first pixel are reset after the second subpixel of the second pixel is reset and before the second subpixel of the second pixel is read out.

7. The image sensor of claim 5, wherein the second horizontal period is subsequent to the first horizontal period based on the exposure time setting value having a first value.

8. The image sensor of claim 5, wherein the fourth sub-pixel of the first pixel is read out and the fifth sub-pixel of the second pixel is reset in a third horizontal period between the first horizontal period and the second horizontal period based on the exposure time setting value having the second value.

9. The image sensor according to claim 5, wherein the exposure time setting value has a third value, in a third horizontal period after the first horizontal period, the fourth subpixel of the first pixel is reset and the fifth subpixel of the second pixel is read out, and in a fourth horizontal period after the third horizontal period, the sixth subpixel of the first pixel is read out and the seventh subpixel of the second pixel is reset, and

The second horizontal period is subsequent to the fourth horizontal period.

10. The image sensor of claim 1, wherein the timing generator comprises:

a register configured to store a set of exposure time setting values and a plurality of adjustment values corresponding to the plurality of exposure time setting values; and

an address generation circuit configured to generate a reference address based on the exposure time setting value, and generate a recalculated row address according to the changed reset order and readout order of the 2N sub-pixels by applying a set of adjustment values corresponding to the exposure time setting value to the reference address.

11. The image sensor of claim 10, wherein the timing generator further comprises: a double buffer configured to:

receiving a set of first exposure time setting values and first adjustment values corresponding to a first frame and a set of second exposure time setting values and second adjustment values corresponding to a second frame from a register, and

in response to the update timing signal, a set of the first exposure time setting value and the first adjustment value or a set of the second exposure time setting value and the second adjustment value is sent to the address generation circuit.

12. The image sensor of claim 1, further comprising: an image data conversion circuit configured to store image data generated from pixel signals output from the pixel array in the line buffer and convert the image data into image data of a bayer pattern.

13. The image sensor of any one of claims 1 to 12, wherein the N sub-pixels are arranged in a 2 x 2 matrix.

14. The image sensor according to claim 13, wherein the two sub-pixels arranged in the first diagonal direction convert optical signals of different frequency bands into electrical signals, and

the other two sub-pixels arranged in the second diagonal direction convert the optical signals of the same frequency band into electrical signals.

15. An image sensor, comprising:

a pixel array including a plurality of pixels arranged in a matrix, each of the plurality of pixels including N sub-pixels sharing a floating diffusion node, wherein N is an integer greater than or equal to 2;

a timing generator configured to set a reset order and a readout order of the 2N sub-pixels according to the exposure time setting value such that: while the 2N sub-pixels of the first and second pixels adjacent in the column direction, which are disposed in the plurality of pixels, are sequentially read out, in a first horizontal period, a first sub-pixel of the first pixel is read out and a second sub-pixel of the second pixel is reset, and in a second horizontal period, a second sub-pixel of the second pixel is read out and a third sub-pixel of the first pixel is reset; and

And a row driver configured to drive the pixel array based on the row address supplied from the timing generator according to the reset order and the readout order of the 2N sub-pixels.

16. The image sensor of claim 15, wherein the second horizontal period is subsequent to the first horizontal period based on the exposure time setting value being set to the first value.

17. The image sensor of claim 15, wherein, when the exposure time setting value is set to the second value, in a third horizontal period between the first horizontal period and the second horizontal period, the fourth subpixel of the first pixel is read out and the fifth subpixel of the second pixel is reset.

18. An electronic device, comprising:

an image sensor including a pixel array including a plurality of pixels, and configured to generate image data based on optical signals received by the pixel array; and

an application processor configured to generate an exposure time setting value based on illuminance information indicating ambient illuminance, and to transmit the exposure time setting value to the image sensor,

wherein the plurality of pixels includes a first pixel and a second pixel connected to the same column line, and each of the first pixel and the second pixel includes a plurality of sub-pixels sharing a floating diffusion node, and

The reset order and the readout order of the plurality of sub-pixels of the first pixel and the second pixel are changed according to the exposure time setting value.

19. The electronic device of claim 18, wherein the image sensor further comprises a register bank configured to store the exposure time setting value and a timing generator configured to determine the reset order and the readout order of the plurality of sub-pixels of the first pixel and the second pixel based on the exposure time setting value.

20. The electronic device of claim 18, wherein,

the image sensor is further configured to determine a reset order and a readout order of the plurality of sub-pixels such that in a first period, a first sub-pixel of the first pixel is read out and a second sub-pixel of the second pixel is reset, and

in the second period, the second subpixel of the second pixel is read out, and the third subpixel of the first pixel is reset.