KR20230103879A - Tiling Display Device - Google Patents

Abstract

In the tiling display device according to the exemplary embodiment of the present specification, a plurality of display modules connected to each other through a first interface circuit and a second interface circuit, and a defect occurrence and location signal generated by any one failure module among the plurality of display modules. A set for receiving from the faulty module through the first interface circuit during the first period, generating a faulty recognition complete signal during a second period subsequent to the first period, and transmitting the faulty recognition complete signal to the faulty module through the second interface circuit. include the board

Description

Tiling display device {Tiling Display Device}

This specification relates to a tiling display device capable of scalability.

A large display can be used in various fields such as outdoor digital advertising. To meet the demand for a large display, a tiling display device capable of scalability has been proposed. A tiling display device configures a single screen by connecting a set board and a plurality of display modules, and has an advantage in that the size of the screen can be adjusted according to the number of display modules.

Since such a tiling display device is mainly installed outdoors due to the characteristics of a commercial product, it is difficult for a user to visually recognize whether or not a defect has occurred. In addition, since the tiling display device includes many parts for configuring a large screen, even if a defect occurs, it may take a lot of time to find the cause of the defect.

Accordingly, the present specification provides a tiling display device capable of automatically checking the defective location of a display module with a set board that is out of order, and further automatically checking the defect details of a failed display module.

In the tiling display device according to the exemplary embodiment of the present specification, a plurality of display modules connected to each other through a first interface circuit and a second interface circuit, and a defect occurrence and location signal generated by any one failure module among the plurality of display modules. A set for receiving from the faulty module through the first interface circuit during the first period, generating a faulty recognition complete signal during a second period subsequent to the first period, and transmitting the faulty recognition complete signal to the faulty module through the second interface circuit. include the board

According to the present embodiment, it is possible to automatically check the defective position of the display module with a set board failure, and further automatically check the failure details of the failed display module. As a result, the tiling display device according to the present embodiment has the advantage of significantly reducing the time required to determine the location and cause of the defect.

Furthermore, according to the present embodiment, since the set board interprets the data transmitted through SPI communication according to a predetermined protocol and identifies the location and cause of the defect, the overall structure required for fault diagnosis is simplified and the manufacturing cost is lowered. there is.

Effects according to this specification are not limited by the contents exemplified above, and more various effects are included in this specification.

1 is a diagram schematically showing a tiling display device according to an exemplary embodiment.
2 is a diagram showing a connection configuration of one display module.
3 and 4 are views showing a micro LED-based display panel.
5 is a schematic equivalent circuit diagram of one pixel included in the display panel.
6 is a diagram showing a structure for diagnosing a failure of a tiling display device according to an exemplary embodiment.
7 is a diagram schematically illustrating a failure diagnosis sequence of a tiling display device according to an exemplary embodiment.
8 and 9 are diagrams showing a failure diagnosis sequence of the tiling display device according to the present embodiment in detail.
10 is a diagram showing an example of a failure diagnosis list corresponding to the failure detail signals of FIGS. 8 and 9 .
11 is a diagram showing a principle of recognizing a failure occurrence of a failed module in a set board.
12 is a diagram showing a principle of recognizing a location of a defective module in a set board.
FIG. 13 is a diagram illustrating the transmission of a failure recognition completion signal to a failure module after confirming a location where a failure occurs in a failure module in a set board.
14 is a diagram showing that a failure module transmits a failure details signal to a set board after receiving a failure recognition completion signal.
15 is a diagram showing an example of a failure diagnosis list corresponding to the failure detail signal of FIG. 14 .
16 is a diagram showing overall configurations of each display module for implementing a failure diagnosis sequence in the tiling display device according to the present embodiment.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of this specification complete, and common knowledge in the art to which this specification belongs. It is provided to completely inform the person who has the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', '~ below', 'next to', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

Although first, second, etc. may be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

1 is a diagram schematically illustrating a tiling display device according to an exemplary embodiment of the present specification. 2 is a diagram showing a connection configuration of one display module.

Referring to FIGS. 1 and 2 , the tiling display device 100 according to the present exemplary embodiment includes a set board SET and a plurality of display modules CB. Each display module CB may also be referred to as a cabinet.

The display modules CB may be connected to each other through an interface circuit to form a large screen. The total resolution of the large screen may be determined as the sum of unit resolutions of each display module (CB). For example, when one screen is composed of 8 display modules (CB) having a unit resolution of 960*1080, the total resolution of the screen may be 3840*2160.

Each display module CB may be implemented as an electroluminescence display type, a liquid crystal display type, or the like. In the present embodiment, a display module CB implemented as a micro LED-based electroluminescence display type will be exemplified. However, the technical spirit of the present specification is not limited by the implementation method of the display module CB.

In order for the set board (SET) to be able to automatically check the defective location of the failed display module (hereinafter referred to as the failed module) and to further automatically check the defect details of the failed module, the set board (SET) and the display modules (CB) may be connected to each other through an interface circuit implemented as SPI (Serial Peripheral Interface).

The interface circuit may be implemented as a bi-directional multi-chain interface of a feedback loop type. The interface circuit enables individual two-way serial communication between the display modules (CB) and between the set board (SET) and the display module (CB), thereby securing a short communication line and mass data communication through the short communication line. speed and reliability can be improved.

Each display module CB may include a plurality of display panels PNL, panel driving circuits for driving the display panels PNL, and a timing controller TCON controlling operation timing of the panel driving circuits. can

The timing control unit TCON is mounted on a control printed circuit board CPCB and may be connected in parallel to panel driving circuits through a branch cable CBL. The timing controller TCON may be further connected to a neighboring display module CB or set board SET through an interface circuit.

The panel driving circuits may be independently connected to each of the plurality of display panels PNL. The panel driving circuits include a source printed circuit board (SPCB) connected to the timing controller (TCON) through a branch cable (CBL), a memory circuit (MEM) mounted on the source printed circuit board (SPCB), and a source printed circuit board (SPCB). A conductive film (COF) electrically connecting the display panel (PNL), a data driver (SIC) bonded on the conductive film (COF), a gate driver and power circuit electrically connected to the source printed circuit board (SPCB). can include

The memory circuit MEM is a non-volatile memory that stores panel characteristics, and a correction value for gamma setting, a first compensation value for compensating for driving characteristic deviation/color deviation between pixels and adjacent display panels PNL. It may be a flash memory and/or an EEPROM for storing a second compensation value for compensating for the boundary deviation and various image quality and driving control data. At this time, the flash memory is used for storing large-capacity data, and the EEPROM may be used for storing low-capacity data.

3 and 4 are views showing a micro LED-based display panel. 5 is a schematic equivalent circuit diagram of one pixel included in the display panel.

Referring to FIGS. 3 and 4 , a pixel array for reproducing an input image is formed on each of the display panels PNL. A plurality of pixels may be disposed in the pixel array, and signal lines for driving the pixels may be disposed. These signal wires include data lines DL for supplying the data voltage Vdata to the pixels, gate lines GL for supplying the gate signal GSIG to the pixels, and power supply voltage to the pixels. It may include power lines for supplying.

Each of the pixels may include a micro LED chip (μLED chip) as a light emitting element EL. The micro LED chips (μLED chips) may include red chips (μLED chip_R), green chips (μLED chip_G), and blue chips (μLED chip_B) positioned on a thin film transistor backplane (TFT Backplane). can The R pixel includes a red chip (μLED chip_R) as a light emitting element (EL), the G pixel includes a green chip (μLED chip_G) as a light emitting element (EL), and the B pixel includes a blue chip (μLED chip_B) as a light emitting element. Include as (EL).

Micro LED chips (μLED chips) can be mounted on a TFT back plane by being transferred from R/G/B donors. Red chips (μLED chip_R) are transferred from the R donor (R Donor), green chips (μLED chip_G) are transferred from the G donor (G Donor), and blue chips (μLED chip_B) are transferred from the B donor (B Door). can The transfer technology may use electrostatic force, laser, speed-dependent adhesive force, load-dependent adhesive force, and the like. The transfer technique is not limited thereto, and self-assembly based on electromagnetic force may be used.

The TFT back plane may have an active matrix structure for efficient driving. On the TFT back plane, pixels may be defined by data lines DL, gate lines GL, and power lines.

A plurality of pixels may constitute one unit pixel. For example, along the extension direction of the gate line GL or the extension direction of the data line DL, R (red), G (green), and B (blue) pixels arranged adjacently constitute one unit pixel. can do.

As shown in FIG. 5 , one pixel PXL may include a light emitting element EL, a driving TFT DT, and a node circuit NCON.

The node circuit NCON may be connected to the gate line GL and the data line DL. The node circuit NCON receives the data voltage Vdata from the data line DL and receives the gate signal GSIG from the gate line GL. The node circuit NCON applies the data voltage Vdata to the gate electrode of the driving TFT DT in synchronization with the gate signal GSIG, so that the voltage between the gate and source of the driving TFT DT meets the driving current generation condition. can be set appropriately. The node circuit NCON may include an internal compensation circuit that senses and compensates for the threshold voltage and/or electron mobility of the driving TFT DT.

The driving TFT (DT) is a driving element that generates a driving current in response to a gate-source voltage. The gate electrode of the driving TFT (DT) is connected to the node circuit (NCON), the first electrode (drain electrode) is connected to the high potential pixel power supply (VDD), and the second electrode (source electrode) is connected to the light emitting element (EL). can be connected to

The light emitting element EL is a light emitting element that emits light with an intensity corresponding to the driving current input from the driving TFT DT. The light emitting element EL may be implemented as a micro light emitting diode including an inorganic light emitting layer. A first electrode of the light emitting element EL is connected to the driving TFT (DT), and a second electrode is connected to the low potential pixel power supply (VSS).

Since the connection configuration and operation of one pixel (PXL) is only an example, the technical idea of the present specification is not limited thereto. For example, the driving TFT (DT) and the node circuit (NCON) may be implemented based on PMOS, NMOS, or CMOS. Also, a plurality of gate lines GL may be connected to the node circuit NCON. In addition, although the light emitting element EL of the present specification is implemented as a circuit of a common cathode, it is not limited thereto and may be implemented as a circuit of a common anode.

6 is a diagram showing a structure for diagnosing a failure of a tiling display device according to an exemplary embodiment. 7 is a diagram schematically showing a failure diagnosis sequence of the tiling display device according to the present embodiment.

Referring to FIG. 6 , the tiling display device according to the present embodiment may use an SPI type first interface circuit and a second interface circuit for automatic fault diagnosis. The first interface circuit may transmit a failure occurrence and location signal of the failure module (eg, CPCB#2) and a failure detail signal from the failure module to the set board (SET). The second interface circuit may transmit a failure recognition completion signal of the set board SET to the failure module. A signal transmission direction of the first interface circuit and a signal transmission direction of the second interface circuit may be opposite to each other.

The fault diagnosis sequence can be performed in the power on sequence section together with the "Auto nID setting process". The power-on sequence period may be a time from when operating power is turned on in the tiling display device to before screen output. "Auto nID setting process" means that the display modules sequentially generate module identification numbers corresponding to the connection sequence under the control of the set board (SET), and transmit a control response signal including the generation result to the set board through a third interface circuit. It means an operation that feeds back to (SET). Through "Auto nID setting process", each display module can know its connection sequence.

The set board (SET) includes a system on chip circuit (SOC) for fault diagnosis. The system on chip circuit (SOC) may include a first input terminal (L-I) connected to the first interface circuit and a second output terminal (LCK-O) connected to the second interface circuit.

Each display module may include any one of the control printed circuit boards (CPCB#1 to CPCB#8) having different connection sequences and any one of the corresponding timing controllers (TCON#1 to TCON#8). . The timing control unit includes a diagnosis control circuit (LCON) for generating or transmitting a defect occurrence and location signal and a defect detail signal, a first input terminal (L-I) and a first output terminal (L-O) connected to the first interface circuit, 2 may include a second input terminal LCK-I and a second output terminal LCK-O connected to the interface circuit.

Referring to FIG. 7 , the set board SET receives a failure occurrence and location signal of a failure module (eg, CPCB#2) from the failure module through the first interface circuit in a first period. Then, the set board (SET) generates a failure recognition completion signal in a second interval subsequent to the first interval and transmits the failure recognition completion signal to the failure module through the second interface circuit. In addition, the set board (SET) further receives the failure details signal of the faulty module from the faulty module through the first interface circuit in a third period subsequent to the second period.

The defect generation and location signals, the defect recognition complete signal, and the defect details signal may be pulse signals that swing between a high logic voltage and a low logic voltage, respectively.

8 and 9 are diagrams showing a failure diagnosis sequence of the tiling display device according to the present embodiment in detail. And, FIG. 10 is a diagram showing an example of a failure diagnosis list corresponding to the failure detail signals of FIGS. 8 and 9 . 8 to 10, the failure module is exemplified as a case including a control printed circuit board (CPCB#2) having a connection sequence number '2'.

8 to 10, the failure module periodically senses the monitoring signal input through the internal bus line to check whether a failure occurs, updates the failure details in a preset failure diagnosis list when a failure occurs, and detects failure occurrence and A position signal can be generated.

The failure module may generate a failure occurrence and location signal as a pulse signal. After the failure module transitions the failure occurrence and position signal from a high logic voltage to a low logic voltage, the failure module may further toggle the voltage of the failure occurrence and position signal by '2' in its connection sequence. Accordingly, the defect occurrence and location signal may include a first falling edge and two first rising edges positioned behind the first falling edge.

The failure occurrence and location signals of the failure module are transmitted to the first input terminal L-I of the set board SET through the first interface circuit. The set board (SET) recognizes the occurrence of a failure in the faulty module according to the occurrence of a failure and the first falling edge of the position signal in the first period, counts the first rising edges of the occurrence of a failure and the position signal, and The location of the faulty module can be recognized according to the number of rising edges.

The set board (SET) may generate a failure recognition completion signal for notifying that the location of the faulty module has been recognized in a second period subsequent to the first period. The defect recognition completion signal is a pulse signal and may include one second rising edge.

The failure recognition completion signal of the set board (SET) is transmitted to the second input terminal (LCK-I) of the failure module through the second interface circuit. The failure module may know the failure recognition completion state of the set board SET according to the second rising edge of the failure recognition completion signal in the second period.

The failure module may generate the failure details signal as a pulse signal in a third interval subsequent to the second interval. The failure module may toggle the voltage of the failure details signal as many times as the number corresponding to the order of setting failure details in the failure diagnosis list. For example, if the failure details are "short/open", the failure details setting sequence in the failure diagnosis list of FIG. 10 becomes "2", and the failure module may toggle the voltage of the failure details signal twice. In this case, the bad detail signal may include two third rising edges.

The failure details signal of the failure module is transmitted to the first input terminal (L-I) of the set board (SET) through the first interface circuit. The set board SET may count the third rising edges of the failure details signal in the third period, and recognize the failure details of the failed module according to the number of the third rising edges. Since the number of the third rising edges is two, the set board (SET) can recognize "short/open" corresponding to "2" in the failure details setting sequence in the failure diagnosis list as failure details of the failure module.

11 is a diagram showing a principle of recognizing the occurrence of a defect in a faulty module in a set board.

Referring to FIG. 11 , the failure occurrence and location signals are transitioned from a high logic voltage (H) to a low logic voltage (L) in the failure module (CPCB#2). This defect occurrence and location signal is sent to the first input terminal of the set board (SET) through the first interface circuit via the display module (CPCB#1) between the set board (SET) and the failure module (CPCB#2). L-I) is transmitted. The set board SET may recognize the occurrence of a failure of the failure module CPCB#2 according to the occurrence of a failure and the first falling edge FE of the position signal.

12 is a diagram showing a principle of recognizing a location of a defective module in a set board.

Referring to FIG. 12, the defect occurrence and position signal is transitioned from a high logic voltage (H) to a low logic voltage (L) in the failure module (CPCB#2), and then the voltage of the failure occurrence and position signal is converted to the failure module (CPCB#2). It toggles more as much as '2' of the connection sequence of #2). This defect occurrence and location signal is sent to the first input terminal of the set board (SET) through the first interface circuit via the display module (CPCB#1) between the set board (SET) and the failure module (CPCB#2). L-I) is transmitted. The set board (SET) recognizes the occurrence of a failure of the faulty module according to the occurrence of a failure and the first falling edge of the position signal, and then counts the occurrence of a failure and the first rising edges of the position signal to display the connection sequence number '2'. The module can be recognized as a faulty module (CPCB#2).

If the failure module (CPCB#2) does not receive the failure recognition completion signal from the set board (SET) within a set time, the transmission failure occurs and the position signal is sent to the first input terminal of the set board (SET) through the first interface circuit. (L-I) can be retransmitted.

13 is a diagram illustrating transmission of a failure recognition completion signal from a set board to a failure module.

Referring to FIG. 13 , the set board (SET) checks the defect occurrence position of the malfunction module (CPCB#2), and then generates a defect recognition completion signal. The set board (SET) transmits the failure recognition completion signal to the second input terminal (LCK-I) of the failure module (CPCB#2) through the second interface circuit. The failure module CPCB#2 may know the failure recognition completion state of the set board SET according to the second rising edge RE of the failure recognition completion signal.

14 is a diagram showing that a failure module transmits a failure details signal to a set board after receiving a failure recognition completion signal. 15 is a diagram showing an example of a failure diagnosis list corresponding to the failure detail signal of FIG. 14 .

Referring to FIG. 14 , the failure module CPCB#2 may generate a failure details signal as a pulse signal after receiving a failure recognition completion signal from the set board SET. The failure module CPCB#2 may toggle the voltage of the failure details signal by the number corresponding to the order of setting failure details in the failure diagnosis list. For example, if the failure details are "GIA Monitoring", the failure details setting sequence in the failure diagnosis list of FIG. 15 is "1", and the failure module (CPCB#2) toggles the voltage of the failure details signal once. can In this case, the defect detail signal may include one third rising edge.

The failure details signal of the failure module CPCB#2 is transmitted to the first input terminal L-I of the set board SET through the first interface circuit. The set board SET may count the third rising edges of the failure details signal and recognize the failure details of the failure module CPCB#2 according to the number of the third rising edges. The set board (SET) knows the fault diagnosis list in advance. Since the number of the 3rd rising edge is 1, the set board (SET) judges "short/open" corresponding to "1", the order of setting the failure details in the failure diagnosis list, as the failure details of the failure module (CPCB#2) can do.

16 is a diagram showing overall configurations of each display module for implementing a failure diagnosis sequence in the tiling display device according to the present embodiment.

Referring to FIG. 16 , each display module includes a timing controller (TCON) mounted on a control printed circuit board (CPCB). The timing controller TCON includes a diagnosis control circuit LCON for generating or transmitting a defect occurrence and location signal and a defect detail signal, and a first input terminal L-I and a first output terminal L-O connected to the first interface circuit. and a second input terminal LCK-I and a second output terminal LCK-O connected to the second interface circuit.

The diagnosis control circuit LCON may include a defect detection unit, a first signal transmission unit, a first signal generation unit, and a second signal transmission unit.

The defect recognition unit checks defect information (defect location/defect details) input through the internal bus line in real time for each specific period, and enables a control signal when the defect information is confirmed.

The first signal transfer unit checks the defect occurrence and location signal transmitted from the adjacent display module and transfers the corresponding signal to the first signal generator.

The first signal generation unit generates a defect occurrence and location signal when an enabled control signal is input from the defect recognition unit, and outputs the signal through the first interface circuit. The first signal generation unit transmits the received defect occurrence and location signal to the first interface circuit when the control signal enabled from the defect detection unit is not input and the defect occurrence and location signal of the adjacent display module is input from the first signal transfer unit. output as it is. On the other hand, when the timing at which the control signal enabled from the failure detection unit is input and the timing at which the timing at which the occurrence and location signals of the adjacent display module are input from the first signal transmission unit overlap, the first signal generation unit enables the control signal Reliability of the operation may be increased by preferentially performing an operation of generating a defect occurrence and a location signal according to the above.

The second signal transfer unit transmits a failure recognition completion signal received from an adjacent display module or set board (SET) to another display module. In the faulty module, the function of the second signal delivery unit may be disabled.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

SET: set board TCON: timing control
CPCB: control printed circuit board

Claims (10)

a plurality of display modules connected to each other through a first interface circuit and a second interface circuit; and
A defect occurrence and location signal generated by any one of the failure modules among the plurality of display modules is received from the failure module through the first interface circuit in a first section, and a defect occurs in a second section subsequent to the first section. A tiling display device including a set board generating a recognition complete signal and transmitting the failure recognition complete signal to the failure module through the second interface circuit. According to claim 1,
The defect occurrence and location signal and the defect recognition completion signal are pulse signals swinging between a high logic voltage and a low logic voltage;
The defect occurrence and location signal includes a first falling edge and at least one first rising edge positioned behind the first falling edge,
The defect recognition completion signal includes a second rising edge. According to claim 2,
In the first section, the set board,
After recognizing the occurrence of a failure in the faulty module according to the first falling edge of the failure occurrence and location signal, counting the first rising edges of the failure occurrence and location signal, and recognizing the location of the faulty module;
In the second period, the failure module,
The tiling display device recognizing the failure recognition completion state of the set board according to the second rising edge of the failure recognition completion signal. According to claim 2,
The number of the first rising edges,
A tiling display device that varies according to a connection position of the failure module among the plurality of display modules. According to claim 2,
The number of the first rising edges,
The tiling display device of the plurality of display modules, the same as a connection sequence of the failure module through the second interface circuit. According to claim 1,
The set board,
The tiling display device further receives a signal detailing the failure of the faulty module from the faulty module through the first interface circuit in a third period subsequent to the second period. According to claim 6,
the failure specification signal is a pulse signal that swings between a high logic voltage and a low logic voltage;
The tiling display device of claim 1 , wherein the defect detail signal includes at least one third rising edge. According to claim 7,
The set board,
The tiling display device counts the third rising edge of the failure details signal and recognizes one of a failure diagnosis list preset according to the number of the third rising edges as the failure details of the failure module. According to claim 8,
The failure diagnosis list of the failure module includes a plurality of failure candidate information having different setting sequences;
The number of the third rising edges,
The tiling display device of claim 1 , wherein the tiling display device is the same as a setting sequence of the failure details of the failure module among the plurality of failure candidate information. According to claim 1,
The tiling display device of claim 1 , wherein the first interface circuit and the second interface circuit are implemented as a Serial Peripheral Interface (SPI).

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