KR20230093394A - Semiconductor memory device and electronic system including the same - Google Patents

Abstract

A semiconductor memory device capable of improving device performance and reliability is provided. A semiconductor memory device includes a first stack including a substrate including a cell region and an alignment region around the cell region, a first mold structure including a plurality of first gate electrodes on the cell region, and a first stack structure on the alignment region. , a second mold structure including a plurality of second gate electrodes on the first mold structure, and a second stack including the second stack structure on the first stack structure, extending in a vertical direction intersecting the top surface of the substrate, A channel structure penetrating the first mold structure and the second mold structure, extending in a vertical direction, penetrating the first stacked structure, and covering a first alignment pattern including a first element and an upper surface of the first alignment pattern; A second alignment pattern overlapping the first alignment pattern in a vertical direction is included in the first liner film including the first element and a second element different from the first element, and the second laminated structure.

Description

Semiconductor memory device and electronic system including it {SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory device and an electronic system including the same. More specifically, the present invention relates to a semiconductor memory device including three-dimensionally arranged memory cells and an electronic system including the same.

It is required to increase the degree of integration of semiconductor memory devices in order to meet the excellent performance and low price demanded by consumers. In the case of a semiconductor memory device, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required.

In the case of a two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for miniaturization of the pattern, although the degree of integration of the 2D semiconductor device is increasing, it is still limited. Accordingly, three-dimensional semiconductor devices having three-dimensionally arranged memory cells have been proposed.

A technical problem to be solved by the present invention is to provide a semiconductor memory device capable of improving device performance and reliability.

Another technical problem to be solved by the present invention is to provide an electronic system including a semiconductor memory device capable of improving device performance and reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor memory device according to some embodiments for achieving the above technical problem provides a substrate including a cell region and an alignment region around the cell region, a first mold structure including a plurality of first gate electrodes on the cell region, and alignment. A first stack including a first stacked structure on a region, a second mold structure including a plurality of second gate electrodes on a first mold structure, and a second stack including a second stacked structure on the first stacked structure; A channel structure extending in a vertical direction intersecting the upper surface of the substrate and penetrating the first mold structure and the second mold structure; A second alignment overlapping the first alignment pattern in the vertical direction within the pattern, the first liner film covering the upper surface of the first alignment pattern and including a first element and a second element different from the first element, and the second laminated structure contains the pattern.

An electronic system according to some embodiments for achieving the other technical problem is a semiconductor memory device including a main substrate, a peripheral circuit structure on the main substrate, and a cell structure stacked on the peripheral circuit structure, and a semiconductor on the main substrate. A controller electrically connected to the memory device, wherein the cell structure includes: a substrate including a cell region and an alignment region around the cell region; a first mold structure including a plurality of first gate electrodes on the cell region; A first stack including the first stacked structure on the alignment area, a second mold structure including a plurality of second gate electrodes on the first mold structure, and a second stack including the second stacked structure on the first mold structure. A stack; a channel structure extending in a vertical direction crossing the upper surface of the substrate and penetrating the first mold structure and the second mold structure; extending in a vertical direction and penetrating the first laminated structure; A first alignment pattern that forms a layer, a first liner film covering an upper surface of the alignment pattern and including a first element and a second element different from the first element, and overlapping the first alignment pattern in the vertical direction within the second laminated structure. It includes a second alignment pattern that

Details of other embodiments are included in the detailed description and drawings.

1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.
2 is an exemplary circuit diagram illustrating a semiconductor memory device according to some embodiments.
3 is a schematic layout diagram illustrating a semiconductor memory device according to some embodiments.
4 is a cross-sectional view taken along line AA of FIG. 3 .
FIG. 5 is an enlarged view for explaining a region Q1 of FIG. 4 .
FIG. 6 is an enlarged view for explaining a region Q2 of FIG. 4 .
FIG. 7 is an enlarged view for explaining the R1 region of FIG. 4 .
8 is a diagram for describing a semiconductor memory device according to some embodiments.
FIG. 9 is an enlarged view for explaining the R1 region of FIG. 8 .
10 is a diagram for describing a semiconductor memory device according to some embodiments.
11 to 21 are intermediate diagrams for explaining a method of manufacturing a semiconductor memory device according to some embodiments.
22 is an exemplary block diagram for describing an electronic system in accordance with some embodiments.
23 is an exemplary perspective view for describing an electronic system according to some embodiments.
FIG. 24 is a schematic cross-sectional view taken along line II of FIG. 23 .

In this specification, although first, second, etc. are used to describe various elements or components, these elements or components are not limited by these terms, of course. These terms are only used to distinguish one element or component from another. Accordingly, it goes without saying that the first element or component mentioned below may also be the second element or component within the technical spirit of the present invention.

Hereinafter, a semiconductor memory device according to example embodiments will be described with reference to FIGS. 1 to 7 .

1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 1 , a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30 .

The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through a bit line BL, a word line WL, at least one string select line SSL, and at least one ground select line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through a word line WL, a string select line SSL, and a ground select line GSL. Also, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit line BL.

The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the semiconductor memory device 10, and may receive data (DATA) from a device outside the semiconductor memory device 10. ) can be sent and received. The peripheral circuit 30 may include a control logic 37 , a row decoder 33 and a page buffer 35 . Although not shown, the peripheral circuit 30 includes an input/output circuit, a voltage generating circuit generating various voltages required for operation of the semiconductor memory device 10, and correcting errors in data DATA read from the memory cell array 20. It may further include various sub-circuits such as an error correction circuit for

The control logic 37 may be connected to the row decoder 33, the input/output circuit and the voltage generation circuit. The control logic 37 may control overall operations of the semiconductor memory device 10 . The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust voltage levels provided to the word line WL and the bit line BL when a memory operation such as a program operation or an erase operation is performed.

The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL of the selected memory cell blocks BLK1 to BLKn. ), at least one string selection line (SSL) and at least one ground selection line (GSL) may be selected. Also, the row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a writer driver or a sense amplifier. Specifically, when a program operation is performed, the page buffer 35 operates as a write driver to apply a voltage according to data DATA to be stored in the memory cell array 20 to the bit line. Meanwhile, when a read operation is performed, the page buffer 35 operates as a sense amplifier to sense data DATA stored in the memory cell array 20 .

2 is an exemplary circuit diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 2 , a memory cell array (eg, 20 of FIG. 1 ) of a semiconductor memory device according to some embodiments includes a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR). include them

The plurality of bit lines BL may be two-dimensionally arranged in a plane including the first direction X and the second direction Y. For example, each of the bit lines BL may extend in the second direction Y and may be spaced apart from each other and arranged along the first direction X. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and the ground select transistor GST and the string select transistor ( It may include a plurality of memory cell transistors MCT disposed between the SSTs. Each of the memory cell transistors MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. Also, a ground select line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2n, and a string select line SSL may be disposed between the common source line CSL and the bit line BL. The ground select line GSL may be used as a gate electrode of the ground select transistor GST, the word lines WL11 to WL1n and WL21 to WL2n may be used as gate electrodes of the memory cell transistors MCT, and the string The selection line SSL may be used as a gate electrode of the string selection transistor SST.

3 is a schematic layout diagram illustrating a semiconductor memory device according to some embodiments. 4 is a cross-sectional view taken along line A-A of FIG. 3 . FIG. 5 is an enlarged view for explaining a region Q1 of FIG. 4 . FIG. 6 is an enlarged view for explaining a region Q2 of FIG. 4 . FIG. 7 is an enlarged view for explaining the R1 region of FIG. 4 .

Referring to FIGS. 3 to 7 , a semiconductor memory device according to some embodiments includes a cell structure (CELL) and a peripheral circuit structure (PERI).

The cell structure CELL includes a cell substrate 100, mold structures MS1 and MS2, stacked structures SS1 and SS2, alignment patterns AP1 and AP2, interlayer insulating films 140a and 140b, a channel structure CS, A word line cutting region WC, a bit line BL, a gate contact 162 and a cell interconnection structure 180 may be included.

The cell substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the cell substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the cell substrate 100 may include impurities. For example, the cell substrate 100 may include n-type impurities (eg, phosphorus (P), arsenic (As), etc.).

The cell substrate 100 may include a cell array area CAR and an extension area EXT.

A memory cell array (eg, 20 in FIG. 1 ) including a plurality of memory cells may be formed in the cell array area CAR. For example, a channel structure CS, a bit line BL, and gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, SSL2, etc. described below are disposed in the cell array region CAR. It can be. In the following description, the surface of the cell substrate 100 on which the memory cell array is disposed may be referred to as a front side of the cell substrate 100 . Conversely, a surface of the cell substrate 100 opposite to the front surface of the cell substrate 100 may be referred to as a back side of the cell substrate 100 .

The extension area EXT may be disposed around the cell array area CAR. In the extension region EXT, gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, which will be described later, may be stacked in a stepwise manner.

In some embodiments, the cell substrate 100 may further include a through region THR and an alignment region AKR. The through region THR may be disposed inside the cell array region CAR and the extension region EXT, or may be disposed outside the cell array region CAR and the extension region EXT. A through via 166 to be described later may be disposed in the through region THR. The alignment area AKR may be disposed around the cell array area CAR. The alignment area AKR may be disposed outside the extension area EXT and the through area THR.

In some embodiments, the alignment area (AKR) may be disposed in the scribe lane area. For example, the scribe lane area may be arranged around a cell array area (CAR). As another example, the scribe lane area may be arranged around the cell array area (CAR), the extension area (EXT), and the through area (THR).

The insulating substrate 101 may be formed in the cell substrate 100 of the extended area EXT. The insulating substrate 101 may be formed in the cell substrate 100 of the alignment area AKR. The insulating substrate 101 may form an insulating region in the cell substrate 100 of the extended region EXT. The insulating substrate 101 may form an insulating region in the cell substrate 100 of the alignment region AKR. The insulating substrate 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but is not limited thereto. In some embodiments, the insulating substrate 101 may be formed in the through region THR of the cell substrate 100 .

It is shown that only the lower surface of the insulating substrate 101 is coplanar with the lower surface of the cell substrate 100, but this is only exemplary. As another example, the lower surface of the insulating substrate 101 may be lower than the lower surface of the cell substrate 100 .

The mold structures MS1 and MS2 may be formed on the entire surface of the cell substrate 100 . The mold structures MS1 and MS2 include a plurality of gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 stacked on the cell substrate 100 and a plurality of mold insulating layers 110, 115) may be included. Each of the gate electrodes (ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2) and each of the mold insulating films 110 and 115 have a layered structure extending parallel to the front surface of the cell substrate 100. can be The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 may be sequentially stacked on the cell substrate 100 while being spaced apart from each other by mold insulating layers 110 and 115.

In some embodiments, the mold structures MS1 and MS2 may include a first mold structure MS1 and a second mold structure MS2 sequentially stacked on the cell substrate 100 .

The first mold structure MS1 may include first gate electrodes ECL, GSL1 , GSL2 , WL11 to WL1n and first mold insulating layers 110 that are alternately stacked on the cell substrate 100 . In some embodiments, the first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n may include an erase control line ECL, a ground select line GSL1 and GSL2 sequentially stacked on the cell substrate 100, and a plurality of It may include first word lines WL11 to WL1n. The ground select lines GSL1 and GSL2 may include a first ground select line GSL1 and a second ground select line GSL2 sequentially stacked. It is shown that the first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n only include two ground select lines GSL1 and GSL2, but this is only exemplary, and the first gate electrodes ECL, GSL1, Of course, GSL2, WL11 to WL1n) may include three or more ground selection lines. In some other embodiments, the erase control line (ECL) may be omitted.

The second mold structure MS2 may include second gate electrodes WL21 to WL2n , SSL1 , and SSL2 and second mold insulating layers 115 that are alternately stacked on the first mold structure MS1 . In some embodiments, the second gate electrodes WL21 to WL2n, SSL1, and SSL2 may include a plurality of second word lines WL21 to WL2n and a string select line SSL1 sequentially stacked on the first mold structure MS1. , SSL2). The string selection lines SSL1 and SSL2 may include a first string selection line SSL1 and a second string selection line SSL2 sequentially stacked. Although the second gate electrodes WL21 to WL2n, SSL1, and SSL2 are shown only including two string select lines SSL1 and SSL2, this is only exemplary, and the second gate electrodes WL21 to WL2n, SSL1, Of course, SSL2) may include three or more string selection lines.

In some embodiments, a protective layer 120 may be further included on the first mold structure MS1 . The protective layer 120 may be disposed between the first mold structure MS1 and the second mold structure MS2. The protective layer 120 may cover the first mold structure MS1. The protective layer 120 may include, for example, tetraethyl orthosilicate (TEOS).

The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 are each made of a conductive material such as metal such as tungsten (W), cobalt (Co), or nickel (Ni) or silicon. It may include a semiconductor material such as, but is not limited thereto.

Each of the mold insulating layers 110 and 115 may include an insulating material such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

In some embodiments, the mold structures MS1 and MS2 of the through region THR may include a plurality of mold sacrificial layers 112 and 117 alternately stacked on the cell substrate 100 and/or the insulating substrate 101 , and A plurality of mold insulating layers 110 and 115 may be included. Each of the mold sacrificial layers 112 and 117 and each of the mold insulating layers 110 and 115 may have a layered structure extending parallel to the upper surface of the cell substrate 100 . The mold sacrificial layers 112 and 117 may be sequentially stacked on the cell substrate 100 while being spaced apart from each other by the mold insulating layers 110 and 115 .

In some embodiments, the first mold structure MS1 of the through region THR may include first mold sacrificial layers 112 and first mold insulating layers 110 that are alternately stacked on the cell substrate 100 . The second mold structure MS2 of the through region THR may include second mold sacrificial layers 117 and second mold insulating layers 115 alternately stacked on the first mold structure MS1. can

Each of the mold sacrificial layers 112 and 117 may include an insulating material such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. In some embodiments, the mold sacrificial layers 112 and 117 may include a material having an etch selectivity with respect to the mold insulating layers 110 and 115 . For example, the mold insulating layers 110 and 115 may include silicon oxide, and the mold sacrificial layers 112 and 117 may include silicon nitride.

Although not shown, the interlayer insulating films 140a and 140b may be formed on the cell substrate 100 to cover the mold structures MS1 and MS2 . In some embodiments, the interlayer insulating films 140a and 140b may include a first interlayer insulating film 140a and a second interlayer insulating film 140b sequentially stacked on the cell substrate 100 . The first interlayer insulating layer 140a may cover the first mold structure MS1 , and the second interlayer insulating layer 140b may cover the second mold structure MS2 . The interlayer insulating layers 140a and 140b may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide, but is not limited thereto.

The channel structure CS may be formed in the mold structures MS1 and MS2 of the cell array region CAR. The channel structure CS may extend in a vertical direction crossing the top surface of the cell substrate 100 (hereinafter referred to as a third direction Z) and pass through the mold structures MS1 and MS2 . For example, the channel structure CS may have a pillar shape (eg, a cylindrical shape) extending in the third direction Z. Accordingly, the channel structure CS may cross each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. In some embodiments, the channel structure CS may have a bent portion between the first mold structure MS1 and the second mold structure MS2.

The channel structure CS may include a first channel structure CS1 and a second channel structure CS2. The first channel structure CS1 may pass through the first mold structure MS1. The second channel structure CS2 may pass through the second mold structure MS2. An upper surface of the first channel structure CS1 and a lower surface of the second channel structure CS2 may be connected. The width of the upper surface of the first channel structure CS1 may be greater than that of the upper surface of the second channel structure CS2. In other words, the uppermost diameter of the first channel structure CS1 may be greater than the lowermost diameter of the second channel structure CS2. Here, the uppermost part of the first channel structure CS1 is connected to the lowermost part of the second channel structure CS2.

As shown in FIGS. 5 and 7 , the channel structure CS may include a semiconductor pattern 130 and a data storage layer 132 .

The semiconductor pattern 130 may extend in the third direction (Z) and pass through the mold structures MS1 and MS2. Although the semiconductor pattern 130 is illustrated only in a cup shape, this is only exemplary. For example, the semiconductor pattern 130 may have various shapes such as a cylindrical shape, a square cylinder shape, and a filled pillar shape. The semiconductor pattern 130 may include, for example, a semiconductor material such as single-crystal silicon, poly-crystal silicon, an organic semiconductor material, and a carbon nanostructure, but is not limited thereto.

The information storage layer 132 may be interposed between the semiconductor pattern 130 and the respective gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the information storage layer 132 may extend along an outer surface of the semiconductor pattern 130 . The information storage layer 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a higher dielectric constant than silicon oxide. The high dielectric constant material may be, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

In some embodiments, the information storage layer 132 may be formed of a multilayer. For example, as shown in FIG. 5 , the information storage layer 132 includes a tunnel insulating layer 132a, a charge storage layer 132b, and a blocking insulating layer 132c sequentially stacked on the outer surface of the semiconductor pattern 130. can include

The tunnel insulating layer 132a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )). The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating layer 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )).

In some embodiments, the channel structure CS may further include a filling pattern 134 . The filling pattern 134 may be formed to fill the inside of the cup-shaped semiconductor pattern 130 . The filling pattern 134 may include an insulating material, for example, silicon oxide, but is not limited thereto.

A semiconductor memory device according to some embodiments may further include a first liner layer 121 . The first liner film 121 may be disposed within the protective layer 120 . The first liner film 121 may be disposed on the upper surface of the first channel structure CS1. The first liner film 121 may surround a lowermost portion of the second channel structure CS2 . In other words, the first liner film 121 may surround a portion of the second channel structure CS2 connected to the first channel structure CS1. The first liner film 121 may have a donut shape surrounding the second channel structure CS2 . The outer diameter of the first liner layer 121 may be the same as the upper surface of the first channel structure CS1 . However, it is not limited thereto.

The first liner film 121 may be a compound containing carbon. The first liner layer 121 may include, for example, silicon carbide (SiC). The first liner film 121 may include the same material as the second liner film 122 to be described later.

In some embodiments, the channel structure CS may further include a channel pad 136 . The channel pad 136 may be formed to be connected to an upper portion of the semiconductor pattern 130 . The channel pad 136 may include, for example, polysilicon doped with impurities, but is not limited thereto.

In some embodiments, the plurality of channel structures CS may be arranged in a zigzag shape. For example, as shown in FIG. 3 , the plurality of channel structures CS may be alternately arranged in the first direction X and the second direction Y, which are parallel to the upper surface of the cell substrate 100 . The plurality of channel structures CS arranged in a zigzag pattern may further improve the degree of integration of the semiconductor memory device. In some embodiments, the plurality of channel structures CS may be arranged in a honeycomb shape.

In some embodiments, the dummy channel structure DCH may be formed in the mold structures MS1 and MS2 of the extension area EXT. The dummy channel structure DCH may be formed in a shape similar to that of the channel structure CS to reduce stress applied to the mold structures MS1 and MS2 in the extension region EXT.

In some embodiments, first source structures 102 and 104 may be formed on the cell substrate 100 . The first source structures 102 and 104 may be interposed between the cell substrate 100 and the mold structures MS1 and MS2. For example, the first source structures 102 and 104 may extend along the upper surface of the cell substrate 100 . The first source structures 102 and 104 may be formed to be connected to the semiconductor pattern 130 of the channel structure CS. For example, as shown in FIG. 5 , the first source structures 102 and 104 may pass through the information storage layer 132 and contact the semiconductor pattern 130 . The first source structures 102 and 104 may serve as a common source line (eg, CSL of FIG. 2 ) of the semiconductor memory device. The first source structures 102 and 104 may include, for example, impurity-doped polysilicon or metal, but are not limited thereto.

In some embodiments, the channel structure CS may pass through the first source structures 102 and 104 . For example, a lower portion of the channel structure CS may pass through the first source structures 102 and 104 and may be disposed in the cell substrate 100 .

In some embodiments, the first source structures 102 and 104 may be formed of multilayers. For example, the first source structures 102 and 104 may include a first source layer 102 and a second source layer 104 sequentially stacked on the cell substrate 100 . The first source layer 102 and the second source layer 104 may each include impurity-doped polysilicon or impurity-non-doped polysilicon, but are not limited thereto. The first source layer 102 may contact the semiconductor pattern 130 and provide a common source line (eg, CSL of FIG. 2 ) of the semiconductor memory device. The second source layer 104 may be used as a support layer to prevent the mold stack from collapsing or collapsing in a replacement process for forming the first source layer 102 .

Although not shown, a base insulating layer may be interposed between the cell substrate 100 and the first source structures 102 and 104 . The base insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

In some embodiments, the first source structures 102 and 104 may not be formed within the extension region EXT where the insulating substrate 101 is formed. It is shown that the upper surface of the insulating substrate 101 is coplanar with the upper surface of the first source structures 102 and 104, but this is only exemplary. As another example, the top surface of the insulating substrate 101 may be higher than the top surfaces of the first source structures 102 and 104 .

In some embodiments, a source sacrificial layer 103 may be formed on a portion of the cell substrate 100 . For example, the source sacrificial layer 103 may be formed on a portion of the cell substrate 100 in the extended area EXT. The source sacrificial layer 103 may include a material having an etch selectivity with respect to the mold insulating layers 110 and 115 . For example, the mold insulating layers 110 and 115 may include silicon oxide, and the source sacrificial layer 103 may include silicon nitride. The source sacrificial layer 103 may be a layer remaining after a portion thereof is replaced with the first source layer 102 during the manufacturing process of the first source structures 102 and 104 .

Each of the block separation region WCf, the first partial separation region WC1, and the second partial separation region WC2 may extend in the first direction X to cut the mold structures MS1 and MS2. The block separation region WCf may completely cut the mold structures MS1 and MS2. For example, the block separation area WCf may continuously extend in the first direction X. The partial isolation region WC may partially cut the mold structures MS1 and MS2, respectively.

The mold structures MS1 and MS2 are divided by block isolation regions WCf and/or partial isolation regions WC arranged along the second direction Y to form a plurality of memory cell blocks (eg, BLK1 in FIG. 1 ). ~BLKn) can be formed. For example, as shown in FIG. 3 , one row of partial separation regions WC may be formed between two adjacent block separation regions WCf. The first row of partial isolation regions WC is separated into two memory cell blocks (eg, a first cell block BLK1 and a second cell block BLK1) by separating the mold structures MS1 and MS2 between the two block isolation regions WCf. A cell block BLK2) may be defined.

It is shown that only one row of partial separation regions WC are disposed between two adjacent block separation regions WCf, but this is only exemplary. As another example, two or more rows of first partial separation regions WC1 may be disposed between two adjacent block separation regions WCf.

The string separation structure SC may extend in the first direction X and cut the string selection lines SSL1 and SSL2. For example, the string separation structure SC formed in the first cell block BLK1 may divide the string selection lines SSL1 and SSL2 into a first region I and a second region II, respectively. Accordingly, the first string selection line SSL1 of the first region I and the first string selection line SSL1 of the second region II may be separated and separately controlled, and the first region I The second string selection line SSL2 of the second region II and the second string selection line SSL2 of the second region II may be separated and separately controlled.

The string isolation structure SC may include an insulating material such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The bit line BL may be formed on the mold structures MS1 and MS2. The bit line BL may extend in the second direction Y and cross the block separation region WCf. Also, the bit line BL may extend in the second direction Y and be connected to a plurality of channel structures CS arranged along the second direction Y. For example, a bit line contact 182 connected to upper portions of each of the channel structures CS may be formed in the second interlayer insulating layer 140b. The bit line BL may be electrically connected to the channel structures CS through the bit line contact 182 .

The cell contact 162 may be connected to the respective gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the cell contact 162 extends in the third direction (Z) within the interlayer insulating films 140a and 140b to form respective gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, SSL2) can be connected. In some embodiments, the cell contact 162 may have a bent portion between the first mold structure MS1 and the second mold structure MS2 .

The source contact 164 may be connected to the first source structures 102 and 104 . For example, the source contact 164 may extend in the third direction (Z) within the interlayer insulating films 140a and 140b and be connected to the cell substrate 100 . In some embodiments, the source contact 164 may have a bent portion between the first mold structure MS1 and the second mold structure MS2.

The through via 166 may be disposed in the through area THR. For example, the through via 166 may extend in the third direction Z within the mold structures MS1 and MS2 of the through area THR. In some embodiments, the through via 166 may have a bent portion between the first mold structure MS1 and the second mold structure MS2 . Although the through via 166 is shown only penetrating the mold structures MS1 and MS2, this is only exemplary. As another example, the through-via 166 may be disposed outside the mold structures MS1 and MS2 and may not penetrate the mold structures MS1 and MS2 .

The cell contact 162 , the source contact 164 , and the through via 166 may be connected to the first interconnection structure 180 on the interlayer insulating films 140a and 140b, respectively. For example, the first inter-wire insulating layer 142 may be formed on the second inter-layer insulating layer 140b. The first interconnection structure 180 may be formed in the first interconnection insulating layer 142 . The cell contact 162 , the source contact 164 , and the through via 166 may be connected to the first interconnection structure 180 through the contact via 184 . Although not specifically shown, the first wiring structure 180 may be connected to the bit line BL.

The alignment area AKR may be disposed around the cell array area CAR. A first stacked structure SS1 and a second stacked structure SS2 described below may be stacked in the alignment area AKR. The alignment area AKR may be defined as an area where the alignment patterns AP1 and AP2 are disposed on the cell substrate 100 . However, it is not limited thereto. For example, the alignment area AKR may be disposed in a scribe lane area, and the scribe lane area may be disposed around the cell substrate 100 .

In some embodiments, the first stacked structure SS1 of the alignment area AKR includes a plurality of first mold sacrificial layers 112 alternately stacked on the cell substrate 100 and/or the insulating substrate 101 , and It may include a plurality of first mold insulating layers 110 . The first mold sacrificial layer 112 and the first mold insulating layer 110 may have a layered structure extending parallel to the upper surface of the cell substrate 100 . The first mold sacrificial layers 112 may be sequentially stacked on the cell substrate 100 and/or the insulating substrate 101 while being spaced apart from each other by the first mold insulating layer 110 .

The second stack structure SS2 may include a plurality of second mold sacrificial layers 117 and a plurality of second mold insulating layers 115 that are alternately stacked on the first stack structure SS1 . The second stacked structure SS2 may include a second alignment pattern AP2.

A first stack ST1 and a second stack ST2 may be sequentially formed on the cell substrate 100 . The first stack ST1 may include a first mold structure MS1 and a first stacked structure SS1. The second stack ST2 may include a second mold structure MS2 and a second stacked structure SS2. The first stack ST1 and the second stack ST2 may be divided into a channel structure CS. Specifically, the first stack ST1 may be a portion where the first channel structure CS1 is formed, and the second stack ST2 may be a portion where the second channel structure CS2 is formed. Also, the first stack ST1 may be a portion where the first alignment pattern AP1 is formed, and the second stack ST2 may be a portion where the second alignment pattern AP2 is formed.

Hereinafter, the alignment patterns AP1 and AP2 in the alignment area AKR will be described in detail with reference to FIGS. 4 and 6 .

The first alignment pattern AP1 may be formed in the alignment area AKR. The first alignment pattern AP1 may extend in a direction perpendicular to the upper surface of the cell substrate 100 and pass through the first stacked structure SS1 . The first alignment pattern AP1 may pass through the upper surface of the insulating substrate 101 . That is, one end of the first alignment pattern AP1 may be disposed inside the insulating substrate 101 . The other end of the first alignment pattern AP1 may protrude beyond the upper surface of the first stacked structure SS1.

Specifically, the first mold sacrificial layer 112 may be disposed on the top of the first stack structure SS1 . An uppermost first mold insulating layer 110 may be disposed under the uppermost first mold sacrificial layer 112 . An upper portion of the first alignment pattern AP1 may protrude beyond the uppermost first mold insulating layer 110 . A top surface of the first alignment pattern AP1 may be disposed higher than a top surface of the uppermost first mold insulating layer 110 . The first mold sacrificial layer 112 may include an opening. The opening may expose an upper portion of the first alignment pattern AP1.

The protective layer 120 may be disposed on the top surface of the first stack structure SS1 . The protective layer 120 may be formed along the top surface of the uppermost first mold sacrificial layer 112 of the first stack structure SS1 . The protective layer 120 may include an opening like the uppermost first mold sacrificial layer 112 . The opening may expose an upper portion of the first alignment pattern AP1.

The second liner layer 122 may be disposed on the first stacked structure SS1 . The second liner layer 122 may be disposed between the first and second stacked structures SS1 and SS2 . The second liner layer 122 may be disposed in the opening of the uppermost first mold insulating layer 110 . The second liner layer 122 may cover the upper surface of the first alignment pattern AP1. The second liner layer 122 may be disposed on the first alignment pattern AP1. The second liner layer 122 may be formed along the protruding portion of the first alignment pattern AP1. In other words, the second liner layer 122 may cover the protruding portion of the first alignment pattern AP1 .

The third liner layer 123 may be disposed on the first stacked structure SS1. The third liner layer 123 may be disposed between the first and second stacked structures SS1 and SS2 . The third liner layer 123 may be disposed in the opening of the uppermost first mold insulating layer 110 . The third liner layer 123 may be formed along the top surface of the uppermost first mold sacrificial layer 112 . That is, the third liner layer 123 may cover the top surface of the uppermost first mold sacrificial layer 112 exposed by the opening.

The first alignment pattern AP1 may include the first element E1. The second liner film 122 may include a first element E1 and a second element E2. The first element E1 is different from the second element E2. The third liner layer 123 may include the second element E2.

In some embodiments, the first element E1 may include carbon. The second element E2 may include silicon. The first alignment pattern AP1 may include, for example, an amorphous carbon layer. The second liner layer 122 may include, for example, silicon carbide (SiC).

In the alignment area AKR, the second stacked structure SS2 may include the second alignment pattern AP2. The second stacked structure SS2 may be disposed on the first stacked structure SS1 and the first alignment pattern AP1. The second stacked structure SS2 may be disposed on the protective layer 120 , the second liner film 122 and the third liner film 123 . A portion of the second stacked structure SS2 may be disposed in the opening of the first stacked structure SS1.

The second alignment pattern AP2 may be a portion protruding in the length direction of the first alignment pattern AP1 in the second stacked structure SS1 . Here, the length direction of the first alignment pattern AP1 is the direction in which the first alignment pattern AP1 extends. As will be described later, the second stacked structure SS2 may be stacked on the first stacked structure SS1. Since the first alignment pattern AP1 protrudes from the upper surface of the first stack structure SS1 , the second alignment pattern AP2 may be formed during the formation of the second stack structure SS2 . The second alignment pattern AP2 may have a convex shape according to the shape of the protruding first alignment pattern AP1. The second alignment pattern AP2 may be formed at a portion overlapping the first alignment pattern AP1 in the longitudinal direction. That is, a portion overlapping the first alignment pattern AP1 in the longitudinal direction within the second stacked structure SS2 may protrude compared to other portions.

The peripheral circuit area PERI may include the peripheral circuit board 200 , the peripheral circuit element PT, and the second interconnection structure 260 .

The peripheral circuit board 200 may be disposed below the cell substrate 100 . For example, the upper surface of the peripheral circuit board 200 may face the lower surface of the cell substrate 100 . The peripheral circuit board 200 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a Silicon-On-Insulator (SOI) substrate or a Germanium-On-Insulator (GOI) substrate.

The peripheral circuit element PT may be formed on the peripheral circuit board 200 . The peripheral circuit element PT may constitute a peripheral circuit (eg, 30 in FIG. 1 ) that controls the operation of the semiconductor memory device. For example, the peripheral circuit element PT may include a control logic (eg, 37 of FIG. 1 ), a row decoder (eg, 33 of FIG. 1 ), and a page buffer (eg, 35 of FIG. 1 ). In the following description, a surface of the peripheral circuit board 200 on which the peripheral circuit element PT is disposed may be referred to as a front side of the peripheral circuit board 200 . Conversely, a surface of the peripheral circuit board 200 opposite to the front surface of the peripheral circuit board 200 may be referred to as a back side of the peripheral circuit board 200 .

The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit element PT may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors. may be

In some embodiments, the rear surface of the cell substrate 100 may face the front surface of the peripheral circuit board 200 . For example, a second inter-wire insulating layer 240 may be formed on the entire surface of the peripheral circuit board 200 to cover the peripheral circuit element PT. The cell substrate 100 and/or the insulating substrate 101 may be stacked on the upper surface of the second inter-wire insulating layer 240 .

The first interconnection structure 180 may be connected to the peripheral circuit element PT through the through via 166 . For example, the second wiring structure 260 connected to the peripheral circuit element PT may be formed in the second inter-wire insulating film 240 . The through via 166 may extend in the third direction (Z) to connect the first interconnection structure 180 and the second interconnection structure 260 . Through this, the bit line BL, each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, and/or the first source structures 102 and 104 are connected to peripheral circuit elements ( PT) can be electrically connected.

In some embodiments, the through via 166 may pass through the insulating substrate 101 and connect the first wiring structure 180 and the second wiring structure 260 . Through this, the through via 166 may be electrically separated from the cell substrate 100 .

8 is a diagram for describing a semiconductor memory device according to some embodiments. FIG. 9 is an enlarged view for explaining the R1 region of FIG. 8 . For convenience of description, the description will focus on points different from those described in FIGS. 1 to 7 .

Referring to FIGS. 8 and 9 , a semiconductor memory device according to some embodiments includes a second source structure 106 .

The second source structure 106 may be formed on the cell substrate 100 . Although the lower part of the second source structure 106 is illustrated only being disposed within the cell substrate 100, this is only exemplary. The second source structure 106 may be connected to the semiconductor pattern 130 of the channel structure CS. For example, the semiconductor pattern 130 may pass through the information storage layer 132 and contact the upper surface of the second source structure 106 . The second source structure 106 may be formed, for example, from the cell substrate 100 by a selective epitaxial growth process, but is not limited thereto.

In some embodiments, an upper surface of the second source structure 106 may cross some of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, a top surface of the second source structure 106 may be formed higher than a top surface of the erase control line ECL. In this case, a gate insulating layer 110S may be interposed between the second source structure 106 and a gate electrode (eg, an erase control line ECL) crossing the second source structure 106 .

10 is a diagram for describing a semiconductor memory device according to some embodiments. For convenience of description, the description will focus on points different from those described in FIGS. 1 to 7 .

Referring to FIG. 10 , in the semiconductor memory device according to some embodiments, the front surface of the cell substrate 100 faces the front surface of the peripheral circuit board 200 .

For example, a semiconductor memory device according to some embodiments may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a memory cell region (CELL) is fabricated on a first wafer (eg, cell substrate 100), and a second wafer (eg, peripheral circuit board 200) different from the first wafer is fabricated. ) on the peripheral circuit area PERI, and then connecting the upper chip and the lower chip to each other by a bonding method.

For example, the bonding method may refer to a method of electrically connecting the first bonding metal 190 formed on the uppermost metal layer of the upper chip and the second bonding metal 290 formed on the uppermost metal layer of the lower chip to each other. there is. For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only exemplary, and the first bonding metal 190 and the second bonding metal 290 may be formed of various other metals such as aluminum (Al) or tungsten (W).

As the first bonding metal 190 and the second bonding metal 290 are bonded, the first wiring structure 180 may be connected to the second wiring structure 260 . Through this, the bit line BL, each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, and/or the first source structures 102 and 104 are connected to peripheral circuit elements ( PT) can be electrically connected.

11 to 21 are intermediate diagrams for explaining a method of manufacturing a semiconductor memory device according to some embodiments. FIG. 14 is an enlarged view for explaining a region Q2 of FIG. 13 . FIG. 18 is an enlarged view for explaining a region Q2 of FIG. 17 .

Referring to FIG. 11 , a first stacked structure SS1 , a first channel hole CH1 , and an alignment pattern hole APH may be formed on the cell substrate 100 and/or the insulating substrate 101 .

The first stack structure SS1 may include a plurality of first mold insulating layers 110 and a plurality of first mold sacrificial layers 112 that are alternately stacked. The first mold sacrificial layer 112 may include a material having an etch selectivity with respect to the first mold insulating layer 110 . For example, the first mold insulating layer 110 may include silicon oxide, and the first mold sacrificial layer 112 may include silicon nitride.

In some embodiments, the source sacrificial layer 302 and the second source layer are formed on the cell substrate 100 and/or the insulating substrate 101 before the first stacked structure SS1 of the cell array area CAR is stacked. (104) can be formed. The source sacrificial layer 302 may include a material having an etch selectivity with respect to the first mold insulating layer 110 . For example, the first mold insulating layer 110 may include silicon oxide, and the source sacrificial layer 302 may include silicon nitride. The second source layer 104 may include impurity doped polysilicon or impurity undoped polysilicon, but is not limited thereto.

In some embodiments, the first stacked structure SS1 of the alignment area AKR may be formed on the insulating substrate 101 . However, it is not limited thereto. For example, the first stacked structure SS1 of the alignment area AKR may be formed on the cell substrate 100 . In this case, the cell substrate 100 may include a source sacrificial layer 302 and a second source layer 104 like the cell array region CAR.

In some embodiments, the cell substrate 100 and/or the insulating substrate 101 may be stacked on the peripheral circuit area PERI. For example, the peripheral circuit element PT, the second interconnection structure 260 , and the second interconnection insulating layer 240 may be formed on the peripheral circuit board 200 . The cell substrate 100 and/or the insulating substrate 101 may be stacked on the second inter-wire insulating layer 240 .

The first channel hole CH1 may be formed in the first stacked structure SS1 of the cell array region CAR. The first channel hole CH1 may extend in a direction perpendicular to the upper surface of the cell substrate 100 and pass through the first stacked structure SS1 . The first channel hole CH1 may expose the cell substrate 100 . The alignment pattern hole APH may be formed in the first stacked structure SS1 of the alignment area AKR. The alignment pattern holes APH may extend in a direction perpendicular to the upper surface of the cell substrate 100 and pass through the first stacked structure SS1 . The alignment pattern hole APH may expose the insulating substrate 101 .

In some embodiments, the first channel hole CH1 and the alignment pattern hole APH may be formed at the same level. Here, "same level" means formed by the same manufacturing process. However, it is not limited thereto.

Referring to FIG. 12 , a first sacrificial pattern SP1 , a first alignment pattern AP1 , and a protective layer 120 may be formed on the first stacked structure SS1 .

The first sacrificial pattern SP1 may fill the first channel hole CH1. The first alignment pattern AP1 may fill the alignment pattern hole APH. The first sacrificial pattern SP1 and the first alignment pattern AP1 may be formed at the same level. Each of the first sacrificial pattern SP1 and the first alignment pattern AP1 may include the first element E1. The first element E1 may include, for example, carbon.

In some embodiments, the protective layer 120 may be formed on the first stacked structure SS1 . The protective layer 120 may cover the first stacked structure SS1 . The protective layer 120 may be formed on the first sacrificial pattern SP1 and the first alignment pattern AP1.

Referring to FIGS. 13 and 14 , a pre-liner film 122P may be formed by the first treatment process S1 .

The first treatment process S1 may be, for example, a thermal process or a plasma process. Silicon (Si) may be provided on top surfaces of the first sacrificial pattern SP1 and the first alignment pattern AP1 through the first treatment process S1 . As a result, the pre-liner layer 122P may be formed on the upper surfaces of the first sacrificial pattern SP1 and the upper surface of the first alignment pattern AP1 through the first treatment process S1 . The pre-liner layer 122P may include, for example, silicon carbide (SiC).

Referring to FIG. 15 , a mask layer 120M may be formed on the protective layer 120 .

The mask layer 120M may cover the upper surface of the protective layer 120 in the cell array area CAR. The mask layer 120M may expose a portion of the protective layer 120 in the alignment region AKR. The exposed protective layer 120 may overlap the first alignment pattern AP1. The mask layer 120M may include, for example, a photoresist material. A photoresist material may be formed on the protective layer 120 and a mask layer 120M may be formed through a photo process.

In some embodiments, the process of forming the protective layer 120 and the first treatment process S1 may be omitted. For example, after the first sacrificial pattern SP1 and the first alignment pattern AP1 are formed, a mask layer 120M may be formed on the first stacked structure SS1.

Referring to FIG. 16 , an opening may be formed on the first stacked structure SS1 of the alignment area AKR.

In detail, an etching process may be performed on the first stacked structure SS1 and the protective layer 120 of the alignment region AKR by using the mask layer 120M as a visual mask. Through the etching process, openings may be formed on the protective layer 120 and the first stack structure SS1 . The opening may expose the first alignment pattern AP1 , the pre-liner layer 122P, and the uppermost first mold sacrificial layer 112 .

Referring to FIGS. 17 and 18 , a second treatment process ( S2 ) may be performed to form a second liner film 122 and a third liner film 123 .

Silicon (Si) ions may be supplied on the first sacrificial pattern SP1 and the first alignment pattern AP1 in the second treatment process S2 . The second treatment process S2 may include, for example, a silicon ion implantation process. After the second treatment process ( S2 ), a heat treatment process may be performed. As a result, the second liner film 122 and the third liner film 123 may be formed.

The second liner layer 122 may be formed along an upper portion of the protruding first alignment pattern AP1. The second liner layer 122 may completely cover the exposed portion of the first alignment pattern AP1 . The third liner layer 123 may be formed along the top surface of the uppermost first mold sacrificial layer 112 . The third liner layer 123 may cover the top surface of the uppermost first mold sacrificial layer 112 exposed by the opening.

The second liner layer 122 may include, for example, silicon carbide (SiC), and the third liner layer 123 may include silicon nitride (SiN).

Referring to FIG. 19 , the mask layer 120M may be removed and the protective layer 120 may be exposed.

Specifically, the mask layer 120M may be removed by an ashing process or a strip process. The mask layer 120M may include, for example, an amorphous carbon layer. When the mask layer 120M is removed, the second liner layer 122 may protect the first alignment pattern AP1. That is, the first alignment pattern AP1 may not be removed during the process of removing the mask layer 120M.

Referring to FIG. 20 , a second stacked structure SS2 may be formed on the first stacked structure SS1 .

The second stacked structure SS2 may include a plurality of second mold insulating layers 115 and a plurality of second mold sacrificial layers 117 that are alternately stacked. In the alignment area AKR, the second stacked structure SS2 may be stacked on the first stacked structure SS1 and the first alignment pattern AP1. A second alignment pattern AP2 may be formed in the second stacked structure SS2 . Specifically, along the protruding portion of the first alignment pattern AP1, each layer of the second stacked structure SS2 is stacked in an upwardly protruding shape. As a result, a second alignment pattern AP2 having a convex shape may be formed at a portion overlapping the first alignment pattern AP1. The alignment patterns AP1 and AP2 may be used as align keys in the process of forming the second channel hole CH2 of the second stack ST2.

Referring to FIG. 21 , a channel hole CH may be formed in the second stacked structure SS2 .

Specifically, the second channel hole CH2 may be formed on the second stacked structure SS2 of the cell array region CAR. At this time, the position where the second channel hole CH2 is formed may be aligned by using the second alignment pattern AP2 as an align key. The second channel hole CH2 may be connected to the first channel hole CH1. The second channel hole CH2 may pass through the pre-liner layer 122P disposed on the first channel hole CH1. As a result, the first liner film 121 may be formed. The second channel hole CH2 may expose the first sacrificial pattern SP1. The first sacrificial pattern SP1 may be removed.

Subsequently, the channel structure CS, the mold structures MS1 and MS2, and the wiring structure 180 may be formed.

In the semiconductor memory device according to some embodiments, when the first channel hole CH1 and the second channel hole CH2 are out of alignment, a device defect may occur. The second channel hole CH2 should overlap the first channel hole CH1. To this end, alignment patterns AP1 and AP2 may be used in the alignment area AKR.

Unlike the illustration, when the mask layer 120M is removed when the second liner layer 122 is not present, an upper portion of the first alignment pattern AP1 may be exposed. In this case, when the mask layer 120M is removed, a portion of the first alignment pattern AP1 may be removed together with the mask layer 120M. By removing the protruding portion of the first alignment pattern AP1 , a step between the upper surface of the first stacked structure SS1 and the first alignment pattern AP1 may be lost. When the first alignment pattern AP1 has no step, the second alignment pattern AP2 may not be formed even if the second stacked structure SS2 is stacked.

However, in a semiconductor memory device according to some embodiments, the second liner layer 122 may cover an upper portion of the first alignment pattern AP1. As a result, the second liner layer 122 may protect the first alignment pattern AP1 when the mask layer 120M is removed. That is, the level difference of the top of the first alignment pattern AP1 may be maintained, and the second alignment pattern AP2 may be formed.

Hereinafter, an electronic system including a semiconductor memory device according to example embodiments will be described with reference to FIGS. 1 to 7 and 11 to 21 .

22 is an exemplary block diagram for describing an electronic system in accordance with some embodiments. 23 is an exemplary perspective view for describing an electronic system according to some embodiments. 24 is a schematic cross-sectional view taken along line II of FIG. 23; For convenience of description, parts overlapping with those described above with reference to FIGS. 1 to 21 are briefly described or omitted.

Referring to FIG. 22 , an electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100 . The electronic system 1000 may be a storage device including one or a plurality of semiconductor memory devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) including one or a plurality of semiconductor memory devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device. .

The semiconductor memory device 1100 may be a non-volatile memory device (eg, a NAND flash memory device), and may be, for example, the semiconductor memory device described above with reference to FIGS. 1 to 10 . The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

The first structure 1100F includes a decoder circuit 1110 (e.g. row decoder 33 in FIG. 1), a page buffer 1120 (e.g. page buffer 35 in FIG. 1) and a logic circuit 1130 (e.g. in FIG. 1). It may be a peripheral circuit structure including the control logic 37 of.

The second structure 1100S may include the common source line CSL, the plurality of bit lines BL, and the plurality of cell strings CSTR described above with reference to FIG. 2 . The cell strings CSTR may be connected to the decoder circuit 1110 through a word line WL, at least one string select line SSL, and at least one ground select line GSL. In addition, the cell strings CSTR may be connected to the page buffer 1120 through bit lines BL.

In some embodiments, the common source line (CSL) and the cell string (CSTR) are connected to the decoder circuit 1110 through first connection wires 1115 extending from the first structure 1100F to the second structure 1100S. can be electrically connected. The first connection wire 1115 may correspond to the through via 166 described above with reference to FIGS. 1 to 12 . That is, the through via 166 may electrically connect each of the gate electrodes ECL, GSL, WL, and SSL to the decoder circuit 1110 (eg, the row decoder 33 of FIG. 1).

In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through second connection lines 1125 extending from the first structure 1100F to the second structure 1100S. The second connection wire 1125 may correspond to the through via 166 described above with reference to FIGS. 1 to 10 . That is, the through via 166 may electrically connect the bit lines BL and the page buffer 1120 (eg, the page buffer 35 of FIG. 1 ).

The semiconductor memory device 1100 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 (eg, the control logic 37 of FIG. 1 ). The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210 , a NAND controller 1220 and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100 .

The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200 . The processor 1210 may operate according to predetermined firmware and access the semiconductor memory device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100 . Through the NAND interface 1221, a control command for controlling the semiconductor memory device 1100, data to be written to the memory cell transistors MCT of the semiconductor memory device 1100, and a memory cell of the semiconductor memory device 1100 Data to be read from the transistors MCT may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

23 and 24, an electronic system according to some embodiments includes a main board 2001, a main controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. can include The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through wiring patterns 2005 formed on the main substrate 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, electronic system 2000 may include interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), and the like. According to any one of them, it is possible to communicate with an external host. In some embodiments, electronic system 2000 may operate with power supplied from an external host through connector 2006 . The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes the power supplied from the external host to the main controller 2002 and the semiconductor package 2003 .

The main controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the electronic system 2000 includes the DRAM 2004 , the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . The first semiconductor package 2003a and the second semiconductor package 2003b include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, and adhesive layers disposed on lower surfaces of the semiconductor chips 2200, respectively. 2300 , a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 , and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100 . ) may be included.

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each semiconductor chip 2200 may include an input/output pad 2210 . The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 22 .

In some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the package upper pads 2130 . Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and the package upper pads 2130 of the package substrate 2100 may be electrically connected to each other. ) and electrically connected. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may include a through electrode (Through Silicon Via, TSV) instead of the bonding wire type connection structure 2400. ) may be electrically connected to each other by a connection structure including.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor chips are connected by wiring formed on the interposer substrate. The chips 2200 may be connected to each other.

In some embodiments, package substrate 2100 may be a printed circuit board. The package substrate 2100 includes the package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, and disposed on or exposed through the lower surface of the package substrate body 2120. lower pads 2125 to be used, and internal wires 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120 . The upper pads 2130 may be electrically connected to the connection structures 2400 . The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 through the conductive connection parts 2800 as shown in FIG. 22 .

In an electronic system according to some embodiments, each of the semiconductor chips 2200 may include the semiconductor memory device described above with reference to FIGS. 1 to 7 . For example, each of the semiconductor chips 2200 may include a peripheral circuit area PERI and a memory cell area CELL stacked on the peripheral circuit area PERI. For example, the peripheral circuit area PERI may include the peripheral circuit board 200 and the second interconnection structure 260 described above with reference to FIGS. 3 to 7 . Also, illustratively, the memory cell region CELL includes the cell substrate 100, the mold structures MS1 and MS2, the channel structure CS, and the stacked structures SS1 and SS2 described above with reference to FIGS. 3 to 7 . , alignment patterns AP1 and AP2, and bit lines BL.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100: cell substrate 101: insulating substrate
110: first mold insulating film 112: first mold sacrificial film
115: second mold insulating film 117: second mold sacrificial film
120: protective layer 121: first liner film
122: second liner film 123: third liner film
AP1: first alignment pattern AP2: second alignment pattern
MS1: first mold structure MS2: second mold structure
SS1: First laminated structure SS2: Second laminated structure
ST1: first stack ST2: second stack

Claims (10)

a substrate including a cell region and an alignment region around the cell region;
a first stack including a first mold structure including a plurality of first gate electrodes on the cell region and a first laminated structure on the alignment region;
a second stack including a second mold structure including a plurality of second gate electrodes on the first mold structure and a second stack structure on the first stack structure;
a channel structure extending in a vertical direction intersecting the upper surface of the substrate and penetrating the first mold structure and the second mold structure;
a first alignment pattern extending in the vertical direction, penetrating the first laminated structure, and including a first element;
a first liner film covering an upper surface of the first alignment pattern and including the first element and a second element different from the first element; and
and a second alignment pattern overlapping the first alignment pattern in the vertical direction in the second stacked structure. According to claim 1,
The semiconductor memory device of claim 1 , wherein the first element includes carbon. According to claim 2,
The second element includes silicon (Si), the semiconductor memory device. According to claim 1,
The semiconductor memory device of claim 1, further comprising a protective layer disposed between the first stacked structure and the second stacked structure and non-overlapping with the first alignment pattern in the vertical direction. According to claim 1,
An upper portion of the first alignment pattern protrudes from an upper surface of the first stacked structure,
The semiconductor memory device of claim 1 , wherein the first liner layer extends along an upper portion of the protruding first alignment pattern. According to claim 1,
The channel structure includes a first channel structure penetrating the first mold structure and a second channel structure penetrating the second mold structure,
The upper surface of the first channel structure is connected to the lower surface of the second channel structure,
and a second liner film disposed on an upper surface of the first channel structure and surrounding a lowermost portion of the second channel structure. According to claim 6,
The semiconductor memory device of claim 1 , wherein the second liner layer and the first liner layer include the same material. According to claim 1,
The first stacked structure includes a sacrificial film and an insulating film that are alternately stacked,
The first stacked structure includes an opening exposing the first alignment pattern and an uppermost sacrificial layer;
Further comprising a third liner film formed along the exposed top surface of the uppermost sacrificial film,
The semiconductor memory device of claim 1 , wherein the third liner layer includes the second element. main board;
a semiconductor memory device including a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate; and
A controller electrically connected to the semiconductor memory device on the main substrate;
The cell structure,
A substrate including a cell region and an alignment region around the cell region;
a first stack including a first mold structure including a plurality of first gate electrodes on the cell region and a first stack structure on the alignment region;
a second mold structure including a plurality of second gate electrodes on the first mold structure and a second stack including a second stack structure on the first stack structure;
a channel structure extending in a vertical direction crossing the upper surface of the substrate and penetrating the first mold structure and the second mold structure;
A first alignment pattern extending in the vertical direction, penetrating the first laminated structure, and including a first element;
a first liner film covering an upper surface of the first alignment pattern and including the first element and a second element different from the first element;
and a second alignment pattern overlapping the first alignment pattern in the vertical direction within the second laminated structure. According to claim 9,
The first element includes carbon,
The electronic system of claim 1 , wherein the second element includes silicon (Si).

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