KR20220050852A - Non-volatile memory device and electronic system including the same - Google Patents

Abstract

The present invention provides a non-volatile memory device capable of improving device performance and reliability. The non-volatile memory device comprises: a substrate; a mold structure including a plurality of gate electrodes and a plurality of mold insulation films alternatively stacked and extending in a first direction on the substrate; and a channel structure disposed in a trench through a second direction perpendicular to a first direction. The channel structure includes a blocking insulation film, a charge storing film, and a tunnel insulation film sequentially provided on a sidewall of the trench. The blocking insulation film includes a first region making contact with a gate electrode and a second region making contact with the mold insulation film. A width in a first direction of the first region of the blocking insulation film is greater than a width in a first direction of the second region of the blocking insulation film. A width in the first direction of the charge storing film and a width in the first direction of the tunnel insulation film are constant from a bottom surface of the channel structure to a top surface of the channel structure.

Description

NON-VOLATILE MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

The present invention relates to a non-volatile memory device and an electronic system including the same.

In order to meet the excellent performance and low price demanded by consumers, it is required to increase the density of the non-volatile memory device. In the case of a non-volatile memory device, since the degree of integration is an important factor determining the price of a product, an increased degree of integration is particularly required.

On the other hand, in the case of a two-dimensional or planar nonvolatile memory device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly affected by the level of fine pattern forming technology. However, since ultra-expensive equipment is required for pattern miniaturization, the degree of integration of the 2D nonvolatile memory device is increasing, but is still limited. Accordingly, three-dimensional nonvolatile memory devices including three-dimensionally arranged memory cells have been proposed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile memory device capable of improving device performance and reliability.

Another object of the present invention is to provide an electronic system capable of improving device performance and reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A nonvolatile memory device according to some embodiments of the present invention for achieving the above technical object includes a plurality of gate electrodes and a plurality of mold insulating layers that are alternately stacked on a substrate and extend in a first direction and a channel structure disposed in a trench penetrating the mold structure in a second direction perpendicular to the first direction, wherein the channel structure includes a blocking insulating film sequentially provided on sidewalls of the trench, a charge storage film, and a tunnel insulating film, wherein the blocking insulating film includes a first portion in contact with the gate electrode and a second portion in contact with the mold insulating film, wherein a width of the first portion of the blocking insulating film in the first direction is the second portion of the blocking insulating film The portion is larger than the width in the first direction, and the width in the first direction of the charge storage layer and the width in the first direction of the tunnel insulating layer are constant from the bottom surface of the channel structure toward the top surface of the channel structure.

An electronic system according to some embodiments of the present invention for achieving the above technical object includes a main board, a nonvolatile memory device on the main board, and a controller on the main board, electrically connected to the nonvolatile memory device, A non-volatile memory device includes: a substrate; a channel structure disposed in a trench penetrating in two directions, wherein the channel structure includes a blocking insulating film, a charge storage film, and a tunnel insulating film sequentially provided on sidewalls of the trench, wherein the blocking insulating film is a first contacting gate electrode a first portion and a second portion in contact with the mold insulating film, wherein a width of the first portion of the blocking insulating film in a first direction is greater than a width of the second portion of the blocking insulating film in the first direction, The width in one direction and the width in the first direction of the tunnel insulating layer are constant from the bottom surface of the channel structure toward the top surface of the channel structure.

The details of other embodiments are included in the description and drawings.

1 is an exemplary block diagram illustrating a nonvolatile memory device according to some embodiments.
2 is an exemplary circuit diagram illustrating a nonvolatile memory device according to some embodiments.
3 is an exemplary cross-sectional view illustrating a nonvolatile memory device according to some embodiments.
FIG. 4 is an enlarged view of an area P of FIG. 3 .
5 is a diagram for describing a nonvolatile memory device according to some exemplary embodiments.
6 to 8 are exemplary cross-sectional views for describing a nonvolatile memory device according to some embodiments.
9 to 15 are views sequentially illustrating a process of manufacturing the nonvolatile memory device having the cross section of FIG. 4 .
16 is an exemplary block diagram for describing an electronic system according to some embodiments.
17 is an exemplary perspective view for explaining an electronic system according to some embodiments.
18 is a schematic cross-sectional view taken along line II of FIG. 17 .

Hereinafter, a nonvolatile memory device according to example embodiments will be described with reference to FIGS. 1 to 8 .

1 is an exemplary block diagram illustrating a nonvolatile memory device according to some embodiments.

Referring to FIG. 1 , a nonvolatile memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30 .

The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through a bit line BL, a word line WL, at least one string select line SSL, and at least one ground select line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word line WL, the string select line SSL, and the ground select line GSL. Also, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit line BL.

The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the nonvolatile memory device 10 , and may receive data from an external device of the nonvolatile memory device 10 . (DATA) can be transmitted and received. The peripheral circuit 30 may include a control logic 37 , a row decoder 33 , and a page buffer 35 . Although not shown, the peripheral circuit 30 detects errors in the input/output circuit, the voltage generating circuit generating various voltages necessary for the operation of the nonvolatile memory device 10 , and the data DATA read from the memory cell array 20 . It may further include various sub-circuits such as an error correction circuit for correcting the error.

The control logic 37 may be connected to the row decoder 33 , the input/output circuit, and the voltage generation circuit. The control logic 37 may control the overall operation of the nonvolatile memory device 10 . The control logic 37 may generate various internal control signals used in the nonvolatile memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage level provided to the word line WL and the bit line BL when a memory operation such as a program operation or an erase operation is performed.

The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and at least one word line WL of the selected memory cell blocks BLK1 to BLKn. ), at least one string selection line SSL, and at least one ground selection line GSL may be selected. Also, the row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, when performing a program operation, the page buffer 35 operates as a write driver to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL. Meanwhile, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to sense data DATA stored in the memory cell array 20 .

2 is an exemplary circuit diagram illustrating a nonvolatile memory device according to some embodiments.

Referring to FIG. 2 , a memory cell array (eg, 20 in FIG. 1 ) of a nonvolatile memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR. ) are included.

The common source line CSL may extend in the first direction X. In some embodiments, the plurality of common source lines CSL may be two-dimensionally arranged. For example, the plurality of common source lines CSL may be spaced apart from each other and extend in the first direction X, respectively. The same voltage may be electrically applied to the common source lines CSL, or different voltages may be applied to be separately controlled.

The plurality of bit lines BL may be two-dimensionally arranged. For example, the bit lines BL may be spaced apart from each other to extend in the second direction Y crossing the first direction X, respectively. A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, a ground select transistor GST, and a string select transistor GST connected to the bit line BL. SST) may include a plurality of memory cell transistors MCT. Each of the memory cell transistors MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. Also, a ground selection line GSL, a plurality of word lines WL1 to WLn, and a string selection line SSL may be disposed between the common source line CSL and the bit line BL. The ground select line GSL may be used as a gate electrode of the ground select transistor GST, the word lines WL1 to WLn may be used as gate electrodes of the memory cell transistors MCT, and the string select line SSL ) may be used as a gate electrode of the string select transistor SST.

In some embodiments, an erase control transistor ECT may be disposed between the common source line CSL and the ground select transistor GST. The common source line CSL may be commonly connected to sources of the erase control transistors ECT. Also, an erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistors ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

3 is an exemplary cross-sectional view illustrating a nonvolatile memory device according to some embodiments. FIG. 4 is an enlarged view of an area P of FIG. 3 .

3 and 4 , a nonvolatile memory device according to some embodiments includes a memory cell area CELL and a peripheral circuit area PERI.

The memory cell region CELL may include a substrate 100 , a mold structure MS, an interlayer insulating layer 120 , a channel structure CH, and a block isolation region WLC.

The substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the substrate 100 may include impurities. For example, the substrate 100 may include n-type impurities (eg, phosphorus (P), arsenic (As), etc.).

A memory cell array (eg, 20 of FIG. 1 ) including a plurality of memory cells may be provided on the substrate 100 . For example, a channel structure CH, a bit line BL, and gate electrodes ECL, GSL, WL1 to WLn, SSL, etc. to be described later may be disposed on the substrate 100 . The substrate 100 may include an upper surface and a lower surface that face each other. A channel structure CH or the like may be formed on the upper surface of the substrate 100 . The upper surface of the substrate 100 may be referred to as a front side of the substrate 100 . Conversely, the lower surface of the substrate 100 may be referred to as a back side of the substrate 100 .

The mold structure MS may be provided on the front surface (eg, the upper surface) of the substrate 100 . The mold structure MS may include a plurality of gate electrodes ECL, GSL, WL1 to WLn, SSL and a plurality of mold insulating layers 110 that are alternately stacked on the substrate 100 . Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL and each of the mold insulating layers 110 may have a layered structure extending parallel to the top surface of the substrate 100 . The gate electrodes ECL, GSL, WL1 to WLn, and SSL are spaced apart from each other by the mold insulating layers 110 and may be sequentially stacked on the substrate 100 .

Although not shown, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may be stacked in a step shape. For example, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may extend to have different lengths in the first direction X to have a step difference. In some embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may have a step difference in the second direction Y.

In some embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include an erase control line ECL, a ground selection line GSL, and a plurality of word lines WL1 sequentially stacked on the substrate 100 . ~WLn). In some other embodiments, the erase control line ECL may be omitted.

Although not shown, the mold insulating layers 110 may be stacked in a step shape. For example, the mold insulating layers 110 may extend to different lengths in the first direction X to have a step difference. In some embodiments, the mold insulating layers 110 may have a step difference in the second direction (Y).

Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon. However, the present invention is not limited thereto. For example, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include tungsten (W). Unlike the drawings, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may be multilayered. For example, when the gate electrodes ECL, GSL, WL1 to WLn, and SSL are multi-layered, the gate electrodes ECL, GSL, WL1 to WLn, SSL may include a gate electrode barrier layer and a gate electrode filling layer. can The gate electrode barrier layer may include, for example, titanium nitride (TiN), and the gate electrode filling layer may include tungsten (W), but is not limited thereto.

The mold insulating layer 110 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the mold insulating layer 110 may include silicon oxide.

The interlayer insulating layer 120 may be provided on the substrate 100 . The interlayer insulating layer 120 may cover the mold structure MS. The interlayer insulating layer 120 may include an oxide-based insulating material. The interlayer insulating layer 120 may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

The channel structure CH may be provided in the mold structure MS. The channel structure CH may extend in a vertical direction (hereinafter, referred to as a third direction Z) intersecting the upper surface of the substrate 100 to pass through the mold structure MS. For example, a trench penetrating the mold structure MS in the third direction Z may be formed. A channel structure CH may be provided in the trench. The channel structure CH may have a pillar shape (eg, a cylindrical shape) extending in the third direction Z. Accordingly, the channel structure CH may cross each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL.

In FIG. 4 , the channel structure CH may include a semiconductor pattern 130 , an information storage layer 132 , and a filling pattern 134 .

The semiconductor pattern 130 may extend in the third direction Z and penetrate the mold structure MS. The semiconductor pattern 130 is illustrated only in the shape of a cup, but this is only an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular cylindrical shape, and a hollow filler shape. The semiconductor pattern 130 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nanostructure, but is not limited thereto.

The information storage layer 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the information storage layer 132 may extend along the outer surface of the semiconductor pattern 130 . The information storage layer 132 may extend along a sidewall of the trench. The information storage layer 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material is, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

In some embodiments, the plurality of channel structures CH may be arranged in a zigzag shape. The plurality of channel structures CH arranged in a zigzag shape may further improve the degree of integration of the nonvolatile memory device. In some embodiments, the plurality of channel structures CH may be arranged in a honeycomb shape.

In some embodiments, the information storage layer 132 may be formed of a multilayer. For example, as shown in FIG. 4 , the information storage layer 132 includes a tunnel insulating layer 132a , a charge storage layer 132b , and a blocking insulating layer 132c sequentially stacked on the outer surface of the semiconductor pattern 130 . may include The blocking insulating layer 132c , the charge storage layer 132b , and the tunnel insulating layer 132a may be sequentially stacked on the sidewall of the trench.

The tunnel insulating layer 132a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating layer 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )).

The filling pattern 134 may be formed to fill the inside of the cup-shaped semiconductor pattern 130 . The filling pattern 134 may include an insulating material, for example, silicon oxide, but is not limited thereto.

In some embodiments, the channel structure CH may further include a channel pad 136 . The channel pad 136 may be formed to be connected to the semiconductor pattern 130 . For example, the channel pad 136 may be formed in the interlayer insulating layer 120 to be connected to an upper portion of the semiconductor pattern 130 . The channel pad 136 may include, for example, polysilicon doped with impurities, but is not limited thereto.

Hereinafter, the information storage layer 132 and the semiconductor pattern 130 according to some embodiments will be described in more detail with reference to FIG. 4 .

Referring to FIG. 4 , the blocking insulating layer 132c according to some embodiments may have a pear-shaped pillar structure. "Baeheulrim pillar structure" means a structure in which the diameter of the middle part of the column is large and the diameter gradually decreases from the middle part to the top and bottom.

For example, the blocking insulating layer 132c includes the first portion 132c_1 overlapping the gate electrodes WLk and WLk-1 in the second direction Y, and the mold insulating layer 110 in the second direction Y. The overlapping second portion 132c_2 may be included. The first portion 132c_1 and the second portion 132c_2 of the blocking insulating layer may be alternately stacked. The width W1 of the first portion 132c_1 of the blocking insulating film 132c in the second direction Y is the width W2 of the second portion 132c_2 of the blocking insulating film 132c in the second direction Y. ) is greater than The blocking insulating layer 132c may have a structure in which the width of the first portion 132c_1 is large and the width of the second portion 132c_2 is small.

In some embodiments, the first portion 132c_1 of the blocking insulating layer 132c has a first surface SUR1 in contact with the gate electrodes WLk and WLk-1 and a second surface SUR1 in contact with the charge storage layer 132b. (SUR2). The first surface SUR1 may be convex with respect to the gate electrodes WLk and WLk - 1 . The second surface SUR2 may be concave with respect to the gate electrodes WLk and WLk - 1 . The width W1 of the first portion 132c_1 of the blocking insulating layer 132c in the second direction (Y) gradually increases from the bottom of the first portion 132c_1 of the blocking insulating layer 132c toward the top. can decrease.

In some embodiments, the angle θ1 between the upper surfaces of the gate electrodes WLk and WLk-1 and the first surface SUR1 may be greater than or equal to 45° and less than or equal to 90°. The angle θ1 between the top surfaces of the gate electrodes WLk and WLk-1 and the first surface SUR1 is the first surface at the point where the top surfaces of the gate electrodes WLk and WLk-1 and the first surface SUR1 meet. It may be an angle formed by the tangent of SUR1 and the upper surfaces of the gate electrodes WLk and WLk-1.

In some embodiments, the second portion 132c_2 of the blocking insulating layer 132c may include the sixth surface SUR6 in contact with the charge storage layer 132b. The sixth surface SUR6 may be a straight line, but is not limited thereto. In some embodiments, the angle θ2 between the sixth surface SUR6 and the second surface SUR2 may be less than 180°. The angle formed by the sixth surface SUR6 and the second surface SUR2 is a tangent line between the sixth surface SUR6 and the second surface SUR2 at the point where the sixth surface SUR6 and the second surface SUR2 meet. It may be an angle formed by this.

In some embodiments, the charge storage layer 132b may be disposed along a profile of the blocking insulating layer 132c. For example, the width of the charge storage layer 132b in the second direction Y may be constant from the bottom surface of the channel structure CH toward the top surface of the channel structure CH.

In some embodiments, the charge storage layer 132b includes the first portion 132c_1 of the blocking insulating layer 132c, the first portion 132b_1 overlapping in the second direction (Y), and a second portion of the blocking insulating layer 132c. A second portion 132b_2 overlapping the 132c_2 in the second direction Y may be included.

The first portion 132b_1 of the charge storage layer 132b may include a second surface SUR2 in contact with the blocking insulating layer 132c and a third surface SUR3 in contact with the tunnel insulating layer 132a. The second surface SUR2 and the third surface SUR3 may be concave with respect to the gate electrodes WLk and WLk - 1 , respectively.

In some embodiments, the tunnel insulating layer 132a may be disposed along a profile of the charge storage layer 132b. For example, the width of the tunnel insulating layer 132a in the second direction Y may be constant from the bottom surface of the channel structure CH toward the top surface of the channel structure CH. The tunnel insulating layer 132a includes a first part 132a_1 overlapping the first part 132c_1 of the blocking insulating layer 132c in the second direction Y, and a second part 132c_2 and a second part of the blocking insulating layer 132c. A second portion 132a_2 overlapping in the direction Y may be included.

The first portion 132a_1 of the tunnel insulating layer 132a may include a third surface SUR3 in contact with the charge storage layer 132b and a fourth surface SUR4 in contact with the semiconductor pattern 130 . The third surface SUR3 and the fourth surface SUR4 may be concave with respect to the gate electrodes WLk and WLk-1, respectively.

In some embodiments, the semiconductor pattern 130 may be disposed along a profile of the tunnel insulating layer 132a. For example, the width of the semiconductor pattern 130 in the second direction Y may be constant from the bottom surface of the channel structure CH toward the top surface of the channel structure CH. The semiconductor pattern 130 includes a first portion 130_1 overlapping the first portion 132c_1 of the blocking insulation film 132c in the second direction Y, and a second portion 132c_2 and a second portion of the blocking insulation film 132c. A second portion 130_2 overlapping in the direction Y may be included.

The first portion 130_1 of the semiconductor pattern 130 may include a fourth surface SUR4 in contact with the tunnel insulating layer 132a and a fifth surface SUR5 in contact with the filling pattern 134 . The fourth surface SUR4 and the fifth surface SUR5 may be concave with respect to the gate electrodes WLk and WLk-1, respectively.

That is, the blocking insulating film 132c according to some embodiments has a baeheulim pillar structure. Accordingly, the thickness of the blocking insulating layer 132c in contact with the gate electrodes ECL, GSL, WL1 to WLn, and SSL is greater than the thickness of the blocking insulating layer 132c in contact with the mold insulating layer 110 . In this case, retention of charges stored in the charge storage layer 132b may be improved. Accordingly, a nonvolatile memory device having improved reliability may be manufactured.

Referring back to FIG. 3 , the source layer 102 and the source support layer 104 may be sequentially formed on the substrate 100 . The source layer 102 and the source support layer 104 may be interposed between the substrate 100 and the mold structure MS. For example, the source layer 102 and the source support layer 104 may extend along the top surface of the substrate 100 .

In some embodiments, the source layer 102 may be formed to be connected to the semiconductor pattern 130 of the channel structure CH. For example, the source layer 102 may penetrate the information storage layer 132 and contact the semiconductor pattern 130 . The source layer 102 may be provided as a common source line (eg, CSL of FIG. 2 ) of the nonvolatile memory device. The source layer 102 may include, for example, polysilicon or metal doped with impurities, but is not limited thereto.

In some embodiments, the channel structure CH may penetrate the source layer 102 and the source support layer 104 . For example, a lower portion of the channel structure CH may be buried in the substrate 100 through the source layer 102 and the source support layer 104 .

In some embodiments, the source support layer 104 may be used as a support layer to prevent collapse or collapse of the mold stack in a replacement process for forming the source layer 102 .

Although not shown, a base insulating layer may be interposed between the substrate 100 and the source layer 102 . The base insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The block separation region WLC may extend in the first direction X to cut the mold structure MS. The mold structure MS may be cut by the plurality of block isolation regions WLC to form a plurality of memory cell blocks (eg, BLK1 to BLKn of FIG. 1 ). For example, two adjacent block separation regions WLC may define one memory cell block therebetween. A plurality of channel structures CH may be disposed in each of the memory cell blocks defined by the block isolation regions WLCs.

In some embodiments, the block isolation region WLC may extend in the first direction X to cut the source layer 102 and the source support layer 104 . Although it is illustrated that the lower surface of the block isolation region WLC is coplanar with the lower surface of the source layer 102 , this is only exemplary. As another example, the lower surface of the block isolation region WLC may be lower than the lower surface of the source layer 102 .

In some embodiments, the block isolation region WLC may include an insulating material. For example, the insulating material may fill the block isolation region WLC. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

In some embodiments, the string separation structure SC may be provided in the mold structure MS. The string separation structure SC may extend in the first direction X to cut the string selection line SSL. Each of the memory cell blocks defined by the block separation regions WLC may be divided by the string separation structure SC to form a plurality of string regions. For example, the string separation structure SC may define two string regions in one memory cell block.

The nonvolatile memory device according to some embodiments may further include an insulating layer 140 between the bit line BL and the first wiring.

The bit line BL may be formed on the mold structure MS and the interlayer insulating layer 120 . The bit line BL may extend in the second direction Y to cross the block separation region WLC. Also, the bit line BL may extend in the second direction Y to be connected to a plurality of channel structures CH arranged along the second direction Y. For example, a bit line contact 162 connected to an upper portion of each of the channel structures CH may be formed in the interlayer insulating layer 120 . The bit line BL may be electrically connected to the channel structures CH through the bit line contact 162 .

The first inter-wiring insulating layer 140 may be provided on the bit line BL. Although not shown, a plurality of wiring patterns may be formed in the first inter-wiring insulating layer 140 .

The peripheral circuit region PERI includes the peripheral circuit board 200 , the peripheral circuit element PT, the second inter-wiring insulating layer 220 , the wiring structures 241 and 242 , and the wiring contacts 231 and 232 . can do.

The peripheral circuit board 200 may be disposed under the substrate 100 . For example, the upper surface of the peripheral circuit board 200 may face the lower surface of the substrate 100 . The peripheral circuit board 200 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like.

The peripheral circuit element PT may be formed on the peripheral circuit board 200 . The peripheral circuit element PT may constitute a peripheral circuit (eg, 30 of FIG. 1 ) that controls the operation of the nonvolatile memory device. For example, the peripheral circuit element PT may include control logic (eg, 37 of FIG. 1 ), a row decoder (eg, 33 of FIG. 1 ), and a page buffer (eg, 35 of FIG. 1 ). In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit element PT is disposed may be referred to as a front side of the peripheral circuit board 200 . Conversely, a surface of the peripheral circuit board 200 opposite to the front surface of the peripheral circuit board 200 may be referred to as a back side of the peripheral circuit board 200 .

The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit element PT may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors. may be

In some embodiments, the rear surface of the substrate 100 may face the front surface of the peripheral circuit board 200 . For example, the second inter-wiring insulating layer 220 covering the peripheral circuit element PT may be formed on the front surface of the peripheral circuit board 200 .

In some embodiments, interconnection structures 241 and 242 connected to the peripheral circuit element PT may be formed in the second inter-wiring insulating layer 220 . The wiring structures 241 and 242 may be connected to each other through the wiring contacts 231 and 232 . Also, the wiring structures 241 and 242 may be electrically connected to the peripheral circuit element PT through the wiring contacts 231 and 232 . Through this, the bit line BL, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL, and/or the source layer 102 may be electrically connected to the peripheral circuit element PT.

The peripheral circuit elements PT may be separated by the peripheral element isolation layer 205 . For example, the peripheral device isolation layer 205 may be provided in the peripheral circuit board 200 . The peripheral device isolation layer 205 may be a shallow trench isolation (STI) layer. The peripheral device isolation layer 205 may define active regions of the peripheral circuit devices PT. The peripheral device isolation layer 205 may include an insulating material. The peripheral device isolation layer 205 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

5 is a diagram for describing a nonvolatile memory device according to some exemplary embodiments. For reference, FIG. 5 may be an enlarged view of area P of FIG. 3 . For convenience of explanation, the description will be focused on points different from those described with reference to FIGS. 3 and 4 .

Referring to FIG. 5 , an angle θ1 between the top surfaces of the gate electrodes WLk and WLk-1 and the first surface SUR1 may be greater than 0° and smaller than 45°. The angle θ1 between the top surfaces of the gate electrodes WLk and WLk-1 and the first surface SUR1 is the first surface at the point where the top surfaces of the gate electrodes WLk and WLk-1 and the first surface SUR1 meet. The angle between the tangent of SUR1 and the upper surfaces of the gate electrodes WL _k and WL _k-1 may be an angle.

Even in this case, the blocking insulating film 132c may have a baeheulrim pillar structure. The charge storage layer 132b may extend along the profile of the blocking insulating layer 132c. The tunnel insulating layer 132a may extend along the profile of the charge storage layer 132b. The semiconductor pattern 130 may extend along a profile of the tunnel insulating layer 132a.

6 to 8 are exemplary cross-sectional views for describing a nonvolatile memory device according to some embodiments. For convenience of description, the points different from those described with reference to FIGS. 1 to 4 will be mainly described.

First, referring to FIG. 6 , the source layer 102 may be connected to the semiconductor pattern 130 . The source layer 102 may contact the bottom surface of the information storage layer 132 and the bottom surface of the semiconductor pattern 130 . The source layer 102 may not expose the sidewall of the semiconductor pattern 130 . The source layer 102 may expose a bottom surface of the semiconductor pattern 130 . In this case, the source support layer ( 104 in FIG. 3 ) may not be provided.

In some embodiments, under the source layer 102 , a metal silicide layer 106 may be provided. The metal silicide layer 106 may be provided between the source layer 102 and the second interline insulating layer 220 . Alternatively, the metal silicide layer 106 may not be provided.

Referring to FIG. 7 , the mold structure MS may include a lower mold structure MS1 and an upper mold structure MS2 . The interlayer insulating layer 120 may include a lower interlayer insulating layer 120a and an upper interlayer insulating layer 120b. The mold insulating layer 110 may include a lower mold insulating layer 112 and an upper mold insulating layer 114 .

In some embodiments, the upper mold structure MS2 may be provided on the lower mold structure MS1 . The lower mold structure MS1 may be configured by alternately stacking lower gate electrodes ECL, GSL, and WL11 to WL1n and a lower mold insulating layer 112 . The upper mold structure MS2 may be configured by alternately stacking upper gate electrodes WL21 to WL2n and SSL and an upper mold insulating layer 114 . The channel structure CH may pass through the upper mold structure MS2 and the lower mold structure MS1 in the third direction Z.

In some embodiments, the lower interlayer insulating layer 120a may be provided between the lower gate electrode WL1n and the upper mold insulating layer 114 . The upper interlayer insulating layer 120b may be provided between the upper gate electrode SSL and the bit line BL.

Referring to FIG. 8 , in the nonvolatile memory device according to some embodiments, the front surface of the substrate 100 faces the front surface of the peripheral circuit board 200 .

For example, the nonvolatile memory device according to some embodiments may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a memory cell region CELL is fabricated on a first wafer (eg, the substrate 100 ), and a second wafer different from the first wafer (eg, the peripheral circuit board 200 ) This means that the upper chip and the lower chip are connected to each other by a bonding method after manufacturing the lower chip including the peripheral circuit region PERI thereon.

For example, the bonding method may refer to a method of electrically connecting the first bonding metal 190 formed in the uppermost metal layer of the upper chip and the second bonding metal 290 formed in the uppermost metal layer of the lower chip to each other. there is. For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only exemplary, and it goes without saying that the first bonding metal 190 and the second bonding metal 290 may be formed of various other metals such as aluminum (Al) or tungsten (W).

As the first bonding metal 190 and the second bonding metal 290 are connected, the bit line BL may be connected to the peripheral circuit element PT. For example, the first bonding metal 190 may be connected to the bit line BL through the first bonding contact 185 . The second bonding metal 290 and the interconnection structures 241 and 242 may be connected to each other through the second bonding contact 285 . Through this, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL and/or the source layer 102 may be electrically connected to the peripheral circuit element PT.

Hereinafter, a method of manufacturing a nonvolatile memory device according to example embodiments will be described with reference to FIGS. 9 to 15 .

9 to 15 are views sequentially illustrating a process of manufacturing the nonvolatile memory device having the cross section of FIG. 4 .

Referring to FIG. 9 , a mold insulating layer 110 and a mold sacrificial layer MSL may be provided. The mold insulating layer 110 and the mold sacrificial layer MSL may be alternately stacked.

The mold insulating layer 110 may include an oxide-based insulating material. The mold sacrificial layer MSL may include a material having an etch selectivity with respect to the mold insulating layer 110 . For example, the mold sacrificial layer MSL may include a nitride-based insulating material. For example, the mold sacrificial layer MSL may include silicon nitride (SiN), but is not limited thereto.

Referring to FIG. 10 , a trench TR may be formed. The trench TR may pass through the mold insulating layer 110 and the mold sacrificial layer MSL. The width of the trench TR may gradually decrease from an upper portion of the trench TR toward a lower portion of the trench TR. This may be due to characteristics of an etching process for forming the trench TR.

Referring to FIG. 11 , a first sacrificial layer SL1 may be formed along the sidewall of the trench TR.

First, a nitride-based insulating material may be formed along the sidewall of the trench TR. Subsequently, a first sacrificial layer SL1 may be formed through an oxidation process. The first sacrificial layer SL1 may include an oxide-based insulating material.

Referring to FIG. 12 , a second sacrificial layer SL2 may be formed on the first sacrificial layer SL1 . For example, the second sacrificial layer SL2 may include polysilicon (poly Si). The second sacrificial layer SL2 may be formed along the profile of the first sacrificial layer SL1 .

Referring to FIG. 13 , a blocking insulating layer 132c may be formed by performing an oxidation process. Oxidation rates of the first sacrificial layer SL1 and the second sacrificial layer SL2 may be different. Accordingly, the blocking insulating layer 132c may have a baeheulrim pillar structure.

The blocking insulating layer 132c may include a first portion 132c_1 overlapping the mold sacrificial layer MSL and a second portion 132c_2 overlapping the mold insulating layer 110 . The width W1 of the first part 132c_1 of the blocking insulating layer 132c is greater than the width W2 of the second part 132c_2 of the blocking insulating layer 132c.

Referring to FIG. 14 , a charge storage layer 132b may be formed along the profile of the blocking insulating layer 132c. The charge storage layer 132b may be formed through atomic layer deposition (ALD). Accordingly, the charge storage layer 132b may be conformally formed. The width of the charge storage layer 132b may be constant.

Subsequently, a tunnel insulating layer 132a may be formed along the profile of the charge storage layer 132b. The tunnel insulating layer 132a may be formed through atomic layer deposition (ALD). Accordingly, the tunnel insulating layer 132a may be conformally formed. The width of the tunnel insulating layer 132a may be constant.

Subsequently, the semiconductor pattern 130 may be formed along the profile of the tunnel insulating layer 132a. The semiconductor pattern 130 may be formed through atomic layer deposition (ALD). Accordingly, the semiconductor pattern 130 may be conformally formed. The width of the semiconductor pattern 130 may be constant.

Subsequently, the blocking insulating layer 132c , the charge storage layer 132b , the tunnel insulating layer 132a , and the filling pattern 134 filling the trench TR remaining after filling the semiconductor pattern 130 may be formed. The blocking insulating layer 132c , the charge storage layer 132b , the tunnel insulating layer 132a , the semiconductor pattern 130 , and the filling pattern 134 may constitute the channel structure CH.

Referring to FIG. 15 , gate electrodes WLk and WLk-1 may be formed. The gate electrodes WLk and WLk-1 may be formed through a replacement process. First, the mold sacrificial layer MSL is removed, and gate electrodes WLk and WLk - 1 may be formed in a space where the mold sacrificial layer MSL is removed.

Hereinafter, an electronic system including a nonvolatile memory device according to example embodiments will be described with reference to FIGS. 1 to 8 and FIGS. 16 to 18 .

16 is an exemplary block diagram for describing an electronic system according to some embodiments. 17 is an exemplary perspective view for explaining an electronic system according to some embodiments. 18 is a schematic cross-sectional view taken along line I-I of FIG. 17 .

Referring to FIG. 16 , the electronic system 1000 according to some embodiments may include a nonvolatile memory device 1100 and a controller 1200 electrically connected to the nonvolatile memory device 1100 . The electronic system 1000 may be a storage device including one or a plurality of nonvolatile memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more non-volatile memory devices 1100 . there is.

The nonvolatile memory device 1100 may be, for example, a NAND flash memory device, for example, the nonvolatile memory device described above with reference to FIGS. 1 to 8 . The nonvolatile memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

The first structure 1100F includes a decoder circuit 1110 (eg, row decoder 33 in FIG. 1 ), a page buffer 1120 (eg, page buffer 35 in FIG. 1 ), and a logic circuit 1130 (eg, FIG. 1 ). may be a peripheral circuit structure including the control logic 37 of

The second structure 1100S may include the common source line CSL, the plurality of bit lines BL, and the plurality of cell strings CSTR described above with reference to FIG. 2 . The cell strings CSTR may be connected to the decoder circuit 1110 through a word line WL, at least one string select line SSL, and at least one ground select line GSL. Also, the cell strings CSTR may be connected to the page buffer 1120 through bit lines BL.

In some embodiments, the common source line CSL and the cell strings CSTR are connected to the decoder circuit 1110 and the decoder circuit 1110 through first connection lines 1115 extending from the first structure 1100F to the second structure 1100S. may be electrically connected.

In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

The nonvolatile memory device 1100 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 (eg, the control logic 37 of FIG. 1 ). The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of non-volatile memory devices 1100 , and in this case, the controller 1200 may control the plurality of non-volatile memory devices 1100 .

The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200 . The processor 1210 may operate according to a predetermined firmware, and may access the nonvolatile memory device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that handles communication with the nonvolatile memory device 1100 . A control command for controlling the nonvolatile memory device 1100, data to be written to the memory cell transistors MCT of the nonvolatile memory device 1100, and the nonvolatile memory device 1100 through the NAND interface 1221 Data to be read from the memory cell transistors MCT of the . The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230 , the processor 1210 may control the nonvolatile memory device 1100 in response to the control command.

16 to 18 , an electronic system according to some embodiments includes a main board 2001 , a main controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and a DRAM 2004 . may include The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 by wiring patterns 2005 formed on the main board 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 includes interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. It can communicate with an external host according to either one. In some embodiments, the electronic system 2000 may operate by power supplied from an external host through the connector 2006 . The electronic system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the main controller 2002 and the semiconductor package 2003 .

The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operating speed of the electronic system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the DRAM 2004 is included in the electronic system 2000 , the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . Each of the first semiconductor package 2003a and the second semiconductor package 2003b includes a package substrate 2100 , semiconductor chips 2200 on the package substrate 2100 , and adhesive layers disposed on lower surfaces of the semiconductor chips 2200 , respectively. 2300 , a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 , and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100 . ) may be included.

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each semiconductor chip 2200 may include an input/output pad 2210 . The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 16 .

In some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the upper package pads 2130 . Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b , the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and the package upper pads 2130 of the package substrate 2100 . ) can be electrically connected to. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b , the semiconductor chips 2200 may be connected to a through-electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400 . ) may be electrically connected to each other by a connection structure comprising a.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor are formed by wiring formed on the interposer substrate. Chips 2200 may be connected to each other.

In some embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 is disposed on or exposed through the package substrate body 2120 , the package upper pads 2130 disposed on the upper surface of the package substrate body 2120 , and the lower surface of the package substrate body 2120 . It may include lower pads 2125 to be formed, and internal wirings 2135 electrically connecting the upper pads 2130 and the lower pads 2125 in the package substrate body 2120 . The upper pads 2130 may be electrically connected to the connection structures 2400 . The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 as shown in FIG. 17 through conductive connectors 2800 .

17 and 18 , in an electronic system according to some embodiments, each of the semiconductor chips 2200 may include the nonvolatile memory device described above with reference to FIGS. 1 to 8 . For example, each of the semiconductor chips 2200 may include a peripheral circuit region PERI and a memory cell region CELL stacked on the peripheral circuit region PERI. For example, the peripheral circuit region PERI may include the peripheral circuit board 200 and the second wiring structures 241 and 242 described above with reference to FIGS. 3 to 8 . Also, for example, the memory cell region CELL includes the substrate 100 , the mold structure MS, the channel structure CH, the block isolation region WLC, and the bit line described above with reference to FIGS. 3 to 8 . (BL).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 102: source layer
104: source support layer 110: mold insulating film
120: interlayer insulating film 140: first inter-wiring insulating film
CH: channel structure 136: channel pad
BL: bit line 162: bit line contact
200: peripheral circuit board PT: peripheral circuit element
205: peripheral element isolation film

Claims (10)

Board;
a mold structure that is alternately stacked on the substrate and includes a plurality of gate electrodes and a plurality of mold insulating layers extending in a first direction; and
and a channel structure disposed in a trench penetrating the mold structure in a second direction perpendicular to the first direction,
The channel structure includes a blocking insulating film, a charge storage film, and a tunnel insulating film sequentially provided on the sidewall of the trench,
The blocking insulating layer includes a first portion in contact with the gate electrode and a second portion in contact with the mold insulating layer,
a width of the first portion of the blocking insulating film in the first direction is greater than a width of the second portion of the blocking insulating film in the first direction;
and a width of the charge storage layer in the first direction and a width of the tunnel insulating layer in the first direction are constant from a bottom surface of the channel structure toward a top surface of the channel structure. The method of claim 1,
The channel structure includes a semiconductor pattern on the tunnel insulating layer,
A width of the semiconductor pattern in the first direction is constant from a bottom surface of the channel structure toward an upper surface of the channel structure. The method of claim 1,
The first portion of the blocking insulating film includes a first surface in contact with the gate electrode, and a second surface in contact with the charge storage film,
An angle between the first surface and the upper surface of the gate electrode is greater than or equal to 45° and less than 90°. 4. The method of claim 3,
The second portion of the blocking insulating film includes a sixth surface in contact with the charge storage film,
and an angle between the second surface and the sixth surface is less than 180°. 4. The method of claim 3,
wherein the first side is convex with respect to the gate electrode and the second side is concave with respect to the gate electrode. The method of claim 1,
The charge storage film includes a first portion overlapping the first portion of the blocking insulating film in the first direction, and a second portion overlapping the second portion of the blocking insulating film in the first direction,
The first portion of the charge storage film includes a second surface in contact with the blocking insulating film, and a third surface in contact with the tunnel insulating film,
and the second surface and the third surface are each concave with respect to the gate electrode. 7. The method of claim 6,
The channel structure includes a semiconductor pattern on the tunnel insulating layer,
The tunnel insulating film includes a first portion overlapping the first portion of the blocking insulating film in the first direction, and a second portion overlapping the second portion of the blocking insulating film in the first direction,
the third surface is in contact with the first portion of the tunnel insulating film;
The first portion of the tunnel insulating layer includes a fourth surface in contact with the semiconductor pattern,
and the fourth side is concave with respect to the gate electrode. The method of claim 1,
The first portion of the blocking insulating film includes a first surface in contact with the gate electrode,
An angle between the first surface and the upper surface of the gate electrode is greater than 0° and less than 45°. The method of claim 1,
and a bit line connected to the channel structure. main board;
a nonvolatile memory device on the main board; and
a controller electrically connected to the nonvolatile memory device on the main board;
The non-volatile memory device comprises:
Board;
a mold structure stacked alternately on the substrate and including a plurality of gate electrodes and a plurality of mold insulating layers extending in a first direction; and
and a channel structure disposed in a trench penetrating the mold structure in a second direction perpendicular to the first direction,
The channel structure includes a blocking insulating film, a charge storage film, and a tunnel insulating film sequentially provided on the sidewall of the trench,
The blocking insulating layer includes a first portion in contact with the gate electrode and a second portion in contact with the mold insulating layer,
a width of the first portion of the blocking insulating film in the first direction is greater than a width of the second portion of the blocking insulating film in the first direction;
and a width of the charge storage layer in the first direction and a width of the tunnel insulating layer in the first direction are constant from a bottom surface of the channel structure toward a top surface of the channel structure.

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