KR20240050250A - Semiconductor memory device, method for fabricating the same and electronic system including the same - Google Patents

Abstract

A semiconductor memory device, a manufacturing method thereof, and an electronic system including the same are provided. The semiconductor memory device includes a cell substrate, a mold structure including a plurality of gate electrodes alternately stacked on the cell substrate, a channel structure penetrating the mold structure, a string selection line on the mold structure, and a channel structure penetrating the string selection line. It includes a string selection channel structure in contact with a string selection channel structure, an anti-arcing contact penetrating the mold structure, an insulating pattern between the anti-arcing contact and a plurality of gate electrodes, and an anti-arcing insulating pattern penetrating the string selection line and in contact with the anti-arcing contact. .

Description

Semiconductor memory device, manufacturing method thereof, and electronic system including the same {SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory device, a manufacturing method thereof, and an electronic system including the same.

There is a need to increase the integration of semiconductor memory devices to meet the excellent performance and low prices demanded by consumers. In the case of semiconductor memory devices, since the degree of integration is an important factor in determining the price of the product, an increased degree of integration is particularly required.

Meanwhile, in the case of two-dimensional or two-dimensional semiconductor memory devices, the degree of integration is mainly determined by the area occupied by a unit memory cell, and is therefore greatly affected by the level of fine pattern formation technology. However, because ultra-expensive equipment is required for pattern miniaturization, the integration of two-dimensional semiconductor devices is increasing but is still limited. Accordingly, three-dimensional semiconductor devices including memory cells arranged three-dimensionally have been proposed.

The technical problem to be solved by the present invention is to provide a semiconductor memory device with improved electrical characteristics and reliability.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor memory device with improved electrical characteristics and reliability.

Another technical problem to be solved by the present invention is to provide an electronic system including a semiconductor memory device with improved electrical characteristics and reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem includes a cell substrate, a mold structure including a plurality of gate electrodes alternately stacked on the cell substrate, a channel structure penetrating the mold structure, and a mold. A string selection line on the structure, a string selection channel structure penetrating the string selection line and in contact with the channel structure, an anti-arcing contact penetrating the mold structure, an insulating pattern between the anti-arcing contact and a plurality of gate electrodes, and a string selection channel structure penetrating the string selection line. and includes an anti-arc insulating pattern in contact with the anti-arc contact.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem includes a cell substrate including a cell array region and an expansion region, stacked sequentially on the cell array region, and stacked in a step shape on the expansion region to form a top surface. A mold structure including a plurality of gate electrodes each including the exposed connection area, a channel structure penetrating the mold structure on the cell array area, a string selection line on the mold structure, and an electrical connection with the channel structure passing through the string selection line. A string selection channel structure connected to the cell array area, an anti-arc contact that penetrates the mold structure and has a structure different from the channel structure, and an insulating pattern between the anti-arc contact and the plurality of gate electrodes.

An electronic system according to some embodiments of the present invention for achieving the above technical problem includes a main board, a semiconductor memory device on the main board, and a controller electrically connected to the semiconductor memory device on the main board, including a semiconductor memory device. The device is a mold structure including a cell substrate including a cell array region and an expansion region, a plurality of gate electrodes each including a connection region that is stacked sequentially on the cell array region and in a stepwise manner on the expansion region to expose the top surface. , on the cell array area, a channel structure penetrating the mold structure, a string selection line on the mold structure, a string selection channel structure penetrating the string selection line and in contact with the channel structure, on the cell array area, an arcing through the mold structure. An anti-arc contact, an insulating pattern between the anti-arc contact and a plurality of gate electrodes, an anti-arc insulating pattern penetrating the string selection line and in contact with the anti-arc contact, and on the expansion area, a plurality of cell contacts electrically connected to the connection area. Includes.

A method of manufacturing a semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem includes forming a mold structure including a plurality of gate electrodes sequentially stacked on a substrate, and forming a channel structure penetrating the mold structure. and forming an anti-arcing contact, wherein the anti-arcing contact contacts the substrate, forms a string selection line on the mold structure, penetrates the string selection line and contacts the anti-arcing contact, and includes an anti-arcing sacrificial material. After forming the film and forming the anti-arcing sacrificial film, forming a string selection channel structure penetrating the string selection line on the channel structure, removing the anti-arcing sacrificial film to form a hole exposing at least a portion of the anti-arcing contact, and forming an anti-arcing insulating pattern that fills the hole.

Specific details of other embodiments are included in the detailed description and drawings.

1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.
FIG. 2 is an example circuit diagram for explaining a semiconductor memory device according to some embodiments.
FIG. 3 is an example layout diagram for explaining a semiconductor memory device according to some embodiments.
Figure 4 is a cross-sectional view taken along II of Figure 3.
Figure 5 is an enlarged view of area Q1 in Figure 4.
Figure 6 is an enlarged view of area A of Figure 4.
Figure 7 is an enlarged view of area B in Figure 4.
Figure 8 is an enlarged view of area C in Figure 4.
FIG. 9 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 10 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 11 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 12 is an enlarged view of area Q2 of FIG. 11.
FIG. 13 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 14 is an enlarged view of area Q3 in FIG. 13.
FIG. 15 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 16 is an enlarged view of area Q4 in FIG. 15.
17 to 28 are intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments.
29 to 31 are other intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments.
32 is an example block diagram for explaining an electronic system according to some embodiments.
Figure 33 is an example perspective view for explaining an electronic system according to some embodiments.
FIG. 34 is a schematic cross-sectional view taken along line II-II in FIG. 33.

1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 1 , a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30.

The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each memory cell block (BLK1 to BLKn) may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through a bit line (BL), a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through a word line (WL), a string select line (SSL), and a ground select line (GSL). Additionally, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit line BL.

The peripheral circuit 30 can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the semiconductor memory device 10, and can receive data (DATA) from devices outside the semiconductor memory device 10. ) can be transmitted and received. The peripheral circuit 30 may include a row decoder 33, a page buffer 35, and control logic 37. The peripheral circuit 30 includes an input/output circuit, a voltage generation circuit for generating various voltages required for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors in data (DATA) read from the memory cell array 20. It may further include various sub-circuits such as circuits.

The control logic 37 may be connected to the row decoder 33, the page buffer 35, the input/output circuit, and the voltage generation circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used within the semiconductor memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage level provided to the word line (WL) and the bit line (BL) when performing a memory operation such as a program operation or an erase operation.

The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and selects at least one word line WL of the selected memory cell blocks BLK1 to BLKn. ), at least one string select line (SSL), and at least one ground select line (GSL) can be selected. Additionally, the row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

The page buffer 35 may be connected to the memory cell array 20 through a bit line BL. The page buffer 35 may operate as a writer driver or a sense amplifier. Specifically, when performing a program operation, the page buffer 35 may operate as a write driver and apply a voltage according to the data (DATA) to be stored in the memory cell array 20 to the bit line (BL). Meanwhile, when performing a read operation, the page buffer 35 operates as a sense amplifier and can sense data (DATA) stored in the memory cell array 20.

FIG. 2 is an example circuit diagram for explaining a semiconductor memory device according to some embodiments.

Referring to FIG. 2, the memory cell array (e.g., 20 in FIG. 1) of a semiconductor memory device according to some embodiments includes a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR). Includes.

The common source line (CSL) may extend in the first direction (X). In some embodiments, a plurality of common source lines (CSL) may be arranged two-dimensionally. For example, the plurality of common source lines (CSL) may be spaced apart from each other and each extend in the first direction (X). The same electrical voltage may be applied to the common source line (CSL), or different voltages may be applied and controlled separately.

A plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may be spaced apart from each other and extend in the second direction Y intersecting the first direction X. A plurality of cell strings (CSTR) may be connected in parallel to each bit line (BL). The cell string (CSTR) may be commonly connected to the common source line (CSL). That is, a plurality of cell strings (CSTR) may be disposed between the bit line (BL) and the common source line (CSL).

Each cell string (CSTR) includes a ground select transistor (GST) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), a ground select transistor (GST), and a string select transistor ( It may include a plurality of memory cell transistors (MCT) disposed between (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GST), string select transistor (SST), and memory cell transistors (MCT) may be connected in series.

The common source line (CSL) may be commonly connected to the sources of the ground select transistor (GST). Additionally, a ground select line (GSL), a plurality of word lines (WL1 to WLn), and a string select line (SSL) may be disposed between the common source line (CSL) and the bit line (BL). The ground select line (GSL) can be used as the gate electrode of the ground select transistor (GST), the word lines (WL1 to WLn) can be used as the gate electrode of the memory cell transistors (MCT), and the string select line (SSL) ) can be used as the gate electrode of a string select transistor (SST).

In some embodiments, an erase control transistor (ECT) may be disposed between the common source line (CSL) and the ground select transistor (GST). The common source line (CSL) may be commonly connected to the sources of the erase control transistor (ECT). Additionally, an erase control line (ECL) may be disposed between the common source line (CSL) and the ground select line (GSL). The erase control line (ECL) can be used as the gate electrode of the erase control transistor (ECT). The erase control transistor (ECT) may generate gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

FIG. 3 is an example layout diagram for explaining a semiconductor memory device according to some embodiments. Figure 4 is a cross-sectional view taken along line II of Figure 3. Figure 5 is an enlarged view of area Q1 in Figure 4. Figure 6 is an enlarged view of area A of Figure 4. Figure 7 is an enlarged view of area B in Figure 4. Figure 8 is an enlarged view of area C in Figure 4.

Referring to FIGS. 3 and 4 , a semiconductor memory device according to some embodiments may include a memory cell structure (CELL) and a peripheral circuit structure (PERI).

The memory cell structure (CELL) includes cell substrates 101 and 102, mold structure (MS), first to seventh interlayer insulating films 141 to 147, channel structure (CH), word line cut structure (WLC), and string selection. line (SSL), string separation structure (SLC), string selection channel structure (SCH), anti-arcing contact 120, anti-arc insulating pattern 155, first insulating pattern 112, second insulating pattern 114 , cell contact 170, source contact 174, input/output contact 176, first metal pattern (186a, 186b, 186c, 186d), first inter-wiring insulating film 190, first bonding via 192, and It may include a first bonding metal 194.

The cell substrates 101 and 102 may include a cell array area (CA), an extension area (EXT), and a pad area (PA).

A memory cell array (eg, 20 in FIG. 1 ) including a plurality of memory cells may be disposed on the cell array area CA. For example, a channel structure (CH), a first metal pattern 186a, gate electrodes (GSL, WL1 to WLn, ECL), and a string selection line (SSL), which will be described later, are disposed on the cell array area (CA). It can be. In the following description, the surface of the cell substrates 101 and 102 on which the memory cell array is disposed may be referred to as the front side of the cell substrates 101 and 102. Conversely, the surface of the cell substrates 101 and 102 opposite to the front surface of the cell substrates 101 and 102 may be referred to as the back side of the cell substrates 101 and 102.

The expansion area EXT may be arranged around the cell array area CA. For example, the extended area (EXT) may surround the cell array area (CA) from a plan view. On the extended area EXT, gate electrodes GSL, WL1 to WLn, and ECL, which will be described later, may be stacked in a stepped shape.

For example, the pad area PA may be defined and placed outside the extended area EXT. For example, the pad area PA may surround the extension area EXT from a plan view. A source contact 174 and an input/output contact 176, which will be described later, may be disposed on the pad area PA.

In some embodiments, the cell substrates 101 and 102 may include an insulating layer 101 and a source layer 102. For example, the insulating layer 101 may be provided in the extension area (EXT) and the pad area (PA), and the source layer 102 may be provided in the cell array area (CA) and the pad area (PA). . In some embodiments, the source layer 102 may be formed on the cell array area (CA) and may not be formed on the extension area (EXT).

The source layer 102 may include a conductive material, for example, polysilicon or metal doped with impurities, but is not limited thereto. The source layer 102 may be provided as a common source line (eg, CSL in FIG. 2) of a semiconductor memory device.

For example, the lower surface of the source layer 102 may be flat. For another example, the source layer 102 is formed along the lower surface of the channel structure (CH), and the source layer 102 is formed from an extension extending along the mold insulating film 110 and the first insulating film 108 from the extension. It may include a protrusion protruding toward. The channel structure CH may overlap the protrusion in the third direction (Z).

The insulating layer 101 may be formed around the source layer 102. The insulating layer 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

The mold structure MS may be disposed on the front surface of the cell substrates 101 and 102. The mold structure MS may include a plurality of gate electrodes (GSL, WL1 to WLn, ECL) and a plurality of mold insulating films 110 stacked on the cell substrates 101 and 102. Each gate electrode (GSL, WL1 to WLn, ECL) and each mold insulating film 110 may have a layered structure extending parallel to the front surface of the cell substrates 101 and 102. The gate electrodes (GSL, WL1 to WLn, and ECL) may be sequentially stacked on the cell substrates 101 and 102 while being spaced apart from each other by the mold insulating film 110.

The gate electrodes (GSL, WL1 to WLn, ECL) may be stacked in a step shape on the extended area (EXT). For example, the gate electrodes (GSL, WL1 to WLn, ECL) may extend to different lengths in the first direction (X) and have a step difference. Accordingly, each of the gate electrodes (GSL, WL1 to WLn, and ECL) may include a connection region (CR) whose upper surface is exposed on the extended region (EXT). The connection region CR may be disposed at an end of each gate electrode (GSL, WL1 to WLn, and ECL). The gate electrodes (GSL, WL1 to WLn, ECL) may extend to different lengths in the second direction (Y) and have a step difference.

For example, the thickness of the gate electrodes (GSL, WL1 to WLn, ECL) in the connection region (CR) may be thicker than the thickness of the gate electrodes (GSL, WL1 to WLn, ECL) in regions other than the connection region (CR). . Hereinafter, the thickness may be based on the third direction (Z). The third direction (Z) may intersect the first direction (X) and the second direction (Y). The third direction (Z) may be a direction perpendicular to the front surfaces of the cell substrates 101 and 102. The first direction (X) and the second direction (Y) may be parallel to the front surfaces of the cell substrates 101 and 102. Hereinafter, the upper surface, lower surface, top and bottom are based on the third direction (Z).

In some embodiments, the gate electrodes (GSL, WL1 to WLn, ECL) are a ground select line (GSL), word lines (WL1 to WLn), and an erase control line (ECL) that are sequentially stacked on the cell substrates 101 and 102. ) may include. The number and arrangement of ground selection lines (GSL), word lines (WL1 to WLn), and erase control lines (ECL) are illustrative only and are not limited to those shown. In some other embodiments, the erase control line (ECL) may be omitted. In some other embodiments, it may further include dummy word lines.

The gate electrodes (GSL, WL1 to WLn, ECL) may each contain a conductive material, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon. It is not limited. For example, each gate electrode (GSL, WL1 to WLn, ECL) may include tungsten (W). The gate electrodes (GSL, WL1 to WLn, ECL) may be, for example, a multilayer. For example, when the gate electrodes (GSL, WL1 to WLn, ECL) are multilayers, the gate electrodes (GSL, WL1 to WLn, ECL) may include a gate electrode barrier film and a gate electrode filling film.

The mold insulating film 110 may be alternately stacked with the gate electrodes (GSL, WL1 to WLn, and ECL). The mold insulating film 110 may be stacked in a stepped shape on the extended area EXT. For example, the mold insulating film 110 may extend to different lengths in the first direction (X) and have a step difference. The mold insulating film 110 may extend to different lengths in the second direction (Y) and have a step difference.

The mold insulating film 110 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the mold insulating film 110 may include silicon oxide.

The first interlayer insulating film 141 may be disposed on the cell substrates 101 and 102 to cover the mold structure MS.

The channel structure (CH) may be disposed on the cell array area (CA). Each of the plurality of channel structures (CH) may extend in the third direction (Z) and penetrate the mold structure (MS). For example, the channel structure CH may be a pillar-shaped (eg, cylindrical) structure extending in the third direction (Z). Accordingly, the channel structure CH may intersect each of the gate electrodes GSL, WL1 to WLn, and ECL. In some embodiments, the width of the channel structure (CH) may decrease toward the cell substrates 101 and 102.

As shown in FIG. 5, the channel structure CH may include a first channel pattern 130 and a first channel insulating pattern 132.

The first channel pattern 130 may extend in the third direction (Z) and penetrate the mold structure (MS). The first channel pattern 130 may have a cup shape, for example. For another example, the first channel pattern 130 may have various shapes, such as a cylindrical shape, a rectangular cylinder shape, or a solid pillar shape. The first channel insulating pattern 132 may be interposed between the first channel pattern 130 and each of the gate electrodes (GSL, WL1 to WLn, and ECL). For example, the first channel insulating pattern 132 may extend along at least a portion of the outer surface of the first channel pattern 130 . In some embodiments, the first channel insulation pattern 132 may be formed as a multilayer. For example, as shown in FIG. 5, the first channel insulating pattern 132 includes a tunnel insulating film 132a, a charge storage film 132b, and a blocking insulating film sequentially stacked on the outer surface of the first channel pattern 130. (132c).

The tunnel insulating film 132a may include, for example, silicon oxide or a high dielectric constant material (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )) having a higher dielectric constant than silicon oxide. The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )).

In some embodiments, the channel structure CH may further include a first filling pattern 134. The first filling pattern 134 may fill the interior of the cup-shaped first channel pattern 130. The first channel pattern 130 may surround the outer wall of the first filling pattern 134.

The source layer 102 may be electrically connected to the first channel pattern 130 of each channel structure (CH). In some embodiments, a portion of the first channel pattern 130 may be disposed within the source layer 102. The lower surface 130ls of the first channel pattern 130 may be disposed in the source layer 102. The first channel insulating pattern 132 may extend along a portion of the side surface of the first channel pattern 130 . The first channel insulating pattern 132 may expose the lower portion of the first channel pattern 130 . The first channel insulating pattern 132 may expose the lower surface 130ls of the first channel pattern 130 and a portion of the side surface of the first channel pattern 130. The lower surface 130ls of the first channel pattern 130 may be disposed lower than the lower surface 132ls of the first channel pattern 130. The lower surface 130ls of the first channel pattern 130 may be in contact with the source layer 102. A portion of the side surface of the first channel pattern 130 may be in contact with the source layer 102.

For example, the lower surface 132ls of the first channel pattern 130 may be flat. Also, for example, the lower surface 132ls of the first channel pattern 130 may have a step. For example, the lower surface of the tunnel insulating film 132a may be placed lower than the lower surface of the charge storage film 132b, and the lower surface of the charge storage film 132b may be placed lower than the lower surface of the blocking insulating film 132c. there is.

In some embodiments, the channel structure (CH) may further include a first channel pad 136. The first channel pad 136 may be electrically connected to the first channel pattern 130.

In some embodiments, the plurality of channel structures CH may be arranged in a zigzag shape or a honeycomb shape. For example, as shown in FIG. 3, a plurality of channel structures (CH) may be arranged to stagger each other in the first direction (X) and the second direction (Y) parallel to the upper surfaces of the cell substrates 101 and 102. there is. This channel structure (CH) can further improve the integration of a semiconductor memory device. The number and arrangement of channel structures (CH) are merely illustrative and are not limited to those shown.

In some embodiments, a dummy channel structure (DCH) may be disposed within the mold structure (MS) of the expansion area (EXT). For example, the dummy channel structure (DCH) may have a shape similar to the channel structure (CH).

Referring to FIG. 6, in some embodiments, the channel structure (CH) may include a first channel (CHa) and a second channel (CHb) connected to each other. For example, the channel structure CH may be formed through a process for the first channel (CHa) and a process for the second channel (CHb). The first channel (CHa) may be at the bottom of the channel structure (CH), and the second channel (CHb) may be at the top of the channel structure (CH). At the boundary between the first channel (CHa) and the second channel (CHb), the width of the first channel (CHa) may be larger than the width of the second channel (CHb). The channel structure CH may have a bent portion at the boundary between the first channel CHa and the second channel CHb.

Additionally, a word line located near the boundary of the first channel (CHa) and the second channel (CHb) may be a dummy word line. For example, the word line (WLk, k is a natural number smaller than n) and the word line (WL(k+1)) that form the boundary of the first channel (CHa) and the second channel (CHb) are dummy word lines. You can. In this case, data may not be stored in memory cells connected to the dummy word line. Alternatively, the number of pages corresponding to memory cells connected to a dummy word line may be less than the number of pages corresponding to memory cells connected to a general word line. The voltage level applied to the dummy word line may be different from the voltage level applied to the general word line.

Referring again to FIGS. 3 to 5, the word line cutting structure (WLC) extends in the first direction (X) to cut the mold structure (MS) on the cell array area (CA) and the extended area (EXT). . Additionally, the plurality of word line cutting structures (WLC) may be spaced apart from each other and extend side by side in the first direction (X). The mold structure MS may be divided by the word line cutting structure WLC to form a plurality of memory cell blocks (eg, BLK1 to BLKn in FIG. 1). For example, two adjacent word line truncation structures (WLCs) may define a block of memory cells between them. A plurality of channel structures (CH) may be disposed within each memory cell block defined by a word line truncation structure (WLC). In some embodiments, the width of the word line truncation structure (WLC) may decrease toward the cell substrates 101 and 102.

The word line cutting structure (WLC) may extend in the first direction (X) to cut the source layer 102. For example, the lower surface of the word line cutting structure (WLC) may be lower than the upper surface of the source layer 102. For another example, the lower surface of the word line cutting structure (WLC) may be disposed on substantially the same plane as the lower surface of the source layer 102.

In some embodiments, the word line truncation structure (WLC) may include an insulating material. For example, the word line truncation structure (WLC) may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The second interlayer insulating film 142 and the third interlayer insulating film 143 may be disposed on the mold structure MS. The second interlayer insulating film 142 may be disposed on the first interlayer insulating film 141, and the third interlayer insulating film 143 may be disposed on the second interlayer insulating film 142.

The string selection line (SSL) and the fourth interlayer insulating film 144 may be disposed on the mold structure (MS). The string selection line (SSL) and the fourth interlayer insulating film 144 may be disposed on the third interlayer insulating film 143. The fourth interlayer insulating film 144 may be disposed on the third interlayer insulating film 143 where the string select line (SSL) is not disposed. For example, the string selection line (SSL) may be provided in the cell array area (CA), and the fourth interlayer insulating film 144 may be provided in the cell array area (CA), expansion area (EXT), and pad area (PA). It can be. The end of the string selection line (SSL) may be provided, for example, in the cell array area (CA). Also, for example, the end of the string selection line (SSL) may be disposed in the extended area (EXT) between the string selection line (SSL) and the first stud (180c) closest to the string selection line (SSL).

The string selection line (SSL) may be stacked with the gate electrodes (GSL, WL1 to WLn, ECL) in a step shape. For example, the string selection line (SSL) may extend to different lengths in the first direction (X) and have a step difference. The string selection line (SSL) may extend to different lengths and have a step difference in the second direction (Y).

For example, the thickness of the string selection line (SSL) may be thicker than the thickness of each gate electrode (GSL, WL1 to WLn, and ECL).

The string select line (SSL) may include a conductive material. The string select line (SSL) may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material containing p-type or n-type impurities. The string select line (SSL) may include polysilicon, for example.

As shown in FIG. 3 , the string separation structure (SLC) extends in the first direction (X) to separate the string selection line (SSL) on the cell array area (CA). Additionally, the plurality of string separation structures (SLC) may be spaced apart from each other and extend side by side in the first direction (X). A memory cell block defined by a word line truncation structure (WLC) may be divided by a string separation structure (SLC) to form a plurality of string areas. For example, the string separation structure (SLC) can define eight string areas within one memory cell block. At least a portion of the string separation structure (SLC) closest to the word line cutting structure (WLC) may overlap the word line cutting structure (WLC) in the third direction (Z). Alternatively, the string separation structure (SLC) closest to the word line cutting structure (WLC) may not overlap the word line cutting structure (WLC) in the third direction (Z).

The string separation structure (SLC) may pass through the string selection line (SSL). For example, the string separation structure (SLC) may further penetrate the third interlayer insulating film 143. In some embodiments, the width of the string isolation structure (SLC) may decrease toward the cell substrates 101 and 102.

The string isolation structure (SLC) may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The string selection channel structure (SCH) may be placed on the cell array area (CA). The string selection channel structure (SCH) may extend in the third direction (Z) and pass through the string selection line (SSL). The string selection channel structure (SCH) may be disposed on the channel structure (CH) through the string selection line (SSL). The fifth interlayer insulating film 145 may be disposed on the string select line (SSL) and the fourth interlayer insulating film 144. The string select channel structure (SCH) may penetrate the fifth interlayer insulating film 145, the string select line (SSL), the third interlayer insulating film 143, and the second interlayer insulating film 142. In some embodiments, the width of the string select channel structure (SCH) may decrease toward the cell substrates 101 and 102.

The string selection channel structure (SCH) may include a second channel pattern 160, a second channel insulating pattern 162, a second filling pattern 164, and a second channel pad 166.

The second channel pattern 160 may extend in the third direction (Z) and pass through the string selection line (SSL). The second channel pattern 160 may contact the first channel pattern 130 and the first channel pad 136 of the channel structure (CH). Accordingly, the string selection channel structure (SCH) may be electrically connected to the channel structure (CH).

In some embodiments, the second channel pattern 160 in the second interlayer insulating film 142 may have a shape that protrudes toward the second interlayer insulating film 142. For example, the second channel pattern 160 may have a cup shape whose width decreases as it approaches the mold structure MS, but the width may increase within the second interlayer insulating film 142.

The first channel pattern 130 and the second channel pattern 160 may each include a semiconductor material such as single crystal silicon, polycrystalline silicon, organic semiconductor material, and carbon nanostructure.

The second channel insulating pattern 162 may be interposed between the second channel pattern 160 and the string select line (SSL). For example, the second channel insulating pattern 162 may extend along the third interlayer insulating film 143, the string select line (SSL), and the outer wall of the second channel pattern 160 in the fifth interlayer insulating film 145. there is. The first channel insulating pattern 132 and the second channel insulating pattern 162 may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. . The high dielectric constant material is, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium. oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

The second filling pattern 164 may fill the interior of the second channel pattern 160. The second channel pattern 160 may surround the outer wall of the second filling pattern 164. The first filling pattern 134 and the second filling pattern 164 may each include an insulating material, for example, silicon oxide.

The second channel pad 166 may be electrically connected to the top of the second channel pattern 160. The first channel pad 136 and the second channel pad 166 may each include, for example, polysilicon doped with impurities.

In some embodiments, at least one string select channel structure (SCH) may be shifted away from the string separation structure (SLC) that does not overlap the word line truncation structure (WLC). For example, based on the center (C1) of the channel structure (CH), the center (C2) of the string selection channel structure (SCH) is a string that does not overlap the word line cut structure (WLC) in the third direction (Z). It can be shifted in a direction away from the separation structure (SLC). Accordingly, the area where the string separation structure (SLC) is formed can be secured. For example, the amount by which the center (C2) of the string selection channel structure (SCH) is shifted based on the center (C1) of the channel structure (CH) may be different for each string selection channel structure (SCH). For another example, among the string selection channel structures (SCH) placed between neighboring string separation structures (SLC), only the string selection channel structure (SCH) closest to the string separation structure (SLC) is used as a string separation structure (SLC). It may also be shifted in a direction away from.

The arcing prevention contact 120 may be disposed on the cell array area (CA). The arcing prevention contact 120 may extend in the third direction (Z) and penetrate the mold structure (MS). For example, the channel structure CH may be a pillar-shaped (eg, cylindrical) structure extending in the third direction (Z). In some embodiments, the width of anti-arc contact 120 may decrease toward cell substrates 101 and 102.

The arcing prevention contact 120 may cut a portion of the cell substrates 101 and 102. For example, the lower surface of the anti-arcing contact 120 may be lower than the front surface of the cell substrates 101 and 102. The lower surface of the arcing prevention contact 120 may be disposed within the cell substrates 101 and 102. The lower surface of the arcing prevention contact 120 may be in contact with the cell substrates 101 and 102.

For example, the arcing prevention contact 120 may overlap the source layer 102 in the third direction (Z). The arcing prevention contact 120 may contact the source layer 102. The arcing prevention contact 120 may be electrically connected to the source layer 102. As another example, the anti-arcing contact 120 may overlap the insulating layer 101 in the third direction (Z). The lower surface of the arcing prevention contact 120 may be disposed within the insulating layer 101. The arcing prevention contact 120 may be in contact with the insulating layer 101.

The arcing prevention contact 120 may have a structure different from the channel structure (CH). The arcing prevention contact 120 may have a single-layer structure. The arcing prevention contact 120 may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon.

Referring to FIG. 7 , in some embodiments, the arcing prevention contact 120 may include a first arcing prevention contact 120a and a second arcing prevention contact 120b connected to each other. For example, the anti-arc contact 120 may be formed through a process for the first anti-arc contact 120a and a process for the second anti-arc contact 120b. The first anti-arc contact 120a may be below the anti-arc contact 120, and the second anti-arc contact 120b may be above the anti-arc contact 120. At the boundary between the first arcing prevention contact 120a and the second arcing prevention contact 120b, the width of the first arcing prevention contact 120a may be larger than the width of the second arcing prevention contact 120b. The arcing prevention contact 120 may have a bent portion at the boundary between the first arcing prevention contact 120a and the second arcing prevention contact 120b.

Referring again to FIGS. 3 to 5 , the arcing prevention contact 120 may be disposed at the end of the string selection line (SSL). The arcing prevention contact 120 may be closer to the extended area EXT than to the channel structure CH. For example, one anti-arcing contact 120 may be disposed between neighboring string isolation structures (SLC).

The first insulating pattern 112 may be disposed between the anti-arcing contact 120 and the mold structure MS. In some embodiments, the first insulating pattern 112 may extend along the side of the anti-arcing contact 120 . Accordingly, the anti-arcing contact 120 may be electrically separated from the gate electrodes (GSL, WL1 to WLn, and ECL). The first insulating pattern 112 may expose the lower surface of the arcing prevention contact 120 .

The first insulating pattern 112 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The anti-arcing insulating pattern 155 may be disposed on the cell array area CA. The anti-arcing insulating pattern 155 may extend in the third direction (Z) and penetrate the string selection line (SSL). The anti-arc insulating pattern 155 may be in contact with the anti-arc contact 120. Accordingly, the arcing prevention contact 120 may be electrically separated from the first metal pattern 186a. In some embodiments, the width of the anti-arc insulating pattern 155 may decrease toward the cell substrates 101 and 102. The anti-arcing insulating pattern 155 may have a single-layer structure. The anti-arcing insulating pattern 155 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The cell contact 170 may be placed on the extended area EXT. The cell contact 170 may extend in the third direction (Z) and penetrate the mold structure (MS) on the extended area (EXT). The cell contact 170 may be electrically connected to each of the gate electrodes (GSL, WL1 to WLn, and ECL) through the connection region CR. For example, the cell contact 170 may penetrate the connection region CR, and a side surface of the cell contact 170 may contact an inner surface of the connection region CR. For example, the lower surface of the cell contact 170 may be disposed within the insulating layer 101.

In some embodiments, the cell contact 170 may include a penetrating portion 171 and a protruding portion 172.

The penetrating portion 171 may extend in the third direction (Z) and penetrate the mold structure (MS) on the extended area (EXT). For example, the penetrating portion 171 may be a pillar-shaped (eg, cylindrical) structure extending in the third direction (Z). In some embodiments, the width of the through portion 171 may decrease toward the cell substrates 101 and 102.

The protrusion 172 may protrude from the side of the penetrating part 171 and contact the connection region CR. For example, the inner surface of the connection region CR may protrude from the side of the penetrating portion 171. For example, the protrusion 172 may be an annular structure surrounding the side surface of the penetrating part 171. Accordingly, the cell contact 170 may be electrically connected to each of the gate electrodes (GSL, WL1 to WLn, and ECL).

The second insulating pattern 114 may be disposed between the cell contact 170 and the mold structure MS. The second insulating pattern 114 may be disposed between the cell contact 170 and the gate electrodes (GSL, WL1 to WLn, and ECL) rather than the connection region (CR). The second insulating pattern 114 may be disposed between the cell contact 170 and the gate electrodes (GSL, WL1 to WLn, ECL) whose top surfaces are not exposed. For example, the second insulating pattern 114 may be a ring-shaped structure surrounding the side surface of the cell contact 170. Accordingly, the cell contact 170 may be electrically connected to the gate electrodes GSL, WL1 to WLn, and ECL disposed at the top, and may be electrically separated from the remaining gate electrodes except for the gate electrode disposed at the top.

The second insulating pattern 114 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

In some embodiments, the thickness of the connection region CR may be thicker than the thickness of other gate electrodes disposed below it. Accordingly, the thickness of the second insulating pattern 114 may be smaller than the thickness of the protrusion 172.

Referring to FIG. 8 , in some embodiments, the cell contact 170 may include a first cell contact 170a and a second cell contact 170b connected to each other. For example, the cell contact 170 may be formed through a process for the first cell contact 170a and a process for the second cell contact 170b. The first cell contact 170a may be below the cell contact 170, and the second cell contact 170b may be above the cell contact 170. At the boundary between the first cell contact 170a and the second cell contact 170b, the width of the first cell contact 170a may be larger than the width of the second cell contact 170b. The cell contact 170 may have a bent portion at the boundary between the first cell contact 170a and the second cell contact 170b.

Referring again to FIGS. 3 to 5 , the source contact 174 and the input/output contact 176 may be disposed on the pad area PA. The source contact 174 and the input/output contact 176 may extend in the third direction (Z) and penetrate the first interlayer insulating film 141 on the pad area (PA). In some embodiments, the width of the source contact 174 and the width of the input/output contact 176 may gradually decrease toward the cell substrates 101 and 102 .

The mold structure MS may expose a portion of the upper surface of the source layer 102. The source contact 174 may be electrically connected to the source layer 102. For example, the lower surface of the source layer 102 may be disposed within the source layer 102. The source contact 184 may penetrate the upper surface of the source layer 102 exposed by the mold structure MS and be electrically connected to the source layer 102. The mold structure MS may expose a portion of the upper surface of the insulating layer 101. The input/output contact 176 may be electrically connected to the first input/output pad 109. For example, the lower surface of the input/output contact 176 may be disposed within the insulating layer 101. The input/output contact 176 may penetrate the upper surface of the insulating layer 101 exposed by the mold structure MS and be electrically connected to the first input/output pad 109.

The first insulating film 108 may be disposed on the cell substrates 101 and 102. The first insulating film 108 may cover the lower surfaces of the cell substrates 101 and 102. The first input/output pad 109 may be disposed on the first insulating film 108 . The first input/output pad 109 may be electrically connected to the peripheral circuit structure (PERI) through the input/output contact 176.

In some embodiments, the contact 178 may penetrate at least a portion of the first insulating film 108 and the insulating layer 101. The first input/output pad 109 may be electrically connected to the input/output contact 176 through a contact 178. In some embodiments, the width of the contact 178 may decrease toward the first interlayer insulating film 141 .

The cell contact 170, source contact 174, input/output contact 176, and contact 178 are each made of a conductive material, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), or silicon. It may include semiconductor materials such as. The first input/output pad 109 may include a conductive material. For example, the first input/output pad 109 may include aluminum (Al).

In some embodiments, the source contact 174 and the input/output contact 176 may each include a first part and a second part connected to each other. For example, the source contact 174 and the input/output contact 176 may be formed through a process for the first part and a process for the second part, respectively. The first part may be a lower part of the source contact 174 and the input/output contact 176, and the second part may be an upper part of the source contact 174 and the input/output contact 176. At the boundary between the first part and the second part, the width of the first part may be greater than the width of the second part. The source contact 174 and the input/output contact 176 may each include a bent portion.

The first metal patterns 186a, 186b, 186c, and 186d may be disposed on the string selection line SSL and the fourth interlayer insulating layer 144. The string select channel structure (SCH), cell contact 170, source contact 174, input/output contact 176, and string select line (SSL) are electrically connected to the first metal patterns 186a, 186b, 186c, 186d, and 186e. It can be connected to .

For example, studs 182a and 184a may be sequentially placed on the string select channel structure (SCH). The string selection channel structure (SCH) may be electrically connected to the first metal pattern 186a through studs 182a and 184a. The first metal pattern 186a may be a bit line (eg, BL in FIG. 2) of a semiconductor memory device. Studs 180b, 182b, and 184b may be sequentially arranged on the cell contact 170. The cell contact 170 may be electrically connected to the first metal pattern 186b through the studs 180b, 182b, and 184b. Studs 180c, 182c, and 184c may be sequentially placed on the source contact 174. The source contact 174 may be electrically connected to the first metal pattern 186c through the studs 180c, 182c, and 184c. Studs 180d, 182d, and 184d may be sequentially arranged on the input/output contact 176. The input/output contact 176 may be electrically connected to the first metal pattern 186d through the studs 180d, 182d, and 184d. Studs 182e and 184e may be sequentially arranged on the string selection line (SSL). The string selection line SSL may be electrically connected to the first metal pattern 186a through the studs 182e and 184e.

The studs 180c, 180d, and 180e may be disposed in the second to fifth interlayer insulating films 142 to 145. The sixth and seventh interlayer insulating films 146 and 147 may be sequentially stacked on the fifth interlayer insulating film 145. The first interconnection insulating film 190 may be disposed on the seventh interlayer insulating film 147 . The studs 182a, 182b, 182c, and 182d may be disposed in the sixth interlayer insulating film 146. The stud 182e may be disposed in the fifth and sixth interlayer insulating films 145 and 146. The studs 184a, 184b, 184c, and 184d may be disposed in the seventh interlayer insulating film 147. The first metal patterns 186a, 186b, 186c, and 186d may be disposed in the first interconnection insulating layer 190.

The first to seventh interlayer insulating films 141 to 147 may each include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material with a dielectric constant smaller than that of silicon oxide. there is. For example, the third interlayer insulating film 143 may include a nitride-based insulating material, and the first and second interlayer insulating films 141 and 142 and the fourth to seventh interlayer insulating films 144 to 147 may include an oxide-based insulating material. It may contain an insulating material.

For example, studs connected to the first metal pattern 186a may not be disposed on the anti-arcing insulating pattern 155. At least one of the first stud and the second stud may not be disposed on the anti-arcing insulating pattern 155. As another example, a stud connected to the first metal pattern 186a may be disposed on the anti-arcing insulating pattern 155. However, the arcing prevention contact 120 and the first metal pattern 186a may be electrically separated by the arcing prevention insulating pattern 155.

The peripheral circuit structure (PERI) includes a peripheral circuit board 200, a peripheral circuit element (PT), a wiring structure 260, a second inter-wiring insulating film 240, a second bonding via 292, and a second bonding metal 294. ) may include.

The peripheral circuit board 200 may include, for example, a semiconductor substrate such as a silicon substrate, germanium substrate, or silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

Peripheral circuit elements PT may be formed on the peripheral circuit board 200 . The peripheral circuit element PT may constitute a peripheral circuit (eg, 30 in FIG. 1) that controls the operation of the semiconductor memory device. For example, the peripheral circuit element PT may include control logic (e.g., 37 in FIG. 1), a row decoder (e.g., 33 in FIG. 1), and a page buffer (e.g., 35 in FIG. 1). In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit element PT is disposed may be referred to as the front side of the peripheral circuit board 200. Conversely, the surface of the peripheral circuit board 200 opposite to the front surface of the peripheral circuit board 200 may be referred to as the back side of the peripheral circuit board 200.

The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, peripheral circuit elements (PT) may include various active elements such as transistors, as well as various passive elements such as capacitors, resistors, and inductors. It may be possible.

The interconnection structure 260 may be formed on the peripheral circuit element PT. For example, a second insulating film 240 between interconnections may be formed on the front surface of the peripheral circuit board 200, and the interconnection structure 260 may be formed within the insulating film 240 between interconnections. The wiring structure 260 may be electrically connected to the peripheral circuit element PT. The number and arrangement of layers of the interconnection structure 260 shown are merely illustrative and are not limited thereto.

The peripheral circuit structure (PERI) may be disposed on the memory cell structure (CELL). In some embodiments, the front surface of the peripheral circuit board 200 may face the front surface of the cell boards 101 and 102. The peripheral circuit structure (PERI) may be disposed on the front surface of the cell substrates 101 and 102. The mold structure MS may be disposed between the cell substrates 101 and 102 and the peripheral circuit structure PERI.

A semiconductor memory device according to some embodiments may have a C2C (chip to chip) structure. The C2C structure fabricates a first chip including a memory cell structure (CELL) on a first wafer (e.g., cell substrates 101 and 102), and fabricates a first chip including a memory cell structure (CELL) on a second wafer (e.g., peripheral circuitry) different from the first wafer. This means manufacturing a second chip including a peripheral circuit structure (PERI) on the substrate 200 and then connecting the first chip and the second chip to each other by a bonding method.

For example, the bonding method refers to a method of electrically connecting the first bonding metal 194 formed on the top metal layer of the first chip and the second bonding metal 294 formed on the top metal layer of the second chip. can do. For example, when the first bonding metal 194 and the second bonding metal 294 are made of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only an example, and of course, the first bonding metal 194 and the second bonding metal 294 may be formed of various other metals such as aluminum (Al) or tungsten (W).

As the first bonding metal 194 and the second bonding metal 294 are bonded, the first metal patterns 186a, 186b, 186c, and 186d may be connected to the wiring structure 260. The first metal patterns 186a, 186b, 186c, and 186d may be electrically connected to the first bonding metal 194 through the first bonding via 192. The first bonding via 192 and the first bonding metal 194 may be disposed in the first interconnection insulating layer 190. The wiring structure 260 may be electrically connected to the second bonding metal 294 through the second bonding via 292. The second bonding via 292 and the second bonding metal 294 may be disposed in the second interconnection insulating layer 240 . Through this, the first metal pattern 186a, each of the gate electrodes (GSL, WL1 to WLn, ECL), or the string selection line (SSL) may be electrically connected to at least one of the peripheral circuit elements (PT).

The second insulating film 208 may be disposed on the peripheral circuit board 200 . The second insulating film 208 may cover the lower surface of the peripheral circuit board 200. The second input/output pad 209 may be disposed on the second insulating film 208. The second input/output pad 209 may be electrically connected to at least one of the peripheral circuit elements PT disposed in the peripheral circuit structure PERI through the second input/output contact 276. The second input/output pad 209 may be electrically separated from the peripheral circuit board 200 by a second insulating film 208 .

FIG. 9 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments. For reference, FIG. 9 is another cross-sectional view taken along line II of FIG. 3. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 will be briefly described or omitted.

Referring to FIG. 9 , in a semiconductor memory device according to some embodiments, the cell contact 170 may extend in the third direction (Z) and penetrate the first interlayer insulating layer 141 on the extended area (EXT). The lower surface of the cell contact 170 may be in contact with the connection region CR of each of the gate electrodes GSL, WL1 to WLn, and ECL. Accordingly, the cell contact 170 may be electrically connected to the gate electrodes GSL, WL1 to WLn, and ECL disposed at the top, and may be electrically separated from the remaining gate electrodes except for the gate electrode disposed at the top. The second insulating pattern (114 in FIG. 4) may be omitted. For example, the lower surface of the cell contact 170 may be disposed within each of the gate electrodes (GSL, WL1 to WLn, and ECL).

FIG. 10 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments. For reference, FIG. 10 is another cross-sectional view taken along line II of FIG. 3. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 will be briefly described or omitted.

Referring to FIG. 10 , in a semiconductor memory device according to some embodiments, the first insulating pattern 112 may be disposed between the arcing prevention contact 120 and the gate electrodes (GSL, WL1 to WLn, and ECL). For example, the first insulating pattern 112 may be a ring-shaped structure surrounding the side surface of the arcing prevention contact 120 . Accordingly, the anti-arcing contact 120 may be electrically separated from the gate electrodes (GSL, WL1 to WLn, and ECL).

FIG. 11 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments. FIG. 12 is an enlarged view of area Q2 in FIG. 11. For reference, FIG. 11 is another cross-sectional view taken along line II of FIG. 3. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 will be briefly described or omitted.

11 and 12, in the semiconductor memory device according to some embodiments, the cell substrates 101, 102, 103, and 104 include an insulating layer 101, a source layer 102, a semiconductor layer 103, and a support layer. It may include (104). For example, the insulating layer 101 may be provided in the extension area (EXT) and the pad area (PA), and the source layer 102, semiconductor layer 103, and support layer 104 may be provided in the cell array area (CA). and may be provided in the pad area (PA). In some embodiments, the source layer 102, the semiconductor layer 103, and the support layer 104 may be formed on the cell array area CA and not on the expansion area EXT.

The semiconductor layer 103 may include, for example, a semiconductor substrate such as a silicon substrate, germanium substrate, or silicon-germanium substrate. Alternatively, the semiconductor layer 103 may include a Silicon-On-Insulator (SOI) substrate or a Germanium-On-Insulator (GOI) substrate. The semiconductor layer 103 may include, for example, polysilicon doped with impurities, metal, or metal silicide. The semiconductor layer 103 may be formed of multiple layers.

The source layer 102 may be interposed between the semiconductor layer 103 and the mold structure MS. The source layer 102 may extend conformally along the top surface of the semiconductor layer 103. The source layer 102 may be electrically connected to the first channel pattern 130 of each channel structure (CH). For example, as shown in FIG. 12, the channel structure CH may penetrate the source layer 102. The lower portion of the channel structure (CH) may be disposed within the semiconductor layer 103. The source layer 102 may penetrate the first channel insulating pattern 132 and contact the side surface of the first channel pattern 130 .

In some embodiments, a portion of the source layer 102 adjacent to the first channel pattern 130 may protrude toward the first channel insulating pattern 132. For example, in an area adjacent to the first channel pattern 130, the length that the source layer 102 extends in the third direction (Z) may be longer. Through this, the source layer 102 can contact the first channel pattern 130 over a larger area.

In some embodiments, a base insulating film may be interposed between the semiconductor layer 103 and the source layer 102. For example, the base insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The support layer 104 may be formed on the semiconductor layer 103 and the source layer 102. The support layer 104 may be interposed between the source layer 102 and the mold structure (MS). For example, the support layer 104 may extend conformally along the top surface of the semiconductor layer 103 and the top surface of the source layer 102. Support layer 104 may include polysilicon, for example.

The support layer 104 may be used as a support to prevent the mold stack from collapsing or falling during a replacement process for forming the source layer 102. For example, the source layer 102 may expose a portion of the upper surface of the semiconductor layer 103, and a portion of the support layer 104 may extend along the exposed upper surface of the semiconductor layer 103 to form the semiconductor layer 103. can be in contact with the upper surface of

For example, the top surface of the support layer 104 may be disposed on substantially the same plane as the top surface of the insulating layer 101. For another example, the top surface of the support layer 104 may be disposed lower than the top surface of the insulating layer 101.

The semiconductor layer 103, source layer 102, and support layer 104 may be provided as a common source line (eg, CSL in FIG. 2) of the semiconductor memory device.

For example, the arcing prevention contact 120 may overlap the source layer 102 in the third direction (Z). The arcing prevention contact 120 may cut portions of the source layer 102, the support layer 104, and the semiconductor layer 103. The lower surface of the arcing prevention contact 120 may be disposed within the semiconductor layer 103. The arcing prevention contact 120 may contact the semiconductor layer 103. As another example, the anti-arcing contact 120 may overlap the insulating layer 101 in the third direction (Z). The lower surface of the arcing prevention contact 120 may be disposed within the insulating layer 101. The arcing prevention contact 120 may be in contact with the insulating layer 101.

The word line cutting structure (WLC) can cut the source layer 102 and the support layer 104. For example, the lower surface of the word line cutting structure (WLC) may be disposed lower than the lower surface of the source layer 102. For another example, the lower surface of the word line cutting structure (WLC) may be disposed on substantially the same plane as the lower surface of the source layer 102.

In a semiconductor memory device according to some embodiments, the front side of the peripheral circuit board 200 may face the back side of the cell substrates 101, 102, 103, and 104. The peripheral circuit structure (PERI) may be disposed on the rear side of the cell substrates 101, 102, 103, and 104. The cell substrates 101, 102, 103, and 104 may be disposed between the mold structure MS and the peripheral circuit structure PERI.

For example, the cell contact 170 or the input/output contact 176 may penetrate the insulating layer 101 and be electrically connected to the wiring structure 260. For another example, the cell contact 170 or the input/output contact 176 may be electrically connected to the wiring structure 260 through a separate contact from the insulating layer 101.

The peripheral circuit structure (PERI) may further include a through via 220. The through via 220 may connect the semiconductor layer 103 and the peripheral circuit board 200.

FIG. 13 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments. FIG. 14 is an enlarged view of area Q3 in FIG. 13. For reference, FIG. 13 is another cross-sectional view taken along line II of FIG. 3. For convenience of explanation, parts that overlap with those described above using FIGS. 11 and 12 will be briefly described or omitted.

Referring to FIGS. 13 and 14 , in the semiconductor memory device according to some embodiments, the lower surface of the first channel pattern 130 of the channel structure (CH) may contact the source layer 102. For example, the source layer 102 may be in further contact with the lower surface of the first channel insulating pattern 132. The channel structure (CH) may not penetrate the source layer 102.

In some embodiments, the cell substrates 101, 102, and 105 may further include a metal silicide layer 105 disposed between the source layer 102 and the peripheral circuit structure (PERI).

FIG. 15 is another example cross-sectional view illustrating a semiconductor memory device according to some embodiments. Figure 16 is an enlarged view of area Q4 in Figure 15. For reference, FIG. 15 is another cross-sectional view taken along line II of FIG. 3. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 12 will be briefly described or omitted.

Referring to FIGS. 15 and 16 , a semiconductor memory device according to some embodiments may include a source pattern 106 . The source pattern 106 may be disposed on the semiconductor layer 103. The source pattern 106 may be electrically connected to the first channel pattern 130 of the channel structure (CH). For example, the first channel pattern 130 may penetrate the first channel insulating pattern 132 and contact the top surface of the source pattern 106. The source pattern 106 and the semiconductor layer 103 may be provided as a common source line (eg, CSL in FIG. 2) of a semiconductor memory device.

The source pattern 106 may include a conductive material, for example, polysilicon or metal doped with impurities, but is not limited thereto. For example, the source pattern 106 may be formed from the semiconductor layer 103 through a selective epitaxial growth process, but is not limited thereto.

For example, the lower portion of the source pattern 106 may be buried within the semiconductor layer 103. For another example, the lower surface of the source pattern 106 may be disposed on substantially the same plane as the upper surface of the semiconductor layer 103.

In some embodiments, the top surface of the source pattern 106 may intersect some of the gate electrodes (GSL, WL1 to WLn, and ECL). For example, the top surface of the source pattern 106 may be formed to be higher than the top surface of the ground selection line (GSL). In this case, a gate insulating layer 110S may be interposed between the source pattern 106 and a gate electrode (eg, ground select line (GSL)) that intersects the source pattern 106 .

The extension portion 102a may extend along the top surface of the semiconductor layer 103. The protrusion 102b may protrude from the extension portion 102a toward the semiconductor layer 103. That is, the top surface of the semiconductor layer 103 may not be flat due to the extension portion 102a. The channel structure CH may overlap the protrusion 102b in the third direction (Z).

For example, the word line cutting structure (WLC) and the anti-arcing contact 120 may overlap the protrusion 102b in the third direction (Z). As another example, at least one of the word line cutting structure (WLC) and the anti-arcing contact 120 may not overlap the protrusion 102b in the third direction (Z).

The arcing prevention contact 120 may contact the source layer 102. For example, the lower surface of the arcing prevention contact 120 may be disposed within the source layer 102 and may be in contact with the source layer 102 . As another example, the lower surface of the anti-arcing contact 120 may be disposed in the semiconductor layer 103, and the side surface of the anti-arcing contact 120 may be in contact with the source layer 102.

17 to 28 are intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 will be briefly described or omitted.

Referring to FIG. 17 , a substrate 300 including a cell array area (CA), an extension area (EXT), and a pad area (PA) may be provided. The substrate 300 may include a cell array area (CA), an extension area (EXT), and a pad area (PA).

A pre-mold structure (pMS) may be formed on the front surface of the substrate 300. The pre-mold structure (pMS) may include a plurality of mold insulating films 110 and a plurality of mold sacrificial films 115 that are alternately stacked on the substrate 300. The pre-mold structure (pMS) on the extended area (EXT) may be patterned in a stepped shape. Accordingly, each mold sacrificial layer 115 on the extended area EXT may include a connection area CR whose upper surface is exposed on the extended area EXT. In the following description, the surface of the substrate 300 on which the pre-mold structure (pMS) is formed may be referred to as the front side of the substrate 300. Conversely, the surface of the substrate 300 opposite to the front surface of the substrate 300 may be referred to as the back side of the substrate 300.

The mold sacrificial layer 115 may include a material having an etch selectivity with respect to the mold insulating layer 110 . For example, the mold insulating layer 110 may include silicon oxide, and the mold sacrificial layer 115 may include silicon nitride.

A first interlayer insulating film 141 may be formed covering the substrate 300 and the pre-mold structure (pMS).

Referring to FIGS. 17 and 18 , a channel structure (CH) penetrating the pre-mold structure (pMS) may be formed on the cell array area (CA). After a channel hole penetrating the pre-mold structure (pMS) is formed, a channel structure (CH) may be formed to fill the channel hole. It may be disposed in the substrate 300 on the lower surface of the channel structure (CH). The channel structure CH may include a first channel pad 136 formed on the top.

An anti-arcing contact 120 that penetrates the pre-mold structure (pMS) may be formed on the cell array area (CA). After an anti-arc hole penetrating the pre-mold structure (pMS) is formed, an anti-arc contact 120 may be formed to fill the anti-arc hole. For example, the channel hole and the anti-arcing hole may be formed simultaneously. The first insulating pattern 112 may be formed on the sidewall of the arcing prevention contact 120 . A portion of the anti-arcing contact 120 may be disposed within the substrate 300 . The lower surface of the arcing prevention contact 120 may be disposed within the substrate 300 .

A cell contact 170 penetrating the pre-mold structure (pMS) may be formed on the extended area (EXT). The cell contact 170 may include a penetrating portion 171 extending in the third direction (Z) and a protruding portion 172 protruding from the penetrating portion 171 toward the mold sacrificial layer 115 in the connection region CR. You can. The second insulating pattern 114 may be formed between the mold sacrificial layer 115 below the protrusion 172 and the penetrating portion 171. The second insulating pattern 114 may be formed between the mold sacrificial layer 115 and the cell contact 170 rather than in the connection region CR. A portion of the cell contact 170 may be disposed within the substrate 300 . The lower surface of the cell contact 170 may be disposed within the substrate 300 .

A source contact 174 penetrating the first interlayer insulating film 141 may be formed on the semiconductor layer 103 in the pad area PA. An input/output contact 176 penetrating the first interlayer insulating film 141 may be formed on the substrate 300 in the pad area PA. A portion of the input/output contact 176 may be disposed within the substrate 300 . The lower surface of the input/output contact 176 may be disposed within the substrate 300.

A word line cutting hole (WLCH) that penetrates the pre-mold structure (pMS) may be formed on the cell array area (CA). The word line cutting hole (WLCH) may penetrate the front surface of the substrate 300. The lower surface of the word line cutting hole (WLCH) may be disposed within the substrate 300.

Gate electrodes (GSL, WL1 to WLn, GSL) may be formed. The gate electrodes (GSL, WL1 to WLn, GSL) may be formed through a replacement process. The mold sacrificial layer 115 exposed by the word line cutting structure (WLC) may be selectively removed. Subsequently, gate electrodes (GSL, WL1 to WLn, ECL) may be formed to replace the area from which the mold sacrificial layer 115 was removed. Through this, a mold structure MS including a plurality of gate electrodes GSL, WL1 to WLn, and ECL can be formed. After the mold structure MS is formed, the word line cut structure WLC may be formed to fill the word line cut hole WLCH.

Referring to FIG. 19 , a second interlayer insulating film 142, a third interlayer insulating film 143, and a string select line (SSL) may be formed sequentially on the first interlayer insulating film 141.

A first hole H1 may be formed penetrating the string selection line SSL. The first hole H1 may overlap the anti-arcing contact 120 in a direction perpendicular to the front surface of the substrate 300. The third interlayer insulating film 143 may include a material having an etch selectivity with respect to the second interlayer insulating film 142 . For example, the second interlayer insulating film 142 may include silicon oxide, and the third interlayer insulating film 143 may include silicon nitride. The first hole H1 may expose the third interlayer insulating film 143. For example, the lower surface of the first hole H1 may be disposed within the third interlayer insulating film 143. The first hole H1 may expose the third interlayer insulating film 143.

Referring to FIG. 20 , the first expansion hole EH1 may be formed by removing the third interlayer insulating film 143 and the second interlayer insulating film 142 through the first hole H1. The first expansion hole EH1 may expose at least a portion of the upper surface of the arcing prevention contact 120.

Referring to FIG. 21 , an anti-arcing sacrificial film 150 may be formed to fill the first expansion hole EH1. The arcing prevention sacrificial layer 150 may contact the arcing prevention contact 120 and the string selection line (SSL). The arcing prevention contact 120 may be electrically connected to the string select line (SSL) through the arcing prevention sacrificial film 150. The string selection line (SSL) may be connected to the substrate 300 through the anti-arc sacrificial layer 150 and the anti-arc contact 120.

The arcing prevention sacrificial layer 150 may include a conductive material. The anti-arcing sacrificial layer 150 may include at least one of polysilicon, tungsten (W), carbon (C), tanium nitride (TiN), and combinations thereof.

Referring to FIG. 22, a string separation structure (SLC) that separates the string selection line (SSL) may be formed on the cell array area (CA). For example, the lower surface of the string separation structure (SLC) may be disposed above the upper surface of the first interlayer insulating film 141.

A fourth interlayer insulating film 144 may be formed on the third interlayer insulating film 143. For example, the top surface of the third interlayer insulating film 143 may be disposed on substantially the same plane as the top surface of the string select line (SSL).

Referring to FIG. 23, a fifth interlayer insulating film 145 may be formed on the string selection line (SSL) and the fourth interlayer insulating film 144.

A second hole H2 may be formed penetrating the fifth interlayer insulating film 145, the string selection line (SSL), and the third interlayer insulating film 143. The second hole H2 may overlap a portion of the channel structure CH in a direction perpendicular to the front surface of the substrate 300 . The second hole H2 may expose the second interlayer insulating film 142. The second hole H2 may be shifted in a direction away from the string separation structure SLC that does not overlap the word line cutting structure WLC. For example, based on the center of the channel structure (CH), the center of the second hole (H2) moves away from the string separation structure (SLC) that does not overlap the word line cutting structure (WLC) in the third direction (Z). can be shifted.

Referring to FIG. 24 , the second expansion hole EH2 may be formed by removing the second interlayer insulating film 142 through the second hole H2. A portion of the second interlayer insulating film 142 exposed by the second hole H2 may be removed to form the second expansion hole EH2. The second expansion hole EH2 may expose a portion of the upper surface of the channel structure CH. The second expansion hole EH2 may expose a portion of the upper surface of the first channel pattern 130 and a portion of the upper surface of the first channel pad 136.

The arcing prevention contact 120 can prevent arcing by grounding the string select line (SSL) during the manufacturing process of the semiconductor memory device. For example, when forming a through hole for forming a string separation structure (SLC) and/or through holes for forming a string selection channel structure (SCH) (e.g., the second hole (H2) in FIG. 23 and the second hole (H2) in FIG. 24 An arcing phenomenon may occur when forming the second expansion hole (EH2). At this time, the charge accumulated in the string selection line (SSL) may be discharged to the substrate 300 through the anti-arcing sacrificial layer 150 and the anti-arc contact 120. That is, the anti-arc sacrificial layer 150 and the anti-arc contact 120 may provide a passage for the charges to be discharged to the substrate 300. Accordingly, the electrical characteristics and reliability of the semiconductor memory device can be improved.

Referring to FIG. 25, a string selection channel structure (SCH) may be formed in the second hole (H2). A string selection channel structure (SCH) including a second channel pattern 160, a second channel insulating pattern 162, a second filling pattern 164, and a second channel pad 166 may be formed. The second channel pattern 160 may contact the first channel pad 136 and the first channel pattern 130.

A third hole H3 may be formed penetrating the fifth interlayer insulating film 145. The third hole H3 may expose the upper surface of the anti-arcing sacrificial layer 150.

Referring to FIG. 26, the anti-arcing sacrificial film 150 can be removed through the third hole H3. Accordingly, a fourth hole H4 exposing the upper surface of the arcing prevention contact 120 may be formed.

Referring to FIG. 27 , an anti-arcing insulating pattern 155 may be formed to fill the fourth hole H4.

Referring to FIG. 28 , studs 180c, 180d, and 180e may be formed in the second to fifth interlayer insulating films 142 to 145. The sixth and seventh interlayer insulating films 146 and 147 may be formed sequentially on the fifth interlayer insulating film 145 . Studs 182a, 182b, 182c, and 182d may be formed in the sixth interlayer insulating film 146. Studs 184a, 184b, 184c, and 184d may be formed in the seventh interlayer insulating film 147. A first interconnection insulating layer 190 may be formed on the seventh interconnection insulating layer 147 . First metal patterns 186a, 186b, 186c, and 186d, first bonding vias 192, and first bonding metal 194 may be formed in the first inter-wiring insulating layer 190.

A peripheral circuit structure (PERI) may be provided. The peripheral circuit structure (PERI) includes a peripheral circuit board 200, a peripheral circuit element (PT), a wiring structure 260, a second inter-wiring insulating film 240, a second bonding via 292, and a second bonding metal 294. ) may include. A second input/output pad 209 electrically connected to the second insulating film 208 and the wiring structure 260 may be formed on the rear surface of the peripheral circuit board 200.

The peripheral circuit structure (PERI) may be bonded on the front surface of the substrate 300. The first bonding metal 194 and the second bonding metal 294 may be bonded to each other.

Substrate 300 may be removed. Accordingly, the lower portion of the channel structure (CH) may be exposed.

Next, referring to FIG. 4 , a portion of the exposed first channel insulation pattern 132 of the channel structure CH may be removed. As a result, the first channel pattern 130 may be exposed. A top surface of the first channel pattern 130 and a portion of the sidewall of the first channel pattern 130 may be exposed.

A source layer 102 may be formed covering the word line cutting structure (WLC), the channel structure (CH), the anti-arcing contact 120, and the source contact 174. The source layer 102 may contact the first channel pattern 130 of the channel structure (CH). Accordingly, the channel structure (CH) may be electrically connected to the source layer 102. An insulating layer 101 may be formed to cover the cell contact 170 and the input/output contact 176 exposed by the source layer 102. Cell substrates 101 and 102 including an insulating layer 101 and a source layer 102 may be formed. A first insulating film 108 and a first input/output pad 109 may be formed on the cell substrates 101 and 102. The first input/output pad 109 may be electrically connected to the input/output contact 176 through a contact 178.

29 to 31 are other intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 28 will be briefly described or omitted.

Referring to FIG. 29, a peripheral circuit structure (PERI) may be provided. A free cell substrate 100p and a free mold structure (pMS) may be formed on the peripheral circuit structure (PERI). The free cell substrate 100p may include an insulating layer 101, a semiconductor layer 103, a source sacrificial layer 111, and a support layer 104. The source sacrificial layer 111 and the support layer 104 may be formed on the semiconductor layer 103. The source sacrificial layer 111 may include a material having an etch selectivity with respect to the mold insulating layer 110 . The support layer 104 may include a material having an etch selectivity with respect to the source sacrificial layer 111 . For example, the source sacrificial layer 111 may include a silicon nitride film, and the support layer 104 may include polysilicon.

A pre-mold structure (pMS) may be formed on the free cell substrate 100p. A first interlayer insulating film 141 may be formed covering the free cell substrate 100p and the free mold structure (pMS).

Referring to FIGS. 29 and 30 , a channel structure (CH) penetrating the pre-mold structure (pMS) may be formed on the cell array area (CA). An anti-arcing contact 120 that penetrates the pre-mold structure (pMS) may be formed on the cell array area (CA). The first insulating pattern 112 may be formed on the sidewall of the arcing prevention contact 120 . The arcing prevention contact 120 may be connected to the peripheral circuit board 200 through the semiconductor layer 103 and the through via 220. A cell contact 170 penetrating the pre-mold structure (pMS) may be formed on the extended area (EXT). The cell contact 170 may be formed between the mold sacrificial layer 115 and the cell contact 170 rather than the second insulating pattern 114 in the connection region CR. A source contact 174 penetrating the first interlayer insulating film 141 may be formed on the semiconductor layer 103 in the pad area PA. The cell contact 170 or the input/output contact 176 may penetrate the insulating layer 101 and be electrically connected to the wiring structure 260.

A word line cutting hole (WLCH) that penetrates the pre-mold structure (pMS) may be formed on the cell array area (CA). The mold sacrificial layer 115 exposed by the word line cutting structure (WLC) can be selectively removed, and gate electrodes (GSL, WL1 to WLn, ECL) replace the area from which the mold sacrificial layer 115 was removed. This can be formed.

Referring to FIG. 31, an anti-arcing sacrificial layer 150, a string selection line (SSL), first to fifth interlayer insulating layers 141 to 145, a string isolation structure (SLC), and a string selection channel structure (SCH) are formed. It can be. The arcing prevention contact 120 may be electrically connected to the string select line (SSL) through the arcing prevention sacrificial film 150. The string selection line (SSL) may be connected to the peripheral circuit board 200 through the anti-arc sacrificial layer 150, the anti-arc contact 120, the semiconductor layer 103, and the through via 220.

The arcing prevention contact 120 can prevent arcing by grounding the string select line (SSL) during the manufacturing process of the semiconductor memory device. For example, when forming a through hole for forming a string separation structure (SLC) and/or through holes for forming a string selection channel structure (SCH) (e.g., the second hole (H2) in FIG. 23 and the second hole (H2) in FIG. 24 An arcing phenomenon may occur when forming the second expansion hole (EH2). At this time, the charge accumulated in the string selection line (SSL) may be discharged to the peripheral circuit board 200 through the anti-arcing sacrificial layer 150 and the anti-arc contact 120. That is, the anti-arc sacrificial layer 150 and the anti-arc contact 120 may provide a path for the charges to be discharged to the peripheral circuit board 200. Accordingly, the electrical characteristics and reliability of the semiconductor memory device can be improved.

Referring to FIG. 11 , studs 180c, 180d, and 180e may be formed in the second to fifth interlayer insulating films 142 to 145. The sixth and seventh interlayer insulating films 146 and 147 may be formed sequentially on the fifth interlayer insulating film 145 . Studs 182a, 182b, 182c, and 182d may be formed in the sixth interlayer insulating film 146. Studs 184a, 184b, 184c, and 184d may be formed in the seventh interlayer insulating film 147. A first interconnection insulating layer 190 may be formed on the seventh interconnection insulating layer 147 . First metal patterns 186a, 186b, 186c, and 186d may be formed in the first inter-wiring insulating film 190.

Figure 32 is an example block diagram for explaining an electronic system according to some embodiments. Figure 33 is an example perspective view for explaining an electronic system according to some embodiments. FIG. 34 is a schematic cross-sectional view taken along line II-II in FIG. 33.

Referring to FIG. 32 , the electronic system 1000 according to some embodiments may include a non-volatile memory device 1100 and a controller 1200 electrically connected to the non-volatile memory device 1100. The electronic system 1000 may be a storage device including one or a plurality of non-volatile memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or a plurality of non-volatile memory devices 1100. there is.

The non-volatile memory device 1100 may be, for example, a NAND flash memory device, for example, the non-volatile memory device described above using FIGS. 1 to 16 . The non-volatile memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

The first structure 1100F includes a decoder circuit 1110 (e.g., row decoder 33 in FIG. 1), a page buffer 1120 (e.g., page buffer 35 in FIG. 1), and a logic circuit 1130 (e.g., FIG. 1). It may be a peripheral circuit structure including control logic 37).

The second structure 1100S may include a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR) described above with reference to FIG. 2 . The cell strings (CSTR) may be connected to the decoder circuit 1110 through a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Additionally, cell strings (CSTR) may be connected to the page buffer 1120 through bit lines (BL).

In some embodiments, the common source line (CSL) and cell string (CSTR) are connected to the decoder circuit 1110 through first connection wires 1115 extending from the first structure 1100F to the second structure 1100S. Can be electrically connected.

In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

The non-volatile memory device 1100 may communicate with the controller 1200 through an input/output pad 1101 that is electrically connected to the logic circuit 1130 (e.g., control logic 37 in FIG. 1). The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of non-volatile memory devices 1100, and in this case, the controller 1200 may control the plurality of non-volatile memory devices 1100.

The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the non-volatile memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that handles communication with the non-volatile memory device 1100. Through the NAND interface 1221, control commands for controlling the non-volatile memory device 1100, data to be written to the memory cell transistors (MCT) of the non-volatile memory device 1100, and non-volatile memory device 1100. Data to be read from the memory cell transistors (MCT), etc. may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 may control the non-volatile memory device 1100 in response to the control command.

32 to 34, an electronic system according to some embodiments includes a main board 2001, a main controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004. may include. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through wiring patterns 2005 formed on the main substrate 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may include interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). You can communicate with an external host according to any one of the following. In some embodiments, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

The main controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b that are spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, and adhesive layers disposed on the lower surfaces of each of the semiconductor chips 2200. (2300), a connection structure 2400 that electrically connects the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. ) may include.

The package substrate 2100 may be a printed circuit board including top pads 2130 of the package. Each semiconductor chip 2200 may include an input/output pad 2210. The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 32.

In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2210 and the top pads 2130 of the package. Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire, and the package upper pads 2130 of the package substrate 2100 may be electrically connected to each other. ) can be electrically connected to. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 use a through electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400. ) may be electrically connected to each other by a connection structure including.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer board different from the main board 2001, and the main controller 2002 and the semiconductor chips are connected by wiring formed on the interposer board. Chips 2200 may be connected to each other.

In some embodiments, package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, and disposed on or exposed through the lower surface of the package substrate body 2120. may include lower pads 2125 and internal wires 2135 that electrically connect the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 may be electrically connected to the connection structures 2400. The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 as shown in FIG. 33 through conductive connectors 2800.

Referring to FIGS. 33 and 34 , in an electronic system according to some embodiments, each of the semiconductor chips 2200 may include the non-volatile memory device described above using FIGS. 1 to 16 . For example, each of the semiconductor chips 2200 may include a peripheral circuit structure (PERI) and a memory cell structure (CELL). Exemplarily, the peripheral circuit structure PERI may include the peripheral circuit board 200 described above using FIGS. 1 to 16 . In addition, by way of example, the memory cell structure (CELL) includes the cell substrate, mold structure (MS), channel structure (CH), string selection channel structure (SCH), and anti-arcing contact ( 120), a first insulating pattern 112, an anti-arcing insulating pattern 155, a string separation structure (SLC), and a cell contact 170.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

101: insulating layer 102: source layer
103: source layer 104: support layer
105: Metal silicide layer 106: Source pattern
108, 208: first and second insulating films 109, 209: first and second input/output pads
110: mold insulating film 112, 114: first and second insulating patterns
120: anti-arcing contact 130, 160: first and second channel patterns
132, 162: first and second channel insulation patterns
134, 164: first and second filling patterns 136: channel pad
141-147: 1st to 7th interlayer insulating films
150: Anti-arc sacrificial film 155: Anti-arc insulating pattern
170: Cell contact 174: Source contact
176: Input/output contact 190, 240: Insulating film between first and second wiring
192, 292: first and second bonding vias 194, 294: first and second bonding metals
200: peripheral circuit board 260: wiring structure
CELL: Memory cell structure PERI: Peripheral circuit structure
CH: Channel structure SCH: String selection channel structure

Claims (20)

cell substrate;
a mold structure including a plurality of gate electrodes alternately stacked on the cell substrate;
a channel structure penetrating the mold structure;
a string selection line on the mold structure;
a string selection channel structure penetrating the string selection line and contacting the channel structure;
An anti-arcing contact penetrating the mold structure;
an insulating pattern between the arcing prevention contact and the plurality of gate electrodes; and
A semiconductor memory device comprising an anti-arcing insulating pattern that passes through the string selection line and contacts the anti-arcing contact. According to clause 1,
The semiconductor memory device wherein the arcing prevention contact is disposed at an end of the string selection line. According to clause 2,
studs, and
Further comprising a bit line on the stud,
The stud is disposed on the string selection channel structure, but is not disposed on the anti-arcing insulating pattern. According to clause 1,
The semiconductor memory device wherein the insulating pattern extends along a sidewall of the arcing prevention contact. According to clause 1,
The cell substrate includes a plate layer,
A semiconductor memory device wherein a sidewall of the channel film of the channel structure is in contact with the plate layer. According to clause 1,
The cell substrate includes a plate layer,
A semiconductor memory device wherein the lower surface of the channel film of the channel structure is in contact with the plate layer. According to clause 1,
peripheral circuit board,
Peripheral circuit elements on the peripheral circuit board, and
On the peripheral circuit board, further comprising a peripheral circuit structure including a wiring structure electrically connected to the peripheral circuit element,
A semiconductor memory device wherein the cell substrate is disposed between the mold structure and the peripheral circuit structure. According to clause 1,
peripheral circuit board,
Peripheral circuit elements on the peripheral circuit board, and
On the peripheral circuit board, further comprising a peripheral circuit structure including a wiring structure electrically connected to the peripheral circuit element,
The mold structure is disposed between the cell substrate and the peripheral circuit structure. According to clause 1,
The anti-arcing contact includes a first portion and a second portion on the first portion,
A semiconductor memory device wherein the width of the top surface of the first portion is greater than the width of the top surface of the second portion. According to clause 1,
A semiconductor memory device wherein the string selection channel structure overlaps a portion of the channel structure. According to clause 1,
The string selection channel structure is:
filling pattern,
a channel pattern surrounding the filling pattern and contacting the channel structure, and
A semiconductor memory device including a channel insulation pattern between the channel pattern and the string selection line. A cell substrate including a cell array region and an expansion region;
a mold structure including a plurality of gate electrodes that are sequentially stacked on the cell array area and are stacked in a step shape on the expansion area, each including a connection area exposing a top surface;
a channel structure penetrating the mold structure on the cell array area;
a string selection line on the mold structure;
a string selection channel structure electrically connected to the channel structure through the string selection line;
An anti-arcing contact on the cell array area, penetrating the mold structure, and having a structure different from that of the channel structure; and
A semiconductor memory device comprising an insulating pattern between the arcing prevention contact and the plurality of gate electrodes. According to clause 12,
The semiconductor memory device wherein the arcing prevention contact overlaps the string selection line in a direction from the cell substrate toward the mold structure. According to clause 12,
A semiconductor memory device further comprising an anti-arc insulating pattern on the cell array area, penetrating the string selection line and contacting the anti-arc contact. According to clause 12,
On the expansion area, further comprising a cell contact electrically connected to the connection area,
A semiconductor memory device wherein the cell contact penetrates the mold structure. According to clause 12,
Further comprising a cell contact on the expansion area electrically connected to the connection area,
A semiconductor memory device wherein a lower surface of the cell contact is disposed in the connection area. According to clause 12,
Further comprising a plurality of string separation structures separating the string selection lines,
The semiconductor memory device wherein the arcing prevention contact is disposed between the string separation structures that are adjacent to each other. main board;
a semiconductor memory device on the main substrate; and
On the main board, it includes a controller electrically connected to the semiconductor memory device,
The semiconductor memory device,
a cell substrate comprising a cell array region and an expansion region;
A mold structure including a plurality of gate electrodes, each of which is sequentially stacked on the cell array area and is stacked in a step shape on the expansion area, each including a connection area exposing a top surface;
A channel structure passing through the mold structure on the cell array area,
A string selection line on the mold structure,
A string selection channel structure passing through the string selection line and contacting the channel structure,
On the cell array area, an anti-arcing contact penetrating the mold structure,
an insulating pattern between the arcing prevention contact and the plurality of gate electrodes,
an anti-arcing insulating pattern penetrating the string selection line and contacting the anti-arcing contact, and
An electronic system comprising a plurality of cell contacts on the expansion area and electrically connected to the connection area. According to clause 18,
An electronic system wherein the anti-arcing insulating pattern has a single-layer structure. According to clause 18,
An electronic system wherein the anti-arcing contact has a single-layer structure.

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