KR20220098088A - Semiconductor memory device and method for fabricating the same - Google Patents

Abstract

A semiconductor memory device and a manufacturing method thereof are provided. The semiconductor memory device comprises: a substrate including a cell region and an extension region adjacent to each other in a first direction; a mold structure including a plurality of insulating layers and a plurality of gate electrode layers alternately stacked on a substrate; a channel structure extending in a direction perpendicular to the substrate in the cell region and penetrating the mold structure; and a cell contact extending in a direction perpendicular to the substrate in the extension region and connected to the plurality of gate electrode layers. The cell contact includes a first contact and a second contact spaced apart in a second direction crossing the first direction. The mold structure includes a dummy mold structure protruding in a direction perpendicular to the substrate between the first contact and the second contact.

Description

BACKGROUND ART Semiconductor memory device and method for fabricating the same

The present invention relates to a semiconductor memory device and a method for manufacturing the same.

In order to meet the high performance and low price demanded by consumers, it is required to increase the density of semiconductor memory devices. In the case of a semiconductor memory device, since the degree of integration is an important factor determining the price of a product, an increased degree of integration is particularly required.

In the case of a two-dimensional or planar semiconductor memory device, the degree of integration is mainly determined by an area occupied by a unit memory cell, and thus is greatly affected by the level of fine pattern forming technology. However, since ultra-expensive equipment is required for pattern miniaturization, the degree of integration of the 2D semiconductor device is increasing, but is still limited. Accordingly, three-dimensional semiconductor devices including memory cells arranged three-dimensionally have been proposed.

SUMMARY The technical problem to be solved by the present invention is to provide a semiconductor memory device having improved process difficulty.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor memory device with improved process difficulty.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical object includes a substrate including a cell region and an extension region adjacent to each other in a first direction, a plurality of insulating layers alternately stacked on the substrate, and a plurality of A mold structure including a gate electrode layer, extending in a direction perpendicular to the substrate in a cell region, a channel structure penetrating through the mold structure, and a cell contact connected to the plurality of gate electrode layers extending in a direction perpendicular to the substrate in the extension region The cell contact includes a first contact and a second contact spaced apart in a second direction intersecting the first direction, and the mold structure protrudes between the first contact and the second contact in a direction perpendicular to the substrate. and a dummy mold structure that is

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical object includes a substrate including a cell region and an extension region adjacent to each other in a first direction, a plurality of insulating layers alternately stacked on the substrate, and a plurality of A mold structure including a gate electrode layer, extending in a first direction, a word line cutting line for cutting the mold structure, and a cell contact extending in a direction perpendicular to the substrate in the extension region, and connected to the plurality of gate electrode layers; The cell contact includes first and second contacts spaced apart from each other in a second direction intersecting the first direction, and the mold structure disposed under the first contact and the second contact has a first height from the upper surface of the substrate. And, between the first contact and the second contact, the mold structure has a second height higher than the first height from the upper surface of the substrate.

In a method for manufacturing a semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem, there is provided a substrate including a cell region and an extension region adjacent to each other in a first direction, and a mold insulating layer and a sacrificial layer on the substrate A plurality of trenches forming a pre-mold structure in which insulating layers are alternately stacked, spaced apart from the pre-mold structure on the extension region in a second direction intersecting the first direction, and recessed toward the substrate from the upper surface of the pre-mold structure forming a plurality of trenches and an interlayer insulating film on the pre-mold structure, forming a channel structure penetrating the pre-mold structure on the cell region, removing the sacrificial insulating layer, and forming a gate electrode layer between the mold insulating layers and forming cell contacts connected to the gate electrode layer in the plurality of trenches.

The details of other embodiments are included in the detailed description and drawings.

1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.
2 is an exemplary circuit diagram illustrating a semiconductor memory device according to some embodiments.
3 is an exemplary layout diagram illustrating a semiconductor memory device according to some embodiments.
4 is a cross-sectional view taken along line AA of FIG. 3 .
FIG. 5 is an enlarged view for explaining a region R1 of FIG. 4 .
6 is a cross-sectional view taken along line BB of FIG. 3 .
7 is a cross-sectional view taken along CC of FIG. 3 .
FIG. 8 is a cross-sectional view taken along DD and EE of FIG. 3 .
9 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 10 is an enlarged view for explaining a region R1 of FIG. 9 .
11 is a cross-sectional view illustrating a semiconductor memory device according to another exemplary embodiment.
12 to 34 are diagrams of intermediate steps for describing a method of manufacturing a semiconductor memory device according to some embodiments.
35 is an exemplary block diagram for describing an electronic system according to some embodiments.
36 is an exemplary perspective view for explaining an electronic system according to some embodiments.
37 is a schematic cross-sectional view taken along II of FIG. 36 .

Hereinafter, embodiments according to the technical spirit of the present invention will be described with reference to the accompanying drawings.

1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 1 , a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30 .

The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through a bit line BL, a word line WL, at least one string select line SSL, and at least one ground select line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word line WL, the string select line SSL, and the ground select line GSL. Also, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit line BL.

The peripheral circuit 30 may receive the address ADDR, the command CMD, and the control signal CTRL from the outside of the semiconductor memory device 10 , and the external device and the data DATA of the semiconductor memory device 10 . ) can be sent and received. The peripheral circuit 30 may include a row decoder 33 , a page buffer 35 , and a control logic 37 . Although not shown, the peripheral circuit 30 is an input/output circuit, a voltage generator circuit for generating various voltages required for operation of the semiconductor memory device 10 , and a method for correcting errors in data DATA read from the memory cell array 20 . It may further include various sub-circuits, such as an error correction circuit for

The control logic 37 may be connected to the row decoder 33 , the page buffer 35 , the input/output circuit, the voltage generation circuit, and the like. The control logic 37 may control the overall operation of the semiconductor memory device 10 . The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage level provided to the word line WL and the bit line BL when a memory operation such as a program operation or an erase operation is performed.

The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and at least one word line WL of the selected memory cell blocks BLK1 to BLKn. ), at least one string selection line SSL, and at least one ground selection line GSL may be selected. Also, the row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, when performing a program operation, the page buffer 35 operates as a write driver to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL. Meanwhile, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to sense data DATA stored in the memory cell array 20 .

2 is an exemplary circuit diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 2 , a memory cell array (eg, 20 of FIG. 1 ) of a semiconductor memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL0 , BL1 , and BL2 , and a plurality of cells. strings (CSTRs).

The common source line CSL may extend in the first direction X. In some embodiments, the plurality of common source lines CSL may be two-dimensionally arranged. For example, the plurality of common source lines CSL may be spaced apart from each other and extend in the first direction X, respectively. The same voltage may be electrically applied to the common source lines CSL, or different voltages may be applied to be separately controlled.

The plurality of bit lines BL may be two-dimensionally arranged. For example, the bit lines BL may be spaced apart from each other to extend in the second direction Y crossing the first direction X, respectively. A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, a ground select transistor GST, and a string select transistor GST connected to the bit line BL. SST) may include a plurality of memory cell transistors MCT. Each of the memory cell transistors MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. Also, a ground select line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2n, and a string select line SSL may be disposed between the common source line CSL and the bit line BL. The ground select line GSL may be used as a gate electrode of the ground select transistor GST, and the word lines WL11 to WL1n and WL21 to WL2n may be used as gate electrodes of the memory cell transistors MCT, and a string The selection line SSL may be used as a gate electrode of the string selection transistor SST.

In some embodiments, an erase control transistor ECT may be disposed between the common source line CSL and the ground select transistor GST. The common source line CSL may be commonly connected to sources of the erase control transistors ECT. Also, an erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistors ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

3 is an exemplary layout diagram illustrating a semiconductor memory device according to some embodiments. 4 is a cross-sectional view taken along line A-A of FIG. 3 . FIG. 5 is an enlarged view for explaining a region R1 of FIG. 4 . 6 is a cross-sectional view taken along line B-B of FIG. 3 . 7 is a cross-sectional view taken along line C-C of FIG. 3 . 8 is a cross-sectional view taken along lines D-D and E-E of FIG. 3 .

3 to 8 , a semiconductor memory device according to some embodiments includes a memory cell region CELL and a peripheral circuit region PERI.

The memory cell region CELL includes the cell substrate 100 , the insulating substrate 101 , the mold structures MS1 and MS2 , the interlayer insulating layers 140a and 140b , the channel structure CH, the word line cutting line WLC, and the string. It may include an isolation structure SC, a bit line BL, a cell contact 162 , a through via 166 , a dummy channel structure DCH, and a source contact 164 .

The cell substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the cell substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the cell substrate 100 may include impurities. For example, the cell substrate 100 may include n-type impurities (eg, phosphorus (P), arsenic (As), etc.).

The cell substrate 100 may include a cell region CAR and an extension region EXT.

A memory cell array (eg, 20 of FIG. 1 ) including a plurality of memory cells may be formed in the cell region CAR. For example, in the cell region CAR, a channel structure CH, a bit line BL, and gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, SSL2, which will be described later, are disposed in the cell region CAR. can In the following description, the surface of the cell substrate 100 on which the memory cell array is disposed may be referred to as a top surface of the cell substrate 100 . Conversely, a surface of the cell substrate 100 opposite to the top surface of the cell substrate 100 may be referred to as a lower surface of the cell substrate 100 .

The extension area EXT may be disposed around the cell area CAR. Gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, which will be described later, may be stacked in the extension area EXT in a stepwise manner.

In some embodiments, the cell substrate 100 may further include a through region THR. The through area THR may be disposed inside the cell array area CAR and the extension area EXT or may be disposed outside the cell array area CAR and the extension area EXT. A through via 166 to be described later may be disposed in the through region THR.

The insulating substrate 101 may be formed in the cell substrate 100 of the extension region EXT. The insulating substrate 101 may form an insulating region in the cell substrate 100 of the extended region EXT. The insulating substrate 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but is not limited thereto. In some embodiments, the insulating substrate 101 may be formed in the cell substrate 100 of the through region THR.

It is illustrated that the lower surface of the insulating substrate 101 is disposed on the same plane as the lower surface of the cell substrate 100 , but this is only exemplary. As another example, the lower surface of the insulating substrate 101 may be lower than the lower surface of the cell substrate 100 .

The mold structures MS1 and MS2 may be formed on the entire surface of the cell substrate 100 . The mold structures MS1 and MS2 include a plurality of gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 and a plurality of mold insulating layers 110 stacked on the cell substrate 100 , 115) may be included. Each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 and each of the mold insulating layers 110 and 115 have a layered structure extending parallel to the front surface of the cell substrate 100 . can be The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 may be sequentially stacked on the cell substrate 100 while being spaced apart from each other by the mold insulating layers 110 and 115 .

In some embodiments, the mold structures MS1 and MS2 may include a first mold structure MS1 and a second mold structure MS2 that are sequentially stacked on the cell substrate 100 .

The first mold structure MS1 may include first gate electrodes ECL, GSL1, GSL2, WL11 to WL1n and first mold insulating layers 110 alternately stacked on the cell substrate 100 . In some embodiments, the first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n include an erase control line ECL, a ground selection line GSL1 and GSL2, and a plurality of sequentially stacked on the cell substrate 100 . It may include first word lines WL11 to WL1n. The ground selection lines GSL1 and GSL2 may include a first ground selection line GSL1 and a second ground selection line GSL2 that are sequentially stacked. The first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n include only the two ground selection lines GSL1 and GSL2, but this is only an example, and the first gate electrodes ECL, GSL1, Of course, GSL2, WL11 to WL1n) may include three or more ground selection lines. In some other embodiments, the erase control line ECL may be omitted.

The second mold structure MS2 may include second gate electrodes WL21 to WL2n, SSL1 and SSL2 and second mold insulating layers 115 that are alternately stacked on the first mold structure MS1 . In some embodiments, the second gate electrodes WL21 to WL2n, SSL1 and SSL2 are a plurality of second word lines WL21 to WL2n and a string selection line SSL1 sequentially stacked on the first mold structure MS1 . , SSL2). The string selection lines SSL1 and SSL2 may include a first string selection line SSL1 and a second string selection line SSL2 that are sequentially stacked. The second gate electrodes WL21 to WL2n, SSL1, and SSL2 include only the two string selection lines SSL1 and SSL2, but this is only an example, and the second gate electrodes WL21 to WL2n, SSL1, Of course, SSL2) may include three or more string selection lines.

The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 are each formed of a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni) or silicon or silicon. It may include a semiconductor material such as, but is not limited thereto.

Each of the mold insulating layers 110 and 115 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The mold structures MS1 and MS2 may include a plurality of dummy mold structures and a plurality of trenches T.

For example, referring to FIGS. 3 and 8 , the mold structures MS1 and MS2 may include a first dummy mold structure DM1 and a second dummy mold structure DM2 . The mold structures MS1 and MS2 may include a plurality of first trenches T1 and a plurality of second trenches T2 . The mold structures MS1 and MS2 may include a plurality of dummy mold structures including a first dummy mold structure DM1 and a second dummy mold structure DM2 . The mold structures MS1 and MS2 may include a plurality of trenches T including a plurality of first trenches T1 and a plurality of second trenches T2 . Hereinafter, the first dummy mold structure DM1 and the second dummy mold structure DM2 , and the plurality of first trenches T1 and the plurality of second trenches T2 will be described as examples.

The plurality of first trenches T1 and the plurality of second trenches T2 may be recessed from the top surfaces of the mold structures MS1 and MS2 toward the top surface of the cell substrate 100 .

A first pad area PAD1 may be disposed in the plurality of first trenches T1 . A first pad area PAD1 may be disposed on the bottom surface of the plurality of first trenches T1 . Specifically, the first pad area PAD1 is a portion of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 exposed by the bottom surfaces of the plurality of first trenches T1 . area can be referred to.

First cell contacts 162a and 162b may be disposed in the first trench T1 . First cell contacts 162a and 162b may be disposed on the bottom surface of the first trench T1 . The first cell contacts 162a and 162b may be disposed on the first pad area PAD1 in the first trench T1 . The first cell contacts 162a and 162b may be surrounded by the interlayer insulating layers 140a and 140b in the first trench T1 .

The first cell contacts 162a and 162b may overlap the first dummy mold structure DM1 in the second direction (Y). The first cell contacts 162a and 162b may be disposed between sidewalls of the first dummy mold structure DM1 exposed by the first trench T1 .

A second pad area PAD2 may be disposed in the plurality of second trenches T2 . A second pad area PAD2 may be disposed on the bottom surface of the plurality of second trenches T2 . Specifically, the second pad area PAD2 is a portion of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 exposed by the bottom surfaces of the plurality of second trenches T2 . area can be referred to.

Second cell contacts 162c and 162d may be disposed in the second trench T2 . Second cell contacts 162c and 162d may be disposed on the bottom surface of the second trench T2 . The second cell contacts 162c and 162d may be disposed on the second pad area PAD2 in the second trench T2 . The second cell contacts 162c and 162d may be surrounded by the interlayer insulating layers 140a and 140b in the second trench T2 .

The second cell contacts 162c and 162d may overlap the second dummy mold structure DM2 in the second direction (Y). The second cell contacts 162c and 162d may be disposed between sidewalls of the second dummy mold structure DM2 exposed by the second trench T2 .

The first dummy mold structure DM1 may be disposed between the plurality of first trenches T1 . The first dummy mold structure DM1 may be disposed between the first cell contacts 162a and 162b disposed in the plurality of first trenches T1 . The first dummy mold structure DM1 may protrude between the first cell contacts 162a and 162b.

The height H_DM1 of the first dummy mold structure DM1 may be higher than the height of the mold structures MS1 and MS2 disposed under the first cell contacts 162a and 162b. Specifically, the mold structures MS1 and MS2 disposed under the first cell contacts 162a and 162b may be the same as the height H_PAD1 of the first pad area PAD1. In this case, the height H_DM1 of the first dummy mold structure DM1 may be greater than the height H_PAD1 of the first pad area PAD1 . This may result from the first dummy mold structure DM1 protruding between the first cell contacts 162a and 162b.

The second dummy mold structure DM2 may be disposed between the plurality of second trenches T2 . The second dummy mold structure DM2 may be disposed between the second cell contacts 162c and 162d disposed in the plurality of second trenches T2 . The second dummy mold structure DM2 may protrude between the second cell contacts 162c and 162d.

The height H_DM2 of the second dummy mold structure DM2 may be higher than the height of the mold structures MS1 and MS2 disposed under the second cell contacts 162c and 162d. Specifically, the mold structures MS1 and MS2 disposed under the second cell contacts 162c and 162d may be equal to the height H_PAD2 of the second pad area PAD2. In this case, the height H_DM2 of the second dummy mold structure DM2 may be greater than the height H_PAD2 of the second pad area PAD2 . This may result from the second dummy mold structure DM2 protruding between the second cell contacts 162c and 162d.

3 and 8 , in a cross-sectional view taken along the second direction Y, the heights of the mold structures MS1 and MS2 may not be uniform. The heights of the mold structures MS1 and MS2 disposed under the cell contact 162 may be different from the heights of the mold structures MS1 and MS2 disposed between the cell contacts 162 . Specifically, the heights of the mold structures MS1 and MS2 disposed between the cell contacts 162 may be greater than the heights of the mold structures MS1 and MS2 disposed under the cell contacts 162 .

3 and 7 , in a cross-sectional view taken along the first direction X between the cell contacts 162 , the heights of the mold structures MS1 and MS2 are in the cell region CAR and the extension region EXT. can be constant across.

The depth of the plurality of trenches T may increase as the distance from the cell area CAR increases. For example, referring to FIGS. 3 and 8 , the depth of the second trench T2 disposed farther from the cell area CAR is greater than the depth of the first trench T1 .

As the distance from the cell area CAR increases, the heights of the mold structures MS1 and MS2 disposed under the cell contact 162 may decrease. That is, as the distance from the cell area CAR increases, the height of the pad area PAD disposed under the cell contact 162 may decrease. For example, referring to FIGS. 3 and 8 , the height of the second cell contacts 162c and 162d is higher than the height H_PAD1 of the first pad area PAD1 disposed under the first cell contacts 162a and 162b. The height H_PAD2 of the lower second pad area PAD2 is smaller.

As the distance from the cell area CAR increases, the height of the cell contact 162 may increase. For example, referring to FIGS. 3 and 8 , the second cell contacts 162c and 162d in the second trench T2 have a higher height than the first cell contacts 162a and 162b in the first trench T1 . Big.

Regardless of the distance from the cell area CAR, the height of the dummy mold structure DM may be the same. For example, referring to FIGS. 3 and 8 , the height H_DM1 of the first dummy structure DM1 protruding between the first cell contacts 162a and 162b moves between the second cell contacts 162c and 162d. It is equal to the height H_DM2 of the protruding second dummy mold structure DM2 .

The mold structures MS1 and MS2 disposed under the cell contact 162 in the extension area EXT may be partially removed to expose the pad area PAD connected to the cell contact 162 . In the extension area EXT, the mold structures MS1 and MS2 that are not disposed under the cell contact 162 and, for example, are disposed between the cell contacts 162 are not removed, but are formed between the cell area CAR and the cell area CAR. They can be stacked at the same height.

The interlayer insulating layers 140a and 140b may be formed on the cell substrate 100 to cover the mold structures MS1 and MS2 . In some embodiments, the interlayer insulating layers 140a and 140b may include a first interlayer insulating layer 140a and a second interlayer insulating layer 140b sequentially stacked on the cell substrate 100 . The first interlayer insulating layer 140a may cover the first mold structure MS1 , and the second interlayer insulating layer 140b may cover the second mold structure MS2 . The interlayer insulating layers 140a and 140b may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto. For example, the interlayer insulating layers 140a and 140b may include TetraEthylOrthoSilicate (TEOS).

The channel structure CH may be formed in the mold structures MS1 and MS2 of the cell region CAR. The channel structure CH may extend in a vertical direction (hereinafter, referred to as a third direction Z) intersecting the upper surface of the cell substrate 100 to pass through the mold structures MS1 and MS2 . For example, the channel structure CH may have a pillar shape (eg, a cylindrical shape) extending in the third direction Z. Accordingly, the channel structure CH may cross each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. In some embodiments, the channel structure CH may have a bent portion between the first mold structure MS1 and the second mold structure MS2 .

4 and 5 , the channel structure CH may include a semiconductor pattern 130 and an information storage layer 132 .

The semiconductor pattern 130 may extend in the third direction Z and penetrate the mold structures MS1 and MS2 . The semiconductor pattern 130 is illustrated only in the shape of a cup, but this is only an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular cylindrical shape, and a hollow filler shape. The semiconductor pattern 130 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nanostructure, but is not limited thereto.

The information storage layer 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2. For example, the information storage layer 132 may extend along the outer surface of the semiconductor pattern 130 . The information storage layer 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material is, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

In some embodiments, the information storage layer 132 may be formed of a multilayer. For example, as shown in FIG. 5 , the information storage layer 132 includes a tunnel insulating layer 132a , a charge storage layer 132b , and a blocking insulating layer 132c sequentially stacked on the outer surface of the semiconductor pattern 130 . may include

The tunnel insulating layer 132a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating layer 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

In some embodiments, the channel structure CH may further include a filling pattern 134 . The filling pattern 134 may be formed to fill the inside of the cup-shaped semiconductor pattern 130 . The filling pattern 134 may include an insulating material, for example, silicon oxide, but is not limited thereto.

In some embodiments, the channel structure CH may further include a channel pad 136 . The channel pad 136 may be formed to be connected to an upper portion of the semiconductor pattern 130 . The channel pad 136 may include, for example, polysilicon doped with impurities, but is not limited thereto.

In some embodiments, the plurality of channel structures CH may be arranged in a zigzag shape. For example, as shown in FIG. 3 , the plurality of channel structures CH may be alternately arranged in a first direction X and a second direction Y parallel to the top surface of the cell substrate 100 . The plurality of channel structures CH arranged in a zigzag shape may further improve the degree of integration of the semiconductor memory device. In some embodiments, the plurality of channel structures CH may be arranged in a honeycomb shape.

In some embodiments, a dummy channel structure DCH may be formed in the mold structures MS1 and MS2 of the extension area EXT. The dummy channel structure DCH may be formed in a shape similar to that of the channel structure CH to reduce stress applied to the mold structures MS1 and MS2 in the extension area EXT. The dummy channel structure DCH is not connected to the bit line BL.

In some embodiments, the first source structures 102 and 104 may be formed on the cell substrate 100 . The first source structures 102 and 104 may be interposed between the cell substrate 100 and the mold structures MS1 and MS2. For example, the first source structures 102 and 104 may extend along the top surface of the cell substrate 100 .

In some embodiments, the channel structure CH may pass through the first source structures 102 and 104 . For example, a lower portion of the channel structure CH may be disposed in the cell substrate 100 through the first source structures 102 and 104 .

The source layer 102 may be formed on the cell substrate 100 . The source layer 102 may be interposed between the cell substrate 100 and the mold structures MS1 and MS2 . For example, the source layer 102 may conformally extend along the top surface of the cell substrate 100 . In some embodiments, the source layer 102 may be formed on the cell region CAR. The source layer 102 may not be formed on the extension area EXT.

The source layer 102 may be connected to the semiconductor pattern 130 of each of the channel structures CH. For example, as shown in FIG. 5 , the source layer 102 may penetrate the information storage layer 132 and contact the side surface of the semiconductor pattern 130 . The source layer 102 may be provided as a common source line (eg, CSL of FIG. 2 ) of the semiconductor memory device. The source layer 102 may include a conductive material, for example, polysilicon or metal doped with impurities, but is not limited thereto.

In some embodiments, a portion of the source layer 102 adjacent to the semiconductor pattern 130 may protrude toward the information storage layer 132 . For example, in the region adjacent to the semiconductor pattern 130 , the length of the source layer 102 extending in the third direction Z may be increased. Through this, the source layer 102 may contact the semiconductor pattern 130 with a larger area.

In some embodiments, the channel structure CH may penetrate the source layer 102 . For example, a lower portion of the channel structure CH may be disposed in the cell substrate 100 under the source layer 102 .

Although not shown, a base insulating layer may be interposed between the cell substrate 100 and the source layer 102 . The base insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

In some embodiments, the cell substrate 100 may include a conductive layer (not shown). The conductive layer may include, for example, polysilicon doped with impurities, metal, or metal silicide. The conductive layer may be formed in multiple layers. For example, the cell substrate 100 may include a first conductive layer including a metal silicide such as tungsten silicide (WSi), and a second conductive layer stacked on the first conductive layer and including doped polysilicon. . The source layer 102 and the conductive layer may be provided as a common source line (eg, CSL of FIG. 2 ) of the semiconductor memory device.

The support layer 104 may be formed on the cell substrate 100 , the source layer 102 , and the source sacrificial layer 103 . The support layer 104 may be interposed between the source layer 102 and the mold structures MS1 and MS2 and between the source sacrificial layer 103 and the mold structures MS1 and MS2 . For example, the support layer 104 may conformally extend along the top surface of the cell substrate 100 , the top surface of the source layer 102 , and the top surface of the source sacrificial layer 103 .

The support layer 104 may include a material having an etch selectivity with respect to the source sacrificial layer 103 . For example, the source sacrificial layer 103 may include a silicon nitride layer, and the support layer 104 may include a polysilicon layer.

The support layer 104 may be used as a support for preventing the mold stack from collapsing or collapsing in a replacement process for forming the source layer 102 . For example, the source layer 102 and/or the source sacrificial layer 103 may expose a portion of the top surface of the cell substrate 100 , and the support layer 104 may expose a portion of the top surface of the cell substrate 100 . It may extend along and contact the upper surface of the cell substrate 100 .

Although not shown, a base insulating layer may be interposed between the cell substrate 100 and the first source structures 102 and 104 . The base insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The source sacrificial layer 103 may be formed on the extension region EXT of the cell substrate 100 . The source sacrificial layer 103 may be interposed between the cell substrate 100 and the mold structures MS1 and MS2. For example, the source sacrificial layer 103 may conformally extend along the top surface of the cell substrate 100 . In some embodiments, the source sacrificial layer 103 may be formed on the extension region EXT, but not on the cell region CAR.

The source sacrificial layer 103 may be disposed on the same level as the source layer 102 . In the present specification, “arranged at the same level” means to be arranged at the same height with respect to the upper surface of the cell substrate 100 . For example, the lower surface of the source sacrificial layer 103 may be disposed at the same height as the lower surface of the source layer 102 .

The source sacrificial layer 103 may be a layer remaining after a portion thereof is replaced with the source layer 102 . In this case, the thickness of the source layer 102 may be the same as the thickness of the source sacrificial layer 103 . In the present specification, the term "same" means not only exactly the same thing, but also includes a minute difference that may occur due to a margin on a process. For example, the top surface of the source sacrificial layer 103 may be disposed at the same height as the top surface of the source layer 102 .

The source sacrificial layer 103 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. In some embodiments, the source sacrificial layer 103 may include a material having an etch selectivity with respect to the mold insulating layers 110 and 115 . For example, each of the mold insulating layers 110 and 115 may include a silicon oxide layer, and the source sacrificial layer 103 may include a silicon nitride layer.

The word line cutting line WLC may extend in the first direction X to cut the mold structures MS1 and MS2 on the cell area CAR and the extension area EXT. Also, the plurality of word line cutting lines WLC may be spaced apart from each other and extend side by side in the first direction X. The mold structures MS1 and MS2 may be divided by the word line cutting lines WLC to form a plurality of memory cell blocks (eg, BLK1 to BLKn of FIG. 1 ). For example, two adjacent word line disconnection lines WLC may define one memory cell block therebetween. A plurality of channel structures CH may be disposed in each of the memory cell blocks defined by the word line cutting lines WLCs.

In some embodiments, the word line cutting line WLC may extend in the first direction X to cut the source layer 102 and the support layer 104 . It is illustrated that the lower surface of the word line cutting line WLC is disposed on the same plane as the lower surface of the source layer 102 , but this is only exemplary. As another example, the lower surface of the word line cut line WLC may be lower than the upper surface of the cell substrate 100 .

In some embodiments, the word line cut line WLC may include an insulating material. For example, the word line cut line WLC may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

In some embodiments, the string separation structure SC may be formed in the second mold structure MS2 . The string separation structure SC may extend in the first direction X to cut the string selection line SSL. Each of the memory cell blocks defined by the word line cutting lines WLC may be divided by the string separation structure SC to form a plurality of string regions. For example, the string separation structure SC may define two string regions in one memory cell block. The string separation structure SC may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The bit line BL may be formed on the mold structures MS1 and MS2. The plurality of bit lines BL may be spaced apart from each other and extend side by side in the second direction Y. Each of the bit lines BL may be connected to at least a portion of the plurality of channel structures CH. For example, a bit line contact 182 connected to an upper portion of each of the channel structures CH may be formed in the second interlayer insulating layer 140b. The bit line BL may be electrically connected to the channel structures CH arranged in the second direction Y through the bit line contact 182 .

The cell contact 162 may be connected to each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the cell contact 162 extends in the third direction Z in the interlayer insulating layers 140a and 140b to form the respective gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, It can be connected with SSL2).

The cell contact 162 may be connected to the pad area PAD of each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2. The pad area PAD may refer to an end of each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 disposed under the cell contact 162 . That is, the cell contact 162 may extend in the third direction Z on the pad area PAD.

In some embodiments, the cell contact 162 may have a bent portion between the first mold structure MS1 and the second mold structure MS2 . The cell contact 162 may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon, but is not limited thereto.

The source contact 164 may be connected to the first source structures 102 and 104 . For example, the source contact 164 may extend in the third direction Z in the interlayer insulating layers 140a and 140b to be connected to the cell substrate 100 . In some embodiments, the source contact 164 may have a bent portion between the first mold structure MS1 and the second mold structure MS2 .

The through via 166 may be disposed in the through region THR. For example, the through via 166 may extend in the third direction Z in the mold structures MS1 and MS2 of the through region THR. In some embodiments, the through via 166 may have a bent portion between the first mold structure MS1 and the second mold structure MS2 . The through-via 166 is only shown passing through the mold structures MS1 and MS2, but this is only exemplary. As another example, the through via 166 may be disposed outside the mold structures MS1 and MS2 and may not penetrate through the mold structures MS1 and MS2 .

The cell contact 162 , the source contact 164 , and the through via 166 may be connected to the first interconnection structure 180 on the interlayer insulating layers 140a and 140b, respectively. For example, the first interline insulating layer 142 may be formed on the second interlayer insulating layer 140b. The first interconnection structure 180 may be formed in the first inter interconnection insulating layer 142 . The cell contact 162 , the source contact 164 , and the through via 166 may be connected to the first interconnection structure 180 by a contact via 184 , respectively. Although not specifically illustrated, the first interconnection structure 180 may be connected to the bit line BL.

The peripheral circuit region PERI may include the peripheral circuit board 200 , the peripheral circuit element PT, and the second wiring structure 260 .

The peripheral circuit board 200 may be disposed under the cell board 100 . For example, the upper surface of the peripheral circuit board 200 may face the lower surface of the cell substrate 100 . The peripheral circuit board 200 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like.

The peripheral circuit element PT may be formed on the peripheral circuit board 200 . The peripheral circuit element PT may constitute a peripheral circuit (eg, 30 of FIG. 1 ) that controls the operation of the semiconductor memory device. For example, the peripheral circuit element PT may include control logic (eg, 37 of FIG. 1 ), a row decoder (eg, 33 of FIG. 1 ), and a page buffer (eg, 35 of FIG. 1 ). In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit element PT is disposed may be referred to as a top surface of the peripheral circuit board 200 . Conversely, a surface of the peripheral circuit board 200 opposite to the upper surface of the peripheral circuit board 200 may be referred to as a lower surface of the peripheral circuit board 200 .

The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit element PT may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors. may be

In some embodiments, the lower surface of the cell substrate 100 may face the upper surface of the peripheral circuit board 200 . For example, the second inter-wiring insulating layer 240 covering the peripheral circuit element PT may be formed on the upper surface of the peripheral circuit board 200 .

The first interconnection structure 180 may be connected to the peripheral circuit device PT through the through via 166 . For example, the second interconnection structure 260 connected to the peripheral circuit element PT may be formed in the second interline insulating layer 240 . The through via 166 may extend in the third direction Z to connect the first interconnection structure 180 and the second interconnection structure 260 . Through this, the bit line BL, each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, SSL2, and/or the first source structures 102 and 104 are connected to the peripheral circuit element ( PT) and may be electrically connected.

In some embodiments, the through via 166 may pass through the insulating substrate 101 to connect the first wiring structure 180 and the second wiring structure 260 . Through this, the through-via 166 may be electrically separated from the cell substrate 100 .

In FIG. 3 , the trench T formed in the extension area EXT has a rectangular cross-section, but the embodiment is not limited thereto. For example, in a plan view, the trench T may have a circular shape. In this case, the cell contact 162 may be formed on the pad area PAD exposed by the circular trench T.

9 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments. FIG. 10 is an enlarged view for explaining a region R1 of FIG. 9 . For convenience of description, points different from those described with reference to FIGS. 1 to 8 will be mainly described.

9 and 10 , a semiconductor memory device according to some embodiments includes a second source structure 106 .

The second source structure 106 may be formed on the cell substrate 100 . Although it is illustrated that the lower portion of the second source structure 106 is disposed in the cell substrate 100 , this is only exemplary. The second source structure 106 may be connected to the semiconductor pattern 130 of the channel structure CH. For example, the semiconductor pattern 130 may penetrate the information storage layer 132 and contact the top surface of the second source structure 106 . The second source structure 106 may be formed by, for example, a selective epitaxial growth process from the cell substrate 100 , but is not limited thereto.

In some embodiments, a top surface of the second source structure 106 may cross some of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2. For example, a top surface of the second source structure 106 may be formed to be higher than a top surface of the erase control line ECL. In this case, a gate insulating layer 110S may be interposed between a gate electrode (eg, an erase control line ECL) crossing the second source structure 106 and the second source structure 106 .

11 is a cross-sectional view illustrating a semiconductor memory device according to another exemplary embodiment. For convenience of explanation, the points different from those described with reference to FIGS. 1 to 10 will be mainly described.

Referring to FIG. 11 , the semiconductor memory device according to some embodiments may include only a first mold structure MS1 . That is, the semiconductor memory device according to some embodiments may have a single stack structure. The channel structure CH, the cell contact 162 , the source contact 164 , and the through via 166 do not have bent portions.

Hereinafter, a method of manufacturing a semiconductor memory device according to some embodiments will be described with reference to FIGS. 1 to 36 .

12 to 36 are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor memory device according to some embodiments.

12 and 13 , a first mold sacrificial layer 112 and a first mold insulating layer 110 that are alternately stacked on the cell substrate 100 and/or the insulating substrate 101 are formed.

The first mold sacrificial layer 112 may include a material having an etch selectivity with respect to the first mold insulating layer 110 . For example, the first mold insulating layer 110 may include silicon oxide, and the first mold sacrificial layer 112 may include silicon nitride.

In some embodiments, before laminating the first mold sacrificial layer 112 and the first mold insulating layer 110 , the source sacrificial layers 102p and 103 and A second source layer 104 may be formed. The source sacrificial layers 102p and 103 may include a material having an etch selectivity with respect to the first mold insulating layer 110 . For example, the first mold insulating layer 110 may include silicon oxide, and the source sacrificial layers 102p and 103 may include silicon nitride. The second source layer 104 may include polysilicon doped with impurities or polysilicon undoped with impurities, but is not limited thereto.

In some embodiments, the cell substrate 100 and/or the insulating substrate 101 may be stacked on the peripheral circuit region PERI. For example, a peripheral circuit element PT, a second wiring structure 260 , and a second insulating interlayer 240 may be formed on the peripheral circuit board 200 . The cell substrate 100 and/or the insulating substrate 101 may be stacked on the second inter-wiring insulating layer 240 .

14 and 15 , the lower trench Ta and the free lower dummy mold structure DMA_P are formed.

A lower trench Ta penetrating through the first mold sacrificial layer 112 and the first mold insulating layer 110 may be formed in the extension region EXT. The lower trenches Ta may be spaced apart from each other in the second direction Y. The free lower dummy mold structure DMA_P may be disposed between the lower trenches Ta.

16 and 17 , a first free interlayer insulating layer 140a_P is formed on the first mold sacrificial layer 112 and the first mold insulating layer 110 .

The first free interlayer insulating layer 140a_P may fill the lower trench Ta. The first free interlayer insulating layer 140a_P may be formed on the free lower dummy mold structure DMA_P.

The lower trench Ta may have a first width W1 in the second direction Y. That is, a distance between the plurality of free lower dummy mold structures DMA_P spaced apart in the second direction Y with the lower trench Ta interposed therebetween may be the first width W1 . The first free interlayer insulating layer 140a_P may be formed at a first height H1 on the free lower dummy mold structure DMA_P. In this case, the first height H1 may be smaller than the first width W1 . For example, the first height H1 may be 1/2 of the first width W1.

The lower trench Ta may be surrounded by the free lower dummy mold structure DMA_P. When depositing the first free interlayer insulating film 140a_P in the lower trench Ta, the first free interlayer insulating film 140a_P may be deposited not only on the bottom surface of the lower trench Ta but also on the inner wall of the lower trench Ta. have. That is, the first free interlayer insulating layer 140a_P may also be deposited on the sidewall of the free lower dummy mold structure DMa_P defining the lower trench Ta. Accordingly, the first free interlayer insulating layer 140a_P may be filled in the lower trench Ta.

Since the first free interlayer insulating layer 140a_P is deposited on the sidewall of the lower trench Ta to fill the lower trench Ta, an excessive amount of the first free interlayer insulating layer 140a_P is formed on the free lower dummy mold structure DMA_P. The first free interlayer insulating layer 140a_P may be filled in the lower trench Ta without forming the first free interlayer insulating layer 140a_P.

18 and 19 , the first free interlayer insulating layer 140a_P formed on the free lower dummy mold structure DMA_P is removed.

Since the lower trench Ta is formed on top of the pre-lower dummy mold structure DMA_P with a first height H1 smaller than the first width W1 in the second direction Y, the cell region CAR and the extension region The first free interlayer insulating layer 140a_P on the free lower dummy mold structure DMA_P may be removed over EXT.

20 and 21 , a preliminary channel pCH, a preliminary cell contact 162P, a preliminary source contact 164P, and a preliminary through-via 166P are formed.

The preliminary channel pCH may extend in the third direction Z to pass through the mold structures MS1 and MS2 . The preliminary cell contact 162P may be connected to each of the mold sacrificial layers 112 and 117 . The preliminary source contact 164P may be connected to the first source structures 102 and 104 . The preliminary through via 166P may be disposed in the through region THR.

The preliminary cell contact 162P may be formed in the lower trench Ta. The preliminary cell contact 162P may be formed in the first interlayer insulating layer 140a filling the lower trench Ta.

Each of the preliminary channel pCH, the preliminary cell contact 162P, the preliminary source contact 164P, and the preliminary through-via 166P may include, but is not limited to, poly Si.

22 and 23 , a second mold sacrificial layer 117 and a second mold insulating layer 115 are formed on the first mold sacrificial layer 112 and the first mold insulating layer 110 .

The second mold sacrificial layer 117 and the second mold insulating layer 115 may be formed on the preliminary channel pCH, the preliminary cell contact 162P, the preliminary source contact 164P, and the preliminary through-via 166P.

24 and 25 , the first trench T1 , the upper trench Tb and the free upper dummy mold structure DMb_P are formed.

A first trench T1 passing through the second mold sacrificial layer 117 and the second mold insulating layer 115 may be formed in the extension region EXT. Also, an upper trench Tb passing through the second mold sacrificial layer 117 and the second mold insulating layer 115 may be formed in the lower trench Ta in the extended region EXT. The first trenches T1 may be spaced apart from each other in the second direction Y. The upper trench Tb may be spaced apart from each other in the second direction Y. The free upper dummy mold structure DMb_P may be disposed between the first trenches T1 and between the upper trenches Tb.

26 and 27 , a second free interlayer insulating layer 140b_P is formed on the second mold sacrificial layer 117 and the second mold insulating layer 115 .

The second free interlayer insulating layer 140b_P may fill the first trench T1 and the upper trench Tb. The second free interlayer insulating layer 140b_P may be formed on the free upper dummy mold structure DMb_P.

The first trench T1 and the upper trench Tb may have a second width W2 in the second direction Y. That is, a distance between the plurality of free upper dummy mold structures DMb_P spaced apart in the second direction Y with the first trench T1 or the upper trench Tb interposed therebetween may be the second width W2 . The second free interlayer insulating layer 140b_P may be formed at a second height H2 on the free upper dummy mold structure DMb_P. In this case, the second height H2 may be smaller than the second width W2. For example, the second height H2 may be 1/2 of the second width W2.

28 to 30 , a channel structure CH is formed.

For example, the spare channel (pCH) may be selectively removed. Subsequently, a channel structure CH replacing the region from which the preliminary channel pCH is removed may be formed.

31 and 32 , a word line cutting hole WLCh is formed, and a plurality of gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 are formed.

For example, the mold sacrificial layers 112 and 117 may be removed using the word line cutting hole WLCh. Since the mold sacrificial layers 112 and 117 have an etch selectivity with respect to the mold insulating layers 110 and 115 , they may be selectively removed. Thereafter, gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 may be formed to replace the region from which the mold sacrificial layers 112 and 117 have been removed.

In some embodiments, a first source structure 102 , 104 may be formed. For example, the source sacrificial layer 102p may be selectively removed using the word line cutting hole WLCh. Subsequently, the first source layer 102 may be formed to replace the region from which the source sacrificial layer 102p has been removed.

33 and 34 , a word line cut line WLC, a cell contact 162 , a source contact 164 and a through via 166 are formed.

After the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 and the first source structures 102 and 104 are formed, the word line cutting hole WLCh is formed with an insulating material (eg, silicon oxide).

The preliminary cell contact 162P, the preliminary source contact 164P, and the preliminary through via 166P may be selectively removed. Subsequently, a cell contact 162 , a source contact 164 , and a through-via 166 may be formed to replace the region in which the preliminary cell contact 162P, the preliminary source contact 164P, and the preliminary through-via 166P are removed. have.

The cell contact 162 may be formed in the first trench T1 or the second trench T2 . The second trench T2 may be defined as a trench in which the upper trench Tb and the lower trench Ta of FIG. 25 are connected.

Next, referring to FIGS. 3 to 8 , the first interconnection structure 180 connected to the cell contact 162 , the source contact 164 , and the through via 166 is formed. Through this, the semiconductor memory device described above with reference to FIGS. 3 to 8 may be manufactured.

35 is an exemplary block diagram for describing an electronic system according to some embodiments. 36 is an exemplary perspective view for explaining an electronic system according to some embodiments. FIG. 37 is a schematic cross-sectional view taken along II-I of FIG. 36 .

Referring to FIG. 35 , the electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100 . The electronic system 1000 may be a storage device including one or a plurality of semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device including one or a plurality of semiconductor memory devices 1100 , a computing system, a medical device, or a communication device. .

The semiconductor memory device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device), for example, the semiconductor memory device described above with reference to FIGS. 1 to 11 . The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

The first structure 1100F includes a decoder circuit 1110 (eg, row decoder 33 in FIG. 1 ), a page buffer 1120 (eg, page buffer 35 in FIG. 1 ), and a logic circuit 1130 (eg, FIG. 1 ). may be a peripheral circuit structure including the control logic 37 of

The second structure 1100S may include the common source line CSL, the plurality of bit lines BL, and the plurality of cell strings CSTR described above with reference to FIG. 2 . The cell strings CSTR may be connected to the decoder circuit 1110 through a word line WL, at least one string select line SSL, and at least one ground select line GSL. Also, the cell strings CSTR may be connected to the page buffer 1120 through bit lines BL.

In some embodiments, the common source line CSL and the cell strings CSTR are connected to the decoder circuit 1110 and the decoder circuit 1110 through first connection lines 1115 extending from the first structure 1100F to the second structure 1100S. may be electrically connected. The first connection wiring 1115 may correspond to the through-via 166 described above with reference to FIGS. 1 to 11 . That is, the through via 166 may electrically connect each of the gate electrodes ECL, GSL, WL, and SSL and the decoder circuit 1110 (eg, the row decoder 33 of FIG. 1 ).

In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first structure 1100F to the second structure 1100S. The second connection line 1125 may correspond to the through-via 166 described above with reference to FIGS. 1 to 11 . That is, the through via 166 may electrically connect the bit lines BL and the page buffer 1120 (eg, the page buffer 35 of FIG. 1 ).

The semiconductor memory device 1100 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 (eg, the control logic 37 of FIG. 1 ). The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100 .

The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200 . The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor memory device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that handles communication with the semiconductor memory device 1100 . Through the NAND interface 1221 , a control command for controlling the semiconductor memory device 1100 , data to be written to the memory cell transistors MCT of the semiconductor memory device 1100 , and a memory cell of the semiconductor memory device 1100 . Data to be read from the transistors MCT may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230 , the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

36 and 37 , an electronic system according to some embodiments includes a main board 2001 , a main controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and a DRAM 2004 . may include The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 by wiring patterns 2005 formed on the main board 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 includes interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. It can communicate with an external host according to either one. In some embodiments, the electronic system 2000 may operate by power supplied from an external host through the connector 2006 . The electronic system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the main controller 2002 and the semiconductor package 2003 .

The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operating speed of the electronic system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the electronic system 2000 includes the DRAM 2004 , the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . Each of the first semiconductor package 2003a and the second semiconductor package 2003b includes a package substrate 2100 , semiconductor chips 2200 on the package substrate 2100 , and adhesive layers disposed on lower surfaces of the semiconductor chips 2200 , respectively. 2300 , a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 , and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100 . ) may be included.

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each semiconductor chip 2200 may include an input/output pad 2210 . The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 35 .

In some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the upper package pads 2130 . Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b , the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and the package upper pads 2130 of the package substrate 2100 . ) can be electrically connected to. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b , the semiconductor chips 2200 may be connected to a through-electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400 . ) may be electrically connected to each other by a connection structure comprising a.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor by wiring formed on the interposer substrate. Chips 2200 may be connected to each other.

In some embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 is disposed on or exposed through the package substrate body 2120 , the package upper pads 2130 disposed on the upper surface of the package substrate body 2120 , and the lower surface of the package substrate body 2120 . It may include lower pads 2125 to be formed, and internal wirings 2135 electrically connecting the upper pads 2130 and the lower pads 2125 in the package substrate body 2120 . The upper pads 2130 may be electrically connected to the connection structures 2400 . The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 as shown in FIG. 37 through conductive connectors 2800 .

In the electronic system according to some embodiments, each of the semiconductor chips 2200 may include the semiconductor memory device described above with reference to FIGS. 1 to 11 . For example, each of the semiconductor chips 2200 may include a peripheral circuit region PERI and a memory cell region CELL stacked on the peripheral circuit region PERI. For example, the peripheral circuit region PERI may include the peripheral circuit board 200 and the second wiring structure 260 described above with reference to FIGS. 3 to 8 . Also, for example, in the memory cell region CELL, the cell substrate 100 , the mold structures MS1 and MS2 , the channel structure CH, and the cell contact 162 described above with reference to FIGS. 3 to 9 are disposed. It may include a trench T, a pad area PAD formed on a bottom surface of the trench T, and a dummy mold structure DM.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: cell substrate 162: cell contact
PAD: pad area MS: mold structure
DM: dummy mold structure EXT: extension area

Claims (10)

a substrate including a cell region and an extension region adjacent to each other in a first direction;
a mold structure including a plurality of insulating layers and a plurality of gate electrode layers alternately stacked on the substrate;
a channel structure extending in a direction perpendicular to the substrate in the cell region and penetrating the mold structure; and
a cell contact extending in a direction perpendicular to the substrate in the extension region and connected to the plurality of gate electrode layers;
The cell contact includes a first contact and a second contact spaced apart from each other in a second direction intersecting the first direction,
The mold structure includes a dummy mold structure that protrudes in a direction perpendicular to the substrate between the first contact and the second contact. The method of claim 1,
a word line cutting line extending in the first direction over the cell region and the extension region;
The word line cutting line in the extension region cuts the dummy mold structure. The method of claim 1,
On a cross-sectional view taken along the second direction,
The height of the mold structure from the top surface of the substrate is not constant. The method of claim 1,
On a cross-sectional view taken along the second direction,
The cell contact is
and disposed in a trench recessed from the top surface of the mold structure toward the top surface of the substrate. 5. The method of claim 4,
and an insulating layer surrounding the cell contact in the trench. The method of claim 1,
On a cross-sectional view taken along the first direction to pass through the dummy mold structure,
The height of the mold structure over the cell region and the extension region is constant. The method of claim 1,
In the extension area,
A height of the dummy mold structure with respect to a top surface of the substrate is the same as a height of the mold structure with respect to a top surface of the substrate disposed in the cell region. The method of claim 1,
Further comprising a trench recessed toward the top surface of the substrate from the top surface of the mold structure in the extension region,
The plurality of gate electrode layers,
and a pad region stacked in a step shape along the first direction on the extension region to expose an upper surface,
the cell contact extends in a direction perpendicular to the substrate on the pad area;
The pad region is disposed on a bottom surface of the trench. a substrate including a cell region and an extension region adjacent to each other in a first direction;
a mold structure including a plurality of insulating layers and a plurality of gate electrode layers alternately stacked on the substrate;
a word line cutting line extending in the first direction and cutting the mold structure; and
a cell contact extending in a direction perpendicular to the substrate in the extension region and connected to the plurality of gate electrode layers;
The cell contact includes a first contact and a second contact spaced apart from each other in a second direction intersecting the first direction,
The mold structure disposed under the first contact and the second contact has a first height from an upper surface of the substrate;
The mold structure between the first contact and the second contact has a second height higher than the first height from a top surface of the substrate. To provide a substrate comprising a cell region and an extension region adjacent to each other in a first direction,
forming a pre-mold structure in which a mold insulating layer and a sacrificial insulating layer are alternately stacked on the substrate;
forming a plurality of trenches spaced apart in a second direction intersecting the first direction in the pre-mold structure on the extension region and recessed toward the substrate from the upper surface of the pre-mold structure;
forming an interlayer insulating film on the plurality of trenches and the pre-mold structure;
forming a channel structure penetrating the pre-mold structure on the cell region;
removing the sacrificial insulating layer, forming a gate electrode layer between the mold insulating layers;
and forming a cell contact connected to the gate electrode layer in the plurality of trenches.

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