KR20230080188A - Circuit board and package substrate comprising the same - Google Patents

Abstract

A circuit board according to an embodiment comprises: a first insulating layer; a first pattern layer disposed on an upper surface of the first insulating layer; and a second insulating layer disposed on the upper surface of the first insulating layer and an upper surface of the first pattern layer and comprising a cavity, wherein a thickness of the first insulating layer is different from a thickness of the second insulating layer, and the thickness of any one of the first and second insulating layers satisfies a range of 110-220 % of the thickness of the other one insulating layer. Therefore, the present invention is capable of improving a physical reliability of the circuit board.

Description

Circuit board and package substrate including the same {CIRCUIT BOARD AND PACKAGE SUBSTRATE COMPRISING THE SAME}

Embodiments relate to circuit boards and package boards.

A printed circuit board (PCB) is formed by printing a circuit line pattern with a conductive material such as copper on an electrically insulating substrate, and refers to a board just before mounting electronic components. That is, in order to densely mount many types of electronic devices on a flat plate, it means a circuit board on which the mounting position of each component is determined, and a circuit pattern connecting the components is printed on the flat surface and fixed.

Such a printed circuit board has a multilayer structure. To this end, a conventional manufacturing process of a printed circuit board includes a process of laminating a second insulating layer on a first insulating layer on which a first circuit pattern layer is formed.

At this time, a problem may occur in that adhesion between the first insulating layer and the second insulating layer is not secured depending on the remaining area of the first circuit pattern layer. And, when the adhesion is not secured, a void such as a bubble is formed between the first insulating layer/the first circuit pattern layer and the second circuit pattern layer, and the second insulating layer is formed due to the void. There is a physical reliability problem in that the film is detached from the first circuit pattern layer and/or the first insulating layer.

Also, the problem of film removal as described above increases as the remaining area of the first circuit pattern layer increases.

Accordingly, there is a need for a new technology capable of securing adhesion between a plurality of insulating layers in a circuit board including a plurality of insulating layers.

In an embodiment, a circuit board having a new structure and a package board including the circuit board are provided.

In addition, in the embodiment, it is intended to provide a circuit board capable of securing adhesion between a plurality of insulating layers and a package substrate including the circuit board.

In addition, in the embodiment, it is intended to provide a circuit board capable of securing adhesion to a molding layer for molding a chip and a package substrate including the circuit board.

Technical problems to be solved in the embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below. You will be able to.

A circuit board according to an embodiment includes a first insulating layer; a first pattern layer disposed on an upper surface of the first insulating layer; and a second insulating layer disposed on the upper surface of the first insulating layer and the upper surface of the first pattern layer and including a cavity, wherein the thickness of the first insulating layer is different from that of the second insulating layer, The thickness of any one of the first and second insulating layers satisfies a range of 110% to 220% of the thickness of the other insulating layer.

In addition, the first pattern layer is disposed under the lower surface of the second insulating layer and is buried in the first insulating layer, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

In addition, the first pattern layer is disposed on the upper surface of the first insulating layer and is buried in the second insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer.

In addition, a third insulating layer is disposed under the first insulating layer, and the thickness of the third insulating layer is smaller than that of the first insulating layer.

In addition, the thickness of the third insulating layer corresponds to the thickness of the second insulating layer.

In addition, a fourth insulating layer is disposed on the second insulating layer, and the fourth insulating layer has a thickness smaller than that of the second insulating layer.

In addition, the thickness of the fourth insulating layer corresponds to the thickness of the first insulating layer.

Further, the first pattern layer includes a pattern portion having an upper surface in contact with the second insulating layer and a side surface exposed through the cavity, and a width of a lower surface of the pattern portion is greater than a width of an upper surface of the pattern portion.

In addition, the pattern unit includes a side surface having an inclination in which a width decreases from a lower surface of the pattern unit toward an upper surface of the pattern unit, and the side surface of the pattern unit includes a curved surface.

In addition, the pattern part includes a recessed part in an inward direction, and at least a part of the lower surface of the second insulating layer vertically overlaps the recessed part, and does not contact the first pattern layer and the first insulating layer. don't

In addition, one of the first and second insulating layers has a thickness ranging from 10 μm to 60 μm, and the other one of the first and second insulating layers has a thickness ranging from 11 μm to 132 μm.

On the other hand, the package substrate according to the embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer and including a cavity; and a first pattern part disposed between the first insulating layer and the second insulating layer and disposed in a first region vertically overlapping the cavity, and disposed in a second region not vertically overlapping the cavity. a first pattern layer including a second pattern part and a third pattern part disposed in a boundary region between the first and second regions; a connection part disposed on the first pattern part; an element mounted on the connection part; and a molding layer molding the element and disposed within the cavity, wherein the third pattern part includes a recessed part inwardly, and at least a part of a lower surface of the second insulating layer, It vertically overlaps the recess and contacts the molding layer.

In addition, the third pattern part includes a side surface having an inclination in which a width decreases from a lower surface of the third pattern part toward an upper surface of the third pattern part, and the side surface of the third pattern part includes a curved surface.

In addition, the first pattern layer is disposed below the lower surface of the second insulating layer and is buried in the first insulating layer, and the thickness of the first insulating layer is 110% to 220% of the thickness of the second insulating layer. % range is satisfied.

In addition, the first pattern layer is disposed on the upper surface of the first insulating layer and is buried in the second insulating layer, and the thickness of the second insulating layer is 110% to 220% of the thickness of the first insulating layer. satisfies the range of

According to an embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a 1-1 insulating layer disposed most adjacent to the first substrate layer and a first pattern layer disposed on an upper surface of the 1-1 insulating layer. The second substrate layer includes a 2-1 insulating layer disposed on the first pattern layer. At this time, the first pattern layer includes a stopper layer for forming the cavity. Most of the stopper layer is removed after the cavity is formed, but is entirely disposed corresponding to the area where the cavity is to be formed during a circuit board manufacturing process before the cavity is formed. Accordingly, the surface area of the first pattern layer during the manufacturing process of the circuit board exceeds 50%, and further exceeds 60% of the surface areas of the 1-1st insulating layer and the 2-1st insulating layer, thereby Adhesion between the 1-1 insulating layer and the 2-1 insulating layer may decrease. Accordingly, in the embodiment, the thickness of the insulating layer in contact with the first pattern layer including the stopper layer is increased to improve adhesion with the insulating layer in contact with the first pattern layer including the stopper layer. Specifically, in the embodiment, the thickness of any one of the thicknesses of the 1-1st insulating layer and the 2-1st insulating layer is greater than the thickness of the other insulating layers. Through this, in the embodiment, adhesion between the first pattern layer, the 1-1 insulating layer, and the 2-1 insulating layer can be improved, and through this, physical reliability of the circuit board can be improved.

In this case, the first pattern layer includes a first pattern part disposed in a first area vertically overlapping the cavity, a second pattern part disposed in a second area not vertically overlapping the cavity, and and a third pattern portion formed in the boundary area between the first and second areas. At this time, the thickness of at least one of the first to third pattern parts in the embodiment is different from the thickness of at least another one. In addition, the upper or lower surface of at least one of the first to third pattern parts in the embodiment is located on a different plane from the upper or lower surface of at least another one. As described above, in the embodiment, the first pattern layer disposed in the region adjacent to the cavity has a structure in which different thicknesses or surfaces are disposed at different positions, thereby improving the cavity formation processability, and may occur during the cavity process. Reliability problems can be solved.

Specifically, in the embodiment, in the process of forming the first pattern layer, it has a two-layer structure including a first metal layer and a second metal layer through two-step plating, and among the first metal layer and the second metal layer One of them is used as a first pattern part, which is a mounting pad, and the other is used as a third pattern part, which is a laser stopper. Through this, in the embodiment, a reliability problem caused by the arrangement of the mounting pad and the stopper on the same plane can be solved. For example, in the comparative example, a separate protective layer (not shown) is formed on the mounting pad to prevent damage to the mounting pad in a laser process for forming a cavity, and a process of removing the protective layer is performed later. In contrast, in the embodiment, a part of the third pattern part used as the laser stopper can be used as a protection part for the first pattern part, which is the mounting pad, and thus, in the process of forming the cavity, the first pattern part, which is the mounting pad, is damaged. While preventing this from happening, a process of forming an additional protective layer for protecting the first pattern portion may be omitted.

In addition, the third pattern portion in the embodiment includes a recessed portion in an inward direction. Also, the recessed portion may be filled with a molding layer for molding a chip mounted in the cavity. Through this, in the embodiment, the bonding force between the circuit board and the molding layer may be improved by allowing the molding layer to fill the cavity and the depression of the third pattern part, and through this, the mounted chip may be stably can be made to be protected. Accordingly, in the embodiment, product reliability may be improved, and operation reliability of the chip may be improved.

The first substrate layer includes a first region vertically overlapping the cavity and a second region excluding the first region. Also, the second substrate layer includes a third region corresponding to the cavity and a fourth region excluding the third region. At this time, the third area of the second substrate layer in the embodiment is an area where the driving element is disposed, and the fourth area is an area where the antenna pattern layer is disposed. In the above embodiment, the driving element is disposed using the cavity of the second substrate layer, and the antenna pattern layer is disposed in the fourth region of the second substrate layer horizontally adjacent to the driving element. Accordingly, in the embodiment, it is possible to minimize the signal transmission distance between the antenna pattern layer and the driving element, thereby minimizing the signal transmission loss. For example, in the embodiment, the signal transmission distance can be reduced compared to connecting the substrate on which the driving element is disposed and the substrate on which the antenna pattern layer is disposed in the comparative example using a separate connection means, and thus a separate Signal transmission loss caused by the connection means can be reduced. In addition, in the embodiment, by having a structure in which the antenna pattern layer and the driving element are disposed in a horizontal direction, the second area of the first substrate layer vertically overlapping the fourth area of the second substrate layer is a second antenna pattern It can be used as a layer, and accordingly, in one circuit pattern, antenna pattern radiation and signal reception in different directions can be made possible.

In addition, in the embodiment, by disposing the driving element in the cavity of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavity.

In addition, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. At this time, with respect to the bottom surface of the cavity, the second inclination has a smaller inclination angle than the first inclination. Also, in the embodiment, the vertical length of the second part having the second slant is longer than the vertical length of the first part having the first slant. Accordingly, in the embodiment, compared to the comparative example, the space occupied by the cavity can be reduced, and thus the degree of integration of the circuit can be improved. For example, in the embodiment, as the space occupied by the cavity is reduced, the length of the antenna pattern layer can be increased in the substrate having the same size as the comparative example, and thus communication performance can be improved.

1A to 1C are diagrams for explaining an adhesion problem of a circuit board according to a comparative example.
FIG. 2 is a diagram illustrating a circuit board according to the first embodiment, and FIG. 3 is an enlarged view of the cavity area of FIG. 2 .
4 is an enlarged view of a disposition area of the first pattern layer of the circuit board according to the first embodiment.
5 is a diagram illustrating a circuit board according to a second embodiment.
6 is a view showing a package substrate according to an embodiment.
7A to 7P are diagrams illustrating a manufacturing method of the circuit board according to the exemplary embodiment shown in FIG. 2 in process order.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in a variety of different forms, and if it is within the scope of the technical idea of the present invention, one or more of the components among the embodiments can be selectively implemented. can be used by combining and substituting.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention, unless explicitly specifically defined and described, can be generally understood by those of ordinary skill in the art to which the present invention belongs. It can be interpreted as meaning, and commonly used terms, such as terms defined in a dictionary, can be interpreted in consideration of contextual meanings of related technologies.

Also, terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when described as "at least one (or more than one) of A and (and) B and C", A, B, and C are combined. may include one or more of all possible combinations.

Also, terms such as first, second, A, B, (a), and (b) may be used to describe components of an embodiment of the present invention. These terms are only used to distinguish the component from other components, and the term is not limited to the nature, order, or order of the corresponding component. And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected to, combined with, or connected to the other component, but also with the component. It may also include the case of being 'connected', 'combined', or 'connected' due to another component between the other components.

In addition, when it is described as being formed or disposed on the "top (above) or bottom (bottom)" of each component, the top (top) or bottom (bottom) is not only a case where two components are in direct contact with each other, but also one A case in which another component above is formed or disposed between two components is also included. In addition, when expressed as "up (up) or down (down)", it may include the meaning of not only the upward direction but also the downward direction based on one component.

Prior to description of an embodiment of the present invention, a circuit board according to a comparative example will be described. Preferably, an antenna circuit board for an antenna package will be described below.

1A to 1C are diagrams for explaining an adhesion problem of a circuit board according to a comparative example.

Referring to (a) of FIG. 1A , the circuit board of the comparative example includes a first insulating layer 10 and a second insulating layer 20 .

In addition, the circuit board of the comparative example includes a circuit pattern layer 30 disposed between the first insulating layer 10 and the second insulating layer 20 .

At this time, in the comparative example, the first insulating layer 10 and the second insulating layer 20 have the same thickness. Accordingly, in the comparative example, the first insulating layer 10 and the second insulating layer 10 and the second insulating layer depend on the surface area of the circuit pattern layer 30 disposed between the first insulating layer 10 and the second insulating layer 20. (20) has a problem that the adhesion between them is lowered.

Specifically, referring to (b) of FIG. 1A , the circuit pattern layer 30 is disposed on the first insulating layer 10 . And, the second insulating layer 20 is stacked on the first insulating layer 10 in a state where the circuit pattern layer 30 is disposed.

At this time, the adhesion between the first insulating layer 10 and the second insulating layer 20 may change according to the surface area of the circuit pattern layer 30 disposed on the first insulating layer 10 . . For example, FIG. 1A shows that the circuit pattern layer 30 is disposed on the first insulating layer 10 and has a first surface area. For example, the first surface area of the circuit pattern layer 30 may be less than 50% of the surface area of the first insulating layer 10 .

And, when the first surface area is less than 50% of the surface area of the first insulating layer 10, in the step of laminating the second insulating layer 20, the entire area of the lower surface of the second insulating layer 20 This means that the area of the area in contact with the upper surface of the first insulating layer 10 is larger than the area in contact with the circuit pattern layer 30 . Also, when the first surface area is less than 50%, adhesion between the first insulating layer 10 and the second insulating layer 20 may be maintained.

Alternatively, referring to (a) and (b) of FIG. 1B, the circuit pattern layer 30a has a larger surface area than the first surface area between the first insulating layer 10 and the second insulating layer 20. It can be placed with a surface area of 2. For example, the second surface area may exceed 60% of the surface area of the first insulating layer 10 . At this time, when the second surface area exceeds 60% of the surface area of the first insulating layer 10, in the step of laminating the second insulating layer 20, the first insulating layer 10 and the second insulating layer Adhesion problems may occur between the layers 20 .

For example, when the second surface area exceeds 60% of the surface area of the first insulating layer 10, in the step of laminating the second insulating layer 20, the second insulating layer 20 This means that the area in contact with the circuit pattern layer 30 is greater than the area in contact with the top surface of the first insulating layer 10 among the entire areas of the lower surface. At this time, the bonding strength between the second insulating layer 20 and the circuit pattern layer 30a is lower than that between the second insulating layer 20 and the first insulating layer 10 . Accordingly, as described above, when the second surface area of the circuit pattern layer 30a exceeds 60% of the surface area of the first insulating layer 10, the second insulating layer 20 and the first insulating layer Adhesion between (10) or between the second insulating layer 20 and the circuit pattern layer 30a may cause problems.

Accordingly, in the comparative example, as shown in FIG. 1C, in the process of laminating a plurality of insulating layers, the second insulating layer 20 is the circuit pattern layer 30a or the second insulating layer 20 due to the adhesion problem as described above. There is a physical reliability problem that is separated from 1 insulating layer 10 .

Accordingly, in the embodiment, the thickness of the insulating layer is increased in proportion to the surface area of the circuit pattern layer, so that adhesion between the plurality of insulating layers can be secured. Preferably, the circuit board of the embodiment includes a cavity. To this end, in the manufacturing process of the circuit board, a process of forming a stopper pattern corresponding to an area where a cavity is to be formed, forming a cavity using the stopper pattern, and finally removing the stopper pattern is performed. At this time, most of the stopper pattern as described above is removed from the final structure of the circuit board, but has a structure that is entirely disposed in the region where the cavity is to be formed during the manufacturing process of the circuit board. Accordingly, when an insulating layer is stacked on the stopper pattern in a state in which the stopper pattern is disposed, a problem may occur in adhesion between the insulating layer and the stopper pattern, and through this, the insulating layer is defilmed. may occur. Accordingly, in the embodiment, the thickness of the insulating layer in contact with the circuit pattern layer corresponding to the stopper pattern is adjusted to solve the problem of deterioration in adhesion caused by the stopper pattern.

Hereinafter, a circuit board and a package substrate according to an embodiment will be described in detail.

FIG. 2 is a diagram illustrating a circuit board according to the first embodiment, and FIG. 3 is an enlarged view of the cavity area of FIG. 2 .

Hereinafter, the overall structure of a circuit board according to an embodiment will be described with reference to FIGS. 2 and 3 .

First, the circuit board 100 of the embodiment may be used as an antenna board. However, embodiments are not limited thereto. For example, the circuit board of the embodiment may be used as another type of package board on which a chip is mounted other than the antenna board. For example, a package substrate having a structure in which a chip is mounted on a circuit board according to an embodiment may be included in an electronic device. At this time, the electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate includes memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory, a central processor (eg, CPU), a graphic processor (eg, GPU), Application processor chips such as digital signal processors, cryptographic processors, microprocessors and microcontrollers, and logic chips such as analog-to-digital converters and application-specific ICs (ASICs) may be mounted. Also, the circuit board of the embodiment may be used as a package board on which a memory chip or a logic chip is mounted.

The circuit board according to the embodiment includes a cavity, and at least one chip, and furthermore, at least two or more chips can be mounted in the cavity. And, as an example, the chip may be an RFIC including a transmitting chip and a receiving chip of an antenna device.

At this time, the electronic device includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is not limited thereto, and may be any other electronic device that processes data in addition to these.

Hereinafter, the circuit board of the embodiment will be described as being used as a package board of an antenna device.

The circuit board 100 of the embodiment may be provided for driving, feeding, and supporting the antenna unit. For example, the circuit board 100 may be a printed circuit board (PCB). The circuit board 100 has a flat plate structure. The circuit board 100 may have a multilayer structure in which a plurality of layers are stacked.

The circuit board 100 may include a ground layer (not shown) for grounding and a power supply unit (not shown) for power supply.

The circuit board 100 of the embodiment may be divided into an antenna unit on which a conductive antenna pattern layer is disposed, and a driving unit on which a driving element for driving the antenna unit is disposed. The conductive antenna pattern layer may refer to any one of a plurality of circuit layers described below.

The conductive antenna pattern layer may be provided for signal transmission and reception in the circuit board of the embodiment. For example, the conductive antenna pattern layer may transmit and receive signals in a predetermined resonant frequency band. For example, the conductive antenna pattern layer may transmit and receive electromagnetic waves by operating in a resonant frequency band. The conductive antenna pattern layer may operate as power is supplied from a power supply unit (not shown) of the circuit board 100 , and power supply operation of the power supply unit may be performed under control of the driving unit.

The conductive antenna pattern layer may resonate in a plurality of resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonance antenna that resonates in different resonance frequency bands. For example, the conductive antenna pattern layer may be a dual resonance antenna resonating in a first frequency band of 24.03 GHz to 25.81 GHz and a second frequency band of 27.07 GHz to 28.80 GHz, respectively, but is not limited thereto. A resonant frequency band of the conductive antenna pattern layer may vary according to a communication standard of an antenna device to which the circuit board is applied.

The circuit board 100 of the embodiment may include a first substrate layer 200 and a second substrate layer 300 .

At this time, the first substrate layer 200 and the second substrate layer 300 do not mean a plurality of substrates manufactured in a state separated from each other and then bonded through a bonding layer, but manufactured through a single manufacturing process. means one board.

For example, in one circuit board, the first substrate layer 200 and the second substrate layer 300 include a first substrate area where the cavity C is formed and a second substrate other than the first substrate area. to demarcate the area.

The first substrate layer 200 may include one single insulating layer, or may include a plurality of insulating layers sequentially stacked in a thickness direction.

At this time, the first substrate layer 200 is connected to at least one chip, and while connecting between the chip and the circuit layer, the main board of the antenna device (eg, electronic device) including the circuit board of the embodiment ( not shown) may be connected.

At this time, although the insulating layer of the first substrate layer 200 may have a one-layer structure, in order to dispose the connection line as described above on the first substrate layer 200 having a one-layer structure, the first substrate layer ( 200) increases in the horizontal direction, and accordingly, the area occupied by the circuit board in the antenna device may increase. Accordingly, the first substrate layer 200 may include two or more insulating layers in order to minimize the distance of the signal connection line while reducing the width of the circuit board in the horizontal direction. Hereinafter, the first substrate layer 200 will be described as having a layer structure of two or more layers. However, the embodiment is not limited thereto, and it will be apparent that the first substrate layer 200 may have a single insulating layer structure.

The second substrate layer 300 may be disposed on the first substrate layer 200 . The second substrate layer 300 may have a layer structure of at least two layers. The second substrate layer 300 provides a circuit layer and a cavity (C). At this time, the circuit layer of the second substrate layer 300 is a conductive antenna pattern layer that functions as an antenna.

In addition, when the second substrate layer 300 has a one-layer structure, a sufficient depth of the cavity C formed in the second substrate layer 300 may not be secured, and through this, a package in which a chip is mounted The effect of reducing the thickness of the substrate may be insignificant. In addition, when the second substrate layer 300 has a one-layer structure, it is not possible to sufficiently secure an arrangement area for the circuit layer within a limited space, and thus communication performance of the antenna pattern may deteriorate. That is, the communication performance of the antenna pattern increases in proportion to the length of the antenna pattern. In this case, when the second substrate layer 300 has a one-layer structure, the length of the antenna pattern is correspondingly reduced, thereby reducing communication performance.

Accordingly, in the embodiment, the second substrate layer 300 is provided in order to provide a cavity C of sufficient space (for example, sufficient depth) for mounting a chip while satisfying the communication performance of the antenna pattern. It should include two or more insulating layers. However, the embodiment is not limited thereto, and depending on the product to which the circuit board of the embodiment is applied or the thickness of a chip mounted in the cavity (C), the second substrate layer 300 may include one insulating layer. It could be.

Hereinafter, the first substrate layer 200 and the second substrate layer 300 according to the embodiment will be described in detail.

The first substrate layer 200 may include an insulating layer, a circuit layer, and a through electrode. The through electrode may also be referred to as a 'connection portion' or 'via' that functions to connect circuit patterns disposed on different layers.

The first substrate layer 200 may include a first insulating layer. The first insulating layer may have a one-layer or two- or more-layered structure. In the drawing, the first insulating layer of the first substrate layer 200 is shown as having a three-layer structure, but is not limited thereto.

The first insulating layer may include a 1-1 insulating layer 211 , a 1-2 insulating layer 212 , and a 1-3 insulating layer 213 . For example, the first insulating layer may include a 1-1 insulating layer 211 , a 1-2 insulating layer 212 , and a 1-3 insulating layer 213 from a region adjacent to the second substrate layer 300 . ) may be included.

The 1-1st insulating layer 211 may refer to a first uppermost insulating layer disposed most adjacent to the second substrate layer 300 among the first insulating layers. Also, the first to third insulating layers 213 may refer to a first lowermost insulating layer farthest from the second substrate layer 300 among the first insulating layers. In addition, the first and second insulating layers 212 may refer to a first inner insulating layer disposed between the first uppermost insulating layer and the first lowermost insulating layer. Also, when the first substrate layer 200 has an insulating layer structure of 4 or more layers, the first inner insulating layer may be composed of a plurality of layers.

The first insulating layer may include a prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass yarn, with an epoxy resin, and then performing thermal compression. However, the embodiment is not limited thereto, and the prepreg constituting the first insulating layer may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

The first insulating layer may include a resin and reinforcing fibers disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to an epoxy resin, and for example, one or more epoxy groups may be included in the molecule, two or more epoxy groups may be included, and, alternatively, four or more epoxy groups may be included. In addition, the resin of the first insulating layer may include a naphthalene group, and may be, for example, an aromatic amine type, but is not limited thereto. For example, the resin is bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy Resins, dicyclopentadiene type epoxy resins, naphthalene type epoxy resins, naphthol type epoxy resins, epoxy resins of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, biphenyl aralkyl type epoxy resins, fluorene type epoxies resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, and phosphorous-type epoxy resins; naphthalene-type epoxy resins, bisphenol A-type epoxy resins, and phenol novolac epoxy resins; , cresol novolak epoxy resins, rubber-modified epoxy resins, and phosphorus-based epoxy resins. In addition, the reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (eg, aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. can The reinforcing fibers may be arranged to cross each other in a planar direction within the resin.

Meanwhile, glass fibers, carbon fibers, aramid fibers (eg, aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials may be used.

However, the embodiment is not limited thereto, and the first insulating layer may be made of an insulating material other than the prepreg.

Alternatively, at least one of the plurality of insulating layers constituting the first insulating layer may include a prepreg, and another insulating layer may include an insulating material other than the prepreg.

For example, at least one of the plurality of insulating layers of the first insulating layer may be rigid or flexible. For example, at least one of the plurality of insulating layers of the first insulating layer may include glass or plastic. In detail, at least one of the first insulating layers includes chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or polyimide (PI) or polyethylene terephthalate , PET), propylene glycol (PPG), reinforced or soft plastics such as polycarbonate (PC), or sapphire. For example, at least one of the plurality of insulating layers of the first insulating layer may include an optical isotropic film. For example, at least one of the plurality of insulating layers of the first insulating layer is COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), light isotropic polycarbonate (polycarbonate, PC) or light isotropic polymethyl methacrylate (PMMA). ) and the like. For example, at least one of the plurality of insulating layers of the first insulating layer may be formed of a material including an inorganic filler and an insulating resin. For example, at least one of the plurality of insulating layers of the first insulating layer is a resin including a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, and a reinforcing material such as an inorganic filler such as silica or alumina, specifically ABF ( Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric Resin), BT, and the like may be used. For example, at least one of the plurality of insulating layers of the first insulating layer may be made of resin coated copper (RCC).

At least one of the plurality of insulating layers constituting the first insulating layer may have a thickness different from that of at least one other insulating layer. For example, in the embodiment, the 1-1st insulating layer 211 disposed most adjacent to the cavity C described below includes the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 may have a different thickness.

For example, the thickness T4 of the 1-1st insulating layer 211 may be greater than the respective thicknesses T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 .

For example, each thickness T5 of the first-second insulating layer 212 and the first-third insulating layer 213 may satisfy a range of 10 μm to 60 μm. For example, each thickness T5 of the first-second insulating layer 212 and the first-third insulating layer 213 may satisfy a range of 12 μm to 45 μm. For example, each thickness T5 of the first-second insulating layer 212 and the first-third insulating layer 213 may satisfy a range of 15 μm to 30 μm.

However, although the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 are illustrated as having the same thickness T5 in the drawing, it is not limited thereto. For example, the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 have different thicknesses while having a smaller thickness than the thickness T4 of the 1-1st insulating layer 211. can have

For example, the 1-2nd insulating layer 212 may be smaller than the thickness T4 of the 1-1st insulating layer 211 and may satisfy a range of 10 μm to 60 μm. In addition, the 1-3 insulating layer 213 is smaller than the thickness T4 of the 1-1 insulating layer 211 and is within the range of 10 μm to 60 μm described above, and the 1-2 insulating layer 213 It may have a thickness less than or greater than the thickness of layer 212 .

Each thickness T5 of the first-second insulating layer 212 and the first-third insulating layer 213 may mean a vertical distance between adjacent circuit layers. When the thickness T5 of each of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 is less than 10 μm, the distance between the adjacent different circuit layers correspondingly decreases, and accordingly It may be weak to noise due to mutual signal interference. When the thickness T5 of each of the first-second insulating layer 212 and the first-third insulating layer 213 exceeds 60 μm, the overall thickness of the circuit board may increase. In addition, when the thickness T5 of each of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 exceeds 60 μm, the thickness of the through electrode increases correspondingly, and the signal corresponding thereto As the transmission distance increases, signal transmission loss may increase.

Also, the thickness T4 of the 1-1st insulating layer 211 may be greater than the thickness T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213 . For example, the thickness T4 of the 1-1st insulating layer 211 is 110% to 220% of the thickness T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213. % can be satisfied. For example, the thickness T4 of the 1-1st insulating layer 211 is 120% to 210% of the thickness T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213. % can be satisfied. For example, the thickness T4 of the 1-1st insulating layer 211 is 130% to 200% of the thickness T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213. % can be satisfied.

The thickness T4 of the 1-1st insulating layer 211 may mean the thickness between adjacent circuit pattern layers. When the thickness T4 of the 1-1st insulating layer 211 is less than 110% of the thickness T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213, the first -1 The adhesion between the insulating layer 211 and the second substrate layer 300 is reduced, and accordingly, the film removal problem in which the 1-1 insulating layer 211 is separated from the second substrate layer 300 can happen In addition, when the thickness T4 of the 1-1st insulating layer 211 exceeds 220% of the thickness T5 of the 1-2nd insulating layer 212 and the 1-3rd insulating layer 213, The overall thickness of the circuit board may increase due to the thickness T4 of the 1-1 insulating layer 211, and the signal transmission distance between the first substrate layer 200 and the second substrate layer 300 may increase. can do.

For example, the thickness T4 of the 1-1st insulating layer 211 may satisfy a range of 11 μm to 132 μm. For example, the thickness T4 of the 1-1st insulating layer 211 may satisfy a range of 14.5 μm to 94.5 μm. For example, the thickness T4 of the 1-1st insulating layer 211 may satisfy a range of 19.5 μm to 60 μm.

At this time, in the first embodiment, the cavity (C) is not formed as described above, and the thickness (T4) of the 1-1st insulating layer 211 disposed most adjacent to the cavity (C) is different from this. It is greater than the thickness T5 of the first insulating layers or the thickness of the second insulating layers.

Preferably, in the embodiment, the thickness of the insulating layer may be changed based on the position of the first pattern layer 221 described below. That is, the first pattern layer 221 includes a pattern used as a stopper in the process of forming the cavity (C). And, in the embodiment, the thickness of the insulating layer in contact with the first pattern layer 221 including the pattern used as the stopper is increased. At this time, the insulating layer in contact with the first pattern layer 221 is the 1-1st insulating layer 211 disposed on the uppermost side of the first substrate layer 200 and the second substrate layer 300. It includes the 2-1st insulating layer 311 disposed on the lowermost side. At this time, in the embodiment, while maintaining the thickness of the 2-1 insulating layer 311 at the existing thickness, only the thickness of the 1-1 insulating layer 211 is increased, so that the 1-1 insulating layer 211 and the first pattern layer 221, and the 1-1 insulating layer 211 improves the adhesive force between the 2-1 insulating layer 311.

At this time, the reason for increasing the thickness of only the 1-1 insulating layer 211 among the 1-1 insulating layer 211 and the 2-1 insulating layer 311 in contact with the first pattern layer 221 is , It may be according to the process sequence of manufacturing the circuit board of the first embodiment of the present application.

For example, one of the 1-1 insulating layer 211 and the 2-1 insulating layer 311 is laminated before the first pattern layer 221 is formed, and the other is the first insulating layer 221 . After the first pattern layer 221 is formed, it is laminated. Preferably, the 2-1 insulating layer 311 is an insulating layer laminated before the first pattern layer 221 is formed, and the 1-1 insulating layer 211 is the first pattern layer ( 221) is formed, it is laminated on the 2-1 insulating layer 311 and the first pattern layer 221. Accordingly, in the embodiment, the thickness T4 of the 1-1st insulating layer 211, which is laminated after the first pattern layer 221 is formed, is set to include the 2-1st insulating layer 311. It is made larger than the thickness T5 of the other insulating layers. Through this, in the embodiment, as the surface area (surface area before etching in the cavity region) of the first pattern layer 221 including the stopper exceeds 60%, the 1-1 insulating layer 211 ) and the first pattern layer 221 and/or the 2-1st insulating layer 311, it is possible to solve the decrease in adhesion, and through this, the physical reliability of the circuit board can be improved.

The first substrate layer 200 of the embodiment may include a first circuit layer. For example, the first substrate layer 200 may include first circuit layers respectively disposed on a plurality of insulating layers of the first insulating layer.

For example, the first substrate layer 200 may include a first pattern layer 221 disposed on an upper surface of the 1-1st insulating layer 211 . For example, the first substrate layer 200 includes a second pattern layer 222 disposed between the lower surface of the 1-1 insulating layer 211 and the upper surface of the 1-2 insulating layer 212. can include For example, the first substrate layer 200 includes a third pattern layer 223 disposed between the lower surface of the first-second insulating layer 212 and the upper surface of the first-third insulating layer 213. can include For example, the first substrate layer 200 may include a fourth pattern layer 224 disposed on a lower surface of the first to third insulating layers 213 .

The first pattern layer 221 may be disposed within the 1-1st insulating layer 211 . For example, at least a portion of a side surface of the first pattern layer 221 may be covered with the 1-1 insulating layer 211 . Preferably, the first pattern layer 221 may have a buried structure in which an upper surface is exposed and at least a portion of a side surface and a lower surface are covered with the 1-1 insulating layer 211 . That is, the 1-1st insulating layer 211 is laminated after the first pattern layer 221 is disposed on the 2-1st insulating layer 311, and thus the first pattern layer 221 is formed. 221 may have a structure buried in the 1-1st insulating layer 211 .

The first pattern layer 221 may refer to a circuit layer disposed on an uppermost side among circuit layers of the first substrate layer. The first pattern layer 221 may have different heights depending on positions. For example, the first pattern layer 221 includes a plurality of pattern parts, and the height of at least one top surface of the plurality of pattern parts may be different from that of at least one other top surface. For example, the upper surface of at least one of the plurality of pattern portions of the first pattern layer 221 may have a step with the upper surface of at least one other. In addition, the lower surface of at least one of the plurality of pattern portions of the first pattern layer 221 may have a height or step different from that of at least one other lower surface. In addition, the thickness of at least one of the plurality of pattern portions of the first pattern layer 221 may be different from the thickness of at least another one.

For example, the first substrate layer 200 may be divided into a plurality of regions in a width direction or a length direction. The first substrate layer 200 may include a first region RB1 vertically overlapping the cavity C and a second region RB2 other than the first region RB1. In this case, the cavity C may include a region whose width changes in the thickness direction. Also, the first region RB1 may refer to a region vertically overlapped with a region having the largest width among all regions of the cavity C. However, the embodiment is not limited thereto, and the first region RB1 may refer to a region vertically overlapped with a region having the smallest width among the entire regions of the cavity C. Alternatively, the cavity ( It may also mean a region vertically overlapped with one region between the upper region and the lower region of C).

The first pattern layer 221 includes a plurality of pattern parts. For example, the first pattern layer 221 includes the first pattern portion 221-1 disposed on the upper surface of the first region RB1 of the 1-1st insulating layer 211, and the first-first pattern portion 221-1. 1 may include a second pattern portion 221 - 2 disposed on the upper surface of the second region RB2 of the insulating layer 211 . Also, the first substrate layer 200 includes a boundary region between the first region RB1 and the second region RB2. The boundary area may overlap at least a portion of the first area RB1 and/or the second area RB2. The boundary region may refer to a region vertically overlapping at least a portion of an inner wall of the cavity C. Also, the first pattern layer 221 may include a third pattern portion 221-3 disposed in the boundary area.

At this time, the thickness of at least one of the first to third pattern portions 221-1, 221-2, and 221-3 of the first pattern layer 221 may be different from the thickness of at least another one. In addition, the top surface of at least one of the first to third pattern portions 221-1, 221-2, and 221-3 of the first pattern layer 221 may be positioned on a different plane from the top surface of at least another one. there is. In addition, the lower surface of at least one of the first to third pattern portions 221-1, 221-2, and 221-3 of the first pattern layer 221 may be positioned on a different plane from the lower surface of at least one other surface. there is.

Preferably, the upper surface of the first pattern part 221-1 may be located lower than the upper surface of the second pattern part 221-2 and the upper surface of the third pattern part 221-3. Also, the first pattern part 221-1 functions as a mounting pad on which a chip is mounted. At this time, in the embodiment, the first pattern part 221-1 is located lower than the second pattern part 221-2 and the third pattern part 221-3, so that the cavity C is formed. In the laser process, it is possible to prevent the first pattern part 221-1 from being damaged, thereby improving the mounting reliability of the chip.

The thickness of each of the first pattern portion 221-1, the second pattern portion 221-2, and the third pattern portion 221-3 and the positional relationship between the upper and lower surfaces of each will be described in detail below. do it with

Meanwhile, the first circuit layer including the first pattern layer 221, the second pattern layer 222, the third pattern layer 223, and the fourth pattern layer 224 is made of gold (Au) or silver (Ag). ), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit layers are at least one selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. It may be formed of a paste containing a metal material or a solder paste. Preferably, the first circuit layer may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

Each of the first circuit layers may have a thickness ranging from 5 μm to 50 μm. For example, each of the first circuit layers may have a thickness ranging from 10 μm to 40 μm. For example, the first circuit layer may have a thickness ranging from 15 μm to 30 μm. When the thickness of the first circuit layer is less than 5 μm, resistance of the circuit layer may increase, and thus signal transmission loss may increase. If the thickness of the first circuit layer is less than 5 μm, problems may occur in communication performance, such as a decrease in allowable current of a signal that can be transmitted through the first circuit layer, and thus a decrease in signal transmission speed. In addition, when the thickness of the first circuit layer exceeds 50 μm, the line width of each pattern part of the first circuit layer increases accordingly, and thus miniaturization of the pattern part may be difficult. In addition, when the thickness of the first circuit layer exceeds 50 μm, the thickness of the circuit board may correspondingly increase.

On the other hand, the first circuit layer is formed by additive process, subtractive process, MSAP (Modified Semi Additive Process), SAP (Semi Additive Process), etc., which are typical circuit board manufacturing processes. It is possible, and a detailed description is omitted here.

Meanwhile, the first substrate layer 200 includes a through portion. For example, the through portion may be formed through each insulating layer of the first substrate layer 200 .

For example, the through part may include a first through electrode 231 penetrating the 1-1st insulating layer 211 . For example, the through portion penetrates the 1-1 insulating layer 211 and electrically connects the first through electrode 231 between the first pattern layer 221 and the second pattern layer 222. can include

In addition, the through portion may include a second through electrode 232 penetrating the first and second insulating layers 212 . For example, the through portion penetrates the first and second insulating layers 212 and connects the second through electrode 232 between the second pattern layer 222 and the third pattern layer 223. can include

The through portion may include a third through electrode 233 passing through the first to third insulating layers 213 . For example, the through portion penetrates through the first to third insulating layers 213 and electrically connects the third through electrode 233 between the third pattern layer 223 and the fourth pattern layer 224. can include

The through-portion as described above may be formed by filling the inside of the through-hole penetrating each insulating layer of the first insulating layer with a conductive material. The through hole may be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by machining, methods such as milling, drilling, and routing may be used, and when the through hole is formed by laser processing, a UV or CO ₂ laser method may be used. In the case of forming by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened using a chemical containing aminosilane, ketones, or the like.

On the other hand, the laser processing is a cutting method that melts and evaporates a part of the material by concentrating optical energy on the surface to take a desired shape, and can easily process complex formations by computer programs, and other methods Even difficult composite materials can be machined.

In addition, the processing by the laser can cut a diameter of up to a minimum of 0.005 mm, and has the advantage of a wide range of processable thickness.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser capable of processing both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser capable of processing only the insulating layer.

When the through hole is formed, each through electrode may be formed by filling the inside of the through hole with a conductive material. The metal material forming the through electrode may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The filling of the conductive material may use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

The second substrate layer 300 may include a plurality of second insulating layers. For example, the second substrate layer 300 includes a 2-1 insulating layer 311, a 2-2 insulating layer 312, a 2-3 insulating layer 313, and a 2-4 insulating layer ( 314) may be included.

For example, the second substrate layer 300 may include four insulating layers. However, the embodiment is not limited thereto, and the second insulating layer constituting the second substrate layer 300 may include three or less insulating layers, and may include five or more insulating layers.

The 2-1 insulating layer 311 may be disposed on the first substrate layer 200 . For example, the 2-1 insulating layer 311 may be disposed on the upper surface of the 1-1 insulating layer 211 disposed on the uppermost side of the first substrate layer 200 .

The 2-2 insulating layer 312 may be disposed on the 2-1 insulating layer 311 . In addition, the 2-3 insulating layer 313 may be disposed on the 2-2 insulating layer 312 . In addition, the 2-4th insulating layer 314 may be disposed on the 2-3rd insulating layer 313 .

The second insulating layer of the four layers constituting the second substrate layer 300 may include the same insulating material as the first insulating layer constituting the first substrate layer 200, but is not limited thereto.

Meanwhile, each of the second insulating layers of the four layers constituting the second substrate layer 300 includes the first-second insulating layer 212 and the first-third insulating layer 213 of the first substrate layer 200 . ) may have the same thickness T6 as the thickness T5.

Specifically, the 2-1st insulating layer 311 may have a different thickness T6 from that of the 1-1st insulating layer 211 although it is in contact with the first pattern layer 221 .

However, embodiments are not limited thereto. For example, among the four second insulating layers, the 2-2 insulating layer 312, the 2-3 insulating layer 313, and the 2-4 insulating layer 314 are the first-2 insulating layers 314. It may have the same thickness T6 as the thickness T5 of the insulating layer 212 and the first to third insulating layers 213 . Also, the 2-1 insulating layer 311 may have the same thickness T6 as the thickness T4 of the 1-1 insulating layer 211 .

In addition, the thickness (T6) of at least one of the 2-1st insulating layer 311, the 2-2nd insulating layer 312, the 2-3rd insulating layer 313, and the 2-4th insulating layer 314 Is smaller than the thickness of the 1-1st insulating layer 211 and different from the thickness of the 1-2nd insulating layer 212 or the 1-3rd insulating layer 213 (eg, large thickness or may have a small thickness).

In conclusion, in the embodiment, based on the position of the first pattern layer 221, the thickness T4 of the 1-1st insulating layer 211 stacked after the first pattern layer 221 is formed It is larger than at least one of the other first insulating layer or the second insulating layer. Through this, in the embodiment, it is possible to fundamentally solve the problem of adhesion according to the area of the first pattern layer 221 used as the stopper layer for forming the cavity.

The second substrate layer 300 may include a second circuit layer.

For example, the second circuit layer may include a fifth pattern layer 321 disposed on the upper surface of the 2-1 insulating layer 311 . For example, the second circuit layer may include a sixth pattern layer 322 disposed on the top surface of the 2-2 insulating layer 312 . For example, the second circuit layer may include a seventh pattern layer 323 disposed on the upper surface of the second-third insulating layer 313 . For example, the second circuit layer may include an eighth pattern layer 324 disposed on the upper surface of the second-fourth insulating layer 314 .

In this case, the second circuit layer constituting the second substrate layer 300 may be a conductive antenna pattern layer that functions as an antenna. For example, the fifth pattern layer 321 , the sixth pattern layer 322 , the seventh pattern layer 323 , and the eighth pattern layer 324 are the first circuit layers of the first substrate layer 200 . Is connected to, and thus may be an antenna unit that functions as an antenna for transmitting a transmission signal to the outside or receiving a signal transmitted from the outside.

The second substrate layer 300 may include a second through portion. For example, the second substrate layer 300 may include a plurality of penetration electrodes respectively penetrating the second insulating layer.

For example, the second through-portion may include a fourth through-electrode 331 passing through the 2-1 insulating layer 311 . The fourth through electrode 331 may electrically connect the first pattern layer 221 of the first substrate layer 200 and the fifth pattern layer 321 . For example, the second through-portion may include a fifth through-electrode 332 penetrating the 2-2 insulating layer 312 . The fifth through electrode 332 may electrically connect the fifth pattern layer 321 and the sixth pattern layer 322 to each other. For example, the second through-portion may include a sixth through-electrode 333 penetrating the second-third insulating layer 313 . The sixth through electrode 333 may electrically connect the sixth pattern layer 322 and the seventh pattern layer 323 . For example, the second through-portion may include a seventh through-electrode 334 passing through the second-fourth insulating layer 314 . The seventh through electrode 334 may electrically connect the seventh pattern layer 323 and the eighth pattern layer 334 to each other.

Meanwhile, the second substrate layer 300 includes a cavity (C).

Accordingly, the second substrate layer 300 may be applied to the region where the cavity C is formed, for example, the third region RT1 vertically overlapping the cavity C and other than the third region RT1. A fourth region RT2 may be included.

The third region RT1 may be a region vertically overlapping the first region RB1 of the first substrate layer 200. The fourth region RT2 may be a region of the first substrate layer 200. It may be an area vertically overlapping the second area RB2.

Also, a cavity C of a mounting space in which chips such as driving elements or passive elements are mounted in the package substrate may be formed in the third region RT1 of the second substrate layer 300 . A second circuit layer, which is an antenna pattern functioning as an antenna, may be formed in the fourth region RT2 of the second substrate layer 300 .

In this case, when the circuit board 100 of the present application is an antenna board applied to an antenna device, the circuit layers disposed on each layer of the circuit board may have different functions.

For example, each of the first pattern layer 221, the second pattern layer 222, the third pattern layer 223, and the fourth pattern layer 224 of the first circuit layer of the first substrate layer 200 may include a first circuit portion that vertically overlaps the first region RB1 and may vertically overlap the cavity C. The first circuit portion may include a driving element or It may function as a mounting pad on which a chip such as a passive element is mounted, or a terminal pad connecting between the circuit board of the embodiment and an external board (eg, the main board of the terminal).

In addition, each of the first pattern layer 221, the second pattern layer 222, the third pattern layer 223, and the fourth pattern layer 224 of the first circuit layer is perpendicular to the second region RB2. It may include a second circuit portion overlapping with. Also, the second circuit part may vertically overlap the second circuit layers formed in the fourth region RT2 of the second substrate layer 300 .

At this time, in one embodiment, the second circuit parts of the first circuit layer may function as terminal pads together with the first circuit part. Further, when the second circuit unit functions as a terminal pad together with the first circuit unit, the circuit board of the embodiment may function as an antenna only in the fourth region RT2 of the second substrate layer 300 . For example, when the second circuit part of the first circuit layer is not an antenna pattern layer functioning as an antenna, the circuit board of the embodiment transmits a signal to the upper side of the fourth region RT2 of the second substrate layer 300. may be transmitted, or a signal transmitted from the upper side of the fourth region (RT2) may be received.

Further, in another embodiment, the second circuit unit is connected to the second circuit layers disposed in the fourth region RT2 of the second substrate layer 300, and thus the antenna pattern functions to transmit or receive signals. can function as

For example, the second circuit layer in the fourth region RT2 of the second substrate layer 300 may be referred to as a first antenna pattern layer, and among the first circuit layers of the first substrate layer 200 The second circuit unit disposed in an area vertically overlapping the second area RB2 may be a second antenna pattern layer connected to the first antenna pattern layer.

In this case, in the embodiment, signals may be transmitted in both directions of the circuit board or signals transmitted in both directions of the circuit board may be received. For example, in the embodiment, signals may be transmitted to the upper side of the first antenna pattern layer and signals may be transmitted to the lower side of the second antenna pattern layer. In addition, in the embodiment, a signal transmitted from the upper side of the first antenna pattern layer may be received, and a signal transmitted from the lower side of the second antenna pattern layer may be received.

On the other hand, in the embodiment, although the first circuit parts vertically overlapping the first region RB1 among the first circuit layers of the first substrate layer 200 function as mounting pads or terminal pads, it is limited thereto. It is not. For example, some of the first circuit units disposed in the first region RB1 of the first substrate layer 200 may function as mounting pads or terminal pads, and the remaining parts may function together with the second antenna pattern layer. It could also function as an antenna pattern.

Hereinafter, the thickness and positional relationship of each pattern part of the cavity C and the first pattern layer 221 according to the embodiment will be described in detail.

Referring to FIG. 3 , the cavity C in the embodiment passes through the second substrate layer 300 . For example, the cavity C passes through the second insulating layer. When the second insulating layer has a multi-layer structure, the cavity C may pass through the second insulating layers of the plurality of layers in common.

The cavity C may include a plurality of parts. For example, the cavity (C) may be divided into a plurality of parts in the thickness direction based on the inclination of the inner wall (IW) of the cavity (C).

For example, the cavity C may include the first part P1 adjacent to the upper surface of the second substrate layer 300 . In addition, the cavity (C) may be adjacent to the lower surface of the second substrate layer 300 and include a second part (P2) under the first part (P1).

In this case, the first part P1 may include a region whose width decreases toward the lower surface of the second substrate layer 300 . For example, the inner wall IW1 of the first part P1 may have a first slope, the width of which decreases toward the first substrate layer 200 . The first inclination of the inner wall IW of the first part P1 may mean an inner angle between a virtual straight line connected to the inner wall IW and the reference line BL. The reference line BL may be parallel to the top surface of the first substrate layer 200 vertically overlapping the cavity C.

Meanwhile, the first inclination θ1 of the inner wall IW1 of the first part P1 may have a range of 115 degrees to 150 degrees. For example, the first slope θ1 of the inner wall IW1 of the first part P1 may have a range of 118 degrees to 148 degrees. For example, the first slope θ1 of the inner wall IW1 of the first part P1 may have a range of 120 degrees to 145 degrees.

When the first inclination θ1 of the inner wall IW1 of the first part P1 is smaller than 115 degrees, the process time required to form the cavity C according to the embodiment may increase. For example, if the first inclination θ1 of the inner wall IW1 of the first part P1 is less than 115 degrees, the width of the laser beam used in the process of forming the primary cavity described below (e.g. For example, this means that the laser mask) is small, and accordingly, the time required for forming the cavity C may increase.

In addition, when the first slope θ1 of the inner wall IW1 of the first part P1 is greater than 150, the degree of integration of circuits may decrease as the width of the upper portion of the cavity C increases. For example, the lower width of the cavity C is determined to correspond to the arrangement space of the device to be mounted, and the cavity forming process is performed based on the determined lower width. In this case, when the width of the upper part of the cavity C increases, it means that the space that is senselessly wasted increases, and accordingly, the space for placing the circuit layer may decrease as much as the width of the upper part of the cavity C increases. . Accordingly, in the embodiment, the first inclination θ1 of the inner wall IW1 of the first part P1 has a range of 115 degrees to 150 degrees.

On the other hand, the cavity (C) of the embodiment includes a second part (P2) below the first part (P1). The second part P2 may include a region whose width decreases toward the lower surface of the second substrate layer 300 . For example, while the width of the second part P2 decreases toward the first substrate layer 200, the first inclination θ1 of the inner wall IW1 of the first part P1 is different from that of the first slope θ1. An inner wall IW2 having a second slope θ2 may be included. For example, the second slope θ2 of the second part P2 may be smaller than the first slope θ1 of the first part P1.

In this case, the second inclination θ2 may mean an inclination of the inner wall IW2 of the second part P2. For example, the second slope θ2 may refer to an interior angle between an imaginary straight line extending from the inner wall IW2 of the second part P2 and the reference line BL.

The second inclination θ2 of the inner wall IW2 of the second part P2 may be smaller than the first inclination θ1 and may have a range of 91 degrees to 120 degrees. For example, the second inclination θ2 of the inner wall IW2 of the second part P2 may be smaller than the first inclination θ1 and may have a range of 95 degrees to 118 degrees. For example, the second inclination θ2 of the inner wall IW2 of the second part P2 may be smaller than the first inclination θ1 and may have a range of 98 degrees to 115 degrees.

When the second inclination θ2 of the inner wall IW2 of the second part P2 is less than 91 degrees, a chip such as a driving element or a passive element may not be stably disposed in the cavity C. Specifically, when the second inclination θ2 of the inner wall IW2 of the second part P2 is smaller than 91 degrees, the width of the second part P2 toward the upper surface of the second substrate layer 300 It may have a decreasing shape, and a sufficient chip placement space may not be provided in the middle region of the cavity C. And, accordingly, the inner wall of the cavity (C) and the chip may come into contact in the middle region of the cavity (C), which causes the mounting position of the chip to be distorted or the chip to be tilted in the mounting process of the chip. Mounting problems may arise.

In addition, when the second inclination θ2 of the inner wall IW2 of the second part P2 is greater than 120 degrees, the cavity C may be formed having a size larger than that required for the device mounting space. there is. Accordingly, when the second inclination θ2 of the inner wall IW2 of the second part P2 is greater than 120 degrees, the difference between the width of the lower region and the upper region of the second part P2 is large. means that Also, the width of the general cavity determines the width of the lower region of the second part P2 corresponding to the size of the chip. When the second inclination θ2 of the inner wall IW2 of the second part P2 is greater than 120 degrees, the space or area occupied by the cavity C may increase compared to the size of the chip. There may be a problem in that , or the width in the horizontal direction or the thickness in the vertical direction of the circuit board increases.

Meanwhile, the lengths of the first part P1 and the second part P2 of the cavity C may be different from each other. For example, the first part P1 of the cavity C has a first length L1, and the second part P2 has a second length L2 longer than the first length L1. can have In this case, the first length L1 may mean the depth of the first part P1 in the vertical direction. For example, the first length L1 may mean a vertical distance of the first part P1. Also, the second length L2 may mean the depth of the second part P2. For example, the second length L2 may mean a depth or a vertical distance of the second part P2 in a vertical direction.

In this case, the second length L2 may be 1.5 times or more than the first length L1. For example, the second length L2 may be three times or more than the first length L1. For example, the second length L2 may be five times or more than the first length L1. For example, the second length L2 may be 10 times or more than the first length L1.

For example, the second length L2 may satisfy a range between 1.5 and 30 times the first length L1. For example, the second length L2 may satisfy a range between 3 times and 28 times the first length L1. For example, the second length L2 may satisfy a range between 5 and 25 times the first length L1. For example, the second length L2 may satisfy a range between 10 and 20 times the first length L1.

At this time, when the second length L2 is less than 1.5 times the first length L1, according to the difference between the first slope of the first part P1 and the second slope of the second part P2. The resulting effect may be insignificant. In addition, when the second length L2 is 30 times or more than the first length L1, the thickness of the second substrate layer 300 to satisfy this increase increases, and thus the overall thickness of the circuit board increases. can

Meanwhile, the cavity (C) of the embodiment may include a third part (P3) under the second part (P2). The third part P3 may be located lower than the second substrate layer 300 . The third part P3 of the cavity C may refer to a structure formed on the first substrate layer 200 instead of a structure formed on the second substrate layer 300 . For example, the third part P3 of the cavity C may overlap at least a portion of the first pattern layer 221 of the first substrate layer 200 in a horizontal direction. That is, the third part P3 may be formed by removing at least one pattern portion of the first pattern layer 221 by etching.

Specifically, the third part P3 is a laser stopper layer (eg, a laser stopper layer formed in a region vertically overlapping the cavity C) of the first pattern layer 221 of the first substrate layer 200. It may be a part formed by removing a part of the third pattern portion 221 - 3 of the first pattern layer 221 .

For example, the total depth of the cavity C may be greater than the total thickness of the second insulating layer constituting the second substrate layer 300 . For example, the depth of the cavity C in the first embodiment may be as large as the sum of the thickness of the third pattern portion 221-3 in the total thickness of the second insulating layer.

Accordingly, the bottom surface of the cavity C may be positioned lower than the bottom surface of the second substrate layer 300 .

The third part P3 may have a third slope. The third inclination may refer to an inclination of the inner wall IW3 of the third part P3. In this case, the inner wall IW1 of the first part P1 and the inner wall IW2 of the second part P2 mean inner walls of the second insulating layer constituting the second substrate layer 300 . Unlike this, the inner wall IW3 of the third part P3 in the first embodiment may refer to an inclination of a side surface of the third pattern portion 221 - 3 of the first pattern layer 221 .

Specifically, the first pattern layer 221 of the first substrate layer 200 surrounds a boundary area between the first area RB1 and the second area RB2, and the third pattern portion ( 221-3). The third pattern part 221 - 3 may be a part of a stopper layer used as a laser stopper in a laser process for forming the cavity (C). A lower width of the cavity C may be smaller than a width of the stopper layer. If the cavity (C) having the same lower width as the width of the stopper layer is formed, the upper surface of the 1-1 insulating layer 211 adjacent to the edge of the stopper layer is formed due to process deviation in the laser process. A problem in which a part is processed with a laser may occur, resulting in a reliability problem. Accordingly, in the embodiment, the cavity (C) has a lower width smaller than the width of the stopper layer. Accordingly, the upper surface of a part of the stopper layer may be exposed through the cavity C, and the upper surface of the other part may not be exposed through the cavity C. In this case, the stopper layer, the upper surface of which is exposed through the cavity C, may be removed by etching to form the third part P3 of the cavity C. In addition, the stopper layer, the upper surface of which is not exposed through the cavity C, is not removed during the etching process, and thus the third pattern portion 221-3 of the first pattern layer 221 can be formed. there is. Also, the inner wall IW3 of the third part P3 of the cavity C may refer to an inclination angle of a side surface of the third pattern part 221 - 3 . A third inclination of the inner wall IW3 of the third part P3 may be determined by an etching condition of the stopper layer.

A third slope of the inner wall IW3 of the third part P3 may have a curved surface. For example, in the embodiment, etching is performed under an over-etching condition in the process of etching the stopper layer. Accordingly, in the embodiment, at least a portion of the stopper layer whose upper surface is not exposed through the cavity (C) is also removed. Accordingly, the third inclination of the inner wall IW3 of the third part P3 in the embodiment may have an inclination in which the width of the cavity C increases toward the second part P2. This will be described in more detail below.

Meanwhile, in the embodiment, the upper surface of the first substrate layer 200 may have a step. For example, the upper surface of the 1-1st insulating layer 211 may have a step. Specifically, the upper surface of the 1-1st insulating layer 211 may include a first upper surface 211T1 and a second upper surface 211T2 having a step difference with the first upper surface 211T1.

For example, the upper surface of the 1-1st insulating layer 211 includes a first upper surface 211T1 vertically overlapping the cavity C and a second upper surface 211T1 vertically overlapping the cavity C ( 211T2). That is, the first upper surface 211T1 of the 1-1st insulating layer 211 corresponds to the first region RB1 of the first substrate layer 200, and The second upper surface 211T2 may correspond to the second region RB2 of the first substrate layer 200 . In addition, the first upper surface 211T1 of the 1-1st insulating layer 211 constitutes the lower surface of the cavity C and may refer to a portion not in contact with the second substrate layer 300 . Also, the second upper surface 211T2 of the 1-1st insulating layer 211 may refer to a portion in contact with the second substrate layer 300 .

At this time, the first upper surface 211T1 has a first overlapping region vertically overlapping with the first pattern portion 221-1 and a first non-overlapping region that does not vertically overlap with the first pattern portion 221-1. area can be included. In addition, the second upper surface 211T2 includes a second overlapping area vertically overlapping the second pattern portion 221-2 and a third overlapping area perpendicularly overlapping the third pattern portion 221-3. , a second non-overlapping region that does not vertically overlap the second pattern portion 221-2 and the third pattern portion 221-3.

At this time, in the circuit board of Comparative Example, the first non-overlapping region of the first upper surface 211T1 of the 1-1st insulating layer 211 is positioned on the same plane as the second non-overlapping region of the second upper surface 211T2. do. Unlike this, the first non-overlapping region of the first upper surface 211T1 of the 1-1st insulating layer 211 in the embodiment may be located on a different plane from the second non-overlapping region of the second upper surface 211T2. can For example, the first non-overlapping region of the first upper surface 211T1 of the 1-1st insulating layer 211 may be located lower than the second non-overlapping region of the second upper surface 211T2 . For example, the first non-overlapping area in the first embodiment may be located lower than the second non-overlapping area by a thickness of the third pattern part 221-3. Hereinafter, the first upper surface 211T1 of the 1-1st insulating layer 211 means the first non-overlapping region, and the second upper surface 211T2 of the 1-1st insulating layer 211 means the first non-overlapping region. 2 will be described as meaning a non-overlapping area.

The first upper surface 211T1 of the 1-1st insulating layer 211 may be located higher than the lower surface of the second pattern portion 221 - 2 of the first pattern layer 221 . The first upper surface 211T1 of the 1-1st insulating layer 211 may be positioned on the same plane as the lower surface of the third pattern portion 221 - 3 of the first pattern layer 221 . At this time, being located on the same plane may mean that the height difference between them is 1 μm or less, or 0.5 μm or less, or 0.1 μm or less.

The second upper surface 211T2 of the 1-1st insulating layer 211 may be positioned higher than the upper surface of the first pattern portion 221 - 1 of the first pattern layer 221 . The second upper surface 211T2 of the 1-1st insulating layer 211 may be positioned on the same plane as the upper surface of the third pattern portion 221-3.

The first upper surface 211T1 and the second upper surface 211T2 of the 1-1st insulating layer 211 may have different surface roughness. For example, the first upper surface 211T1 of the 1-1st insulating layer 211 may have a surface roughness corresponding to the surface roughness of the lower surface of the first pattern layer 221 formed through a plating process. Alternatively, the second upper surface 211T2 of the 1-1st insulating layer 211 may have a surface roughness corresponding to that of the lower surface of the 2-1st insulating layer 311 .

The first pattern portion 221-1 of the first pattern layer 221 according to the first embodiment is disposed in a first region RB1 vertically overlapping the cavity C. In addition, the second pattern portion 221 - 2 of the first pattern layer 221 is disposed in a second area RB2 that does not vertically overlap the cavity C. Also, the third pattern portion 221 - 3 of the first pattern layer 221 is disposed in a boundary area between the first area RB1 and the second area RB2 .

Any one of the first pattern part 221-1, the second pattern part 221-2, and the third pattern part 221-3 may have a different thickness from the other one. An upper surface of any one of the first pattern part 221-1, the second pattern part 221-2, and the third pattern part 221-3 may be positioned on a different plane from the upper surface of the other one. For example, the lower surface of any one of the first pattern part 221-1, the second pattern part 221-2, and the third pattern part 221-3 may be located on a different plane than the lower surface of the other one. can

Hereinafter, with reference to the drawings, the respective thicknesses and Their positional relationship will be described.

4 is an enlarged view of a disposition area of the first pattern layer of the circuit board according to the first embodiment.

Referring to FIG. 4 , the first pattern layer 221 includes a first pattern portion 221-1, a second pattern portion 221-2, and a third pattern portion 221-3.

The first pattern part 221 - 1 is disposed in the first region RB1 of the 1-1st insulating layer 211 . That is, the first pattern part 221-1 may vertically overlap the cavity (C). The upper surface of the first pattern part 221-1 is formed by other pattern parts (eg, the second pattern part 221-2 and the third pattern part 221-3) of the first pattern layer 221. It may be located lower than the upper surface of. For example, the upper surface of the first pattern portion 221-1 may be positioned lower than the second upper surface 211T2 of the 1-1st insulating layer 211. For example, an upper surface of the first pattern portion 221-1 may be positioned lower than a lowermost side of the second substrate layer 300. The first pattern portion 221-1 may have a first thickness T1. Specific characteristics of the first thickness T1 will be described below.

The second pattern portion 221 - 2 may be disposed in the second region RB2 of the 1-1st insulating layer 211 . The second pattern part 221-2 may not vertically overlap the cavity C. A top surface of the second pattern portion 221-2 may be positioned higher than a top surface of the first pattern portion 221-1. An upper surface of the second pattern portion 221 - 2 may be positioned higher than the first upper surface 211T1 of the 1-1st insulating layer 211 . A top surface of the second pattern portion 221-2 may be positioned on the same plane as a top surface of the third pattern portion 221-3. An upper surface of the second pattern portion 221 - 2 may be positioned on the same plane as the second upper surface 211T2 of the 1-1 insulating layer 211 . A lower surface of the second pattern portion 221 - 2 may be positioned lower than a first upper surface 211T1 of the 1-1st insulating layer 211 . A lower surface of the second pattern portion 221-2 may be positioned lower than an upper surface of the first pattern portion 221-1. The lower surface of the second pattern part 221-2 may be positioned on the same plane as the lower surface of the first pattern part 221-1. A lower surface of the second pattern portion 221-2 may be positioned lower than a lower surface of the third pattern portion 221-3. The second pattern part 221-2 may have a multi-layer structure. For example, the second pattern portion 221-2 may have a two-layer structure formed through a two-step plating process. At this time, when the second pattern part 221-2 has a two-layer structure, when the second pattern part 221-2 is formed by the SAP or MSAP process, the copper foil layer and the chemical copper plating layer used as the seed layer It may mean that the electrolytic plating layer except for is composed of two layers. In this case, the second pattern portion 221-2 may have a second thickness T2 greater than the first thickness T1.

The third pattern portion 221 - 3 may be formed in a boundary area between the first area RB1 and the second area RB2 . Accordingly, a portion of the third pattern portion 221-3 may vertically overlap the cavity C, and may not vertically overlap otherwise. Preferably, at least a portion of the third pattern portion 221-3 may vertically overlap at least a portion of the inner wall IW of the cavity C.

A top surface of the third pattern portion 221-3 may be positioned higher than a top surface of the first pattern portion 221-1. An upper surface of the third pattern portion 221 - 3 may be located higher than the first upper surface 211T1 of the 1-1 insulating layer 211 . An upper surface of the third pattern portion 221-3 may be positioned on the same plane as an upper surface of the second pattern portion 221-2. An upper surface of the third pattern portion 221 - 3 may be positioned on the same plane as the second upper surface 211T2 of the 1-1 insulating layer 211 . The lower surface of the third pattern portion 221-3 may be positioned on the same plane as the upper surface of the 1-1 insulating layer 211 or the upper surface of the first pattern portion 221-1. A lower surface of the third pattern portion 221-3 may be positioned higher than a lower surface of the first pattern portion 221-1 and a lower surface of the second pattern portion 221-2. The third pattern portion 221-3 may have a third thickness T3 smaller than the second thickness T2 of the second pattern portion 221-2.

The first thickness T1 of the first pattern portion 221-1 may be determined based on the second thickness T2 of the second pattern portion 221-2.

That is, the second thickness T2 of the second pattern portion 221-2 is the pattern layer other than the first pattern portion 221-1 and the third pattern portion 221-3 in the circuit board of the embodiment. can correspond to the thickness they have.

For example, the second thickness T2 of the second pattern portion 221-2 may satisfy a range of 5 μm to 50 μm. For example, the second thickness T2 of the second pattern portion 221-2 may satisfy a range of 10 μm to 40 μm. For example, the second thickness T2 of the second pattern portion 221-2 may have a thickness ranging from 15 μm to 30 μm.

And, the sum (T1+T3) of the first thickness T1 of the first pattern portion 221-1 and the third thickness T3 of the third pattern portion 221-3 in the first embodiment is, It may correspond to the second thickness T2 of the second pattern portion 221-2.

That is, in the embodiment, the first pattern layer 221 includes a first metal layer and a second metal layer through a two-step plating process, and the first metal layer formed in the two-step plating process is the first pattern portion ( 221-1) and the third pattern portion 221-3, and the second metal layer is used for the second pattern portion 221-2 and the third pattern portion 221-3.

Accordingly, in the embodiment, the first pattern part 221-1 may include only the first metal layer, and the third pattern part 221-3 may include only the second metal layer. Also, the second pattern portion 221-2 may include both the first metal layer 221-21 and the second metal layer 221-22. Accordingly, the first metal layer 221-21 of the second pattern portion 221-2 may have a first thickness T1 corresponding to the first pattern portion 221-1, and the second The second metal layer 221 - 22 of the pattern portion 221 - 2 may have a third thickness T3 corresponding to the third pattern portion 221 - 3 .

As described above, in the embodiment, the first pattern layer 221 is divided into two layers and used as a mounting pad and a laser stopper layer, respectively. Accordingly, in the embodiment, the first pattern portion 221-1 corresponding to the mounting pad and the third pattern portion 221-3 corresponding to the stopper layer may be disposed on different planes. Through this, in the embodiment, it is possible to prevent the first pattern part 221-1, which is a mounting pad, from being damaged in the process of forming the cavity C.

The first thickness T1 of the first pattern portion 221-1 may satisfy 51% to 85% of the second thickness T2 of the second pattern portion 221-2. The first thickness T1 of the first pattern portion 221-1 may satisfy a range of 53% to 83% of the second thickness T2 of the second pattern portion 221-2. For example, the first thickness T1 of the first pattern portion 221-1 may satisfy a range of 55% to 80% of the second thickness T2 of the second pattern portion 221-2. there is.

When the first thickness T1 of the first pattern portion 221-1 is less than 51% of the second thickness T2 of the second pattern portion 221-2, the third pattern portion corresponds thereto. The third thickness T3 of (221-3) may increase. In addition, when the third thickness T3 of the third pattern portion 221-3 increases, after the formation of the cavity C is completed, the third pattern portion 221-3 is formed in a region vertically overlapping the cavity C. The time required to remove the 3-pattern portion 221-3 by etching increases, and accordingly, processability may deteriorate. In addition, when the third thickness T3 of the third pattern portion 221-3 increases, the third pattern portion 221-3 in a region vertically overlapping the cavity C in the etching process. A part of may not be removed, and through this, a reliability problem such as a short circuit due to electrical connection of the first pattern part 221-1 to the third pattern part 221-3 may occur. In addition, when the first thickness T1 of the first pattern portion 221-1 is less than 51% of the second thickness T2 of the second pattern portion 221-2, the first pattern portion ( The allowable current of 221-1) is reduced, and thus communication performance may be deteriorated. Meanwhile, when the first thickness T1 of the first pattern portion 221-1 exceeds 85% of the second thickness T2 of the second pattern portion 221-2, the third A third thickness T3 of the pattern portion 221-3 may decrease. Accordingly, in the laser process of forming the cavity (C), a problem may occur that the laser penetrates the third pattern portion 221-3, and accordingly, in the process of forming the cavity (C), the first -1 A problem of damage to the upper surface of the insulating layer 211 may occur. Preferably, the first thickness T1 of the first pattern portion 221-1 may satisfy a range of 2.7 μm to 42.5 μm. For example, the first thickness T1 of the first pattern portion 221-1 may satisfy a range of 5.1 μm to 33.2 μm. For example, the first thickness T1 of the first pattern portion 221-1 may satisfy a range of 7.65 μm to 25.5 μm.

The third thickness T3 of the third pattern portion 221-3 may satisfy 15% to 49% of the second thickness T2 of the second pattern portion 221-2. The third thickness T3 of the third pattern portion 221-3 may satisfy a range of 17% to 47% of the second thickness T2 of the second pattern portion 221-2. For example, the third thickness T3 of the third pattern portion 221-3 may satisfy a range of 20% to 45% of the second thickness T2 of the second pattern portion 221-2. there is.

When the third thickness T3 of the third pattern portion 221-3 is less than 15% of the second thickness T2 of the second pattern portion 221-2, the cavity C is formed. In the laser process, a laser may pass through the third pattern portion 221-3, and thus the upper surface of the 1-1 insulating layer 211 may be damaged in the process of forming the cavity C. problems can arise.

When the third thickness T3 of the third pattern portion 221-3 is greater than 49% of the second thickness T2 of the second pattern portion 221-2, it vertically overlaps the cavity C. The time required to remove the third pattern part 221 - 3 by etching in the area where it is formed increases, and thus processability may deteriorate. In addition, when the third thickness T3 of the third pattern portion 221-3 is greater than 49% of the second thickness T2 of the second pattern portion 221-2, the cavity ( A portion of the third pattern portion 221-3 in an area vertically overlapping C) may not be removed, and through this, the first pattern portion 221-1 may be formed by the third pattern portion 221-3. ) and reliability problems such as shorts may occur due to electrical connection. When the third thickness T3 of the third pattern portion 221-3 is greater than 49% of the second thickness T2 of the second pattern portion 221-2, the first pattern layer 221 In the first metal layer and the second metal layer, it may be difficult to perform etching as precise as the thickness corresponding to the second metal layer, and accordingly, as the second metal layer is partially etched in the etching process, the first pattern portion 221- As the thickness of 1) decreases, communication performance problems may occur.

Meanwhile, in the above description, the thickness T1 of the first pattern portion 221-1 is greater than the thickness T3 of the third pattern portion 221-3, but the thickness of the first pattern portion 221-1 The thickness and the thickness of the third pattern portion 221-3 may be the same. For example, the first metal layer 221 - 21 and the second metal layer 221 - 22 of the second pattern portion 221 - 2 may have the same thickness. However, the communication performance of the circuit board improves as the thickness of the first pattern part 221-1 increases, and accordingly, in the embodiment, the first pattern part ( 221-1a) increases the thickness. Through this, in the embodiment, the communication performance according to the increase in the thickness of the first pattern part 221-1 can be maximized while reducing the time required for the etching process of the third pattern part 221-3.

As described above, in the embodiment, in the process of forming the first pattern layer 221, it is subjected to two-step plating to have a two-layer structure including a first metal layer and a second metal layer, and the first metal layer and One of the second metal layers is used as a mounting pad and the other is used as a stopper, and both are used to configure the second pattern part. Through this, in the embodiment, a reliability problem caused by the arrangement of the mounting pad and the stopper on the same plane can be solved. For example, in the comparative example, a separate protective layer (not shown) is formed on the mounting pad to prevent damage to the mounting pad in a laser process for forming a cavity, and a process of removing the protective layer is performed later. On the other hand, in the embodiment, a part of the third pattern part 221-3 used as the laser stopper can be used as a protection part for the first pattern part 221-1 that is the mounting pad, thereby forming the cavity In the process of preventing the first pattern portion 221-1, which is the mounting pad, from being damaged, a process of forming an additional protective layer for protecting the first pattern portion 221-1 may be omitted.

Meanwhile, other pattern layers other than the first pattern layer 221 may have a second thickness T2 that the second pattern portion 221 - 2 of the first pattern layer 221 has.

Specifically, the second pattern layer 222, the third pattern layer 223, the fourth pattern layer 224, the fifth pattern layer 321, the sixth pattern layer 322, and the seventh pattern layer 323 ) and the eighth pattern layer 324 may have the same second thickness T2 as that of the second pattern portion 221 - 2 of the first pattern layer 221 .

However, the second pattern layer 222, the third pattern layer 223, the fourth pattern layer 224, the fifth pattern layer 321, the sixth pattern layer 322, and the seventh pattern layer 323 And the eighth pattern layer 324 may have a layer structure different from that of the second pattern portion 221 - 2 of the first pattern layer 221 . For example, the second pattern portion 221-2 of the first pattern layer 221 is formed to have the second thickness T2 through a two-step plating process in order to distinguish between a stopper and a mounting pad. . The second pattern layer 222, the third pattern layer 223, the fourth pattern layer 224, the fifth pattern layer 321, the sixth pattern layer 322, the seventh pattern layer 323, and the Unlike the second pattern portion 221-2 of the first pattern layer 221, the 8-pattern layer 324 does not require layer division, and thus can be formed through a single plating process. For example, the second pattern layer 222, the third pattern layer 223, the fourth pattern layer 224, the fifth pattern layer 321, the sixth pattern layer 322, and the seventh pattern layer ( 323) and the eighth pattern layer 324 may have a one-layer structure based on the electrolytic plating layer. However, the embodiment is not limited thereto, and the second pattern layer 222, the third pattern layer 223, the fourth pattern layer 224, the fifth pattern layer 321, and the sixth pattern layer 322 , The seventh pattern layer 323 and the eighth pattern layer 324 may also be formed by performing two-step plating like the second pattern portion 221-2 of the first pattern layer 221, and accordingly It may have a two-layer structure based on the electrolytic plating layer.

Meanwhile, one side surface of the third pattern part 221 - 3 adjacent to the cavity C overlaps the cavity C horizontally and is adjacent to the inner wall IW3 of the third part P3 of the cavity C. ) constitutes

In this case, the third pattern portion 221-3 may include a recess portion 221-3U that is depressed in an inward direction. After the formation of the cavity C is completed, in the process of removing a part of the third pattern portion 221-3 vertically overlapping the cavity C by etching, etching conditions are adjusted (e.g., For example, it can be achieved by over-etching conditions). For example, the side surface of the third pattern part 221-3 may be spaced apart from the lower end of the inner wall IW2 of the second part P2 of the cavity C in a horizontal direction away from the cavity C. there is. Through this, the width of the third part P3 of the cavity C may be greater than the width of the lower region of the second part P2 by an area corresponding to the recess 221 - 3U.

That is, the width of the third pattern portion 221-3 may change from the lower surface to the upper surface. For example, the width of the lower surface of the third pattern portion 221-3 may be greater than the width of the upper surface. In addition, the side surface of the third pattern portion 221-3 may have an inclination in which a width decreases from the lower surface toward the upper surface. And, the slope may be formed by the recessed portion 221-3U.

The horizontal distance of the recess 221-3U may range from 1 μm to 12 μm. The horizontal distance of the recess 221-3U may range from 2 μm to 10 μm. A horizontal distance of the recess 221 - 3U may range from 3 μm to 8 μm. Here, the horizontal distance may mean a horizontal distance from an inner wall of the cavity C adjacent to the recessed portion 221-3U to one side surface of the third pattern portion 221-3. In this case, the third pattern portion 221 - 3 may include a region whose width changes (eg, increases or decreases) from the lower surface to the upper surface according to etching conditions. And, the horizontal distance means any one of the maximum horizontal distance of the most depressed area, the minimum horizontal distance of the least depressed area, and the average distance of the horizontal distance of the entire area of the recess 221-3U. You will be able to.

The recess 221 - 3U may vertically overlap the 2-1 insulating layer 311 . For example, in the embodiment, at least a portion of the lower surface of the 2-1 insulation layer 311 may be exposed through the recessed portion 221-3U. Also, the recessed portion 221 - 3U as described above may be filled with a molding layer in a chip molding process. Accordingly, the molding layer may contact at least a portion of the lower surface of the 2-1 insulating layer 311 while filling the recess 221 - 3U. Through this, in the embodiment, adhesion between the molding layer and the circuit board may be further improved.

According to an embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a 1-1 insulating layer disposed most adjacent to the first substrate layer and a first pattern layer disposed on an upper surface of the 1-1 insulating layer. The second substrate layer includes a 2-1 insulating layer disposed on the first pattern layer. At this time, the first pattern layer includes a stopper layer for forming the cavity. Most of the stopper layer is removed after the cavity is formed, but is entirely disposed corresponding to the area where the cavity is to be formed during a circuit board manufacturing process before the cavity is formed. Accordingly, the surface area of the first pattern layer during the manufacturing process of the circuit board exceeds 50%, and further exceeds 60% of the surface areas of the 1-1st insulating layer and the 2-1st insulating layer, thereby Adhesion between the 1-1 insulating layer and the 2-1 insulating layer may decrease. Accordingly, in the embodiment, the thickness of the insulating layer in contact with the first pattern layer including the stopper layer is increased to improve adhesion with the insulating layer in contact with the first pattern layer including the stopper layer. Specifically, in the embodiment, the thickness of any one of the thicknesses of the 1-1st insulating layer and the 2-1st insulating layer is greater than the thickness of the other insulating layers. Through this, in the embodiment, adhesion between the first pattern layer, the 1-1 insulating layer, and the 2-1 insulating layer can be improved, and through this, physical reliability of the circuit board can be improved.

In this case, the first pattern layer includes a first pattern part disposed in a first area vertically overlapping the cavity, a second pattern part disposed in a second area not vertically overlapping the cavity, and and a third pattern portion formed in the boundary area between the first and second areas. At this time, the thickness of at least one of the first to third pattern parts in the embodiment is different from the thickness of at least another one. In addition, the upper or lower surface of at least one of the first to third pattern parts in the embodiment is located on a different plane from the upper or lower surface of at least another one. As described above, in the embodiment, the first pattern layer disposed in the region adjacent to the cavity has a structure in which different thicknesses or surfaces are disposed at different positions, thereby improving the cavity formation processability, and may occur during the cavity process. Reliability problems can be solved.

Specifically, in the embodiment, in the process of forming the first pattern layer, it has a two-layer structure including a first metal layer and a second metal layer through two-step plating, and among the first metal layer and the second metal layer One of them is used as a first pattern part, which is a mounting pad, and the other is used as a third pattern part, which is a laser stopper. Through this, in the embodiment, a reliability problem caused by the arrangement of the mounting pad and the stopper on the same plane can be solved. For example, in the comparative example, a separate protective layer (not shown) is formed on the mounting pad to prevent damage to the mounting pad in a laser process for forming a cavity, and a process of removing the protective layer is performed later. In contrast, in the embodiment, a part of the third pattern part used as the laser stopper can be used as a protection part for the first pattern part, which is the mounting pad, and thus, in the process of forming the cavity, the first pattern part, which is the mounting pad, is damaged. While preventing this from happening, a process of forming an additional protective layer for protecting the first pattern portion may be omitted.

In addition, the third pattern portion in the embodiment includes a recessed portion in an inward direction. Also, the recessed portion may be filled with a molding layer for molding a chip mounted in the cavity. Through this, in the embodiment, the bonding force between the circuit board and the molding layer may be improved by allowing the molding layer to fill the cavity and the depression of the third pattern part, and through this, the mounted chip may be stably can be made to be protected. Accordingly, in the embodiment, product reliability may be improved, and operation reliability of the chip may be improved.

The first substrate layer includes a first region vertically overlapping the cavity and a second region excluding the first region. Also, the second substrate layer includes a third region corresponding to the cavity and a fourth region excluding the third region. At this time, the third area of the second substrate layer in the embodiment is an area where the driving element is disposed, and the fourth area is an area where the antenna pattern layer is disposed. In the above embodiment, the driving element is disposed using the cavity of the second substrate layer, and the antenna pattern layer is disposed in the fourth region of the second substrate layer horizontally adjacent to the driving element. Accordingly, in the embodiment, it is possible to minimize the signal transmission distance between the antenna pattern layer and the driving element, thereby minimizing the signal transmission loss. For example, in the embodiment, the signal transmission distance can be reduced compared to connecting the substrate on which the driving element is disposed and the substrate on which the antenna pattern layer is disposed in the comparative example using a separate connection means, and thus a separate Signal transmission loss caused by the connection means can be reduced. In addition, in the embodiment, by having a structure in which the antenna pattern layer and the driving element are disposed in a horizontal direction, the second area of the first substrate layer vertically overlapping the fourth area of the second substrate layer is a second antenna pattern It can be used as a layer, and accordingly, in one circuit pattern, antenna pattern radiation and signal reception in different directions can be made possible.

In addition, in the embodiment, by disposing the driving element in the cavity of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavity.

In addition, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. At this time, with respect to the bottom surface of the cavity, the second inclination has a smaller inclination angle than the first inclination. Also, in the embodiment, the vertical length of the second part having the second slant is longer than the vertical length of the first part having the first slant. Accordingly, in the embodiment, compared to the comparative example, the space occupied by the cavity can be reduced, and thus the degree of integration of the circuit can be improved. For example, in the embodiment, as the space occupied by the cavity is reduced, the length of the antenna pattern layer can be increased in the substrate having the same size as the comparative example, and thus communication performance can be improved.

5 is a diagram illustrating a circuit board according to a second embodiment.

Referring to FIG. 5 , the circuit board 1100 includes a first substrate layer 1200 and a second substrate layer 1300 . The first substrate layer 1200 includes a first insulating layer including a 1-1 insulating layer 1211, a 1-2 insulating layer 1212, and a 1-3 insulating layer 1213. . In addition, the first substrate layer 1200 includes a first circuit layer including a first pattern layer 1221, a second pattern layer 1222, a third pattern layer 1223, and a fourth pattern layer 1224. do. Also, the first substrate layer 1200 may include a first through portion including a first through electrode 1231 , a second through electrode 1232 , and a third through electrode 233 .

The second substrate layer 1300 includes a 2-1 insulating layer 1311, a 2-2 insulating layer 1312, a 2-3 insulating layer 1313, and a 2-4 insulating layer 1314. It includes a second insulating layer to. In addition, the second substrate layer 1300 includes a second circuit layer including a fifth pattern layer 1321, a sixth pattern layer 1322, a seventh pattern layer 1323, and an eighth pattern layer 1324. do. In addition, the second substrate layer 1300 includes a second through portion including a fourth through electrode 1331, a fifth through electrode 1332, a sixth through electrode 1333, and a seventh through electrode 1334. can do.

In this case, the circuit board of the second embodiment has only a difference in the position of the first pattern layer 1221 compared to the circuit board of the first embodiment, and other structures other than this may be substantially the same.

In the first embodiment, the first pattern layer has a structure buried in the 1-1 insulating layer 211 of the first substrate layer 200 . Unlike this, the first pattern layer 1221 in the second embodiment has a structure buried in the 2-1 insulating layer 1311 of the second substrate layer 1300 .

In other words, the first pattern layer 1221 in the second embodiment has a structure protruding above the top surface of the 1-1 insulating layer 1211 .

Accordingly, in the structure of the second embodiment, the first pattern layer 1221 may have the same thickness for each region. For example, the first pattern layer 1221 in the first embodiment includes first to third pattern portions having different thicknesses for each region. Unlike this, although the second embodiment includes the first to third pattern parts, they may have the same thickness and be disposed on the same layer.

Meanwhile, the manufacturing process sequence in the first embodiment has an order in which the 1-1 insulating layer is stacked after the first pattern layer is formed.

Unlike this, in the manufacturing process in the second embodiment, after the first pattern layer 1221 is disposed on the 1-1 insulating layer 211, the lamination process of the 2-1 insulating layer 1311 this is going on Accordingly, in the second embodiment, the 1-1 insulating layer 211 has the same thickness T5 as other first insulating layers except for the 2-1 insulating layer 1311 .

Also, the 2-1st insulating layer 1311 may have a thickness T4 greater than the thickness T5 of other insulating layers including the 1-1st insulating layer 211 .

In addition, other second insulating layers other than the 2-1st insulating layer 1311 may have a thickness T6 smaller than the thickness T4 of the 2-1st insulating layer 1311 .

6 is a view showing a package substrate according to an embodiment.

Referring to FIG. 6 , the package substrate includes the circuit board 100 shown in FIG. 2 .

Also, the package substrate may include a first protective layer 340 disposed on the upper surface of the second substrate layer 300 of the circuit board 100 . In addition, the package substrate may include a second protective layer 240 disposed on the lower surface of the first substrate layer 200 of the circuit board 100 .

In addition, the package substrate includes a first pattern part 221 - 1 disposed in a region vertically overlapping the cavity C among the first pattern layers 221 of the first substrate layer 200 . A connection part 410 may be included. A planar shape of the first connector 410 may be circular. Alternatively, the planar shape of the first connector 410 may be a quadrangle. The first connector 410 may be disposed on the first pattern unit 221-1 to connect the first pattern unit 221-1 and the terminal 425 of the element 420. The first connection part 410 may be, for example, a solder ball. In the first connection part 410, solder may contain materials of different components. The solder may be composed of at least one of SnCu, SnPb, and SnAgCu. In addition, the material of the heterogeneous component may include any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

An element 420 is disposed on the first connection part 410. The element 420 may be a driver element. For example, the element 420 may be a driving element that drives an antenna pattern layer included in the circuit board. In addition, in the drawings, it is illustrated that only one element is mounted in the cavity (C), but is not limited thereto. For example, a passive element (not shown) for operating the element 420 may be additionally mounted in the cavity C, in addition to the element 420 .

Meanwhile, a molding layer 430 may be formed in the cavity C to cover the element 420 . The molding layer 430 may be EMC (Epoxy Molding Compound), but is not limited thereto. In this case, the molding layer 430 may be formed to fill the recess 221 - 3 of the first pattern layer 221 .

In addition, the embodiment includes the second connector 440 disposed on the lower surface of the pattern layer disposed on the lower surface of the first region RB1 of the first substrate layer 200 . The second connector 440 may connect the package substrate and an external substrate (eg, a main board of a terminal).

Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described in the order of processes.

In this case, the circuit board in the embodiment may have a coreless structure as shown in FIG. 2 .

However, the embodiment is not limited thereto. For example, the circuit board of the embodiment may be a core board including a core insulating layer. For example, the circuit board of the embodiment may have an ETS structure manufactured by an embedded trace substrate (ETS) method. However, for convenience of explanation, the embodiment will be described as having a coreless substrate structure.

7A to 7P are diagrams illustrating a manufacturing method of the circuit board according to the exemplary embodiment shown in FIG. 2 in process order.

Hereinafter, a method of manufacturing the circuit board according to the first embodiment of FIG. 2 will be described with reference to FIGS. 7A to 7P. However, circuit boards of other embodiments other than the first embodiment may be manufactured using a process described below.

The manufacturing process of the circuit board according to the embodiment of the present application includes a first process of manufacturing a part of the first substrate layer and a part of the second substrate layer using a carrier board, and the top and bottom surfaces of the substrate layer manufactured through the first process. A process of manufacturing the remaining part of the first substrate layer and the remaining part of the second substrate layer, respectively, and a process of forming a cavity in the second substrate layer, and removing the stopper layer in the region vertically overlapping the cavity process may be included.

First, referring to FIG. 7A , a carrier board, which is a basic material for manufacturing a circuit board according to an embodiment, may be prepared.

The carrier board may include a carrier insulating layer 510 and a carrier copper foil layer 520 disposed on one surface of the carrier insulating layer 510 .

The carrier copper foil layer 520 may be disposed on one side of the carrier insulating layer 510, or may be disposed on both sides differently. When the carrier copper foil layer 520 is disposed on both sides of the carrier insulating layer 510, in the following process, a circuit board manufacturing process is performed on both sides of the carrier board until the carrier board is removed. You will be able to.

The carrier copper foil layer 520 may be formed by performing electroless plating on the surface of the carrier insulating layer 510 . Alternatively, the carrier insulation layer 510 and the carrier copper foil layer 520 may be CCL (copper clad laminate).

In this case, the carrier board may be divided into a plurality of regions corresponding to the first region RB1 and the second region RB2 of the first substrate layer 200 .

Next, in the embodiment, a process of forming a mask 530 on the lower surface of the carrier copper foil layer 520 may be performed. At this time, a process of forming the opening 540 in the mask 530 may be performed. The opening 540 of the mask 530 may vertically overlap a region of the lower surface of the carrier copper foil layer 520 where the fifth pattern layer 321 is to be formed.

Next, as shown in FIG. 7B, electrolytic plating is performed on the carrier copper foil layer 520 as a seed layer to form a fifth pattern layer 321 filling the opening 540 of the mask 530. process can proceed.

And, in the embodiment, when the fifth pattern layer 321 is formed, a process of removing the mask 530 may be performed. Next, in the embodiment, as the mask 530 is removed, the second insulating layer of the second substrate layer 300 is formed on the lower surface of the carrier copper foil layer 520 and the lower surface of the fifth pattern layer 321. A process of forming a part of the 2-1st insulating layer 311 may be performed.

Next, as shown in FIG. 7C , in the embodiment, a process of forming a through hole (not shown) penetrating the 2-1 insulating layer 311 may be performed. Next, in the embodiment, a process of forming a first dry film DF1 on the lower surface of the 2-1 insulating layer 311 may be performed. The first dry film DF1 may include an opening (not shown) vertically overlapping the region where the first pattern layer 221 is to be formed. Next, in the embodiment, the fourth through electrode 331 filling the through hole of the 2-1 insulating layer 311 and a part of the first pattern layer 221 of the first substrate layer 200 are formed. process can proceed.

Preferably, the first pattern layer 221 is processed through a two-step plating process. Here, the two-step plating may mean that the plating process of the electrolytic plating layer excluding the seed layer is performed twice. For example, in a typical circuit board manufacturing process, electroplating is performed on a seed layer to form a pattern layer. Accordingly, the electrolytic plating layer of the pattern layer has a one-layer structure. Unlike this, in the embodiment, as the function of each region of the first pattern layer 221 is different, in order to form a pattern part suitable for each function, the first pattern layer 221 is formed through two-step plating. Accordingly, the electrolytic plating layer of the first pattern layer 221 may have a two-layer structure.

For example, in the embodiment, a process of forming the first electrolytic plating layer 221a filling at least a part of the opening of the first dry film DF1 on the lower surface of the 2-1 insulating layer 311 may be performed. . At this time, the first electrolytic plating layer 221a corresponds to the second metal layer 221-22 and the third pattern portion 221-3 of the second pattern portion 221-2 of the first pattern layer 221. can

Next, as shown in FIG. 7D , in the embodiment, a process of forming a second dry film DF2 on at least a part of the lower surface of the first electrolytic plating layer 221a may be performed. At this time, the second dry film DF2 is formed to cover at least a portion of the first electrolytic plating layer 221a. In other words, the second dry film DF2 includes an opening (not shown) vertically overlapping at least a portion of the lower surface of the first electrolytic plating layer 221a.

Next, as shown in FIG. 7E, in the embodiment, secondary electroplating is performed on the lower surface of the first electrolytic plating layer 221a to fill at least a part of the opening of the second dry film DF2. A process of forming the plating layer 221b may be performed.

At this time, the second electrolytic plating layer 221b corresponds to the first pattern portion 221-1 of the first pattern layer 221 and the first metal layer 221-21 of the second pattern portion 221-2. can Accordingly, the planar area of the first electrolytic plating layer 221a may be different from the planar area of the second electroplating layer 221b. For example, the planar area of the first electrolytic plating layer 221a may be larger than the planar area of the second electroplating layer 221b. Specifically, the entire area of the second electrolytic plating layer 221b may vertically overlap the first electrolytic plating layer 221a. However, the first electrolytic plating layer 221a may include an overlapping area vertically overlapping the second electrolytic plating layer 221b and a non-overlapping area not vertically overlapping the second electrolytic plating layer 221b. . For example, in the embodiment, the first electrolytic plating layer 221a corresponds to a laser stopper and protects the upper surface of the second electrolytic plating layer 221b corresponding to the first pattern portion 221-1 during a laser process. function can be Accordingly, the planar area of the first electrolytic plating layer 221a may be larger than the planar area of the second electrolytic plating layer 221b to correspond to the planar area of the region where the cavity C is to be formed.

Next, as shown in FIG. 7F , in the embodiment, a process of removing the first dry film DF1 and the second dry film DF2 may be performed. In addition, in the embodiment, a process of removing the carrier insulating layer 510 and the carrier copper foil layer 520 may be performed.

Thereafter, in the embodiment, a process of manufacturing a part of the second substrate layer 300 and a part of the first substrate layer 200 may be performed on the top and bottom of the 2-1st insulating layer 311, respectively.

For example, as shown in FIG. 7G, in the embodiment, the 1-1 insulating layer 211 is formed on the lower surface of the 2-1 insulating layer 311, and the 1-1 insulating layer 211 ), and a process of forming the second pattern layer 222 on the lower surface of the 1-1 insulating layer 211 may be performed. In addition, in the embodiment, the 2-2 insulating layer 312 is formed on the upper surface of the 2-1 insulating layer 311, and the fifth through electrode 332 penetrates the 2-2 insulating layer 312. ) and a process of forming the sixth pattern layer 322 on the upper surface of the 2-2 insulating layer 312 may proceed.

At this time, the first pattern layer 221 is entirely formed in an area vertically overlapping the area where the cavity is to be formed. Accordingly, the surface area of the first pattern layer 221 compared to the surface area of the 2-1 insulating layer 311 may exceed 60%.

At this time, in the embodiment, in order to improve adhesion between the first pattern layer 221 and the 2-1 insulating layer 311, the thickness of the 1-1 insulating layer 211 is increased. For example, in the embodiment, the 1-1st insulating layer 211 is formed with a thickness T4 greater than the thickness T5 of the 2-1st insulating layer 311 .

In addition, as shown in FIG. 9H , in the embodiment, a process of forming a 1-2 insulating layer 212 on the lower surface of the 1-1 insulating layer 211 may be performed. At this time, the 1-2 insulating layer 212 may have a thickness corresponding to the thickness of the 2-1 insulating layer 311 while having a smaller thickness than the 1-1 insulating layer 211. there is.

In addition, in the embodiment, the process of forming the second through electrode 232 penetrating the 1-2 insulating layer 212 and the third pattern layer 223 on the lower surface of the 1-2 insulating layer 212 can proceed.

In addition, in the embodiment, a process of forming the 2-3 insulating layer 313 on the upper surface of the 2-2 insulating layer 312 may be performed. In addition, in the embodiment, the process of forming the sixth through electrode 333 penetrating the 2-3 insulating layer 313 and the seventh pattern layer 323 on the upper surface of the 2-3 insulating layer 313 can proceed.

Next, in the embodiment, as shown in FIG. 7i , in the embodiment, a process of forming the 1-3 insulating layer 213 on the lower surface of the 1-2 insulating layer 212 may be performed. In addition, in the embodiment, the process of forming the third through electrode 233 penetrating the 1-3 insulating layer 213 and the fourth pattern layer 224 on the lower surface of the 1-3 insulating layer 213 can proceed.

In addition, in the embodiment, a process of forming the 2-4th insulating layer 314 on the upper surface of the 2-3rd insulating layer 313 may be performed. Next, in the embodiment, a process of forming the seventh through electrode 334 penetrating the 2-4th insulating layer 314 and the 8th pattern layer 324 on the 2-4th insulating layer 314 can proceed.

Through this, in the embodiment, manufacturing of the circuit board 100 including the first substrate layer 200 and the second substrate layer 300 before the cavity C is formed may be completed.

Meanwhile, in the embodiment, as shown in FIG. 10J, in the process of forming the eighth pattern layer 324, a portion of the seed layer of the eighth pattern layer 324 is left without being removed, and the cavity is formed using this. It can be used as a mask in the process of forming (C).

For example, as shown in FIG. 7K, looking at the manufacturing process of the eighth pattern layer 324, the eighth pattern layer 324 is electrolytically plated on the upper surface of the second-fourth insulating layer 314. A seed layer 324-1 for forming is located. Also, the seed layer 324 - 1 may be used as a seed layer for electroplating the eighth pattern layer 324 .

Next, as shown in FIG. 7L, in the embodiment, as the eighth pattern layer 324 is formed, the seed layer 324-1 does not vertically overlap with the eighth pattern layer 324. You can proceed with the process of removing the area. At this time, in the embodiment, the region 324-1a of the seed layer 324-1 adjacent to the region where the cavity C is to be formed is left without being removed. In the embodiment, in the cavity forming process described below, a cavity forming process is performed only in a portion corresponding to the third region RT1 by using the region 324-1a of the seed layer 324-1 as a laser mask. can proceed. In this case, the region RB1 of the seed layer 324 - 1 may cover a portion of the third region RT1 , which is the region where the cavity C is to be formed. This may be due to undercut due to process variation occurring in the laser forming process.

Next, as shown in FIG. 7M, in the embodiment, a first cavity penetrating the second insulating layers of the second substrate layer 300 is formed by utilizing the region RB1 of the seed layer 324-1. The process of forming (C1) may proceed. At this time, the first cavity C1 is a top surface (for example, the third pattern portion 221-3 of the first electrolytic plating layer 221a, which is a part of the first pattern layer 221 of the first substrate layer 200). ) may be formed up to the upper surface of). In this case, the inner wall IW1 of the first cavity C1 may have a first slope. For example, in an embodiment, a first cavity process may be performed. In this case, the width of the laser mask in the first cavity process may have a first width. The laser mask determines the width of a laser beam in a laser device. At this time, in the embodiment, the first cavity process may be performed by using a first laser beam having a relatively large width in order to open the entire region where the cavity is to be formed. Accordingly, the inner wall IW1 of the first cavity C1 formed by the first cavity process has a first slope corresponding to the first laser beam as a whole.

Next, as shown in FIG. 7N , in the embodiment, a process of forming a second cavity C2 may be performed by performing a secondary cavity process on the first cavity C1. In this case, the width of the laser mask in the second cavity process may have a second width smaller than the first width. Also, the second cavity process may be performed only in a portion corresponding to the inner wall of the first cavity C1 formed in the first cavity process. As the width of the laser mask in the secondary cavity process has a second width smaller than the first width, the inner wall of the second cavity C2 may have a plurality of slopes. For example, the inner wall of the second cavity C2 may include a first slope formed by the first cavity process and a second slope formed by the second cavity process.

For example, referring to FIG. 7O , in the embodiment, a process of forming the first cavity C1 by irradiating a first laser beam L1 corresponding thereto using a mask having a first width of about 280 μm is performed. can proceed Thereafter, in the embodiment, a process of forming the second cavity C2 may be performed by irradiating a second laser beam L2 corresponding thereto using a mask having a second width smaller than the first width of about 100 μm. there is. Accordingly, the cavity in the embodiment includes a first slope corresponding to the first laser beam (L1) and a second slope corresponding to the second laser beam (L2). At this time, the overall inclination of the cavity may have the second inclination, but in the first cavity forming process, the first laser beam L1 is applied to the lower surface of the region RB1 of the seed layer 324-1. penetrates into, and thus includes an undercut region. A portion of the cavity C corresponding to the first slope may correspond to an undercut region formed in the first cavity process.

Next, as shown in FIG. 7P , a process of removing a portion of the third pattern portion 221 - 3 exposed through the secondary cavity process may be performed. For example, the third pattern part 221 - 3 may be removed from an area vertically overlapping the cavity C after the process of forming the cavity C is completed. However, the third pattern part 221 - 3 may have an area larger than that of the lower area of the cavity C. Accordingly, in the etching process, at least a portion of the third pattern portion 221-3 may remain without being removed. For example, the third pattern portion 221-3 in the boundary area of the first area RB1 vertically overlapping the cavity C and the second area RB2 excluding the first area RB1. may not be removed. And, in the embodiment, as a part of the third pattern part 221-3 is removed, the third part of the cavity C may be formed. In this case, the inner wall of the third part may be a side surface of the third pattern part 221-3. And, in the embodiment, in the process of etching the third pattern portion 221-3, etching is performed under an over-etching condition, thereby forming a recessed portion 221-3U that is inwardly dented in the third pattern portion 221-3. ) is formed.

On the other hand, when the circuit board having the characteristics of the above-described invention is used in IT devices or home appliances such as smart phones, server computers, TVs, etc., functions such as signal transmission or power supply can be stably performed. For example, when a circuit board having the characteristics of the present invention performs a semiconductor package function, it can function to safely protect a semiconductor chip from external moisture or contaminants, and can prevent leakage current or electrical short circuit between terminals. Alternatively, it is possible to solve the problem of electrical opening of terminals supplied to the semiconductor chip. In addition, when it is responsible for the function of signal transmission, it is possible to solve the noise problem. Through this, the circuit board having the characteristics of the above-described invention can maintain the stable function of the IT device or home appliance, so that the entire product and the circuit board to which the present invention is applied can achieve functional integrity or technical interoperability with each other.

When the circuit board having the characteristics of the above-described invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of signals transmitted to the transportation device, or to safely protect a semiconductor chip that controls the transportation device from the outside, and to prevent leaks. The stability of the transportation device can be further improved by solving the problem of electrical short circuit between currents or terminals or electrical openness of terminals supplying semiconductor chips. Therefore, the transport device and the circuit board to which the present invention is applied can achieve functional integrity or technical interoperability with each other.

Features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified with respect to other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to these combinations and variations should be interpreted as being included in the scope of the embodiments.

Although the above has been described centering on the embodiment, this is only an example and is not intended to limit the embodiment, and those skilled in the art to which the embodiment belongs may find various things not exemplified above to the extent that they do not deviate from the essential characteristics of the present embodiment. It will be appreciated that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims (15)

a first insulating layer;
a first pattern layer disposed on an upper surface of the first insulating layer; and
A second insulating layer disposed on the upper surface of the first insulating layer and the upper surface of the first pattern layer and including a cavity;
The thickness of the first insulating layer is different from the thickness of the second insulating layer,
The thickness of any one of the first and second insulating layers satisfies the range of 110% to 220% of the thickness of the other insulating layer,
circuit board. According to claim 1,
The first pattern layer,
It is disposed under the lower surface of the second insulating layer and is buried in the first insulating layer,
The thickness of the first insulating layer,
greater than the thickness of the second insulating layer,
circuit board. According to claim 1,
The first pattern layer,
Disposed on the upper surface of the first insulating layer and buried in the second insulating layer,
The thickness of the second insulating layer is greater than the thickness of the first insulating layer,
circuit board. According to claim 2,
A third insulating layer disposed under the first insulating layer,
The thickness of the third insulating layer is smaller than the thickness of the first insulating layer,
circuit board. According to claim 4,
The thickness of the third insulating layer corresponds to the thickness of the second insulating layer,
circuit board. According to claim 3,
A fourth insulating layer disposed on the second insulating layer,
The thickness of the fourth insulating layer is smaller than the thickness of the second insulating layer,
circuit board. According to claim 6,
The thickness of the fourth insulating layer corresponds to the thickness of the first insulating layer,
circuit board. According to any one of claims 1 to 7,
The first pattern layer,
A pattern portion having an upper surface in contact with the second insulating layer and a side surface exposed through the cavity;
The width of the lower surface of the pattern portion is greater than the width of the upper surface of the pattern portion,
circuit board. According to claim 8,
The pattern part,
And a side surface having an inclination in which the width decreases from the lower surface of the pattern part toward the upper surface of the pattern part,
The side surface of the pattern portion includes a curved surface,
circuit board. According to claim 8,
The pattern portion includes a recessed portion in an inward direction,
At least a part of the lower surface of the second insulating layer,
It overlaps vertically with the indentation and does not come into contact with the first pattern layer and the first insulating layer.
circuit board. According to claim 1,
Any one of the first and second insulating layers has a thickness in the range of 10 μm to 60 μm,
The other one of the first and second insulating layers has a thickness in the range of 11 μm to 132 μm,
circuit board. a first insulating layer;
a second insulating layer disposed on an upper surface of the first insulating layer and including a cavity; and
A first pattern part disposed between the first insulating layer and the second insulating layer and disposed in a first region vertically overlapping the cavity, and a first pattern portion disposed in a second region not vertically overlapping the cavity. a first pattern layer including two pattern parts and a third pattern part disposed in a boundary area between the first and second areas;
a connection part disposed on the first pattern part;
an element mounted on the connection part; and
A molding layer molding the device and disposed in the cavity;
The third pattern part,
The third pattern portion includes a recessed portion in an inward direction,
At least a part of the lower surface of the second insulating layer,
Vertically overlapping the recess and contacting the molding layer,
package substrate. According to claim 12,
The third pattern part,
A side surface having an inclination in which a width decreases from the lower surface of the third pattern part toward the upper surface of the third pattern part, and the side surface of the third pattern part includes a curved surface,
package substrate. According to claim 12,
The first pattern layer,
It is disposed under the lower surface of the second insulating layer and is buried in the first insulating layer,
The thickness of the first insulating layer satisfies the range of 110% to 220% of the thickness of the second insulating layer,
package substrate. According to claim 12,
The first pattern layer,
Disposed on the upper surface of the first insulating layer and buried in the second insulating layer,
The thickness of the second insulating layer satisfies the range of 110% to 220% of the thickness of the first insulating layer,
package substrate.

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