KR20230077618A - Semiconductor device and communication device comprising the same - Google Patents

Abstract

A semiconductor device and a communication device including the same are provided. The semiconductor device includes an amplifier that receives a first input signal and a second input signal, amplifies the received signal, and outputs a first output signal and a second output signal, wherein the amplifier outputs the first input signal and the second input signal. A first amplifying circuit that amplifies and outputs a first amplified signal and a second amplified signal, a first amplifying transistor that is turned on based on the first amplified signal to generate a first output signal, and based on the second amplified signal A second amplification circuit including a second amplifying transistor turned on to output a second output signal and a first bias transistor turned on based on the first bias signal to generate a first output signal; A first filter circuit connected to a bias transistor and generating a first bias signal using a first bias voltage and a first bias capacitor; receiving first and second output signals; and a common mode feedback circuit for outputting a feedback signal adjusted so that the average thereof corresponds to the reference signal to the first amplifier, wherein the first filter circuit comprises the output of the first bias capacitor in a disabled state in which the amplifier does not perform an amplification operation. A voltage of the first bias capacitor is adjusted such that the first voltage corresponds to a second voltage of the first bias capacitor in an enabled state in which the amplifier performs an amplification operation.

Description

Semiconductor device and communication device comprising the same

The present invention relates to a semiconductor device and a communication device including the same.

In recent analog communication systems, there is an increasing demand for devices capable of miniaturization with low power consumption. In addition, since a high data transmission rate is required, a demand for a device having a wide bandwidth is also increasing. Accordingly, research is being conducted on a device capable of operating at high speed while satisfying these requirements.

A technical problem to be solved by the present invention is to provide a semiconductor device capable of high-speed operation and a communication device including the same.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments for achieving the above technical problem includes an amplifier that receives a first input signal and a second input signal and outputs a first output signal and a second output signal by amplifying the first input signal, wherein the amplifier comprises: , A first amplification circuit for first amplifying the first input signal and the second input signal to output the first amplification signal and the second amplification signal, and a first amplification circuit that is turned on based on the first amplification signal to generate a first output signal. 1 amplification transistor, a second amplification transistor turned on based on the second amplification signal to output a second output signal, and a first bias transistor turned on based on the first bias signal to generate a first output signal A second amplification circuit, a first filter circuit connected to the first amplification transistor and the first bias transistor, and generating a first bias signal using a first bias voltage and a first bias capacitor, and first and second outputs and a common mode feedback circuit for receiving the signal and outputting a feedback signal to a first amplifier for adjusting an average of the first and second output signals to correspond to a reference signal, wherein the first filter circuit performs an amplification operation by the amplifier. A voltage of the first bias capacitor is adjusted such that a first voltage of the first bias capacitor in an enabled state in which the amplifier performs an amplification operation corresponds to a second voltage of the first bias capacitor in an enabled state in which the amplifier performs an amplification operation.

A semiconductor device according to some embodiments to achieve the above technical problem includes a first amplifying circuit that first amplifies a first input signal and a second input signal and outputs a first amplified signal and a second amplified signal, and a first amplified signal. A first amplifying transistor turned on based on the signal to generate a first output signal, a second amplifying transistor turned on based on the second amplification signal and outputting a second output signal, and turned on based on the first bias signal A second amplification circuit including a first bias transistor generating a first output signal, a first bias capacitor connected to the first amplification transistor and the first bias transistor, a bias voltage at one end of the first bias capacitor and the first amplification circuit A first switch circuit for controlling the supply of one of the signals, and a feedback signal for receiving the first and second output signals and adjusting the average of the first and second output signals to correspond to the reference signal is output to the first amplifier. It includes a common mode feedback circuit that

A communication device according to some embodiments for achieving the above technical problem includes a transimpedance amplifier that receives first and second input signals from a receive mixer, amplifies and outputs them, and a receive filter that filters the output of the transimpedance amplifier. The transimpedance amplifier includes a first amplifying circuit that first amplifies the first input signal and the second input signal to output the first amplified signal and the second amplified signal, and is turned on based on the first amplified signal to generate a second amplified signal. A first amplifying transistor for generating 1 output signal, a second amplifying transistor that is turned on based on the second amplification signal and outputs a second output signal, and a second amplifying transistor that is turned on based on the first bias signal and generates a first output signal A second amplification circuit including a first bias transistor, a first filter circuit connected to the first amplification transistor and the first bias transistor and generating a first bias signal using the first bias capacitor; A common mode feedback circuit receiving two output signals and outputting a feedback signal to a first amplifier for adjusting an average of the first and second output signals to correspond to a reference signal, wherein the first filter circuit comprises a transimpedance amplifier of the first bias capacitor such that a first voltage of the first bias capacitor in a disabled state in which the amplification operation is not performed corresponds to a second voltage of the first bias capacitor in an enabled state in which the transimpedance amplifier performs an amplification operation. adjust the voltage

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram illustrating a communication device in accordance with some embodiments.
2 is a circuit diagram showing the transimpedance amplifier of FIG. 1;
3 is a circuit diagram of the amplifier of FIG. 2;
4 and 5 are diagrams for explaining the operation of an amplifier according to some embodiments.
6 to 8 are diagrams for explaining effects of a transimpedance amplifier according to some embodiments.
9 is a circuit diagram of an amplifier according to some other embodiments.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a communication device in accordance with some embodiments.

Referring to FIG. 1 , a communication device 1000 may include a transceiver 1100, a data processor 1200, a switch 1300, and an antenna 1400.

The transceiver 1100 includes a low noise amplifier 1111, a receive mixer 1113, a transimpedance amplifier (TIA) 1114, a receive filter 1116, a transmit filter 1121, a transimpedance amplifier 1122, A transmit mixer 1124 and a power amplifier 1125 may be included.

In the reception mode, the switch 1300 may output the first reception signal Rx1 received through the antenna 1400 to the low noise amplifier 1111 . The low noise amplifier 1111 may generate a second received signal Rx2 by amplifying the first received signal Rx1. The receive mixer 1113 may generate a third received signal Rx3 by down-converting the second received signal Rx2.

The transimpedance amplifier 1114 may generate a fourth received signal Rx4 by amplifying the third received signal Rx3. In some embodiments, the receive filter 1116 may generate a fifth received signal Rx5 by filtering the fourth received signal Rx4 and output it to the data processor 1200 .

In some embodiments, the transimpedance amplifier 1114 and the receive filter 1116 convert the down-converted radio frequency (RF) current signal through the receive mixer 1113 into an intermediate frequency (IF) voltage signal. and can play a filtering role.

In the transmission mode, the data processor 1200 may generate a first transmission signal Tx1 and output it to the transceiver 1100 . The transmit filter 1121 generates a second transmit signal Tx2 by filtering the first transmit signal Tx1, and the transimpedance amplifier 1122 amplifies the second transmit signal Tx2 to generate a third transmit signal Tx3. ) can be created. In some embodiments, transimpedance amplifier 1122 may include a transimpedance amplifier.

The transmit mixer 1124 generates a fourth transmit signal Tx4 by performing up-converting on the third transmit signal Tx3, and the power amplifier 1125 generates a fourth transmit signal Tx4 A fifth transmission signal Tx5 may be generated by amplifying . The switch 1300 may connect the power amplifier 1125 and the antenna 1400, and the fifth transmission signal Tx5 may be externally output through the antenna 1400.

2 is a circuit diagram showing the transimpedance amplifier of FIG. 1;

Referring to FIG. 2, the transimpedance amplifier 1114 includes an amplifier 100 receiving input signals VIP and VIN, a feedback resistor RM and a feedback capacitor CM connected in parallel to the input and output terminals of the amplifier 100. ) may be included.

Here, the configuration of the transimpedance amplifier 1114 of FIG. 1 will be described, but the transmit amplifier (1122 of FIG. 1) may also include the same configuration as the configuration to be described below.

Input signals VIP and VIN provided to the amplifier 100 may be amplified by the amplifier 100 and output as output signals VOP and VON. In some embodiments, the input signals VIP and VIN may be, for example, differential signals, but the embodiments are not limited thereto. In addition, the amplifier 100 may include an Operational Transconductance Amplifier (OTA), but embodiments are not limited thereto.

The feedback resistor RM and the feedback capacitor CM may include, for example, a variable resistor and a variable capacitor. By changing the resistance level of the feedback resistor RM, the gain and cutoff frequency of the transimpedance amplifier 1114 can be changed.

For example, the cut-off frequency of the transimpedance amplifier 1114 may have a characteristic that is inversely proportional to the resistance level of the feedback resistor RM and the capacitance level of the feedback capacitor CM.

That is, when the resistance level of the feedback resistor RM and the capacitance level of the feedback capacitor CM increase, the cut-off frequency of the transimpedance amplifier 1114 decreases, so that the transimpedance amplifier 1114 receives an input signal having a low frequency. It can act as a narrowband filter that passes .

In addition, when the resistance level of the feedback resistor RM and the capacitance level of the feedback capacitor CM decrease, the cutoff frequency of the transimpedance amplifier 1114 increases, so that the transimpedance amplifier 1114 receives an input signal having a high frequency. It can act as a wideband filter that passes .

In some embodiments, the feedback resistor RM and the feedback capacitor CM may be set to increase or decrease linearly or exponentially, for example controlled by a digital code.

3 is a circuit diagram of the amplifier of FIG. 2;

Referring to FIG. 3, the amplifier 100 includes a first amplifier A1, a second amplifier A2, a common mode feedback circuit CFC, filter circuits FC1 and FC2, and switch circuits. (SC1, SC2) may be included.

The first amplifier A1 may first amplify the first input signal VIP and the second input signal VIN to output the first amplified signal VAP and the second amplified signal VAN.

The first amplifier A1 includes a bias transistor MP3 turned on based on the bias voltage VB, a transistor MP1 turned on based on the first input signal VIP, and a second input signal. It may include a transistor MP2 turned on based on (VIN) and transistors MN1 and MN2 turned on based on the feedback signal VCMFB.

A source terminal of the bias transistor MP3 may be connected to the power supply voltage VDD, and a drain terminal of the bias transistor MP3 may be connected to the source terminals of the transistors MP1 and MP2. A bias voltage VB may be provided to a gate terminal of the bias transistor MP3.

The first input signal VIP is provided to a gate terminal of the transistor MP1 , and a drain terminal of the transistor MP1 may be connected to a drain terminal of the transistor MN1 . The second input signal VIN is provided to a gate terminal of the transistor MP2, and a drain terminal of the transistor MP2 may be connected to a drain terminal of the transistor MN2.

The feedback signal VCMFB is provided to a gate terminal of the transistor MN1, and a source terminal of the transistor MN1 may be grounded. The feedback signal VCMFB is provided to a gate terminal of the transistor MN2, and a source terminal of the transistor MN2 may be grounded.

In some embodiments, bias transistor MP3 and transistors MP1 and MP2 may include P-type transistors, and transistors MN1 and MN2 may include N-type transistors, but embodiments are not limited thereto. .

The first input signal VIP is first amplified by the bias current generated when the transistor MP1 is turned on based on the first input signal VIP and the transistor MN1 is turned on based on the feedback signal VCMFB. As a result, the first amplified signal VAP may be generated. Then, the generated first amplification signal VAP may be transmitted to the second amplifier A2 (eg, a gate terminal of the transistor MN6).

The second input signal VIN is first amplified by the bias current generated when the transistor MP2 is turned on based on the second input signal VIN and the transistor MN2 is turned on based on the feedback signal VCMFB. As a result, the second amplified signal VAN may be generated. Then, the generated second amplified signal VAN may be transmitted to the second amplifier A2 (eg, a gate terminal of the transistor MN7).

In some embodiments, the first amplifier A1 may include a Miller compensation circuit MCC3 including a resistor RB and a capacitor CC.

The Miller compensation circuit MCC3 may be connected between the gate and drain terminals of the transistors MN1 and MN2 to perform a compensation operation.

The second amplifier A2 may second amplify the first amplification signal VAP and the second amplification signal VAN to output the first output signal VOP and the second output signal VON.

The second amplifier A2 includes a bias transistor MP6 turned on based on the first bias signal VBP, a bias transistor MP7 turned on based on the second bias signal VBN, and a first amplifier A1. An amplification transistor MN6 turned on based on the first amplification signal VAP output from ) and an amplification transistor MN7 turned on based on the second amplification signal VAN output from the first amplifier A1. can include

The first output signal VOP may be generated by adding a bias current generated by the bias transistor MP6 to a current generated by the amplification transistor MN6. That is, the first output signal VOP may be generated by the current generated by the amplification transistor MN6 and the bias transistor MP6.

The second output signal VON may be generated by adding the bias current generated by the bias transistor MP7 to the current generated by the amplification transistor MN7. That is, the second output signal VON may be generated by the current generated by the amplification transistor MN7 and the bias transistor MP7.

A source terminal of the bias transistor MP6 may be connected to the power supply voltage VDD, and a drain terminal of the bias transistor MP6 may be connected to a drain terminal of the amplification transistor MN6. A gate terminal of the bias transistor MP6 may be connected to the filter circuit FC1.

A source terminal of the bias transistor MP7 may be connected to the power supply voltage VDD, and a drain terminal of the bias transistor MP7 may be connected to a drain terminal of the amplification transistor MN7. A gate terminal of the bias transistor MP7 may be connected to the filter circuit FC2.

A source terminal of the amplification transistor MN6 may be grounded, and a drain terminal of the amplification transistor MN6 may be connected to a drain terminal of the bias transistor MP6. The first output signal VOP may be output to the drain terminal of the amplification transistor MN6. A gate terminal of the amplifying transistor MN6 may be connected to a drain terminal of the transistor MP1 and a drain terminal of the transistor MN1 of the first amplifier A1. A gate terminal of the amplifying transistor MN6 may be connected to the filter circuit FC1 through the switch circuit SC1.

A source terminal of the amplification transistor MN7 may be grounded, and a drain terminal of the amplification transistor MN7 may be connected to a drain terminal of the bias transistor MP7. The second output signal VON may be output to the drain terminal of the amplification transistor MN7. A gate terminal of the amplifying transistor MN7 may be connected to a drain terminal of the transistor MP2 and a drain terminal of the transistor MN2 of the first amplifier A1. A gate terminal of the amplification transistor MN7 may be connected to the filter circuit FC2 through the switch circuit SC2.

In some embodiments, the bias transistors MP7 and MP6 may include P-type transistors, and the amplification transistors MN7 and MN6 may include N-type transistors, but embodiments are not limited thereto.

In some embodiments, the second amplifier A2 may include a first mirror compensation circuit MCC1 and a second mirror compensation circuit MCC2 including a variable resistor RZ and a variable capacitor CC.

The first Miller compensation circuit MCC1 may be connected between the gate terminal and the drain terminal of the transistor MN6 to perform a compensation operation. The second Miller compensation circuit MCC2 is connected between the gate terminal and the drain terminal of the transistor MN7 to perform a compensation operation.

In some embodiments, the amplifier 100 includes first and second Miller compensation circuits MCC1 and MCC2 performing dominant pole compensation using a common mode feedback circuit (CFC) and a Miller effect. can include

The common mode feedback circuit (CFC) receives the first output signal (VOP) and the second output signal (VON), and the average of the first output signal (VOP) and the second output signal (VON) is the reference signal (VCM). A feedback signal VCMFB adjusted to correspond to may be output.

In the amplifier 100, when there is no difference between the first input signal VIP and the second input signal VIN, which are differential signals, the first output signal VOP and the second output signal VON of the amplifier 100 Should be located at the middle level of the entire voltage swing range, but due to changes in power, temperature, process, between the input common mode and the output common mode of the amplifier 100, or the change in the output common mode due to noise, the amplifier The operation of the amplifier 100 may be limited because the output of the amplifier 100 is biased to a level other than the intermediate level.

For this purpose, a common mode feedback circuit (CFC) may be used. The common mode feedback circuit (CFC) detects the common mode voltage of the amplifier 100, compares the detected common mode voltage with a reference voltage, and determines the comparison result. It is a negative feedback circuit that makes the sensed common mode voltage close to the reference voltage.

A common mode feedback circuit (CFC) may be used at the output of amplifier 100 to establish the common mode of the differential output signals.

The common mode feedback circuit CFC includes a bias transistor MP8 turned on based on the bias voltage VB and a transistor MP9 turned on based on the average of the first output signal VOP and the second output signal VON. ), the transistor MP10 turned on based on the reference signal VCM, the transistor MN8 turned on by the output of the drain terminal of the transistor MP9, and the transistor turned on by the output of the drain terminal of the transistor MP10 ( MN9) may be included.

A source terminal of the bias transistor MP8 may be connected to the power supply voltage VDD, and a drain terminal of the bias transistor MP8 may be connected to the source terminals of the transistors MP9 and MP10. A bias voltage VB may be provided to a gate terminal of the bias transistor MP8.

An average of the first output signal VOP and the second output signal VON may be provided to the gate terminal of the transistor MP9 by the resistors RS and the capacitors CS. A drain terminal of the transistor MP9 may be connected to a drain terminal of the transistor MN8. The reference signal VCM is provided to a gate terminal of the transistor MP10, and a drain terminal of the transistor MP10 may be connected to a drain terminal of the transistor MN9.

The gate terminal of the transistor MN8 is connected to the drain terminal of the transistor MN8, and the feedback signal VCMFB may be output through the drain terminal of the transistor MN8. A source terminal of the transistor MN8 may be grounded. A gate terminal of the transistor MN9 is connected to a drain terminal of the transistor MN8, and a source terminal of the transistor MN9 may be grounded.

In some embodiments, the bias transistor MP8 and the transistors MP9 and MP10 may include a P-type transistor, and the transistors MN8 and MN9 may include an N-type transistor, but the embodiment is not limited thereto. .

The transistors MP9, MP10, MN8, and MN9 may generate a feedback signal VCMFB for adjusting an average of the first output signal VOP and the second output signal VON to correspond to the reference signal VCM. there is. The generated feedback signal VCMFB may be provided to the first amplifier A1. For example, the generated feedback signal VCMFB may be provided to gate terminals of the transistors MN1 and MN2 of the first amplifier A1.

The filter circuit FC1 may include a resistor R1 and a bias capacitor C1. In some embodiments, the filter circuit FC1 may be a high pass filter including a resistor R1 and a bias capacitor C1. The filter circuit FC1 may generate the first bias signal VBP using the resistor R1 and the bias capacitor C1.

One end of the resistor R1 may be provided with the bias voltage VB and the other end of the resistor R1 may be connected to the bias capacitor C1. The bias capacitor C1 may be referred to as a current reuse capacitor since the bias transistor MP6 of the second amplifier A2 is used to generate an additional bias current. In addition, the bias capacitor C1 may be referred to as a gain boosting capacitor since the bias transistor MP6 of the second amplifier A2 is used to generate additional gain.

One end of the bias capacitor C1 may be connected to the switch circuit SC1, and the other end of the bias capacitor C1 may be connected to the resistor R1.

The switch circuit SC1 may control one end of the bias capacitor C1 to provide one of the bias voltage VA and the first amplification signal VAP. That is, the switch circuit SC1 may connect one terminal of the bias capacitor C1 to the bias voltage VA or connect it to the gate terminal of the amplifying transistor MN6 of the second amplifier A2.

In some embodiments, the bias voltage VA may be a different voltage than the bias voltage VB. For example, the bias voltage VA may have a voltage greater than the ground voltage GND and smaller than the power supply voltage VDD, but different from the bias voltage VB.

In some embodiments, the bias voltage VA is the voltage of the bias capacitor C1 in a disabled state in which the amplifier 100 does not perform an amplification operation, and the voltage of the bias capacitor C1 enables the amplifier 100 to perform an amplification operation. It may be a voltage corresponding to the voltage of the bias capacitor C1 in the (enable) state. For example, the magnitude of the bias voltage VA is such that when the amplifier 100 is in a disabled state, the voltage difference between both ends of the bias capacitor C1 is equal to that of the bias capacitor C1 when the amplifier 100 is in an enabled state. It may be determined to be substantially equal to the voltage difference between both ends.

For example, when the power supply voltage VDD is 1.2V, in an enabled state in which the amplifier 100 performs an amplification operation, the first bias signal ( VBP) may become 0.8V, and the first amplification signal VAP may become 0.4V. In this case, when the amplifier 100 is enabled, the voltage difference between both ends of the bias capacitor C1 is 0.4V.

Accordingly, in this case, the bias voltage VA may be determined to be 0.8V. In this way, when the bias voltage VA is determined to be 0.8V, in a disabled state in which the amplifier 100 does not perform an amplification operation, 1.2V, which is the power supply voltage VDD, is applied to one end of the bias capacitor C1 and bias A bias voltage VA of 0.8V may be applied to the other terminal of the capacitor C1, so that a voltage difference between both terminals of the bias capacitor C1 may be 0.4V in a disabled state of the amplifier 100. A more detailed description of this will be described later.

In some embodiments, the switch circuit FC1 may include a switch S5 and a switch S6. The switch S5 controls whether the bias voltage VA and the bias capacitor C1 are connected, and the switch S5 controls whether the gate terminal of the amplification transistor MN6 and the bias capacitor C1 are connected. there is.

The filter circuit FC2 may include a resistor R2 and a bias capacitor C2. In some embodiments, the filter circuit FC2 may be a high pass filter including a resistor R2 and a bias capacitor C2. The filter circuit FC2 may generate the second bias signal VBN by using the resistor R2 and the bias capacitor C2.

One end of the resistor R2 may be provided with the bias voltage VB and the other end of the resistor R2 may be connected to the bias capacitor C2. As described above, the bias capacitor C2 may also be referred to as a current reuse capacitor or a gain boosting capacitor.

One end of the bias capacitor C2 may be connected to the switch circuit SC2, and the other end of the bias capacitor C2 may be connected to the resistor R2.

The switch circuit SC2 may control one end of the bias capacitor C2 to provide one of the bias voltage VA and the second amplification signal VAN. That is, the switch circuit SC2 may connect one terminal of the bias capacitor C2 to the bias voltage VA or connect it to the gate terminal of the amplifying transistor MN7 of the second amplifier A2.

In some embodiments, the switch circuit FC2 may include a switch S7 and a switch S8. The switch S7 controls whether the bias voltage VA and the bias capacitor C2 are connected, and the switch S8 controls whether the gate end of the amplifying transistor MN7 and the bias capacitor C2 are connected. there is.

The switch S1 may control whether the power voltage VDD is applied to the gate terminal of the bias transistor MP6. When the amplifier 100 is in a disabled state, the switch S1 is turned on to provide the power supply voltage VDD to the gate terminal of the bias transistor MP6, and when the amplifier 100 is in an enabled state, the switch ( S1) can be turned off.

The switch S3 may control whether or not the ground voltage GND is applied to the gate terminal of the amplification transistor MN6. When the amplifier 100 is in a disabled state, the switch S3 is turned on to provide a ground voltage (GND) to the gate terminal of the amplifying transistor MN6, and when the amplifier 100 is in an enabled state, the switch ( S3) can be turned off.

The switch S2 may control whether the power voltage VDD is applied to the gate terminal of the bias transistor MP7. When the amplifier 100 is in a disabled state, the switch S2 is turned on to provide the power supply voltage VDD to the gate terminal of the bias transistor MP6, and when the amplifier 100 is in an enabled state, the switch ( S2) can be turned off.

The switch S4 may control whether or not the ground voltage GND is applied to the gate terminal of the amplification transistor MN7. When the amplifier 100 is in a disabled state, the switch S4 is turned on to provide a ground voltage (GND) to the gate terminal of the amplification transistor MN7, and when the amplifier 100 is in an enabled state, the switch ( S4) can be turned off.

4 and 5 are diagrams for explaining the operation of a transimpedance amplifier according to some embodiments. 4 is a circuit diagram when the amplifier is disabled, and FIG. 5 is a circuit diagram when the amplifier is enabled.

First, referring to FIG. 4, when the amplifier 100 is in a disabled state, switches S1, S2, S3, S4, S5, and S7 are turned on, and switches S6 and S8 are turned off. .

Accordingly, the voltage difference between the bias capacitor C1 and the bias capacitor C2 becomes VDD-VA.

Next, referring to FIG. 5, when the amplifier 100 is in an enabled state, switches S6 and S8 are turned on, and switches S1, S2, S3, S4, S5 and S7 are turned off. .

Accordingly, the voltage difference between both ends of the bias capacitor C1 becomes VBP-VAP, and the voltage difference between both ends of the bias capacitor C2 becomes VBN-VAN. Here, the magnitudes of the first and second bias signals VBP and VBN and the first and second amplification signals VAP and VAN may vary according to design characteristics of elements included in the amplifier 100 . In this embodiment, the magnitude of the bias voltage VA may be determined to satisfy Equation 1 below.

The magnitude of the bias voltage VA is set in this way, the switch circuits SC1 and SC2 are controlled as shown in FIG. 4 in the disabled state of the amplifier 100, and in the enabled state of the amplifier 100 When the switch circuits SC1 and SC2 are controlled as shown in FIG. 5, the start-up time of the amplifier 100 is reduced even when the capacitance of the bias capacitors C1 and C2 is designed to be large. However, high-speed operation may be possible.

Hereinafter, this will be described in more detail with reference to FIGS. 6 to 8 .

6 to 8 are diagrams for explaining effects of a transimpedance amplifier according to some embodiments.

6 is a circuit diagram of an amplifier 99 having a configuration different from the previously described amplifier (100 in FIG. 3). 7 is a circuit diagram when the amplifier of FIG. 6 is disabled, and FIG. 8 is a circuit diagram when the amplifier of FIG. 6 is enabled.

Referring to FIG. 6 , the amplifier 99 does not include switch circuits (SC1 and SC2 in FIG. 3 ) unlike the amplifier (100 in FIG. 3 ) described above.

Since the filter circuits FC1 and FC2 are high pass filters, a cutoff frequency of the high pass filter is determined by 1/RC. Accordingly, as the capacitance values of the bias capacitors C1 and C2 increase, the filter linearity of the filter circuits FC1 and FC2 may improve even at low frequencies. Therefore, in order to improve the performance of the filter circuits FC1 and FC2, it is necessary to design the capacitance values of the bias capacitors C1 and C2 to be large.

However, when the capacitance values of the bias capacitors C1 and C2 are designed to be large, the amount of charge change in the bias capacitors C1 and C2 increases when the amplifier 99 is switched from a disabled state to an enabled state.

For example, as shown in FIG. 7, when the amplifier 99 is in a disabled state, the voltages of the bias capacitors C1 and C2 are VDD-GND (eg, 1.2V-0V = 1.2V), As shown in FIG. 8, when the amplifier 99 is enabled, the voltages of the bias capacitors C1 and C2 are VBP(VBN) - VAP(VAN) (e.g., 0.8V-0.4V=0.4V). ) turns into This voltage change becomes a factor that increases the start-up time of the amplifier 99, thereby slowing down the operating speed of the amplifier 99.

However, when the amplifier 100 according to the present embodiment described above is in a disabled state, the voltages of the bias capacitors C1 and C2 are changed by the switch circuits SC1 and SC2 to VDD-VA (eg, , 1.2V-0.8V = 0.4V). Further, in the amplifier 100 according to the present embodiment described above, when in an enabled state, the voltages of the bias capacitors C1 and C2 are VBP(VBN) - VAP(VAN) (eg, 0.8V-0.4 V=0.4V).

That is, when the amplifier 100 is in a disabled state, the voltages of the bias capacitors C1 and C2 are previously adjusted to the voltages of the bias capacitors C1 and C2 in which the amplifier 100 is enabled (for example, , charging) to minimize the amount of charge change in the bias capacitors C1 and C2 when the amplifier 100 is switched from a disabled state to an enabled state.

Accordingly, even if the capacitance values of the bias capacitors C1 and C2 are designed to increase the performance of the filter circuits FC1 and FC2, the start-up time of the amplifier 100 does not increase. High-speed operation is possible.

9 is a circuit diagram of an amplifier according to some other embodiments.

Hereinafter, descriptions common to the above-described embodiments will be omitted and differences will be mainly described.

Referring to FIG. 9 , the amplifier 101 may further include variable resistors R11 and R22 disposed between the power supply voltage VDD and the ground voltage GND.

In this embodiment, the variable resistors R11 and R22 may be distribution resistors for generating the bias voltage VA. That is, the bias voltage VA may be generated by the resistance values of the variable resistors R11 and R22.

For example, when the magnitude of the power supply voltage VDD is 1.2V and the magnitude of the bias voltage VA is 0.8V, the ratio of the resistance value of the variable resistor R11 to that of the variable resistor R12 is 1. : Can be 2.

Operations of the switch circuits SC1 and SC2 when the amplifier 101 operates in a disabled state and in an enabled state are the same as those described above, so duplicate descriptions are omitted.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100: amplifier
A1: first amplifier
A2: second amplifier
CFC: common mode feedback circuit

Claims (20)

An amplifier receiving a first input signal and a second input signal and outputting a first output signal and a second output signal by amplifying them,
The amplifier is
A first amplification circuit for first amplifying the first input signal and the second input signal and outputting a first amplification signal and a second amplification signal;
A first amplification transistor turned on based on the first amplification signal to generate a first output signal, a second amplification transistor turned on based on the second amplification signal to output a second output signal, and a first bias signal A second amplifier circuit including a first bias transistor turned on based on and generating the first output signal;
a first filter circuit connected to the first amplifying transistor and the first bias transistor and configured to generate the first bias signal using a first bias voltage and a first bias capacitor;
A common mode feedback circuit receiving the first and second output signals and outputting a feedback signal to the first amplifier for adjusting an average of the first and second output signals to correspond to a reference signal do,
The first filter circuit is such that a first voltage of the first bias capacitor in a disabled state in which the amplifier does not perform an amplification operation is equal to a voltage of the first bias capacitor in an enabled state in which the amplifier performs an amplification operation. A semiconductor device configured to adjust a voltage of the first bias capacitor to correspond to a second voltage. According to claim 1,
The first bias capacitor is connected to a gate terminal of the first amplifying transistor and a gate terminal of the first bias transistor. According to claim 2,
The semiconductor device of claim 1 , wherein the first filter circuit includes a resistor having one end provided with the first bias voltage and another end connected to one end of the first bias capacitor and a gate terminal of the first bias transistor. According to claim 2,
The second amplifier circuit,
A second bias transistor turned on based on a second bias signal to generate the second output signal;
The amplifier is
A second filter circuit connected to the second bias transistor and the second amplifying transistor and configured to generate the second bias signal using a second bias voltage and a second bias capacitor;
The second filter circuit,
and adjusting a voltage of the second bias capacitor such that a third voltage of the second bias capacitor in the disabled state corresponds to a fourth voltage of the second bias capacitor in the enabled state. According to claim 4,
the second bias capacitor is connected to a gate terminal of the second amplifying transistor and a gate terminal of the second bias transistor;
The second filter circuit includes a resistor to which the second bias voltage is applied at one end and a resistor whose other end is connected to one end of the second bias capacitor and a gate terminal of the second bias transistor. According to claim 1,
The amplifier is
A switch circuit providing a second bias voltage to one terminal of the first bias capacitor in the disabled state and providing the first amplification signal to one terminal of the first bias capacitor in the enabled state semiconductor device. According to claim 6,
The semiconductor device of claim 1 , wherein the first filter circuit includes a resistor to which the first bias voltage is applied at one end and a resistor whose other end is connected to the other end of the first bias capacitor and the gate end of the first bias transistor. According to claim 6,
The switch circuit,
a first switch providing the second bias voltage to one terminal of the first bias capacitor;
and a second switch providing the first amplification signal to one terminal of the first bias capacitor. According to claim 6,
The semiconductor device further includes a first resistor and a second resistor configured to generate the second bias voltage from a power supply voltage. a first amplifying circuit that first amplifies the first input signal and the second input signal and outputs the first amplified signal and the second amplified signal;
A first amplification transistor turned on based on the first amplification signal to generate a first output signal, a second amplification transistor turned on based on the second amplification signal to output a second output signal, and a first bias signal a second amplifier circuit including a first bias transistor turned on based on and generating the first output signal;
a first bias capacitor connected to the first amplifying transistor and the first bias transistor;
a first switch circuit which controls to provide one of a bias voltage and the first amplification signal to one terminal of the first bias capacitor; and
and a common mode feedback circuit receiving the first and second output signals and outputting, to the first amplifier, a feedback signal for adjusting an average of the first and second output signals to correspond to a reference signal. According to claim 10,
One terminal of the first bias capacitor is connected to the gate terminal of the first amplifying transistor through the first switch circuit, and the other terminal of the first bias capacitor is connected to the gate terminal of the first bias transistor. . According to claim 11,
The first switch circuit,
a first switch providing the bias voltage to one terminal of the first bias capacitor;
and a second switch providing the first amplification signal to one terminal of the first bias capacitor. According to claim 12,
The bias voltage is smaller than the power supply voltage and larger than the ground voltage. According to claim 10,
The semiconductor device further includes a first resistor and a second resistor configured to generate the bias voltage from a power supply voltage. According to claim 14,
One end of the first bias capacitor is connected to the gate end of the first amplifying transistor and the first resistor through the first switch circuit, and the other end of the first bias capacitor is connected to the gate end of the first bias transistor. semiconductor device to be connected. According to claim 10,
a second bias capacitor; and
A second switch circuit for controlling the bias voltage and the second amplification signal to be provided to one terminal of the second bias capacitor;
The second amplifier circuit,
A second bias transistor turned on based on a second bias signal to generate the second output signal;
The second bias capacitor,
A semiconductor device coupled to the second amplification transistor and the second bias transistor. a transimpedance amplifier receiving first and second input signals from the receiving mixer and amplifying and outputting the first and second input signals; and
Including a receive filter for filtering the output of the transimpedance amplifier,
The transimpedance amplifier,
A first amplification circuit for first amplifying the first input signal and the second input signal and outputting a first amplification signal and a second amplification signal;
A first amplification transistor turned on based on the first amplification signal to generate a first output signal, a second amplification transistor turned on based on the second amplification signal to output a second output signal, and a first bias signal A second amplifier circuit including a first bias transistor turned on based on and generating the first output signal;
a first filter circuit connected to the first amplifying transistor and the first bias transistor and configured to generate the first bias signal using a first bias voltage and a first bias capacitor;
A common mode feedback circuit receiving the first and second output signals and outputting a feedback signal to the first amplifier for adjusting an average of the first and second output signals to correspond to a reference signal;
The first filter circuit is configured so that the first voltage of the first bias capacitor in a disabled state in which the transimpedance amplifier does not perform an amplification operation corresponds to the first voltage in an enabled state in which the transimpedance amplifier performs an amplification operation. 1 The communication device for adjusting the voltage of the first bias capacitor to correspond to the second voltage of the bias capacitor. According to claim 17,
The transimpedance amplifier,
A switch circuit providing a second bias voltage to one terminal of the first bias capacitor in the disabled state and providing the first amplification signal to one terminal of the first bias capacitor in the enabled state communication device. According to claim 18,
The second bias voltage is smaller than the power supply voltage and larger than the ground voltage. According to claim 19,
The communication device of claim 1 , wherein the first filter circuit includes a resistor to which the first bias voltage is applied at one end and a resistor whose other end is connected to the other end of the first bias capacitor and the gate end of the first bias transistor.

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