KR20230056559A - Semiconductor device and communication device comprising the same - Google Patents

Abstract

Provided are a semiconductor device and a communication device comprising the same. The semiconductor device comprises: a first amplifier primarily amplifying a first input signal and a second input signal and outputting a first amplified signal and a second amplified signal; a second amplifier receiving the first amplified signal and the second amplified signal, secondarily amplifying the same, and outputting a first output signal and a second output signal; a feedforward circuit receiving the first and second input signals and performing feedforward control on the first and second output signals; and a common mode feedback circuit receiving the first and second output signals and outputting a feedback signal that adjusts the average of the first and second output signals to correspond to a reference signal. The feedback signal output by the common mode feedback circuit is provided to the first amplifier and the feedforward circuit. Therefore, the semiconductor device can be made compact and operated stably.

Description

Semiconductor device and communication device comprising the same

The present invention relates to a semiconductor device and a communication device including the same.

In recent analog communication systems, there is an increasing demand for devices capable of miniaturization with low power consumption. In addition, since a high data transmission rate is required, a demand for a device having a wide bandwidth is also increasing. Accordingly, research on a device capable of stably operating while satisfying these requirements is being conducted.

A technical problem to be solved by the present invention is to provide a semiconductor device that can be miniaturized and stably operated, and a communication device including the same.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments for achieving the above technical problem includes a first amplifier that first amplifies a first input signal and a second input signal and outputs a first amplified signal and a second amplified signal; and a first amplified signal. And a second amplifier receiving a second amplification signal and amplifying it a second time to output a first output signal and a second output signal, receiving first and second input signals and feeding forward the first and second output signals (common mode feedback) that receives a feed forward circuit that performs feedforward control, and first and second output signals and outputs a feedback signal that adjusts the average of the first and second output signals to correspond to the reference signal. feedback) circuit, but the feedback signal output from the common mode feedback circuit is provided to the first amplifier and the feed forward circuit.

A semiconductor device according to some embodiments for achieving the above technical problem includes a first transistor turned on based on a first input signal, a second transistor turned on based on a second input signal, and one terminal of the first transistor. A first amplifier including a third transistor connected to and turned on based on a feedback signal, and a fourth transistor connected to one terminal of the second transistor and turned on based on a feedback signal, based on a first input signal A fifth transistor turned on, a sixth transistor turned on based on the second input signal, a seventh transistor connected to one end of the fifth transistor and turned on based on a bias signal, and connected to one end of the second transistor A feed forward circuit including an eighth transistor turned on based on a feedback signal, a ninth transistor having a gate terminal connected between the first transistor and a third transistor and outputting a first output signal to a drain terminal, and a gate terminal A second amplifier including a tenth transistor connected between the second transistor and the fourth transistor and outputting the second output signal to a drain terminal, and receiving the first and second output signals and receiving the first and second output signals and a common mode feedback circuit outputting a feedback signal for adjusting the average to correspond to the reference signal.

A communication device according to some embodiments for achieving the above technical problem includes a receiving mixer performing down-converting on an output of a low noise amplifier, a receiving amplifier amplifying and outputting an output of the receiving mixer, and A receive filter for filtering an output of the receive amplifier, wherein an output of the receive mixer includes first and second input signals, and the receive amplifier amplifies the first and second input signals to obtain first and second output signals. An amplifier that outputs, a common mode feedback circuit that receives first and second output signals and outputs a feedback signal for adjusting an average of the first and second output signals to correspond to a reference signal, and first and second inputs. and a feed forward circuit receiving a signal and a feedback signal and performing feed forward control on the first and second output signals based on the first and second input signals and the feedback signal.

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram illustrating a communication device in accordance with some embodiments.
FIG. 2 is a circuit diagram illustrating the receive amplifier of FIG. 1 .
3 is a block diagram illustrating the amplifier of FIG. 2;
4 is a circuit diagram of the amplifier of FIG. 2;
5 to 8 are diagrams for explaining an effect of a receiving amplifier according to some embodiments.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a communication device in accordance with some embodiments.

Referring to FIG. 1 , a communication device 1000 may include a transceiver 1100, a data processor 1200, a switch 1300, and an antenna 1400.

The transceiver 1100 includes a low noise amplifier 1111, a receive mixer 1113, a receive amplifier 1114, a receive filter 1116, a transmit filter 1121, a transmit amplifier 1122, a transmit mixer 1124, and a power amplifier ( 1125) may be included.

In the reception mode, the switch 1300 may output the first reception signal Rx1 received through the antenna 1400 to the low noise amplifier 1111 . The low noise amplifier 1111 may generate a second received signal Rx2 by amplifying the first received signal Rx1. The receive mixer 1113 may generate a third received signal Rx3 by down-converting the second received signal Rx2.

The receiving amplifier 1114 may generate a fourth received signal Rx4 by amplifying the third received signal Rx3. In some embodiments, the receive filter 1116 may generate a fifth received signal Rx5 by filtering the fourth received signal Rx4 and output it to the data processor 1200 .

In some embodiments, the receive amplifier 1114 includes a Trans Impedence Amplifier (TIA), and the receive amplifier 1114 and the receive filter 1116 are down-converted RF through the receive mixer 1113. It can play a role of converting a (Radio Frequency) current signal into an Intermediate Frequency (IF) voltage signal and filtering it.

In the transmission mode, the data processor 1200 may generate a first transmission signal Tx1 and output it to the transceiver 1100 . The transmit filter 1121 generates a second transmit signal Tx2 by filtering the first transmit signal Tx1, and the transmit amplifier 1122 amplifies the second transmit signal Tx2 to obtain a third transmit signal Tx3. can create In some embodiments, transmit amplifier 1122 may include a transimpedance amplifier.

The transmit mixer 1124 generates a fourth transmit signal Tx4 by performing up-converting on the third transmit signal Tx3, and the power amplifier 1125 generates a fourth transmit signal Tx4 A fifth transmission signal Tx5 may be generated by amplifying . The switch 1300 may connect the power amplifier 1125 and the antenna 1400, and the fifth transmission signal Tx5 may be externally output through the antenna 1400.

FIG. 2 is a circuit diagram illustrating the receive amplifier of FIG. 1 .

Referring to FIG. 2, the receiving amplifier 1114 includes the amplifier 100 receiving the input signals VIP and VIN through the input resistor RG1 and the feedback resistor RM connected in parallel to the input terminal and the output terminal of the amplifier 100. ) and a feedback capacitor (CM).

Here, the configuration of the receive amplifier 1114 of FIG. 1 will be described, but the transmit amplifier (1122 of FIG. 1) may also include the same configuration as the configuration to be described below.

Input signals VIP and VIN provided to the amplifier 100 may be amplified by the amplifier 100 and output as output signals VOP and VON. In some embodiments, the input signals VIP and VIN may be, for example, differential signals, but the embodiments are not limited thereto. In addition, the amplifier 100 may include an Operational Transconductance Amplifier (OTA), but embodiments are not limited thereto.

The input resistor RG1 and the feedback resistor RM may include, for example, variable resistors. By changing the resistance levels of the input resistor RG1 and the feedback resistor RM, the gain and cutoff frequency of the receiving amplifier 1114 may be changed.

For example, the cutoff frequency of the receiving amplifier 1114 may have a characteristic that is inversely proportional to the resistance level of the feedback resistor RM.

That is, when the resistance level of the feedback resistor RM increases, the cutoff frequency of the receiving amplifier 1114 decreases, so that the receiving amplifier 1114 operates as a narrowband filter that passes an input signal having a low frequency. can do.

In addition, when the resistance level of the feedback resistor RM decreases, the cutoff frequency of the receiving amplifier 1114 increases, so that the receiving amplifier 1114 operates as a wideband filter that passes an input signal having a high frequency. can

Finally, when the resistance level of the feedback resistor RM is maintained in a certain range, the receiving amplifier 1114 operates as a middleband filter that passes an input signal having a frequency between the first frequency and the second frequency. can do.

In some embodiments, the feedback resistor RM and the feedback capacitor CM may be set to increase or decrease linearly or exponentially, for example controlled by a digital code.

3 is a block diagram illustrating the amplifier of FIG. 2; 4 is a circuit diagram of the amplifier of FIG. 2;

3 and 4, the amplifier 100 includes a first amplifier A1, a second amplifier A2, a feedforward circuit (FFA) and a common mode feedback circuit (CFC). can include

Resistors R1 and R2 and capacitors C1 and C2 shown in FIG. 3 represent resistance components and capacitance components existing on a path inside the amplifier 100 .

The first amplifier A1 may first amplify the first input signal VIP and the second input signal VIN to output the first amplified signal VAP and the second amplified signal VAN.

The first amplifier A1 includes a bias transistor MP3 turned on based on the bias voltage VB, a transistor MP1 turned on based on the first input signal VIP, and a second input signal. It may include a transistor MP2 turned on based on (VIN) and transistors MN1 and MN2 turned on based on the feedback signal VCMFB.

A source terminal of the bias transistor MP3 may be connected to the power supply voltage VDD, and a drain terminal of the bias transistor MP3 may be connected to the source terminals of the transistors MP1 and MP2. A bias voltage VB may be provided to a gate terminal of the bias transistor MP3.

The first input signal VIP is provided to a gate terminal of the transistor MP1 , and a drain terminal of the transistor MP1 may be connected to a drain terminal of the transistor MN1 . The second input signal VIN is provided to a gate terminal of the transistor MP2, and a drain terminal of the transistor MP2 may be connected to a drain terminal of the transistor MN2.

The feedback signal VCMFB is provided to a gate terminal of the transistor MN1, and a source terminal of the transistor MN1 may be grounded. The feedback signal VCMFB is provided to a gate terminal of the transistor MN2, and a source terminal of the transistor MN2 may be grounded.

In some embodiments, bias transistor MP3 and transistors MP1 and MP2 may include P-type transistors, and transistors MN1 and MN2 may include N-type transistors, but embodiments are not limited thereto. .

The first input signal VIP is first amplified by the bias current generated when the transistor MP1 is turned on based on the first input signal VIP and the transistor MN1 is turned on based on the feedback signal VCMFB. As a result, the first amplified signal VAP may be generated. Then, the generated first amplification signal VAP may be transmitted to the second amplifier A2 (eg, a gate terminal of the transistor MN6).

The second input signal VIN is first amplified by the bias current generated when the transistor MP2 is turned on based on the second input signal VIN and the transistor MN2 is turned on based on the feedback signal VCMFB. As a result, the second amplified signal VAN may be generated. Then, the generated second amplified signal VAN may be transmitted to the second amplifier A2 (eg, a gate terminal of the transistor MN7).

The second amplifier A2 may second amplify the first amplification signal VAP and the second amplification signal VAN to output the first output signal VOP and the second output signal VON.

The second amplifier A2 includes a transistor MP6 used by the feed forward circuit FFA to perform feed forward control on the first output signal VOP, and the feed forward circuit FFA controls the second output signal VON. A transistor MP7 used to perform feed forward control for , a transistor MN6 turned on based on the first amplification signal VAP output from the first amplifier A1, and an output from the first amplifier A1 A transistor MN7 turned on based on the second amplified signal VAN may be included.

A source terminal of the transistor MP6 may be connected to the power supply voltage VDD, and a drain terminal of the transistor MP6 may be connected to a drain terminal of the transistor MN6. A gate terminal of the transistor MP6 may be connected to a drain terminal of the transistor MP4 of the feed forward circuit FFA.

A source terminal of the transistor MP7 may be connected to the power supply voltage VDD, and a drain terminal of the transistor MP7 may be connected to a drain terminal of the transistor MN7. A gate terminal of the transistor MP7 may be connected to a drain terminal of the transistor MP5 of the feed forward circuit FFA.

A source terminal of the transistor MN6 may be grounded, and a drain terminal of the transistor MN6 may be connected to a drain terminal of the transistor MP6. The first output signal VOP may be output to the drain terminal of the transistor MN6. A gate terminal of the transistor MN6 may be connected to a drain terminal of the transistor MP1 and a drain terminal of the transistor MN1 of the first amplifier A1.

A source terminal of the transistor MN7 may be grounded, and a drain terminal of the transistor MN7 may be connected to a drain terminal of the transistor MP7. The second output signal VON may be output to the drain terminal of the transistor MN7 . A gate terminal of the transistor MN7 may be connected to a drain terminal of the transistor MP2 and a drain terminal of the transistor MN2 of the first amplifier A1.

In some embodiments, the transistors MP7 and MP6 may include P-type transistors, and the transistors MN7 and MN6 may include N-type transistors, but embodiments are not limited thereto.

In some embodiments, the second amplifier A2 may include a first mirror compensation circuit MCC1 and a second mirror compensation circuit MCC2 including a variable resistor RZ and a variable capacitor CC.

As such, when the second amplifier A2 includes the first mirror compensation circuit MCC1 and the second mirror compensation circuit MCC2, the first mirror is between the input terminal and the output terminal of the second amplifier A2 shown in FIG. A compensation circuit MCC1 and a second Miller compensation circuit MCC2 may be added.

The first Miller compensation circuit MCC1 may be connected between the gate terminal and the drain terminal of the transistor MN6 to perform a compensation operation. The second Miller compensation circuit MCC2 is connected between the gate terminal and the drain terminal of the transistor MN7 to perform a compensation operation.

In some embodiments, the amplifier 100 includes first and second Miller compensation circuits MCC1 and MCC2 performing dominant pole compensation using a common mode feedback circuit (CFC) and a Miller effect. can include Accordingly, the gain of the common mode feedback circuit (CFC) can be sufficiently increased without deteriorating the stability of the entire system, so that the amplifier 100 can stably operate in the common mode.

When the transistor MN6 is turned on based on the first amplification signal VAP generated by the transistor MP1 of the first amplifier A1 and the transistor MN1, the generated bias current generates the first amplified signal VAP. A second amplification may generate the first output signal VOP. Also, the first output signal VOP may be generated by a bias current generated when the transistor MP6 is turned on based on the output of the feed forward circuit FFA. That is, the first output signal VOP can be generated by the operation of the transistor MN6, which is part of the amplification path, and the transistor MP6, which is part of the feed forward path.

In addition, the second amplification signal ( VAN) may be second amplified to generate the second output signal VON. In addition, the second output signal VON may be generated by a bias current generated when the transistor MP7 is turned on based on the output of the feed forward circuit FFA. That is, the second output signal VON can be generated by the operation of the transistor MN7, which is part of the amplification path, and the transistor MP7, which is part of the feed forward path.

The common mode feedback circuit (CFC) receives the first output signal (VOP) and the second output signal (VON), and the average of the first output signal (VOP) and the second output signal (VON) is the reference signal (VCM). A feedback signal VCMFB adjusted to correspond to may be output.

In the amplifier 100, when there is no difference between the first input signal VIP and the second input signal VIN, which are differential signals, the first output signal VOP and the second output signal VON of the amplifier 100 Should be located at the middle level of the entire voltage swing range, but due to changes in power, temperature, process, between the input common mode and the output common mode of the amplifier 100, or the change in the output common mode due to noise, the amplifier The operation of the amplifier 100 may be limited because the output of the amplifier 100 is biased to a level other than the middle level.

For this purpose, a common mode feedback circuit (CFC) may be used. The common mode feedback circuit (CFC) detects the common mode voltage of the amplifier 100, compares the detected common mode voltage with a reference voltage, and determines the comparison result. It is a negative feedback circuit that makes the sensed common mode voltage close to the reference voltage.

A common mode feedback circuit (CFC) may be used at the output of amplifier 100 to establish the common mode of the differential output signals.

The common mode feedback circuit CFC includes a bias transistor MP8 turned on based on the bias voltage VB and a transistor MP9 turned on based on the average of the first output signal VOP and the second output signal VON. ), the transistor MP10 turned on based on the reference signal VCM, the transistor MN8 turned on by the output of the drain terminal of the transistor MP9, and the transistor turned on by the output of the drain terminal of the transistor MP10 ( MN9) may be included.

A source terminal of the bias transistor MP8 may be connected to the power supply voltage VDD, and a drain terminal of the bias transistor MP8 may be connected to the source terminals of the transistors MP9 and MP10. A bias voltage VB may be provided to a gate terminal of the bias transistor MP8.

An average of the first output signal VOP and the second output signal VON may be provided to the gate terminal of the transistor MP9 by the resistors RS and the capacitors CS. A drain terminal of the transistor MP9 may be connected to a drain terminal of the transistor MN8. The reference signal VCM is provided to a gate terminal of the transistor MP10, and a drain terminal of the transistor MP10 may be connected to a drain terminal of the transistor MN9.

The gate terminal of the transistor MN8 is connected to the drain terminal of the transistor MN8, and the feedback signal VCMFB may be output through the drain terminal of the transistor MN8. A source terminal of the transistor MN8 may be grounded. A gate terminal of the transistor MN9 is connected to a drain terminal of the transistor MN8, and a source terminal of the transistor MN9 may be grounded.

In some embodiments, the bias transistor MP8 and the transistors MP9 and MP10 may include a P-type transistor, and the transistors MN8 and MN9 may include an N-type transistor, but the embodiment is not limited thereto. .

The transistors MP9, MP10, MN8, and MN9 generate a feedback signal VCMFB for adjusting the average of the first output signal VOP and the second output signal VON to correspond to the reference signal VCM, The generated feedback signal VCMFB may be provided to the first amplifier A1 and the feed forward circuit FFA.

The feed forward circuit FFA may receive the first input signal VIP and the second input signal VIN and perform feed forward control on the first output signal VOP and the second output signal VON. .

The feed forward circuit FFA includes a transistor MP4 used to perform feed forward control on the first output signal VOP and a transistor MP5 used to perform feed forward control on the second output signal VON. , the transistor MN3 turned on based on the first input signal VIP, the transistor MN4 turned on based on the second input signal VIN, and the feed forward circuit FFA are enabled. transistor MN51 for controlling the flow of the fixed current IF in the feed forward circuit FFA while the feed forward circuit FFA is enabled, and a bias based on the feedback signal VCMFB in the feed forward circuit FFA while the feed forward circuit FFA is enabled. A transistor MN52 for controlling current IB to flow may be included.

A source terminal of the transistor MP4 may be connected to the power supply voltage VDD, and a drain terminal of the transistor MP4 may be connected to the resistor RL and the drain terminal of the transistor MN3. A gate terminal of the transistor MP4 may be connected to the resistor RL and the gate terminal of the transistor MP5. A drain terminal of the transistor MP4 is connected to a gate terminal of the transistor MP6 of the second amplifier A2 to perform feed forward control.

A source terminal of the transistor MP5 may be connected to the power supply voltage VDD, and a drain terminal of the transistor MP5 may be connected to the resistor RL and the drain terminal of the transistor MN4. A gate terminal of the transistor MP5 may be connected to the resistor RL and the gate terminal of the transistor MP4. The drain terminal of the transistor MP5 is connected to the gate terminal of the transistor MP7 of the second amplifier A2 to perform feed forward control.

The first input signal VIP is provided to the gate terminal of the transistor MN3, and the source terminal of the transistor MN3 may be connected to the drain terminal of the transistor MN51 and the drain terminal of the transistor MN52.

The second input signal VIN is provided to the gate terminal of the transistor MN4, and the source terminal of the transistor MN4 may be connected to the drain terminal of the transistor MN51 and the drain terminal of the transistor MN52.

A source terminal of the transistor MN51 may be grounded, and a drain terminal of the transistor MN51 may be connected to a drain terminal of the transistor MN3. The bias voltage VBN is applied to the gate terminal of the transistor MN51, and the transistor MN51 is turned on based on the bias voltage VBN while the feed forward circuit FFA is enabled, thereby supplying the feed forward circuit FFA. It can be controlled so that a fixed current (IF) flows. That is, the transistor MN51 can always be turned on so that the fixed current IF flows in the feed forward circuit FFA while the forward circuit FFA is enabled.

A source terminal of the transistor MN52 may be grounded, and a drain terminal of the transistor MN52 may be connected to a drain terminal of the transistor MN4. The feedback signal VCMFB is provided to the gate terminal of the transistor MN52, and the transistor MN52 receives the feedback signal VCMFB provided from the common mode feedback circuit CFC while the feed forward circuit FFA is enabled. It can be turned on to control the bias current IB to flow through the feed forward circuit FFA. That is, while the forward circuit FFA is enabled, the transistor MN52 has a bias current IB whose size changes based on the feedback signal VCMFB provided from the common mode feedback circuit CFC to the feed forward circuit FFA. ) can be controlled to flow.

In some embodiments, the transistors MP4 and MP5 may include P-type transistors, and the transistors MN3 , MN4 , MN51 and MN52 may include N-type transistors, but embodiments are not limited thereto.

5 to 8 are diagrams for explaining an effect of a receiving amplifier according to some embodiments.

First, FIG. 5 is a block diagram showing an amplifier different from the present embodiment. FIG. 6 is a circuit diagram of FIG. 5 . FIG. 7 is a graph showing frequency response characteristics of the amplifiers shown in FIGS. 5 and 6 .

Referring to FIG. 5 , the feed forward circuit FFA1 of the amplifier 99 does not receive the feedback signal VCMFB from the common mode feedback circuit CFC. That is, the feed forward circuit FFA1 of the amplifier 99 does not consider the feedback signal VCMFB output from the common mode feedback circuit CFC when performing the feed forward control.

Referring to FIG. 6 , the feed forward circuit FFA1 of the amplifier 99 is turned on based on the bias voltage VBN while the feed forward circuit FFA1 is enabled to supply a fixed current ( It includes only the transistor MN51 that controls the IF) to flow.

In this case, due to the impedance of the amplifier 99, as shown in FIG. 7, the frequency response characteristics of the amplifier 99 are divided into a common mode loop (CL1) and a differential mode loop ( There is a gain difference between DL1).

In the case of the differential mode loop DL1, the pole P2 is nulled by the first and second Miller compensation circuits MCC1 and MCC2, and the pole P3 is fed to the feed forward circuit FFA1. It may be nulled by , and may have the characteristics of a one-pole system.

However, in the case of the common mode loop CL1, the pole P2 can be nulled by the first and second Miller compensation circuits MCC1 and MCC2, but the pole P3 is not nulled, so that the two poles have two poles. Due to the characteristics of a two-pole system, problems such as circuit oscillation may occur.

8 is a graph showing frequency response characteristics of the amplifier according to this embodiment.

As described above with reference to FIG. 3, the feed forward circuit (FFA) of the amplifier 100 according to the present embodiment receives the feedback signal (VCMFB) from the common mode feedback circuit (CFC) and performs feed forward control based on this. carry out That is, the feed forward circuit (FFA) of the amplifier 100 considers the feedback signal (VCMFB) output from the common mode feedback circuit (CFC) in performing the feed forward control.

Accordingly, as shown in FIG. 4 , the feed forward circuit (FFA) of the amplifier 100 is turned on based on the bias voltage (VBN) while the feed forward circuit (FFA) is enabled, so that the feed forward circuit (FFA) ), which is turned on based on the feedback signal VCMFB provided from the common mode feedback circuit CFC while the transistor MN51 controls the flow of the fixed current IF and the feed forward circuit FFA is enabled, so that the feed forward A transistor MN52 for controlling the bias current IB to flow in the circuit FFA is included.

Accordingly, as shown in FIG. 8, a loop (CLM) of a new response characteristic is added to the frequency response characteristic of the amplifier, so that the common mode loop (CL2) can have the characteristic of a one-pole system. there is.

Specifically, in the case of the differential mode loop DL2, the pole P2 is nulled by the first and second Miller compensation circuits MCC1 and MCC2, and the pole P3 is nulled by the feed forward circuit FFA. It may have the characteristics of a one-pole system.

And, even in the case of the common mode loop CL2, the pole P2 is nulled by the first and second Miller compensation circuits MCC1 and MCC2, and the pole P3 is fed back from the common mode feedback circuit CFC. It may have characteristics of a one-pole system by being nulled by the feed forward circuit FFA that performs feed forward control based on the signal VCMFB.

As such, the reception amplifier according to the present embodiment can operate stably because both the differential mode loop DL2 and the common mode loop CL2 have characteristics of a one-pole system.

Furthermore, the sum of the size of the transistor MN51 and the size of the transistor MN52 of the amplifier 100 according to the present embodiment may be substantially equal to the size of the transistor MN51 of the amplifier 99. That is, when the transistor MN51 of the amplifier 99 is composed of, for example, four unit transistors, the transistor MN51 of the amplifier 100 according to this embodiment is composed of two unit transistors. and the transistor MN52 may be composed of two unit transistors. Also, in another embodiment, the transistor MN51 of the amplifier 100 according to this embodiment may be composed of one unit transistor, and the transistor MN52 may be composed of three unit transistors. The transistor MN51 of the amplifier 100 may be composed of three unit transistors, and the transistor MN52 may be composed of one unit transistor.

In other words, in order to improve operational stability of the receiving amplifier, an additional passive component is not required, and thus the receiving amplifier can be miniaturized.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100: amplifier
A1: first amplifier
A2: second amplifier
CFC: common mode feedback circuit
FFA: Feed Forward Circuit

Claims (20)

a first amplifier that first amplifies the first input signal and the second input signal and outputs the first amplified signal and the second amplified signal;
a second amplifier receiving the first amplified signal and the second amplified signal and amplifying the first and second amplified signals to output a first output signal and a second output signal;
a feed forward circuit receiving the first and second input signals and performing feedforward control on the first and second output signals; and
A common mode feedback circuit receiving the first and second output signals and outputting a feedback signal for adjusting an average of the first and second output signals to correspond to a reference signal,
The semiconductor device of claim 1 , wherein a feedback signal output from the common mode feedback circuit is provided to the first amplifier and the feed forward circuit. According to claim 1,
The feed forward circuit,
A first transistor turned on based on the first input signal;
a second transistor turned on based on the second input signal;
a third transistor connected to one end of the first transistor and turned on based on a first signal;
and a fourth transistor connected to one terminal of the second transistor and turned on based on the feedback signal. According to claim 2,
The third transistor is turned on while the feed forward circuit is enabled. According to claim 2,
The third transistor controls a fixed current to flow in the feed forward circuit while the feed forward circuit is enabled;
The fourth transistor controls a bias current based on the feedback signal to flow in the feed forward circuit while the feed forward circuit is enabled. According to claim 2,
The third transistor is connected to one terminal of the second transistor, and the fourth transistor is connected to one terminal of the first transistor. According to claim 2,
The first amplifier,
A fifth transistor turned on based on the first input signal;
A sixth transistor turned on based on the second input signal;
a seventh transistor connected to one end of the fifth transistor and turned on based on the feedback signal;
and an eighth transistor connected to one terminal of the sixth transistor and turned on based on the feedback signal. According to claim 6,
The second amplifier,
a ninth transistor having a gate terminal connected between the fifth transistor and the seventh transistor and outputting the first output signal to a drain terminal;
and a tenth transistor having a gate terminal connected between the sixth transistor and the eighth transistor, and outputting the second output signal to a drain terminal. According to claim 7,
a first mirror compensation circuit connected between the gate terminal and the drain terminal of the ninth transistor;
The semiconductor device further includes a second Miller compensation circuit connected between a gate terminal and a drain terminal of the tenth transistor. According to claim 1,
The feed forward circuit,
a first transistor controlling a fixed current to flow in the feed forward circuit while the feed forward circuit is enabled;
and a second transistor controlling a bias current based on the feedback signal to flow in the feed forward circuit while the feed forward circuit is enabled. According to claim 1,
The semiconductor device of claim 1 , wherein the first input signal and the second input signal are differential signals. According to claim 1,
The semiconductor device is an Operational Transconductance Amplifier (OTA). A first transistor turned on based on a first input signal, a second transistor turned on based on a second input signal, and a third transistor connected to one terminal of the first transistor and turned on based on a feedback signal; a first amplifier including a fourth transistor connected to one end of the second transistor and turned on based on the feedback signal;
A fifth transistor turned on based on the first input signal, a sixth transistor turned on based on the second input signal, and a seventh transistor connected to one end of the fifth transistor and turned on based on a bias signal. and a feed forward circuit including an eighth transistor connected to one end of the second transistor and turned on based on the feedback signal;
A ninth transistor having a gate terminal connected between the first transistor and the third transistor and outputting a first output signal through a drain terminal; and a gate terminal connected between the second transistor and the fourth transistor and outputting a first output signal through a drain terminal. a second amplifier including a tenth transistor outputting a second output signal; and
and a common mode feedback circuit receiving the first and second output signals and outputting the feedback signal for adjusting an average of the first and second output signals to correspond to a reference signal. According to claim 12,
a first mirror compensation circuit connected between the gate terminal and the drain terminal of the ninth transistor;
The semiconductor device further includes a second Miller compensation circuit connected between a gate terminal and a drain terminal of the tenth transistor. According to claim 12,
The seventh transistor is connected to one terminal of the sixth transistor, and the eighth transistor is connected to one terminal of the fifth transistor. a receive mixer that performs down-converting on the output of the low-noise amplifier;
a receiving amplifier for amplifying and outputting an output of the receiving mixer; and
Including a receive filter for filtering the output of the receive amplifier,
The output of the receive mixer includes first and second input signals;
The receiving amplifier,
an amplifier configured to amplify the first and second input signals and output first and second output signals;
a common mode feedback circuit receiving the first and second output signals and outputting a feedback signal for adjusting an average of the first and second output signals to correspond to a reference signal;
A feed forward circuit receiving the first and second input signals and the feedback signal and performing feed forward control on the first and second output signals based on the first and second input signals and the feedback signal. A communication device comprising a. According to claim 15,
The amplifier is
The first and second input signals are first amplified by receiving the first and second input signals and the feedback signal, and first amplifying the first and second input signals based on the first and second input signals and the feedback signal. A first amplifier outputting a signal;
and a second amplifier receiving the first and second amplified signals and amplifying them a second time to output the first and second output signals. According to claim 16,
The feed forward circuit,
A first transistor turned on based on the first input signal;
a second transistor turned on based on the second input signal;
a third transistor connected to one end of the first and second transistors and turned on based on a bias signal;
and a fourth transistor connected to one end of the first and second transistors and turned on based on the feedback signal. According to claim 15,
The feed forward circuit,
a first transistor controlling a fixed current to flow in the feed forward circuit while the feed forward circuit is enabled;
and a second transistor controlling a bias current based on the feedback signal to flow in the feed forward circuit while the feed forward circuit is enabled. According to claim 18,
The amplifier is
The first and second input signals are first amplified by receiving the first and second input signals and the feedback signal, and first amplifying the first and second input signals based on the first and second input signals and the feedback signal. A first amplifier outputting a signal;
and a second amplifier receiving the first and second amplified signals and amplifying them a second time to output the first and second output signals. According to claim 15,
The receiving amplifier includes a transimpedance amplifier (TIA),
The amplifier is a communication device including an Operational Transconductance Amplifier (OTA).

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